REDUCED SIZE RESONANT TUNNEL FIELD EFFECT TRANSISTOR

Abstract

Device comprising the following: an n-hetero-junction tunnel field-effect transistor, n-heTFET, with a source electrode (1107), a channel (1108) and a drain electrode (1109), wherein (a) the channel (1108) has a principal axis corresponding to the channel length and a secondary axis corresponding to the channel width and orthogonal to the principal axis, (b) the channel length is less than 10 nm and the channel width is less than 4 nm, (c) the source electrode (1107) is positively doped and has a first conduction band, (d) the drain electrode (1109) is negatively doped and the drain electrode (1109) has a second conduction band whose energy is higher than that of the first conduction band, wherein (e) the source electrode (1107) InAs and the drain electrode (1109) GaSb, or the source electrode (1107) Si and the drain electrode (1109) InAs or SiGe, or the source electrode (1107) GaAsSb and the drain electrode (1109) InAsSb or the source electrode (1107) InGaAs and the drain electrode (1109) InP.

Description

background

[0001] A tunnel field-effect transistor (TFET) structure is similar to a metal-oxide-semiconductor field-effect transistor (MOSFET) structure and has a source electrode, a drain electrode, and a channel coupled to a gate electrode. TFETs are available in various forms, such as n-type (nTFET) devices and p-type (pTFET) devices. The drain current (I d ) decreases for an nTFET with increasing gate voltage (V g ) to and for a pTFET with decreasing V g The nTFET switches at a gate / source voltage (V g ), which is greater than the threshold voltage, through (“on state”), while the pTFET at a V gthat is less than the threshold voltage. The source electrode in an nTFET is p-doped, while the drain electrode is n-doped, and the source electrode in a pTFET is n-doped, while the drain electrode is p-doped. The channel is undoped or less doped in terms of doping concentration than either the source electrode or the drain electrode.

[0002] US 020120032227 A1 describes a low-voltage tunnel field-effect transistor comprising a pn tunnel junction, a gate dielectric, a gate, a source contact, and a drain contact. The pn tunnel junction includes a depletion zone connecting a source layer and a drain layer. The depletion zone includes a source tunnel region of the source layer and a drain tunnel region of the drain layer.

[0003] US 020120298961 A1 describes a method for fabricating a heterojunction in a tunnel field-effect transistor device configuration (e.g., in a segmented nanowire TFET). A thin junction layer is inserted between the source region and the channel region, so that outdiffusion is restricted to a very limited area of ​​a few nm. This ensures extremely good doping slope due to the lower diffusion of the dopants in the junction layer.

[0004] Vinay Saripalli et al. “An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores” ; 2011 48th ACM / EDAC / IEEE Design Automation Conference (DAC) describes an energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores.

[0005] DE 000069232185 T2 describes a three-terminal tunneling device featuring forward carrier tunneling. The device comprises an intrinsic semiconductor region, a degenerate n-type semiconductor source region adjacent to one side of the intrinsic semiconductor region, a degenerate p-type semiconductor drain region adjacent to an opposite side of the intrinsic semiconductor region, an isolation region separating the three semiconductor regions from a semiconductor substrate, and a gate electrode provided above the intrinsic semiconductor region through an isolation layer.

[0006] US 020100163845 A1 describes a TFET comprising a source region, a drain region, a channel region between the source region and the drain region, and a gate region adjacent to the channel region.

[0007] US 020120115296 A1 describes a tunnel field-effect transistor (TFET). In one embodiment, the transistor comprises a gate that is not aligned with a drain and overlaps only with the source, extending at least to the interface of the source-channel region and optionally overlapping with a portion of the channel. The shorter gate reduces the overall gate capacitance, which directly translates into improved device switching speed.

[0008] US 020120223390 A1 describes a TFET comprising a substrate, a channel region formed in the substrate, a source region and a drain region formed on two sides of the channel region, and a gate stack formed on the channel region.

[0009] US 020120043607 A1 describes a vertical tunnel field effect transistor comprising a semiconductor body with a source region doped with a first dopant type and a pocket region doped with a second dopant type, wherein the pocket region is formed above the source region.

[0010] US 020120187376 A1 describes a tunnel field-effect transistor that can be operated at a low subthreshold and is easy to manufacture. The tunnel field-effect transistor comprises a group IV semiconductor substrate having a (111) surface and doped with a first conductivity type, a group III-V compound semiconductor nanowire disposed on the (111) surface and including a first region connected to the (111) surface and a second region doped with a second conductivity type, a source electrode connected to the group IV semiconductor substrate, a drain electrode connected to the second region, and a gate electrode for applying an electric field to an interface between the (111) surface and the group III-V compound semiconductor nanowire or an interface between the first region and the second region. Short description of the drawing

[0011] Features and advantages of embodiments of the present invention will become apparent from the appended claims, the following detailed description of one or more exemplary embodiments, and the corresponding figures. The Fig. 1 - 2 concern MOSFET, TFET and heterojunction TFET (heTFET) blocking / on-state characteristics. Fig. 3 concerns a conventional heTFET structure. Fig. 4 relates to a reverse heTFET structure according to one embodiment. The Fig. 5 - 6 relate to MOSFET, heTFET and reverse heTFET blocking / on-state characteristics according to one embodiment. The Fig. 7-8 relate to MOSFET, heTFET, and reverse heTFET blocking / on-state characteristics according to one embodiment. Fig. 9 relates to a reverse heTFET energy band diagram according to an embodiment. The Fig. 10(a)-(d) relate to the density of states (DOS) for one embodiment. Fig. 11 shows a schematic sectional view of an embodiment. Detailed description

[0012] In the following description, numerous specific details are set forth; however, embodiments of the invention may be practiced without these specific details. Well-known circuits, structures, and techniques have not been shown in detail in order not to obscure this description. "One embodiment," "one embodiment," "various embodiments," and the like indicate that embodiment(s) so described may include certain features, structures, or characteristics; however, not every embodiment necessarily includes the specific features, structures, or characteristics. Some embodiments may include some, all, or none of the features described for other embodiments."First," "second," "third," and the like describe a common object and indicate that reference is being made to various instances of comparable objects. These adjectives do not imply that objects so described must exist in a given temporal, spatial, ranked, or other sequence. "Connected" may indicate that elements are in direct physical or electrical contact with each other, and "coupled" may indicate that elements cooperate or interact with each other, but they may or may not be in direct physical or electrical contact. Although similar or identical numbers may be used to refer to similar or identical parts in different figures, this does not imply that all figures having similar or identical numbers constitute a single or identical embodiment.

[0013] The inverse “subliminal slope” dVg / d log (I d ) of a MOSFET has a theoretical lower limit of 60 mV / decade (“dec”) at room temperature. The sub-limit slope refers to the slope of the current-voltage characteristic near the “off” state of the device (i.e., where I d is small, also known as I sperr or “off-state current”), and the “on state” of the device (ie where a significant I d is present, also as I durch or “turn-on current”). For a given off-state current target (which is determined by a standby power requirement for a device incorporating the MOSFET), I dfor a MOSFET, the on-state current can only rise at this maximum rate of 60 mV / dec. This limits the on-state current and consequently the circuit performance (e.g., the speed of transistor switching). For devices operating with low active power, operation at lower supply voltages is desirable due to the strong dependence of the active power on the supply voltage (proportional to the square of the supply voltage). Due to the limited subthreshold slope of the MOSFET, when a MOSFET is operated at low supply voltages, the on-state current is significantly lower because the MOSFET is operating near its threshold voltage (which is required to switch from the off-state to the on-state).

[0014] Fig. Figure 1 shows various transistor behavior characteristics, showing, for example, that a TFET (lane 102) can exhibit a sharper turn-on behavior (i.e., a steeper subthreshold slope) than a MOSFET (lane 101). The conditions for Fig. 1 include an I sperr of 1 nA / µm, an equivalent oxide thickness (EOT) of 0.8 nm and a gate length (L g ) of 15 nm. This sharpness advantage for the TFET is in Fig. 1 of V gfrom 0.0 to 0.2 V, where MOSFET 101 has a 74 mV / dec slope and TFET 102 has a 41 mV / dec slope in this same range. In other words, the TFET has a steeper and more desirable subthreshold slope. This enables higher turn-on currents than with the MOSFET when the devices are operated at low supply voltages. A heTFET (trace 103) uses a combination of two semiconductor materials (one for the source electrode and another for the channel and drain electrodes; hence the term heterojunction) to enable higher tunneling current and better TFET characteristics. The subthreshold slope for heTFET 103 is approximately 35 mV / dec, which is better (steeper) than either TFET 102 or MOSFET 101.

[0015] However, this advantage of TFET devices over MOSFETs diminishes with aggressively scaled (shorter) gate lengths. Fig. 1 Data for devices with an L g of 15 nm, Fig. 2 Data for the same conditions as in Fig. 1, but for an L g of only 9 nm. Fig. 2 shows that the subthreshold slopes for 201, 202, 203 for V g from 0.0 to 0.1 V are similar, which is in contrast to Fig. 1, demonstrating the clear advantage (steeper slopes) of the TFET over the MOSFET in this region. The sub-threshold slope difference between the three devices decreases as the gate length decreases. In other words, traces 202 and 203 (both of which are TFETs) have a lower slope than the MOSFET between the Fig. 1 and Fig. 2 a minor improvement in gradient steepness.

[0016] Fig. Figure 3 shows a conventional heTFET design that combines the semiconductor material at the source electrode (e.g., gallium antimonide (GaSb)) with a material with a lower conduction band at the channel and drain electrode (e.g., indium arsenide (InAs)). Fig. 4 shows an embodiment of the invention comprising a reversed heTFET with the strip material sequence reversed. In other words, the reversed heTFET design of Fig. 4 the semiconductor material at the source electrode (e.g. InAs) with a material with a higher conduction band at the channel and drain electrode (e.g. GaSb). However, in Fig. 4 the band discontinuity due to the different materials counteracts the tunnel current density and leads to a much more difficult tunnel path.

[0017] Embodiments of the invention are not limited to source / drain combinations such as the InAs / GaSb material system described above. Other embodiments include material combinations that produce significant band discontinuity. Other examples include materials such as silicon (Si), germanium (Ge), and phosphorus (P), and include, but are not limited to, source / drain combinations such as Si / InAs, Si / SiGe, GaAsSb / InAsSb, and InGaAs / InP.

[0018] This is based on the difference in operating characteristics between conventional and inverted heTFET devices, each of which has L g = 20 nm, which are shown in the Fig. 5 and Fig. 6. In the Fig. 5 and Fig. 6 are MOSFET (traces 501, 601), conventional heTFET (source electrode = GaSb, drain electrode = InAs) (traces 503, 603) and reverse heTFET (source electrode = InAs, drain electrode = GaSb) (traces 504, 604) for reverse current targets of 1 nA / µm ( Fig. 5, Element 505) and 10 pA / µm ( Fig. 6, element 605). These figures show conventional heTFETs, which have a higher turn-on current than reversed heTFETs, for various reverse current targets and supply voltages when the devices are L g = 20 nm.

[0019] However, this behavior changes with a very short L g with limited channel dimensions. For a short L gAn inverted heTFET has a very sharp subthreshold slope. This enables operation with a low supply voltage and operation with a low reverse current target, both of which enable very low-power products. For example, one embodiment has a channel with L g = 9 nm, which is contained in a 3 nm wide and 3 nm high nanowire (a semiconductor nanoscale structure). As shown in the Fig. 7 and Fig. As can be seen in Figure 8, this inverted heTFET embodiment has a very sharp subthreshold slope. MOSFET (traces 701, 801), conventional heTFET (source electrode = GaSb, drain electrode = InAs) (traces 703, 803), and inverted heTFET (source electrode = InAs, drain electrode = GaSb) (traces 704, 804) are each for I sperr -Targets of 1 nA / µm ( Fig. 7) and 10 pA / µm ( Fig. 8). All devices have L g= 9 nm. The inverted heTFETs show the best subthreshold slope and work best at both I sperr -targets with low supply voltages. In particular, the reversed heTFET trace 804 in Fig. 8 a sub-threshold slope of 25 mV / dec (between 0.0 and 0.1 V g ), while heterojunction device trace 803 exhibits a subthreshold slope of 47 mV / dec and MOSFET 801 exhibits a subthreshold slope of 63 mV / dec. Accordingly, this embodiment of a reverse heTFET achieves better turn-on current than both MOSFET and conventional heTFET at low supply voltages.

[0020] One embodiment has improved transistor characteristics, for example, due to the discrete resonant states created by three-dimensional confinement of the channel of the inverted heTFET. For example, one embodiment has a channel with L gless than 10 nm, with two dimensions limited by the use of a nanowire width and height of 3 nm, and a third dimension limited by the profile of the band discontinuity between the source electrode and the channel of the embodiment. These resonance states enable a rapid change of I due to the high density of states (DOS) property. sperr to I durch .

[0021] This rapid change of I sperr to I durch is not obvious when considering a classical potential profile. For example, in an embodiment featuring a reverse heTFET, the energy bands do not accurately explain the actual device operation. Fig. Figure 9 shows classical band edges for the reversed heTFET at I sperr (Traces 910) and I durch(Traces 911). Traces 910 correspond to the conduction and valence bands at 0.0 eV, and traces 911 correspond to the conduction and valence bands at 0.3 eV. The tunneling gap 920 is large, but even the tunneling gap 921 remains large, indicating a very low (undesired) channel current in the on state.

[0022] The Fig. However, Figures 10(a)-(d) better illustrate the operation according to one embodiment of the device and why a highly confined channel geometry makes inverted heTFETs advantageous over non-inverted heTFETs and MOSFETs. Due to the strong channel confinement, the allowed electron energies have peaks around the heterojunction interface region. In particular, Fig. 10(a)-(d) Density of states (DOS) properties. DOS equals the density per unit volume and energy to the number of solutions of the Schrödinger equation. Fig. 10(a) and (b) correspond to blocking and on-states for a conventional heTFET (L g = 9 nm). The Fig. 10(c) and (d) correspond to blocking and on-states for a reversed heTFET (L g = 9 nm). Until discrete energy states are aligned with the valence band on the source side (range 1021 for each of the Fig. 10(a)-(d)), the tunneling current is low due to the low DOS in the region, which is necessary to conduct electrons. Accordingly, Fig. 10(a) shows a conventional heTFET in the off-state with a large tunnel pitch of 1020. Fig. Figure 10(c) shows an embodiment of a reversed heTFET in the off-state with a large tunnel pitch 1030.

[0023] In Fig. 10(c) exists as soon as V g for the conventional heTFET, a low DOS is still present at the source / channel junction 1023 (as can be understood from the shaded contour markings). Fig. 10(d) however, the energy of the discrete levels was reduced to the level of the valence band of the source side 1021 (due to the increasing V g ), there is a sharp increase in the tunneling current, producing a sharp subthreshold slope. In other words, the source / channel junction 1033 has a high DOS protrusion 1034 (which resembles a horizontal "needle" pointing to the left in the graph). The high DOS protrusion 1031 is connected to the valence band 1021 of the source electrode at I sperr misaligned ( Fig. 10(c)), however, projection 1034 is in Fig. 10(d) is aligned with the valence band 1021 of the source electrode. More generally, Fig. 10(d) higher DOS (darker sections are higher DOS) as a function of energy along the device near the source / channel junction (near the 10 nm mark on the x-axis). Therefore, inverted heTFETs work at small L gbetter than conventional TFET, resulting in better on-state current at a lower V g is provided.

[0024] An embodiment is implemented with the same or a similar approach as conventional heTFET (only with the changed semiconductor materials in the source region and in the channel / drain regions, as in Fig. 4). This enables heterogeneous integration of two devices, where, for example, circuits requiring high performance use the conventional heterojunction device and circuits requiring low power use the inverted heTFET on the same substrate.

[0025] Various methods are available for creating a narrow channel suitable for an inverted heTFET. Such methods are described, for example, in U.S. Patent 6,897,098, entitled "Method of fabricating an ultra-narrow channel semiconductor device," assigned to Intel Corporation (Santa Clara, California, USA). As detailed in U.S. Patent 6,897,098, a small-sized channel suitable for use in accordance with various embodiments of the invention is fabricated as follows. A nanowire 1106 is deposited on a first dielectric layer 1104 formed on the substrate 1102 (see Fig.11). The nanowire has a first dimension. The nanowire provides a first region 1108, a second region 1107, and a third region 1109. A sacrificial gate stack including a sacrificial dielectric layer and a sacrificial gate electrode layer is deposited over the first region 1108 of the nanowire, leaving the second region and the third region of the nanowire exposed. A first spacer is deposited adjacent to each side of the sacrificial gate stack. A second dielectric layer is deposited over the first dielectric layer to cover the second region and the third region. The sacrificial gate electrode and the sacrificial dielectric layer are removed after the first spacer is deposited. Removing the sacrificial gate electrode and the sacrificial dielectric layer exposes the first region of the nanowire.The first region of the nanowire is thinned by at least one thermal oxidation and oxide removal process. After thinning, the first region has a second dimension that is smaller than the first dimension. By thinning the first region of the nanowire, the first region of the nanowire is provided with a cross-sectional dimension that is significantly smaller (e.g., ten times or at least twice smaller) than those of the second region and the third region. The first region may be a central region 108 of the nanowire, and the second and third regions 1107, 1109 may be the side regions of the nanowire. A dielectric layer 1125 and a gate electrode layer 1123 may be added.

[0026] According to one embodiment, the nanowire has first cross-sectional dimensions that are on the nanoscale order. The nanowire has a length 1130 of about 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15 nm, a height 132 of about 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15 nm, and a width 134 of about 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15 nm. The height, width, and length can be changed depending on the methods used to form the nanowire. As shown above, some embodiments include length, width, and height combinations of 10.3 and 3 nm. However, other embodiments include, for example and without limitation, length, width, and height combinations of 8.3 and 3 nm, 12.3 and 3 nm, 8.2 and 2 nm, and the like.

[0027] According to one embodiment, the central region, prior to thinning, has the same initial thickness or cross-sectional dimension as the rest of the nanowire. After thinning, the central region has a cross-sectional dimension that is smaller or significantly smaller than other sections of the nanowire 1106. According to one embodiment, the thinned central section has a width and / or height that is less than about 5 nm or less than about 2-3 nm. According to some embodiments, no thinning of the central section 1108, which has the same height and width as sections 1007, 1109, occurs.

[0028] According to one embodiment, the second region and the third region are implanted using conventional techniques such as ion implantation to form the source / drain regions for a semiconductor device. For example, for an n-heTFET, region 1107 may be a p-doped source electrode, channel region 1108 may be intrinsic, and region 1109 may be an n-doped drain electrode. According to another embodiment, for a p-heTFET, region 1107 may be a p-doped drain electrode, channel region 1108 may be intrinsic, and region 1109 may be an n-doped source electrode. The source and drain electrodes may comprise different materials with respect to doping concentration, material concentrations (e.g., In x Ga 1-x Ace and In y Ga 1-y As, where x is not equal to y) and materials (e.g. InAs and GaSb).

[0029] A silicide layer may be formed over each of the second region and the third region after implantation to facilitate contacts to the source / drain regions. The silicide layer provides low contact resistance to the source / drain regions formed in the second region and the third region. The silicide layer may be formed from a metal such as cobalt, nickel, and the like. The silicide layer may be formed using conventional techniques that deposit the metal over the second region and the third region. After the metal is deposited, heat is applied to these regions to allow the silicon in these regions to react with the metals to form silicide.

[0030] Accordingly, as stated above, one embodiment comprises a heTFET having a source electrode, a channel, and a drain electrode, wherein the channel has a major axis corresponding to the channel length and a minor axis corresponding to the channel width and orthogonal to the major axis. According to one embodiment, the channel length is less than 10 nm, but according to other embodiments, the length is greater (e.g., 10 or 15 nm) or less (e.g., 3 or 4 nm). According to one embodiment, the channel width is less than 5 nm, but according to other embodiments, the width is greater (e.g., 7 or 9 nm) or less (e.g., 2 or 3 nm). According to one embodiment, the channel height is less than 5 nm, but according to other embodiments, the height is greater (e.g., 7 or 9 nm) or less (e.g., 2 or 3 nm).For a p-heTFET, the source electrode is doped with a first polarity (n) and has a first conduction band, and the drain electrode is doped with a second polarity (p) and has a second conduction band higher than the first conduction band. The doping polarity is opposite for an n-heTFET. According to one embodiment, the off-state current is less than 3 nA and can, for example, be as low as 1 pA. However, according to other embodiments, the off-state current can be 1 or 2 nA, or 4, 5, 6, 7, 8, 9, or more nA. According to one embodiment, the ratio between the subthreshold gate voltage and the logarithm of the drain current (the subthreshold slope) occurring at the transition between the off-state and the on-state is less than 30 mV / dec, but according to other embodiments the slope is 15, 20, 25, 35 or 40 mV / dec.

[0031] One embodiment includes a device comprising: a heterojunction tunneling field-effect transistor having a source electrode, a channel, and a drain electrode, wherein (a) the channel has a major axis corresponding to the channel length and a minor axis corresponding to the channel width and orthogonal to the major axis, (b) the channel length is less than 10 nm, (c) the source electrode is doped with a first polarity and has a first conduction band, (d) the drain electrode is doped with a second polarity opposite to the first polarity, and the drain electrode has a second conduction band whose energy is higher than that of the first conduction band. In one embodiment, the first polarity is positive. In one embodiment, the source electrode comprises InAs. In one embodiment, the drain electrode comprises GaSb. In one embodiment, the channel width is less than 4 nm.According to one embodiment, the channel comprises a nanowire. According to one embodiment, the off-state current is less than 3 nA. According to one embodiment, the ratio between the subthreshold gate voltage and the drain current occurring at the transition between the off-state and the on-state is less than 30 mV / dec. According to one embodiment, the DOS has a triangular protrusion at a junction between the source electrode and the channel that is misaligned with a valence band for the source electrode in an off-state and aligned with the valence band in an on-state. According to one embodiment, allowed electron energy states in an on-state have a peak at a junction between the source electrode and the channel. According to one embodiment, the heTFET is an inverted heterojunction TFET, wherein the device comprises a non-inverted heterojunction TFET (i.e.a heterojunction TFET) in a substrate that also contains the inverted heterojunction TFET.

[0032] One embodiment includes a device comprising: a heterojunction tunneling field-effect transistor having a source electrode, a channel, and a drain electrode, wherein the channel length is less than 10 nm, the drain electrode has a conduction band whose energy is higher than that of a conduction band of the source electrode, and the transistor has a ratio between the subthreshold gate voltage and the drain current occurring at the junction between the "off" state and the "on" state of less than 30 mV / dec. According to one embodiment, the DOS has a triangular protrusion at a junction between the source electrode and the channel, which is misaligned with a valence band for the source electrode in a "off" state and aligned with the valence band in an "on" state.According to one embodiment, allowed electron energy states in an on-state have a spacing at a junction between the source electrode and the channel.

[0033] One embodiment includes a device comprising: a substrate, a first heTFET having a first source electrode, a first channel, and a first drain electrode, wherein the length of the first channel is less than 10 nm, the first drain electrode has a conduction band whose energy is higher than that of a conduction band of the first source electrode, and wherein the heTFET is formed on the substrate, and a second heTFET having a second source electrode, a second channel, and a second drain electrode, wherein the second drain electrode has a conduction band whose energy is lower than that of a conduction band of the second source electrode, and wherein the second heTFET is formed on the substrate.According to one embodiment, the first heTFET has a slope between the sub-threshold gate voltage and the drain current, which occurs at the transition between the "off" state and the "on" state, of less than 30 mV / dec. According to one embodiment, the first channel width is less than 4 nm. According to one embodiment, the off-state current for the first heTFET is less than 3 nA.

[0034] Although the present invention has been described with reference to a limited number of embodiments, numerous modifications and variations thereof will occur to those skilled in the art. It is intended that the appended claims cover all such modifications and variations as fall within the spirit and scope of the present invention.

Claims

[1] Device comprising: an n-heterojunction tunnel field-effect transistor, n-heTFET, having a source electrode (1107), a channel (1108) and a drain electrode (1109), wherein (a) the channel (1108) has a major axis corresponding to the channel length and a minor axis corresponding to the channel width and orthogonal to the major axis, (b) the channel length is less than 10 nm and the channel width is less than 4 nm, (c) the source electrode (1107) is positively doped and has a first conduction band, (d) the drain electrode (1109) is negatively doped and the drain electrode (1109) has a second conduction band whose energy is higher than that of the first conduction band, wherein (e) the source electrode (1107) InAs and the drain electrode (1109) GaSb, or the source electrode (1107) Si and the drain electrode (1109) InAs or SiGe, or the source electrode (1107) GaAsSb and the drain electrode (1109) InAsSb or the source electrode (1107) comprises InGaAs and the drain electrode (1109) comprises InP. [2] The device of claim 1, wherein the channel (1108) comprises a nanowire (1106). [3] The device of claim 1, comprising a heTFET on a substrate also comprising the n-heTFET, the n-heTFET having an additional source and an additional drain, the additional source having a higher energy conduction band than a conduction band of the additional drain. [4] Device comprising: a p-heterojunction tunnel field-effect transistor, p-heTFET, with a negatively doped source electrode (1109), a channel (1108) and a positively doped drain electrode (1107), wherein the channel length is less than 10 nm and the channel width is less than 4 nm, the drain electrode (1107) has a conduction band whose energy is lower than that of a conduction band of the source electrode (1109), wherein the source electrode (1109) InAs and the drain electrode (1107) GaSb, or the source electrode (1109) Si and the drain electrode (1107) InAs or SiGe, or the source electrode (1109) GaAsSb and the (1107) drain electrode InAsSb or the source electrode (1109) is InGaAs and the drain electrode (1107) is InP. [5] Device comprising: a substrate (1102), a first n-heterojunction tunnel field-effect transistor, n-heTFET, having a first positively doped source electrode (1107), a first channel (1108) and a first negatively doped drain electrode (1109), wherein the length of the first channel (1108) is less than 10 nm and the channel width is less than 4 nm, the first drain electrode (1109) has a conduction band whose energy is higher than that of a conduction band of the first source electrode (1107), and wherein the first n-heTFET is formed on the substrate (1102), and a second heTFET having a second source electrode, a second channel, and a second drain electrode, wherein the second drain electrode has a conduction band whose energy is lower than that of a conduction band of the second source electrode, and wherein the second heTFET is formed on the substrate, wherein the first source electrode (1107) InAs and the first drain electrode (1109) GaSb, or the first source electrode (1107) Si and the first drain electrode (1109) InAs or SiGe, or the first source electrode (1107) GaAsSb and the first drain electrode (1109) InAsSb or the first source electrode (1107) comprises InGaAs and the first drain electrode (1109) comprises InP.

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