Method for manufacturing a plurality of optoelectronic semiconductor chips and optoelectronic semiconductor chip

Abstract

Method for producing a plurality of optoelectronic semiconductor chips (1), each having a plurality of pixels (25), comprising the steps: a) Providing a sequence of semiconductor layers (2) with an active region (20) for generating and / or detecting radiation, which is formed between a first semiconductor layer (21) and a second semiconductor layer (22); b) Providing a carrier (5) with a plurality of first connection surfaces (51); c) Attaching the semiconductor layer sequence (2) to the support (5) so that the first semiconductor layer (21) is electrically connected to the first contact surfaces (51); d) Forming separation trenches (27) in the semiconductor layer sequence (2) attached to the support (5) to form the image pixels (25), wherein the separation trenches (27) extend through the semiconductor layer sequence (2); e) Forming a contact layer (6), wherein each pixel (25) has at least one recess (28) in the semiconductor layer sequence (2) and the contact layer (6) extends from a second contact surface (52) through the recess (28) to the second semiconductor layer (22), and the second semiconductor layer (22) is electrically connected to the second contact surface (52) of the support (5); and f) Separating the carrier (5) into a plurality of semiconductor chips (1), each having a plurality of pixels (25), wherein the first contact surface (51) surrounds at least a second contact surface (52) or extends along at least two edges of a second contact surface (52).

Description

[0001] The present application relates to a method for producing a plurality of optoelectronic chips, each having a plurality of pixels, and to such an optoelectronic semiconductor chip.

[0002] Methods for producing a plurality of optoelectronic chips and such an optoelectronic semiconductor chip are already known from the documents US 2008 / 0 029 761 A1, DE 10 2008 062 933 A1, US 2011 / 0 266 579 A1 and US 5 789 766 A.

[0003] When manufacturing display devices based on light-emitting diodes, high demands are placed on alignment accuracy, for example when positioning the radiation-emitting layers relative to a control circuit for the display device.

[0004] One object is to provide a method by which optoelectronic semiconductor chips, each having a plurality of pixels, can be manufactured in a simple and reliable manner. Furthermore, an optoelectronic semiconductor chip is to be provided that is characterized by good controllability of the individual pixels.

[0005] This object is achieved, inter alia, by a method or by an optoelectronic semiconductor chip according to the independent patent claims.

[0006] Embodiments and further developments are the subject of the dependent patent claims.

[0007] The method involves producing a plurality of optoelectronic semiconductor chips, each having a plurality of pixels.

[0008] In one step of the method, a semiconductor layer sequence is provided with an active region provided for generating and / or detecting radiation, which is formed between a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is expediently different from the second semiconductor layer in terms of conductivity type. For example, the first semiconductor layer is p-conductive and the second semiconductor layer is n-conductive, or vice versa. For example, the semiconductor layer sequence is provided for generating and / or detecting radiation in the infrared, visible, or ultraviolet spectral range.

[0009] In a further step of the method, a carrier with a plurality of first connection areas is provided. Furthermore, the carrier can have at least one second connection area. A control circuit for controlling the pixels of the finished semiconductor chip is preferably integrated into the carrier. During operation of the finished semiconductor chip, charge carriers can be injected into the active region from opposite sides of the active region via the first connection area assigned to the pixel and the second connection area, where they can recombine while emitting radiation. In the case of a radiation receiver, charge carriers generated in the active region by radiation absorption can be removed from the active region.The control circuit is preferably designed as an active matrix circuit so that each pixel can be controlled individually and several pixels, in particular all pixels, can be operated simultaneously.

[0010] In a further step of the method, the semiconductor layer sequence is attached to the carrier. The first semiconductor layer is electrically conductively connected to the first connection pads. Preferably, the first semiconductor layer extends continuously over a plurality of first connection pads, in particular over the entire surface of all first connection pads. The first semiconductor layer can therefore be attached to the carrier in an unstructured form. In particular, after being attached to the carrier, the first semiconductor layer can electrically conductively connect at least a first connection pad and a second connection pad. The electrical separation of the connection pads required for operation takes place at a later stage of the method.

[0011] In a further step of the method, separation trenches are formed in the semiconductor layer sequence to form the pixels, with the separation trenches extending through the semiconductor layer sequence. For example, the separation trenches can completely separate the semiconductor layer sequence in the vertical direction. The vertical direction is a direction that runs perpendicular to a main extension plane of the semiconductor layers of the semiconductor layer sequence. For example, the separation trenches are formed using wet-chemical etching or dry-chemical etching.

[0012] According to at least one embodiment of the method, the separation trenches are formed after the semiconductor layer sequence has already been attached to the carrier. The pixels are thus only defined after the semiconductor layer sequence has been attached to the carrier. In particular, the pixels are only formed after at least one semiconductor layer of the semiconductor layer sequence has already been electrically connected to the first connection area of ​​the carrier and, in particular, to the control circuit integrated into the carrier.

[0013] In a further step of the method, a contact layer is formed. The contact layer electrically connects the second semiconductor layer to the second connection area of ​​the carrier. The carrier has, in particular, at least one second connection area for each semiconductor chip. For example, the carrier has a second connection area for each pixel.

[0014] In a further step of the method, the carrier is singulated into a plurality of semiconductor chips, each of which has a plurality of pixels. The singulation of the carrier into semiconductor chips is advantageously carried out after the semiconductor layer sequence has already been attached to the carrier and electrically connected to the carrier by means of the contact layer.

[0015] In at least one embodiment of the method, a semiconductor layer sequence is provided with an active region provided for generating and / or detecting radiation, which region is formed between a first semiconductor layer and a second semiconductor layer. A carrier with a plurality of first connection pads is provided. The semiconductor layer sequence is attached to the carrier such that the first semiconductor layer is electrically conductively connected to the first connection pads. To form the pixels, separating trenches are formed in the semiconductor layer sequence attached to the carrier, wherein the separating trenches extend through the semiconductor layer sequence. A contact layer is formed, which electrically conductively connects the second semiconductor layer to a second connection pad of the carrier. The carrier is singulated into the plurality of semiconductor chips, each having a plurality of pixels.In particular, the semiconductor chips are manufactured in a wafer assembly and the wafer assembly is divided in the singulation step.

[0016] The attachment of the semiconductor layer sequence to the carrier, the formation of the isolation trenches, the formation of the contact layer, and the separation of the carrier preferably occur in the specified order. The isolation trenches are therefore only formed after the semiconductor layer sequence has already been attached to the carrier. A finely adjusted positioning of already formed pixels of a semiconductor layer sequence relative to the associated connection surfaces of a carrier can therefore be dispensed with. "Finely adjusted" is understood in particular to mean that the maximum deviation in the positioning accuracy is at most as large, preferably at most half as large, as the center-to-center distance between two adjacent pixels.

[0017] According to at least one embodiment of the method, the semiconductor layer sequence is free of recesses during attachment to the carrier, at least in the region from which the semiconductor chips emerge. In other words, the semiconductor layer sequence is unstructured in the lateral direction, i.e., in a direction running along the main extension plane of the semiconductor layers of the semiconductor layer sequence. In particular, no photolithographic step for removing material from the semiconductor layer sequence for forming separation trenches between the pixels is performed before the semiconductor layer sequence is attached to the carrier.

[0018] According to at least one embodiment of the method, an alignment is performed during the formation of the separation trenches relative to alignment marks formed on the carrier. For example, a mask for photolithography to define the separation trenches on the side of the semiconductor layer sequence facing away from the carrier can be positioned relative to the alignment marks. This simplifies the finely aligned formation of the pixels relative to the corresponding connection areas of the carrier.

[0019] According to at least one embodiment of the method, the semiconductor layer sequence is provided with a metallic intermediate layer before being attached to the carrier. The metallic intermediate layer can be single-layered or multi-layered. The metallic intermediate layer is, in particular, directly adjacent to the semiconductor layer sequence. For example, the metallic intermediate layer is applied to the prefabricated semiconductor layer sequence by vapor deposition or sputtering.

[0020] According to at least one embodiment of the method, the metallic interlayer is severed after the semiconductor layer sequence has been attached to the carrier and before the carrier is separated into the semiconductor chips. In particular, the metallic interlayer is severed in the region of the separation trenches, so that adjacent pixels are not electrically connected to one another via the metallic interlayer. Alternatively or additionally, the metallic intermediate layer is severed in the area of ​​the second connection surfaces. The contact layer can be applied in the area of ​​the second connection surfaces thus exposed.

[0021] According to at least one embodiment of the method, alignment windows are formed in the metallic intermediate layer before the semiconductor layer sequence is attached to the carrier. The alignment windows extend, in particular, completely through the metallic intermediate layer in the vertical direction. A cross-sectional area of ​​the alignment windows is preferably larger than the cross-sectional area of ​​the alignment marks.

[0022] When attaching the semiconductor layer sequence to the carrier, the semiconductor layer sequence is positioned in particular such that the alignment marks on the carrier overlap with the alignment windows. For example, the positioning is carried out such that the alignment marks are each arranged entirely within the alignment windows. The alignment windows allow the alignment marks to be visually detected through the metallic intermediate layer.

[0023] According to at least one embodiment of the method, the semiconductor layer sequence is deposited epitaxially on a growth substrate. For example, the semiconductor layer sequence can be deposited using an MOCVD or MBE process. The growth substrate is removed from the semiconductor layer sequence, in particular before the formation of the separation trenches. For example, the growth substrate is removed after the semiconductor layer sequence has been attached to the carrier and before the formation of the separation trenches in the semiconductor layer sequence. The growth substrate can be removed, for example, mechanically, for example by grinding, lapping, or polishing, and / or chemically, for example by wet-chemical or dry-chemical etching. Alternatively, a laser lift-off (LLO) process can be used.

[0024] The growth substrate and the carrier are preferably matched to each other with regard to their thermal expansion coefficients, i.e., the thermal expansion coefficients differ by no more than 10%. Particularly preferably, the growth substrate and the carrier contain the same material. Silicon is particularly suitable. However, another material can also be used, for example, silicon carbide, gallium arsenide, or sapphire.

[0025] An optoelectronic semiconductor chip comprises a semiconductor layer sequence with an active region provided for generating and / or receiving radiation, which is arranged between a first semiconductor layer and a second semiconductor layer. The semiconductor layer sequence is divided into a plurality of pixels.

[0026] The semiconductor chip comprises a carrier on which the semiconductor layer sequence is arranged and which has a control circuit for the individual pixels. The control circuit is designed, in particular, as an active matrix circuit.

[0027] The carrier has a first connection surface for each pixel, which is electrically conductively connected to the first semiconductor layer of the pixels.

[0028] The second semiconductor layer is electrically connected to a second connection surface of the carrier via a contact layer. The contact layer covers at least part of a radiation passage surface of the semiconductor layer sequence facing away from the carrier.

[0029] In at least one embodiment of the semiconductor chip, the semiconductor chip has a semiconductor layer sequence which has an active region provided for generating and / or receiving radiation, wherein the active region is arranged between a first semiconductor layer and a second semiconductor layer. The semiconductor layer sequence is divided into a plurality of pixels. The semiconductor chip has a carrier on which the semiconductor layer sequence is arranged and which has a control circuit for the individual pixels. For each pixel, the carrier has a first connection area which is electrically conductively connected to the first semiconductor layer of the pixels. The second semiconductor layer is electrically conductively connected to a second connection area via a contact layer, wherein the contact layer at least partially covers a radiation passage area facing away from the carrier.

[0030] According to at least one embodiment of the semiconductor chip, the pixels of the semiconductor layer sequence taper in the vertical direction, at least in some regions, with increasing distance from the carrier. The base area of ​​the pixels facing the carrier is thus larger than the base area of ​​the radiation passage area. Pixels with such a shape can be produced during manufacture by forming separation trenches using wet-chemical etching after the semiconductor layer sequence has already been attached to the carrier. However, another method, for example, a dry-chemical etching method or mechanical back-sputtering, can also be used.

[0031] According to at least one embodiment of the semiconductor chip, the second semiconductor layer of each pixel is electrically connected via the contact layer to at least one second connection area assigned to the pixel. Each pixel is thus assigned a first connection area and a second connection area, so that the pixels can be electrically contacted completely independently of one another.

[0032] According to at least one embodiment of the semiconductor chip, the first connection area surrounds the at least one second connection area. For example, the first connection area is frame-shaped. Two or more second connection areas can also be assigned to each pixel.

[0033] According to at least one embodiment of the semiconductor chip, the at least one second connection pad is arranged in an edge region or in a corner region of the first connection pad. This means that the first connection pad has an indentation on at least one side surface or in at least one corner, in which the first connection pad is at a greater distance from the edge of the pixel than at at least one other location on the first connection pad.

[0034] According to at least one embodiment of the semiconductor chip, the first connection area extends at least along two edges of the second connection area. In particular, the first connection area can completely surround the second connection area. A connection area extending along two edges can, for example, be L-shaped.

[0035] Each pixel has at least one recess in the semiconductor layer sequence. The contact layer extends from the second connection area through the recess to the second semiconductor layer. The recess thus serves to electrically contact the second semiconductor layer. In particular, the contact layer is routed over a side surface of the recess.

[0036] According to at least one embodiment of the semiconductor chip, the second semiconductor layers of at least two adjacent pixels are electrically connected to one another via the contact layer. In particular, the contact layer can form a common contact layer for all pixels. The contact layer or at least a partial layer of the contact layer can completely cover the pixels. Alternatively, the contact layer can also have a radiation window on the radiation passage surfaces of the pixels, through which the radiation to be generated or received during operation passes.

[0037] The pixels are separated from each other by separation trenches, with the contact layer running partially within the separation trenches. The contact layer can be made radiation-opaque, particularly in the separation trenches.

[0038] According to at least one embodiment of the semiconductor chip, the contact layer comprises a metallic layer extending in a grid-like manner within the separation trenches. A surface of the metallic layer in the separation trenches facing away from the carrier can be formed between the carrier and the radiation passage area. Alternatively, the metallic layer can project vertically beyond the semiconductor layer sequence and be arranged on the radiation passage area of ​​the pixels.

[0039] According to at least one embodiment of the semiconductor chip, the contact layer comprises a TCO material. TCO materials are transparent conductive oxides, for example, indium tin oxide (ITO), tin oxide (SnO), or zinc oxide (ZnO). Such a contact layer can cover the radiation passage surfaces of the pixels over a large area or even completely.

[0040] The method described above is particularly suitable for producing the semiconductor chip described. Features mentioned in connection with the method can therefore also be applied to the semiconductor chip, and vice versa.

[0041] Further features, embodiments and expediencies emerge from the following description of the embodiments in conjunction with the figures.

[0042] They show: Fig. 1A to 1K show a first exemplary embodiment of a method for producing optoelectronic semiconductor chips using intermediate steps, shown in a schematic sectional view ( Fig. 1A, 1B and 1F to 1K) and in supervision ( Fig. 1C to 1E); Fig. 2A to 2C show a second embodiment of a method based on intermediate steps shown schematically in sectional view; Fig. 3A and Fig. 3B shows a third embodiment of a method for producing optoelectronic semiconductor chips; and Fig. 4A to 4C and 5A to 5C each show examples of the design of the connection surfaces on the carrier.

[0043] Identical, similar or similarly acting elements are provided with the same reference symbols in the figures.

[0044] The figures and the proportions of the elements depicted in the figures are not to be considered to scale. Rather, individual elements may be exaggerated for clarity and / or clarity.

[0045] As in Fig. As shown in Figure 1A, a semiconductor layer sequence 2 is provided, wherein an active region 20 is formed between a p-conducting first semiconductor layer 21 and an n-conducting second semiconductor layer 22, which is provided for receiving and / or generating radiation. The active region can be formed, for example, as a pn junction or as a multi-quantum well (MQW) structure.

[0046] The semiconductor layer sequence 2, in particular the active region 20, preferably contains a III-V compound semiconductor material. The semiconductor layer sequence can, of course, also be inverted with respect to conduction type, i.e., the first semiconductor layer can be n-conducting and the second semiconductor layer p-conducting. The first semiconductor layer, the second semiconductor layer, and the active region can each be multilayered. This is not explicitly shown for the sake of simplicity. The semiconductor layer sequence is preferably deposited epitaxially, for example, using MOCVD or MBE, on a growth substrate 23.

[0047] After completion of the epitaxy, a metallic intermediate layer is deposited on the side of the semiconductor layer sequence 2 facing away from the growth substrate 23, for example by means of vapor deposition or sputtering ( Fig. 1B). In the exemplary embodiment shown, the metallic intermediate layer is formed in multiple layers and, for example, has a mirror layer 31 facing the semiconductor layer sequence 2, a barrier layer 32, and a connection metallization 33. For example, a layer that contains silver or consists of silver is suitable as a mirror layer. A layer of titanium tungsten nitride, for example, is suitable as a barrier layer. Gold, for example, is suitable for the connection metallization. However, other materials can also be used; for example, rhodium is also characterized by high reflectivity in the visible spectral range. In this case, the barrier layer 32 can also be omitted.

[0048] The structure of the metallic intermediate layer can be varied within wide limits with regard to layer sequences, layer thicknesses, and materials. For example, a layer containing a TCO material can be formed in the metallic intermediate layer 3 or between the semiconductor layer sequence 2 and the metallic intermediate layer 3.

[0049] The metallic intermediate layer 3 is formed in such a way that it has adjustment windows 35 ( Fig. 1C). The adjustment windows extend vertically completely through the metallic intermediate layer.

[0050] As in Fig. 1F, the semiconductor layer sequence 2 is attached to a carrier 5 with the metallic intermediate layer 3. The attachment is preferably carried out by means of a connecting layer, such as a solder layer or an electrically conductive adhesive layer (in Fig. 1F not explicitly shown).

[0051] A control circuit for the individual pixels is integrated into the carrier, such as an active matrix control circuit. The control circuit can be implemented in the carrier, for example, using CMOS technology. For simplified illustration, only a plurality of first connection areas 51 and second connection areas 52 are shown in the figures. In the exemplary embodiment shown, exactly one first connection area 51 and one second connection area 52 are provided for each pixel 25. The first connection area 51 surrounds the second connection area 52 in a frame-like manner. In the Fig. At the stage shown in Figure 1F, the first semiconductor layer 21 is electrically connected to both the first connection pads 51 and the second connection pads 52. The first semiconductor layer thus connects the first connection pads to the second connection pads. Electrical separation only occurs at a later stage of production.

[0052] As in Fig. As shown in Figure 1D, the carrier has a plan view of a plurality of chip regions 56 arranged side by side. The chip regions are each provided for a finished semiconductor chip. Each chip region 56 has first connection pads 51 and second connection pads 52 corresponding to the number of pixels of each semiconductor chip. To increase reflectivity, the connection pads, in particular the second connection pads 52, can be provided with a coating. Rhodium, for example, is suitable for this purpose due to its high reflectivity in the visible spectral range.

[0053] Additionally, alignment marks 55 are formed on the carrier 5. The lateral extent of the alignment marks is smaller than the pitch in which the semiconductor chips are arranged, so that for each alignment mark 55, only one semiconductor chip is lost during production. However, the alignment marks can also be larger than the pitch in which the semiconductor chips are arranged. Of course, it is also conceivable to arrange the alignment marks in the edge region of the carrier so that no area usable for semiconductor chips is lost.

[0054] It is advisable that the center distances between adjacent alignment marks are equal to the center distances between the corresponding alignment windows 35.

[0055] When attaching the semiconductor layer sequence 2 to the carrier 5, the alignment windows 35 and the alignment marks 55 are positioned relative to one another such that the alignment marks 55 overlap with the alignment windows 35 and are preferably arranged completely within the alignment windows ( Fig. 1E). During this alignment step, the semiconductor layer sequence 2 is still completely unstructured laterally, so the requirements for alignment accuracy are comparatively low. In particular, the alignment tolerance during positioning can also be greater than the center-to-center distance between adjacent pixels. The required alignment accuracy is essentially determined by the size of the alignment windows 35. The requirements for alignment accuracy are particularly low when the alignment windows are significantly larger than the alignment marks.

[0056] After attaching the semiconductor layer sequence 2 to the carrier 5, the growth substrate 23 is formed as shown in Fig. 1G. In the case of a nitride compound semiconductor material, such as Al x In y Ga 1-x-y For semiconductor layer sequences 2 based on N with 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1, sapphire or silicon, for example, are suitable as growth substrates. A mechanical process, such as grinding, lapping, or polishing, and / or a chemical process, such as wet or dry chemical etching, are suitable for removing the growth substrate. Depending on the material of the growth substrate, for example, in the case of a sapphire growth substrate, a laser detachment process is also suitable.

[0057] Deviating from the described embodiment, the growth substrate 23 can also be removed before the semiconductor layer sequence 2 is attached to the carrier 5. In this case, the semiconductor layer sequence is preferably attached to an auxiliary carrier before being attached to the carrier 5, which auxiliary carrier is removed after the semiconductor layer sequence 2 has been attached to the carrier 5.

[0058] A radiation passage surface 24 of the semiconductor layer sequence 2 facing away from the carrier 5 is, as in Fig. 1H, is provided with a roughening 26. For example, a wet-chemical etching process, such as using KOH, is suitable for forming pyramidal or truncated pyramid-shaped depressions in the second semiconductor layer 22. The roughening serves to improve radiation extraction in the case of a radiation-emitting semiconductor chip or to improve radiation coupling in the case of a radiation-receiving semiconductor chip. The roughening can be carried out over the entire surface of the semiconductor layer sequence 2. A photolithographic process is therefore not required for this.

[0059] As in Fig. As shown in Figure 1I, separation trenches 27 are formed in the semiconductor layer sequence 2, which define the individual pixels 25 of the semiconductor chips 1. The separation trenches preferably extend completely in the vertical direction through the semiconductor layer sequence 2 and the metallic intermediate layer 3. The first connection areas 51 of the adjacently arranged pixels, which are connected to one another via the metallic intermediate layer 3 before the formation of the separation trenches 27, are electrically insulated from one another by the formation of the separation trenches 27.

[0060] In the same process step, recesses 28 are formed, which also extend through the semiconductor layer sequence 2 and the intermediate layers 3. The second connection pads 52 are exposed in the region of the recesses 28. Additionally, chip trenches 29 are formed in this manufacturing step, which separate the semiconductor layer sequences of the subsequent individual semiconductor chips from one another. This ensures that during the subsequent singulation of the semiconductor chips, only the material of the carrier 5 needs to be severed. The formation of the individual pixels by forming the separation trenches 27 is carried out using a photolithographic process in which the alignment takes place relative to the alignment marks 55 on the carrier 5. This step is the first finely adjusted photolithographic step of the process. The alignment tolerance is preferably at most half the center-to-center distance between two adjacent pixels 25.

[0061] In the area of ​​the separation trenches 27, the material of the semiconductor layer sequence 2 is preferably removed using a wet-chemical process. This creates inclined side flanks, so that the cross-section of the pixels 25 decreases in the vertical direction, at least in some regions, with increasing distance from the carrier 5. However, another process, such as a dry-chemical etching process or mechanical back-sputtering, can also be used to form the separation trenches.

[0062] Subsequently, an insulation layer 4 is applied over the entire surface of the semiconductor layer sequence 2. As in Fig. As shown in FIG. 1J, the insulation layer 4 is patterned using a second finely adjusted photolithographic process. The patterned insulation layer has a connection opening 41 in which the second connection area 52 is exposed. Furthermore, the insulation layer 4 has at least one contact opening 42 for each pixel 25, in which the second semiconductor layer 22 is exposed.

[0063] Furthermore, the insulation layer 4 has a trench opening 43. The material of the carrier 5 is exposed in this trench opening for singulating the semiconductor chips. Suitable materials for the insulation layer include, for example, an oxide, such as silicon oxide or titanium oxide, a nitride, such as silicon nitride, or an oxynitride, such as silicon oxynitride. The insulation layer 4 serves in particular as a dielectric encapsulation to protect the semiconductor layer sequence 2 and the metallic intermediate layer 3 from moisture. For example, this can prevent the degradation of a silver-containing mirror layer.

[0064] As in Fig. 1K, a contact layer 6 is formed, which electrically conductively connects the second connection surface 52 in the region of the contact opening 42 to the second semiconductor layer 22. The contact layer 6 partially covers the radiation passage area 24. On the side flanks of the recess 28, in particular at the level of the active region 20, the insulation layer 4 is arranged between the contact layer 6 and the semiconductor layer sequence 2 to prevent an electrical short circuit. A TCO material, such as ITO, ZnO, or SnO2, is particularly suitable for the contact layer 6. In this way, shading of the radiation passage area 24 can be avoided. Alternatively or additionally, a metal can also be used for the contact layer 6. The structuring of the contact layer 6 takes place using a third finely adjusted photolithographic process.

[0065] Subsequently, the wafer assembly with carrier 5 and semiconductor layer sequence 2 is singulated into individual semiconductor chips 1 along the chip trenches 29. For this purpose, a singulation trench 57 is formed, which completely separates the carrier. Suitable methods for singulation include, for example, a sawing process or a laser separation process.

[0066] With the described method, semiconductor chips can be produced using only three finely adjusted photolithography processes, each of which has a plurality of pixels, wherein the pixels can each be individually contacted and controlled by means of an active matrix circuit.

[0067] In particular, a complex and error-prone fine adjustment of a semiconductor layer sequence already pre-structured into pixels relative to a carrier with a control circuit is not required. Contrary to the usual procedure, when attaching the semiconductor layer sequence 2 via the first semiconductor layer 21, an inherently undesirable electrically conductive connection is created between the first connection pad 51 and the second connection pad 52. The electrical isolation required for operation only occurs after attachment to the carrier. Furthermore, all finely adjusted manufacturing steps can be performed after the semiconductor layer sequence 2 has already been attached to the carrier 5.

[0068] The semiconductor chip 1 completed by the dicing is in Fig. 1K is shown in a section. The semiconductor chip is suitable, for example, for a display device, an adaptive headlight system, or a photo light for a mobile device or camera.

[0069] In the illustrated embodiment, the second connection area 52 is arranged centrally within the first connection area 51. With a central arrangement of the second connection area, a uniform current supply to the second semiconductor layer 22 can be achieved in a simple manner.

[0070] Alternative designs of the first connection surface 51 and the second connection surface 52 are shown in the Fig. 4A to 4C and 5A to 5C. In the Fig. In the embodiment illustrated in Figure 4A, each pixel 25 has a plurality of second connection areas 52. The second connection areas 52 can thus be reduced in cross-section compared to a single connection area. Compared to a single central contact area, this reduces the risk of a disturbing dark area appearing in the center of the pixels. Such a dark area can be particularly disturbing if an imaging optics system is arranged downstream of the semiconductor chip 1 in the emission direction.

[0071] In the Fig. In the embodiment shown in Figure 4B, the second connection surface 52 is arranged in an edge region 511 of the first connection surface 51. In this configuration, a darker region only occurs at one edge of the pixel 25. However, this can lead to a comparatively uneven current supply to the pixels 25 in the lateral direction.

[0072] To avoid uneven current supply, the Fig. In the embodiment shown in Figure 4C, the second connection surfaces 52 are each arranged in the corner regions 512 of the first connection surface 51. However, it may also be sufficient if a second connection surface 52 is not provided in all corner regions, for example, only in one corner or only in two corners.

[0073] At the Fig. In the variant shown in Figure 5A, the second contact surface 52 surrounds the first contact surface 51 along its entire circumference. This allows for homogeneous current distribution without a darker center region of the pixels 25. However, this design requires particularly high alignment accuracy and a particularly high degree of structural fidelity.

[0074] These requirements can be reduced if the second connection surface 52 does not run along all edges of the first connection surface 51. In Fig. 5B, the second connection surface 52 is L-shaped and runs along second edges of the first connection surface 51. In the embodiment according to Fig. 5C, the first connection surface 51 and the second connection surface 52 are arranged next to each other, so that the second connection surface runs only along one edge of the first connection surface.

[0075] A second and third embodiment of a method for producing optoelectronic semiconductor chips is described in the Fig. 2A to 2C and 3A and 3B, respectively, are shown using intermediate steps shown schematically in sectional view. These two further embodiments differ from the first embodiment essentially in the type of contacting of the second semiconductor layer 22.

[0076] In particular, the fastening of the semiconductor layer sequence 2 to the carrier 5 can be carried out as described in connection with the Fig. 1H to 1I. The carrier 5 differs in the further embodiments only in that each semiconductor chip 1 has only one second connection area 52, which is electrically conductively connected to all pixels 25.

[0077] For this purpose, as in Fig. 2A, a contact layer 6 is applied over the entire surface of the semiconductor layer sequence 2. On the radiation passage surface 24, the contact layer borders at least partially on the radiation passage surface 24 and is electrically conductively connected to the second semiconductor layer 22. As shown in Fig. As shown in Figure 2B, the contact layer 6 is structured so that a trench opening 63 of the contact layer is formed at the location where the semiconductor chips will later be singulated. To improve the transverse conductivity of the contact layer 6, a metallic layer 61 is formed in the separating trenches 27 between adjacent pixels. Furthermore, the metallic layer can also extend along the edge regions of the semiconductor chips. A surface 610 of the metallic layer 61 facing away from the carrier 5 extends vertically between the carrier 5 and the radiation passage area 24.

[0078] The metallic layer 21 therefore does not cover the radiation passage area 24. In addition to the improved transverse conductivity, the metallic layer 61 in the separation trenches 27 between the pixels 25 can reduce optical crosstalk between the pixels.

[0079] The separation of the semiconductor chips can be carried out as described in connection with the first embodiment. A finished semiconductor chip 1 is shown in Fig. 2C shown.

[0080] The Fig. 3A and Fig. The third exemplary embodiment shown in Figure 3B also has a common contact layer 6 for all pixels 25 of a semiconductor chip 1. In contrast to the second exemplary embodiment, the contact layer 6 is formed as a single layer, a metallic layer. For radiation extraction, the contact layer 6 has a radiation window 62 on each of the radiation passage surfaces 24 of the semiconductor chips. In the region of the radiation window, the radiation passage surface 24 is thus free of metallic material, so that the radiation windows define the region of the pixels from which the radiation generated during operation emerges or into which the radiation to be detected enters. A finished semiconductor chip according to the third exemplary embodiment is shown in Fig. 3B shown.

Claims

[1] Method for producing a plurality of optoelectronic semiconductor chips (1), each having a plurality of pixels (25), comprising the steps: a) providing a semiconductor layer sequence (2) with an active region (20) provided for generating and / or detecting radiation, which is formed between a first semiconductor layer (21) and a second semiconductor layer (22); b) providing a carrier (5) having a plurality of first connection surfaces (51); c) attaching the semiconductor layer sequence (2) to the carrier (5) so that the first semiconductor layer (21) is electrically conductively connected to the first connection surfaces (51); d) forming separation trenches (27) in the semiconductor layer sequence (2) attached to the carrier (5) for forming the pixels (25), the separation trenches (27) extending through the semiconductor layer sequence (2); e) forming a contact layer (6), wherein each pixel (25) has at least one recess (28) in the semiconductor layer sequence (2) and the contact layer (6) extends from a second connection surface (52) through the recess (28) to the second semiconductor layer (22), and the second semiconductor layer (22) is electrically conductively connected to the second connection surface (52) of the carrier (5); and f) separating the carrier (5) into the plurality of semiconductor chips (1), each having a plurality of pixels (25), wherein the first connection surface (51) surrounds at least one second connection surface (52) or runs along at least two edges of a second connection surface (52). [2] Method according to claim 1, wherein the semiconductor layer sequence (2) in step c) is free of recesses in the region of the semiconductor chips (1). [3] Method according to one of the preceding claims, wherein an adjustment is carried out during the formation of the separating trenches (27) relative to adjustment marks (55) formed on the carrier (5). [4] Method according to one of the preceding claims, wherein the semiconductor layer sequence (2) is provided with a metallic intermediate layer (3) before step c). [5] Method according to claim 4, wherein the metallic intermediate layer (3) is severed between step c) and step f). [6] Method according to claim 1 or 2, wherein -the semiconductor layer sequence (2) is provided with a metallic intermediate layer (3) before step c); - adjustment windows (35) are formed in the metallic intermediate layer (3) before step c); and - the semiconductor layer sequence (2) is positioned relative to the carrier (5) in step c) such that alignment marks (55) on the carrier (5) overlap with the alignment windows (35). [7] Method according to one of the preceding claims, wherein the semiconductor layer sequence (2) is deposited epitaxially on a growth substrate (23) and the growth substrate (23) is removed before step d). [8] Optoelectronic semiconductor chip (1) with a semiconductor layer sequence (2) which has an active region (20) provided for generating and / or receiving radiation, which is arranged between a first semiconductor layer (21) and a second semiconductor layer (22), wherein - the semiconductor layer sequence (2) is divided into a plurality of pixels (25); - the semiconductor chip (1) has a carrier (5) on which the semiconductor layer sequence (2) is arranged and which has a control circuit for the individual pixels (25); - the carrier (5) has a first connection surface (51) for each pixel (25) which is electrically conductively connected to the first semiconductor layer (21) of the pixels (25); - the second semiconductor layer (22) is electrically conductively connected to a second connection surface (52) via a contact layer (6), wherein the contact layer (6) covers at least partially a radiation passage surface (24) facing away from the carrier (5); - the first connection surface (21) surrounds the second connection surface (22) or runs along at least two edges of the second connection surface (52), - each pixel (25) has at least one recess (28) in the semiconductor layer sequence (2) and the contact layer (6) extends from the second connection surface (52) through the recess (28) to the second semiconductor layer (22), and - the pixels (25) are separated from each other by separating trenches (27). [9] Semiconductor chip (1) according to claim 8, wherein the pixels (25) of the semiconductor layer sequence (2) taper at least in regions with increasing distance from the carrier (5). [10] Semiconductor chip (1) according to claim 8 or 9, wherein the second semiconductor layer (22) of each pixel (25) is electrically conductively connected via the contact layer (6) to at least one second connection surface (52) assigned to the pixel (25). [11] Semiconductor chip (1) according to claim 8 or 9, wherein the second semiconductor layers (22) of at least two adjacent pixels (25) are electrically conductively connected to one another via the contact layer (6). [12] Semiconductor chip (1) according to one of claims 8 to 11, wherein the contact layer (6) extends partially in the separating trenches (27). [13] Semiconductor chip (1) according to claim 12, wherein the contact layer (6) comprises a metallic layer (61) which runs in a grid-like manner in the separating trenches (27). [14] Semiconductor chip (1) according to one of claims 8 to 13, wherein the contact layer (6) comprises a TCO material. [15] Optoelectronic semiconductor chip (1) according to one of claims 8 to 13, which is manufactured according to one of claims 1 to 7.

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