Performance module

Abstract

Performance module, which includes: a base plate (101); a first semiconductor chip (11; 21) having four edges, wherein the first semiconductor chip (11; 21) is soldered to the base plate (101); a second semiconductor chip (12; 22) having four edges, one of the four edges being adjacent to a first edge of the first semiconductor chip (11; 21), the second semiconductor chip (12; 22) being soldered to the base plate (101); and a third semiconductor chip (13; 23) having four edges, one of the four edges being adjacent to a second edge of the first semiconductor chip (11; 21), the third semiconductor chip (13; 23) being soldered to the base plate (101), wherein a third edge or a fourth edge of the first semiconductor chip (11; 21) is arranged adjacent to an associated lateral end (E1; E2; E4) of the base plate (101) or a third edge and a fourth edge of the first semiconductor chip (11; 21) are each arranged adjacent to an associated lateral end (E1, E2; E4, E2) of the base plate (101), and at half a distance (a / 2) from the first edge of the first semiconductor chip (11; 21) to one edge of the second semiconductor chip (12; 22), at half a distance (b / 2) from the second edge of the first semiconductor chip (11; 21) to one edge of the third semiconductor chip (13; 23), and at a distance (c; d) from the third edge or from the fourth edge of the first semiconductor chip (11; 21), which is adjacent to the associated lateral end (E1; E2; E4) of the base plate (101), to the associated lateral end (E1; E2; E4) of the base plate (101) of solder fillets (51a, 51b, 51c; 51a, 51b, 51d) formed on these edges of the first semiconductor chip (11; 21), the length (I) of a solder fillet under these solder fillets (51a, 51b, 51c; 51a, 51b, 51d), which is formed on an edge of the first semiconductor chip (11; 21) at a shorter distance, is formed in a shorter length and the length (I) of the solder fillet under these solder fillets (51a, 51b, 51c;51a, 51b, 51d), which is formed on the edge of the first semiconductor chip (11; 21) at the shortest distance, is formed in the shortest length.;

Description

Technical area

[0001] The present invention relates to a power module provided with a power semiconductor chip. State of the art

[0002] Vehicles such as hybrid vehicles, plug-in hybrid vehicles, and electric vehicles are equipped with a rechargeable high-voltage power battery and a converter that converts the DC output of the rechargeable high-voltage battery into AC high-voltage output to drive a motor and other devices. The converter contains a power module with a built-in power semiconductor chip.

[0003] A power module is a structure in which a semiconductor chip is mounted between a pair of circuit boards thermally coupled with a heat dissipation plate. A power module is also known that also uses a circuit board as a heat dissipation plate. The semiconductor chip has one surface and another surface opposite to one surface. The one surface and the other surface of the semiconductor chip are respectively soldered to one or the other of a pair of circuit boards, with the semiconductor chip sandwiched between the pair of circuit boards. To achieve high packaging density, sometimes multiple semiconductor chips are mounted between a pair of circuit boards. The area around the semiconductor chip is sometimes filled with a sealing resin (see, for example, Patent Literature 1).

[0004] Patent Literature 2 relates to a ceramic circuit board whose metallization has cuts between the metallization surfaces to which electronic components are attached by solder layers. This limits the flow of the solder layers beyond the side edges of the electronic components.

[0005] Patent Literature 3 relates to a system and method for forming solder joints. The system comprises a substrate having a recess on the bottom of which a conductive pad and a solder pad are arranged, the solder pad having a greater width than the conductive pad. By establishing contact with the conductive pad of a component, the solder pad forms a stretchable solder joint between the conductive pad of the substrate and the conductive pad of the component, forming an inverse meniscus along the circumference of the solder joint.

[0006] Patent Literature 4 relates to a power semiconductor module with a terminal element butt-soldered to a conductor track. Since solders have wetting properties, solder menisci form between the two connecting partners, the terminal element and the conductor track, due to surface tension. Patent Literature 5 relates to a circuit board onto which a component is soldered. The surface tension of the liquid solder enables automatic, passive alignment of the component on the circuit board, simultaneously connecting two corresponding terminals, one on the component and the other on the circuit board.

[0007] Patent Literature 6 relates to a semiconductor device. Patent Literature 7 relates to a structure for attaching a power component to a carrier by soldering. Patent Literature 8 relates to a self-centering electrode for a power device. Patent Literature 9 relates to a method for contacting a semiconductor and a contact structure for a semiconductor. Citation listPatent literature Patent literature 1: JP 2005- 244 166 A Patent literature 2: JP 2003- 100 983 A Patent literature 3: US 2001 / 0 010 323 A1 Patent literature 4: DE 10 2006 058 695 A1 Patent literature 5: DE 197 50 073 A1 Patent literature 6: US 2013 / 0 307 130 A1 Patent literature 7: DE 103 32 695 A1 Patent Literature 8: US 4,935,803 A Patent literature 9: DE 10 2011 086 687 A1 Summary of the inventionTechnical problem

[0008] There is a demand to achieve high packaging density and further reduce the distances between semiconductor chips mounted on a printed circuit board or the distances between the semiconductor chips and the outer edges of the printed circuit board. Conventionally, however, the distances between semiconductor chips and the distances between the semiconductor chips and the outer edges of a printed circuit board were all equal to each other. Thus, even if some of the distances between semiconductor chips and the distances between the semiconductor chips and the outer edges of the printed circuit board are shorter than a predetermined distance, this brings with it a possibility of causing a short circuit between the semiconductor chips due to solder overflow from the formation regions of solder fillets that connect the semiconductor chip to the printed circuit board, or a possibility of causing solder overflow from the formation regions of solder fillets to the outer edges of the printed circuit board.When solder overflows in the formation areas of the solder fillets from the outer edges of the circuit board, short circuits occur between other elements, or the overflowed solder is peeled off, so that it is a conductive foreign substance, which leads to a factor to cause a failure or a factor to deteriorate the performance. Solution to the problem

[0009] The object is solved by the features of independent patent claim 1. Advantageous developments of the invention are described in the subclaims. Advantageous effects of the invention

[0010] According to the present invention, a short circuit between semiconductor chips or overflow of solder from the lateral end of a base plate due to overflow of solder from solder fillet formation regions can be suppressed. Brief description of the drawings Fig. 1 is a perspective view of the appearance of an embodiment of a power module according to the present invention. Fig. 2 is a cross-sectional view of the power module in Fig. 1, taken along the line II-II in Fig. 1. Fig. 3 is a schematic plan view of a mounting structure of semiconductor chips. Fig. Figure 4 is an enlarged cross-sectional view of area IV in Fig. 2, taken along the line IV-IV in Fig. 3. Fig. 5 shows diagrams for explaining the relationship between the increased amount of the surface area of ​​a solder fillet and the length of a solder fillet formation region; (a) is a cross-sectional view for illustrating the criteria of the soldering structure of a semiconductor chip, and (b) is a typical view of the relationship between the increased amount of the surface area of ​​the solder fillet and the length of the solder fillet formation region. Fig. 6 is a schematic plan view of a second embodiment of the present invention, showing the mounting structure of semiconductor chips provided on a power module. Fig. Figure 7 is a cross-sectional view taken along the line VII-VII in Fig. 6. Fig. 8 is a cross-sectional view of a third embodiment of the present invention, showing the mounting structure of semiconductor chips provided on a power module. Fig. 9 is a cross-sectional view of a fourth embodiment of the present invention, showing the mounting structure of semiconductor chips provided on a power module. Fig. 10 is a schematic plan view of a fifth embodiment of the present invention, showing the mounting structure of semiconductor chips provided on a power module. Fig. 11 is a diagram of an exemplary modification of the fifth embodiment. Fig. 12 is a schematic plan view of a sixth embodiment of the present invention, showing the mounting structure of semiconductor chips provided on a power module. Fig. 13 is a diagram of a first exemplary modification of the sixth embodiment. Fig. 14 is a diagram of a second exemplary modification of the sixth embodiment. Fig. 15 is a schematic plan view of a seventh embodiment of the present invention, showing the mounting structure of semiconductor chips provided on a power module. Fig. 16 is a diagram of an exemplary modification of the seventh embodiment. Fig. 17 is a diagram of a first effect of the present invention, showing the frequency of occurrence of short circuits between semiconductor chips according to the first embodiment of the present invention. Fig. 18 is a diagram of a second effect of the present invention, showing the frequency of occurrence of overflow of solder to the lateral end of a frame according to the second embodiment of the present invention. Description of embodiments

[0011] The invention is explained in more detail below with reference to the figures. First embodiment (overall structure of a power module)

[0012] In the following, with reference to the Fig. 1 to 4, a first embodiment of a power module according to the present invention is described.

[0013] Fig. 1 is a perspective view of the appearance of an embodiment of a power module according to the present invention. Fig. 2 is a cross-sectional view of the power module in Fig. 1, taken along the line II-II in Fig. 1.

[0014] For example, a power module 100 according to the embodiment of the present invention may be used in a device such as an on-vehicle power converter of an electric machine drive system installed on a motor vehicle.

[0015] The power module 100 includes a module housing 201 that houses a plurality of power semiconductor chips 11 to 14, which will be described later, mounted between a first lead frame 101 and a second lead frame 102 (see Fig. 3 and other drawings).

[0016] The module housing 201 is formed of an aluminum alloy material such as Al, AlSi, AlSiC, and Al-C, for example, having a can-like shape seamlessly formed in one piece (hereinafter referred to as a can type). Here, the can type means a container in a nearly rectangular parallelepiped shape with a bottom, the container having an insertion opening 306 on a predetermined one side. The module housing 201 has a structure that has no openings other than the insertion opening 306. The outer edge of the insertion opening 306 is surrounded by a flange 304B.

[0017] A metal housing in such a shape is formed. Thus, even though the module housing 201 is inserted into a passage through which a cooling medium such as water and oil flows, sealing against the cooling medium can be ensured by the flange 304B. In other words, with a simple configuration, the cooling medium can be prevented from entering the interior and the connecting portion of the module housing 201.

[0018] The shape of the module housing 201 below the flange 304B is a thin rectangular parallelepiped shape, which includes a pair of heat dissipation bases 307 on which fins 305 are evenly arranged. A curved portion 304A, whose thickness is extremely thin, is formed at the connecting parts of the heat dissipation bases 307 to the flange 304B. An insulating film 333 of high thermal conductivity is provided between the inner surfaces of the heat dissipation bases 307 and the first and second lead frames 101 and 102. During operation, the power semiconductor chips 11 to 14 generate heat, and their temperature becomes high. In the power module 100 according to the embodiment, heat generated by the semiconductor chips 11 to 14 during operation is dispersed in the first and second lead frames 101 and 102 and conducted to the insulating film 333.The heat is dissipated to a cooling medium by the heat dissipation bases 307 formed on the module case 201 and the fins 305 provided on the heat dissipation bases 307. Thus, high cooling performance can be achieved.

[0019] The semiconductor chips 11 to 14 are mounted between the first and second lead frames 101 and 102 by soldering, and areas around the semiconductor chips 11 to 14 are sealed with a primary sealing material 350. The mounting structure of the semiconductor chips 11 to 14 on the first and second lead frames 101 and 102 will be described later.

[0020] The first lead frame 101 has a plurality of leads 111 extending upward. The end tips of the leads 111 are exposed to the exterior by the primary sealing material 350. In other words, the first lead frame 101 is integrally formed with the primary sealing material 350, with the end tips of the leads 111 exposed. Positive and negative DC electrode terminals 121, an AC terminal 121, and a plurality of external signal terminals 122 are joined to the end tips of the leads 111, for example, by soldering. The positive and negative DC electrode terminals 121, the AC terminal 121, the plurality of external signal terminals 122, and the leads 111 of the first lead frame 101 are integrally formed with an additional molding body 380.

[0021] The primary sealing material 350, which is integrally formed with the first lead frame 101, is housed in the module case 201, and the positive and negative DC electrode terminals 121 and the AC terminal 121 and the plurality of external signal terminals 122, which are integrally formed with an additional molding body 380, are connected to the corresponding leads 111 of the first lead frame 101. In this state, a secondary sealing material 351 is supplied from the insertion opening 306 of the flange 304B. The secondary sealing material 351 is supplied into the inside of the flange 304B and the space between the edges of the first and second lead frames 101 and 102 and the primary sealing material 350. The secondary sealing material 351 is also supplied between the bottom surface of the module case 210 and the lower surface of the primary sealing material 350. The power module 100 has such a structure.The power module 100 converts the power of the DC high-voltage output of a high-voltage rechargeable battery into the power of an AC high-voltage output, for example, to function as a converter for driving a motor. (Assembly structure of semiconductor chips)

[0022] Fig. 3 is a schematic plan view of a mounting structure of the semiconductor chips. Fig. Figure 4 is an enlarged cross-sectional view of area IV in Fig. 2, taken along the line IV-IV in Fig. 3. It is pointed out that in Fig. 3 the semiconductor chips are shown with the second lead frame 102 removed. In Fig. 4 are the components such as the lines 111, which are located on the outside of area IV in Fig. 2 are omitted.

[0023] The first base plate, i.e., the first lead frame 101, and the second base plate, i.e., the second lead frame 102, are formed by stamping a metal plate. Materials such as copper, aluminum, and iron can be used for the metal plate. The first and second lead frames 101 and 102 preferably have high thermal conductivities. Thus, copper and aluminum materials, which have excellent thermal conductivities, are particularly preferable.

[0024] The first and second lead frames 101 and 102 are arranged opposite each other at a distance from each other. Four semiconductor chips 11 to 14 are arranged between the first and second lead frames 101 and 102. As shown in Fig. As shown in Figure 4, four protrusions 103 are formed on the second lead frame 102 opposite the respective semiconductor chips 11 to 14. The four protrusions 103 are arranged in a two-by-two matrix configuration.

[0025] The semiconductor chips 11 to 14 are configured in a thin rectangular parallelepiped shape and, for example, from insulated gate bipolar transistors (IGBTs). The semiconductor chips 11 to 14 may include diodes and passive devices along with IGBTs. The semiconductor chips 11 to 14 have an area f L , which has a lower surface in Fig. 4, and another area f U , which has an upper surface in Fig. 4. On the further surface f U Each of the semiconductor chips 11 to 14, for example, forms the collector electrode of the IGBT. On one side f L Each of the semiconductor chips 11 to 14 has the emitter electrode of the IGBT and several control electrodes. The control electrodes, in Fig. 4 not shown, are connected to the line 111 by bonding wires.

[0026] The one area f LEach of the semiconductor chips 11 to 14 is soldered to a first soldering point 50 on the first lead frame 101. The further area f U Each of the semiconductor chips 11 to 14 is soldered to the protrusion 103 of the second lead frame 102 with a second soldering point 60. The protrusion 103 is formed in a rectangular shape slightly smaller than the sizes of the semiconductor chips 11 to 14 in a plan view. The structure is provided in which the further area f U soldered to the protrusion 103 of the second lead frame 102. Thus, similar to the protrusions 103, the semiconductor chips 11 to 14 are arranged in a two-by-two matrix configuration.

[0027] As the solder materials of the first and second solder joints 50 and 60, in addition to Sn-rich materials, Au, Zn-Al, and Al materials can be used. In addition to the solder materials, materials containing a resin, such as Ag paste, Cu paste, sintered Ag, and sintered Cu, can also be used. Materials containing a resin preferably have a low viscosity.

[0028] The assembly structure of the semiconductor chips used in the Fig. 3 and Fig. 4 is formed, for example, by the following procedures.

[0029] A solder material to be cured as the first solder joint 50 is supplied to the first lead frame 101. A layer solder joint can be used for this solder joint. Alternatively, methods in which a solder paste is formed by printing and in which a molten solder is supplied can also be used. The semiconductor chips 11 to 14 are placed on the solder material to be cured as the first solder joint. A solder material to be cured as the second solder joint 60 is placed on the semiconductor chips 11 to 14. The supply of this solder material can be carried out similarly to the supply of the solder material to be cured as the first solder joint. The projections 103 are aligned with the solder material to be cured as the second solder joint 60, and then the second lead frame 102 is placed on the solder material to be cured as the second solder joint 60.The first and second lead frames 101 and 102 are heated with the second lead frame 102 being pressed against the first lead frame 101 to solder the semiconductor chips 11 to 14 to the first and second lead frames 101 and 102. Thus, the mounting structure of the semiconductor chips 11 to 14 shown in FIGS. Fig. 3 and Fig. 4 is prepared.

[0030] Next, the mounting structure of the semiconductor chips 11 to 14 will be described in more detail. (Soldering structure of the semiconductor chips on the first lead frame)

[0031] As in the Fig. 3 and Fig. As shown in Figure 4, the semiconductor chips 11 to 14 are not arranged in the central portion of the first solder joint 50. The semiconductor chips 11 to 14 are arranged at positions close to the adjacent other semiconductor chips 11 to 14, not in the central portion.

[0032] The distances a to d in Fig. 3 are defined as follows. It is noted that four edges of the first lead frame, ie the lateral ends E1 to E4, are in Fig. 3 are shown.

[0033] A distance between the semiconductor chip 11 and the semiconductor chip 12, that is, a distance between the edges of the semiconductor chip 11 and the semiconductor chip 12 which are opposite to each other, is defined as a; a distance between the semiconductor chip 11 and the semiconductor chip 13, ie, a distance between the edges of the semiconductor chip 11 and the semiconductor chip 13 which are opposite to each other, is defined as b; a distance between the left edge of the semiconductor chip 11 and the left lateral end E1 of the first lead frame 101 is defined as c; and a distance between the upper edge of the semiconductor chip 11 and the upper lateral end E2 of the first lead frame 10 is defined as d.

[0034] A solder fillet 51a of the semiconductor chip 11 and a solder fillet 52a of the semiconductor chip 12 are formed between the semiconductor chip 11 and the semiconductor chip 12. A solder fillet 51b of the first semiconductor chip 11 and a solder fillet 53b of the semiconductor chip 13 are formed between the semiconductor chip 11 and the semiconductor chip 13.

[0035] It is assumed that the length of the solder fillet 51a is equal to the length of the solder fillet 52a, and the length of the solder fillet 51b is equal to the length of the solder fillet 53b. In this case, the lengths of the solder fillets 51a and 52a must be a / 2 or less, and the lengths of the solder fillets 51b and 53b must be b / 2 or less. It is noted that in the present specification, as in Fig. 5(a), the length of the solder fillet is defined as a length l from the edge of the semiconductor chip to the end tip of the solder fillet.

[0036] The semiconductor chips 11 to 14 are arranged at the positions near adjacent other semiconductor chips 11 to 14, not in the center parts of four chip mounting areas that are almost equally divided on the first lead frame 101. Here, the centers of four protrusions 103 of the second lead frame 102 are aligned with the centers of the semiconductor chips 11 to 14 that are not mounted in the centers of the chip mounting areas. The distances a / 2 and b / 2 are shorter than the distances c and d. The shorter the distance between the semiconductor chips or the shorter the distance between the semiconductor chip and the side end of the base plate, the greater the possibility of the semiconductor chips being short-circuited due to the overflow of the solder fillet or the overflow of the solder fillet from the side end of the base plate.

[0037] Therefore, in the semiconductor chips 11 and 12, the lengths of the solder fillets 51a and 52a formed on the edges adjacent to the other semiconductor chips 11 and 12 are formed shorter than the lengths of the solder fillets 51c and 51d formed on two edges of the semiconductor chip 11 adjacent to the lateral ends E1 and E2 of the first lead frame 101. In other words, the lengths of the solder fillets 51c and 51d are formed longer than the lengths of the solder fillets 51a and 52a. Thus, a short circuit between the semiconductor chips 11 and 12 due to the overflow of solder from the formation regions of the solder fillets 51a and 52a can be suppressed.

[0038] Similarly, in the semiconductor chips 11 and 13, the lengths of the solder fillets 51b and 53b formed on the edges adjacent to the other semiconductor chips 11 and 13 are formed shorter than the lengths of the solder fillets 51c and 51d formed on two edges of the semiconductor chip 11 adjacent to the lateral ends E1 and E2 of the first lead frame 101. In other words, the lengths of the solder fillets 51c and 51d are formed longer than the lengths of the solder fillets 51b and 53b. Thus, a short circuit between the semiconductor chips 11 and 13 due to the overflow of solder from the formation regions of the solder fillets 51b and 53b can be suppressed.

[0039] Comparing the distance a with the distance b, the length of the solder fillet formed on the edge at a shorter distance is shortened. For example, in the case where the distance a is shorter than the distance b, the length of the solder fillet 51a is formed shorter than the length of the solder fillet 51b.

[0040] Comparing the distance c with the distance d, the length of the solder fillet formed on the edge at a shorter distance can be formed shorter. For example, in the case where the distance c is shorter than the distance d, the length of the solder fillet 51c can be formed shorter than the length of the solder fillet 51d.

[0041] In one embodiment, the reason why the lengths of the solder fillets 51a, 51b, 52a and 53b may be formed shorter will be described.

[0042] Since surface tension forces act on the surface of a liquid, the surface tension force acts to reduce the surface area, i.e., to reduce the surface energy. Thus, in this case, increasing the surface area requires energy to counteract the surface tension force. The greater the increased surface area of ​​the solder, the more energy is required for this increase.

[0043] Solder overflow during fillet formation is caused by increasing the pressure in the solder, causing the solder to warp in the fillet formation region due to the short length of the fillet formation region relative to a predetermined solder volume. When the volumes of solder used to form fillets are equal, the increased amount of solder surface area varies depending on the length of the fillets.

[0044] The Fig. 5 shows an example of the correlation between the length I of the solder fillet and the increased amount of the surface of the solder. Fig. 5(a) is a cross-sectional view illustrating the criteria of the soldering structure of a semiconductor chip. Fig. 5(b) is a typical view of the relationship between the increased amount of the solder fillet surface and the length of the solder fillet formation region.

[0045] In the soldering structure of the semiconductor chip on the base plate, which is Fig. As shown in Figure 5(a), the chip size is 10 mm square. The thickness t of the solder joint is 0.2 mm.

[0046] The increased amount of the surface of the solder fillet in Fig. Figure 5(b) shows the increased amount of the solder fillet surface area derived in the case where the semiconductor chip is recessed from the solder joint surface by 0.05 mm. The solder joint surface is assumed to curve the solder fillet into an arc shape.

[0047] Fig. 5(b) shows that the longer the length l of the fillet formation region, the smaller the increased surface area. In other words, the shorter the length l of the fillet formation region, the larger the increased surface area of ​​the solder in the fillet. As described above, the larger the increased surface area of ​​the solder, the more energy is required for this enlargement. By utilizing this phenomenon, energy supplied to the solder material having the first solder joint 50, which is melted with the pressing of the semiconductor chip 11 against the first lead frame 101, is dissipated by increasing the surface areas of the fillets 51c and 51d having a long length l of the fillet formation region. Thus, enlargement of the surface areas of the fillets 51a and 51b having a short length l of the fillet formation region, that is, overflow of solder from the fillet formation regions, can be suppressed.

[0048] Referring to Fig. 4, the semiconductor chips 11 to 14 and the protrusions 103 are arranged on the same central portions. In other words, the gaps between four edges of each of the semiconductor chips 11 to 14 and four edges of the protrusion 103 are almost equal. Thus, the second solder joint 60, which joins the semiconductor chips 11 to 14 to the protrusions 103, has a solder fillet 61 formed on four edges of each of the semiconductor chips 11 to 14 of equal length.

[0049] The length of the solder fillet 61 may be formed shorter than the lengths of the solder fillets 51a and 51b. The reason is as follows.

[0050] As described above, the semiconductor chips 11 to 14 are heated, pressure is applied to them, and they are soldered, with the first lead frame 101, the first soldering pad, the semiconductor chips 11 to 14, the second soldering pad 60, and the second lead frame 102 stacked. In other words, during soldering, both the first and second soldering pads 50 and 60 are melted. In this state, the first and second soldering pads 50 and 60 are formed separately from each other. However, the relationship between the amount of enlargement of the surface area of ​​the solder fillet and the length of the solder fillet formation region has the Fig. 5(b). Thus, the energy supplied to the solder material when melting the first and second solder joints 50 and 60 is consumed by increasing the surface areas of the fillets 51c and 51d, which have a long fillet formation region length l, and the surface areas of the fillets 51a and 51b. As a result, an increase in the surface area of ​​the fillet 61, which has a short fillet formation region length l, that is, overflow of solder from the fillet formation regions, can be suppressed.

[0051] It should be noted that the length of the solder fillet 61 is not necessarily shorter than the lengths of the solder fillets 51a and 51b.

[0052] It should be noted that in the above description, the semiconductor chip 11 was described. The semiconductor chips 12 to 14 are the same as in the case of the semiconductor chip 11. In other words, in the semiconductor chips 12 to 14, the lengths of the solder fillets formed on the edges adjacent to the other semiconductor chips 11 to 14 are also formed shorter than the lengths of the solder fillets formed on the edges adjacent to the lateral ends E1 to E4 of the first lead frame 101.

[0053] According to the embodiment, the following effects are exerted. (1) The semiconductor chips 11 to 14 were soldered to the first lead frame 101 with the first solder joint 50. In the semiconductor chips 11 to 14, the lengths of the solder fillets formed on the edges adjacent to the lateral ends E1 to E4 of the first lead frame 101 were made longer than the lengths of the solder fillets formed on the edges adjacent to the other semiconductor chips 11 to 14.

[0054] As a result, in the semiconductor chips 11 to 14, overflow of solder from the formation regions of the solder fillets formed on the edges adjacent to the other semiconductor chips 11 to 14 can be suppressed, and a short circuit between the semiconductor chips 11 to 14 can be prevented. Second embodiment

[0055] Fig. 6 is a schematic plan view of a second embodiment of the present invention, showing the mounting structure of semiconductor chips provided on a power module. Fig. Figure 7 is a cross-sectional view taken along the line VII-VII in Fig. 6. In the second embodiment, the first and second lead frames 101 and 102, the semiconductor chips 11 to 14, and the first and second solder pads 50 and 60 are the same elements as those of the first embodiment. The second embodiment differs from the first embodiment in that the semiconductor chips 11 to 14 are arranged at positions near the corners of the first lead frame 101 and are not arranged in the central part of the first solder pad.

[0056] In other words, assuming that the definitions of the distances a, b, c, and d in the second embodiment are the same as those in the first embodiment, the following configuration is provided.

[0057] The semiconductor chip 11 is used as an example for description. The lengths of the solder fillets 51c and 51d formed on the two edges adjacent to the lateral ends E1 and E2 of the first lead frame 101 are formed shorter than the length of the solder fillet 51a formed on the edge of the semiconductor chip 11 adjacent to the semiconductor chip 12 and the length of a solder fillet 52a formed on the edge of the semiconductor chip 12 adjacent to the semiconductor chip 11. In other words, the lengths of the solder fillets 51a and 52a formed on the semiconductor chips 11 and 12 are formed longer than the lengths of the solder fillets 51c and 51d formed on two edges of the semiconductor chip 11. Thus, the overflow of solder from the formation regions of the solder fillets 51c and 51d to the lateral ends E1 and E2 of the first lead frame 101 is suppressed.

[0058] Similarly, the lengths of the solder fillets 51c and 51d formed on two edges of the semiconductor chip 11 adjacent to the lateral ends E1 and E2 of the first lead frame 101 are formed shorter than the one solder fillet 51b formed on the edge of the semiconductor chip 11 adjacent to the semiconductor chip 13 and the length of one solder fillet 53b formed on the edge of the semiconductor chip 13 adjacent to the semiconductor chip 11. In other words, the lengths of the solder fillets 51b and 53b formed on the semiconductor chips 11 and 13 are formed longer than the lengths of the solder fillets 51c and 51d formed on two edges of the semiconductor chip 11. Thus, the overflow of solder from the formation regions of the solder fillets 51c and 51d to the two lateral ends E1 and E2 of the first lead frame 101 is suppressed.

[0059] Comparing the distance c with the distance d, the length of the solder fillet formed on the edge at a shorter distance is shortened. For example, when the distance c is shorter than the distance d, the length of the solder fillet 51c is formed shorter than the length of the solder fillet 51d.

[0060] Comparing the distance a with the distance b, the length of the solder fillet formed on the edge at a shorter distance can be shortened. For example, if the distance a is shorter than the distance b, the length of the solder fillet 51a is formed shorter than the length of the solder fillet 51b.

[0061] It should be noted that, in the semiconductor chips 12 to 14, the relationship of half the distance a and half the distance b between the edges adjacent to the other semiconductor chips 12 to 14 to the distances c and d from the edges of the semiconductor chips 12 to 14 to the lateral ends E1 to E4 of the first lead frame 101 is similar to the case of the semiconductor chip 11. The lengths of the solder fillets formed on the edges of the semiconductor chips 12 to 14 are similar to the solder fillets formed on the edges of the semiconductor chip 11. In other words, in the semiconductor chips 12 to 14, the lengths of the solder fillets formed on the edges adjacent to the lateral ends E1 to E4 of the first lead frame 101 are also shorter than the lengths of the solder fillets formed on the edges adjacent to the other semiconductor chips 11 to 14.

[0062] According to the second embodiment, the following effect is achieved. (1) The semiconductor chips 11 to 14 were soldered to the first lead frame 101 with the first solder joint 50. In the semiconductor chips 11 to 14, the lengths of the solder fillets formed on the edges adjacent to the other semiconductor chips 11 to 14 were made longer than the lengths of the solder fillets formed on the edges adjacent to the lateral ends of the first lead frame 101. As a result, overflow of solder from the solder fillet formation regions formed on the edges of the semiconductor chips 11 to 14 adjacent to the lateral ends of the first lead frame 101 to the lateral ends of the first lead frame 101 can be suppressed. Third embodiment

[0063] Fig. 8 is a cross-sectional view of a third embodiment of the present invention, showing the mounting structure of semiconductor chips provided on a power module. Fig. 8 is a diagram of an area that Fig. 4 corresponds to the first embodiment of the power module.

[0064] A power module 100 according to the third embodiment differs from the first embodiment in that a recess 102b is formed on an inner surface 102a of a second lead frame 102 opposite a first lead frame 101. The other configurations of the power module 100 according to the third embodiment are similar to those of the first embodiment.

[0065] As described in the first embodiment, the solder fillets 51c and 51d are formed on the edges adjacent to the lateral ends E1 and E2 of the first lead frame 101. The lengths of the solder fillets 51c and 51d are formed longer than the lengths of the solder fillets 51a and 52a formed on the edges adjacent to the other semiconductor chips 11 and 12. Thus, the solder easily overflows from the formation regions of the solder fillets 51c and 51d.

[0066] In the third embodiment, the recess 102b is formed on the inner surface 102a of the second lead frame 102 at a portion where the solder fillets 51c and 52c are opposite to each other. Fig. 8, the lateral ends E1 and E3 of the second lead frame 102 are described. However, the recess 102b is similarly formed on the lateral ends E2 and E4. As described above, when the length of the solder fillet formation region is long, solder easily overflows. Thus, solder overflows from the formation regions of the solder fillets 51c, 52c, 51d, and 52d, which have a long length of the solder fillet formation region, and contacts the second lead frame 102, sometimes causing a short circuit between the first and second lead frames 101 and 102. In the third embodiment, the recess 102b is formed on the second lead frame 102 corresponding to portions where solder easily overflows. As a result, a short circuit between the first and second lead frames 101 and 102 can be prevented.

[0067] The other structures of the third embodiment are the same as those of the first embodiment. Thus, effects similar to effect (1) of the first embodiment are achieved.

[0068] As described above, in the third embodiment, in the solder fillets formed on the edges of the semiconductor chips 11 to 14, the recess 102b is formed on the second lead frame 102 at portions opposite to the solder fillets formed on the edges adjacent to the first lead frame 101, that is, long solder fillets. As a result, even if solder overflows from the formation regions of the long solder fillets, a short circuit between the first and second lead frames 101 and 102 can be prevented. Fourth embodiment

[0069] Fig. 9 is a cross-sectional view of a fourth embodiment of the present invention, showing the mounting structure of semiconductor chips provided on a power module. Fig. 9 is a diagram of an area that Fig. 7 corresponds to the second embodiment of the power module.

[0070] A power module 100 according to the fourth embodiment differs from the second embodiment in that a recess 102c is formed on an inner surface 102a of a second lead frame 102 opposite a first lead frame 101. The other configurations of the power module 100 according to the fourth embodiment are similar to those of the second embodiment.

[0071] As described in the second embodiment, the solder fillets 51a and 52a are formed on the edges of the semiconductor chips 11 and 12 adjacent to the edges of the other semiconductor chips 11 and 12. The lengths of the solder fillets 51a and 52a are formed longer than the lengths of the solder fillets 51c and 51d of the semiconductor chip 11 formed on the edges adjacent to the lateral ends E1 and E2 of the first lead frame 101. Thus, the solder easily overflows from the formation regions of the solder fillets 51a and 52a.

[0072] In the fourth embodiment, the recess 102c is formed on the inner surface 102a of the second lead frame 102 at portions opposite the solder fillets 51a and 52a. In Fig. 9, the solder fillets 51a and 52a between the semiconductor chips 11 and 12 are described. The recess 102c is formed on the portions opposite the solder fillets between the semiconductor chips 11 and 13, the solder fillets between the semiconductor chips 12 and 14, and the solder fillets between the semiconductor chips 13 and 14. As a result, a short circuit between the first and second lead frames 101 and 102 can be prevented, which results from overflow of solder from the formation regions of the solder fillets 51a and 52a, causing the solder to contact the second lead frame 102.

[0073] The other structures of the fourth embodiment are the same as those of the second embodiment. Thus, an effect similar to effect (1) of the second embodiment is achieved.

[0074] As described above, in the fourth embodiment, in the fillets formed on the edges of the semiconductor chips 11 to 14, the recess 102c is formed on the second lead frame 102 opposite to the fillets formed on the edge adjacent to the edge of the other semiconductor chips 11 to 14, that is, long fillets. As a result, even if a long fillet overflows, a short circuit between the first and second lead frames 101 and 102 can be prevented. Fifth embodiment

[0075] Fig. 10 is a schematic plan view of a fifth embodiment of the present invention, showing the mounting structure of semiconductor chips provided on a power module.

[0076] A power module 100 according to the fifth embodiment includes three linearly arrayed semiconductor chips 21 to 23. First solder pads 50 that secure the semiconductor chips 21 to 23 are rectangular in shape in a plan view in which the length in the array direction (i.e., the length in the lateral direction) is longer than the length in a direction orthogonal to the array direction (i.e., the length in the vertical direction). The semiconductor chips 21 to 23 are square in a plan view. The semiconductor chips 21 to 23 are arranged almost in the center of the first solder pad 50 in the lateral direction and the vertical direction.

[0077] The distances a to d in Fig. 10 are defined as below.

[0078] A distance from the edge of the semiconductor chip 21 adjacent to the semiconductor chip 22 to the edge of the semiconductor chip 22 adjacent to the semiconductor chip 21 is defined as a; a distance from the edge of the semiconductor chip 21 adjacent to the conductor of the chip 23 to the edge of the semiconductor chip 23 adjacent to the semiconductor chip 21 is defined as b; a distance from the edge of the semiconductor chip 21 adjacent to a lower lateral end E4 of a first lead frame 101 to the lower lateral end E4 of the first lead frame 101 is defined as c; and a distance from the edge of the semiconductor chip 21 adjacent to an upper lateral end E2 of a first lead frame 101 to the upper lateral end E2 of the first lead frame 101 is defined as d.

[0079] In the fifth embodiment, the distances a / 2 and b / 2 are shorter than the distances c and d.

[0080] The lengths of the solder fillets 51a and 52a of the semiconductor chips 21 and 22 formed on the edges adjacent to the other semiconductor chips 21 and 22 are formed shorter than the lengths of the solder fillets 51c and 51d formed on the edges of the semiconductor chip 21 adjacent to the lateral ends E2 and E4 of the first lead frame 101. In other words, the lengths of the solder fillets 51c and 51d formed on the semiconductor chip 21 are formed longer than the lengths of the solder fillets 51a and 52a formed on the semiconductor chips 21 and 22. Thus, a short circuit between the semiconductor chips 21 and 22 due to the overflow of solder from the formation regions of the solder fillets 51a and 52a can be suppressed.

[0081] Similarly, the lengths of the solder fillets 51b and 53b of the semiconductor chips 21 and 23 formed on the edges adjacent to the other semiconductor chips 21 and 23 are formed shorter than the lengths of the solder fillets 51c and 51d formed on the edges of the semiconductor chip 21 adjacent to the lateral ends E2 and E4 of the first lead frame 101. In other words, the lengths of the solder fillets 51c and 51d formed on the semiconductor chip 21 are formed longer than the lengths of the solder fillets 51b and 53b formed on the semiconductor chips 21 and 23. Thus, a short circuit between the semiconductor chips 21 and 23 due to the overflow of solder from the formation regions of the solder fillets 51b and 53b can be suppressed.

[0082] Comparing the distance a with the distance b, the length of the solder fillet formed on the edge at a shorter distance is shortened. For example, in the case where the distance a is shorter than the distance b, the length of the solder fillet 51a is made shorter than the length of the solder fillet 51b.

[0083] Comparing the distance c with the distance d, the length of the solder fillet formed on the edge at a shorter distance can be made shorter. For example, if the distance c is shorter than the distance d, the length of the solder fillet 51c can be made shorter than the length of the solder fillet 51d.

[0084] In the fifth embodiment, the lengths of the solder fillets 51c and 51d formed on the edges of the semiconductor chip 21 adjacent to the lateral ends E2 and E4 of the first lead frame 101 were formed longer than the lengths of the solder fillets 51a and 51b formed on the edges of the semiconductor chip 21 adjacent to the semiconductor chips 22 and 23.

[0085] Thus, similar to the effect (1) of the first embodiment, overflow of solder from the formation regions of the solder fillets 51a and 51b formed on the edges of the semiconductor chip 21 adjacent to the semiconductor chips 22 and 23 can be suppressed, and a short circuit between the semiconductor chips 21 and 23 can be prevented.

[0086] It should be noted that similar to the third embodiment (see Fig. 8) In the fifth embodiment, a recess 102b may be formed on an inner surface 102a of a second lead frame 102. In other words, the recess 102b may be formed on the inner surface 102a of the second lead frame 102 at portions corresponding to the solder fillets 51dc and 51d formed on the periphery of the semiconductor chips 21 to 23 adjacent to the lateral ends E2 and E4 of the first lead frame 101. Exemplary modification of the fifth embodiment

[0087] Fig. 11 is a diagram of an exemplary modification of the Fig. 10 shown fifth embodiment.

[0088] In the Fig. In the exemplary modification shown in Figure 11, the semiconductor chips 21 to 23 are grouped in two rows.

[0089] The relationship between the lengths of the solder fillets 51a to 51d formed on the edges of the semiconductor chips 21 arranged in two rows is the same as that shown in Fig. 10. Thus, the exemplary modification of the fifth embodiment produces the effect similar to the effect of the fifth embodiment.

[0090] The semiconductor chips 21 to 23 may also be formed in three or more rows. The number of semiconductor chips 21 to 23 arranged in each row may be four or more. Sixth embodiment

[0091] Fig. 12 is a schematic plan view of a sixth embodiment of the present invention, showing the mounting structure of semiconductor chips provided on a power module.

[0092] Similar to the fifth embodiment, a power module 100 according to the sixth embodiment includes three semiconductor chips 21 to 23 grouped linearly. However, the semiconductor chips 21 to 23 are arranged at positions outside the center portion of a first solder joint 50.

[0093] If the definitions of the distances a to d in Fig. 12 are the same as those of the fifth embodiment, in the sixth embodiment, a distance b / 2 and a distance c are shorter than the distances a and d. The distance b / 2 is almost equal to the distance c. The distance a is almost equal to the distance d.

[0094] The lengths of the solder fillets 51b and 53b of the semiconductor chips 21 and 23 formed on the edges adjacent to the other semiconductor chips 21 and 23 are almost equal to the length of a solder fillet 51c formed on the edge of the semiconductor chip 21 adjacent to a lateral end E4 of a first lead frame 101. The length of a solder fillet 51a formed on the edge of the semiconductor chip 21 adjacent to the semiconductor chip 22 is almost equal to the length of a solder fillet 51d formed on the edge of the semiconductor chip 21 adjacent to a lateral end E2 of the first lead frame 101. The lengths of the solder fillets 51b and 51b formed on the semiconductor chips 21 and 23 and the length of the solder fillet 51c formed on the semiconductor chip 21 are formed shorter than the lengths of the solder fillets 51a and 51d formed on the semiconductor chip 21.

[0095] In other words, the lengths of the solder fillets 51a and 51d formed on the semiconductor chip 21 are longer than the lengths of the solder fillets 51b and 53b formed on the semiconductor chips 21 and 23, and the length of the solder fillet 51c formed on the semiconductor chip 21. Note that the length of the solder fillet 52a formed on the edge of the semiconductor chip 22 adjacent to the semiconductor chip 21 is almost equal to the lengths of the solder fillets 51b and 53b.

[0096] In the sixth embodiment, the lengths of the solder fillets 51a and 51d formed on the semiconductor chip 21 are formed longer than the lengths of the solder fillets 51b and 53b formed between the semiconductor chip 21 and the semiconductor chip 23. Thus, a short circuit between the semiconductor chips 21 and 23 caused by the solder fillets 51b and 53b can be prevented. The lengths of the solder fillets 51a and 51d formed on the semiconductor chip 21 are formed longer than the length of the solder fillet 51c formed on the semiconductor chip 21. As a result, overflow of solder from the formation region of the solder fillet 51c formed on the semiconductor chip 21 to the lateral end E4 of the first lead frame 101 can be suppressed.

[0097] It should be noted that, as in the third and fourth embodiments (see Fig. 8 and Fig. 9), in the sixth embodiment, a recess 102b or 102c may be formed on an inner surface 102a of a second lead frame 102. In other words, the recess 102c or 102b may be formed on the inner surface 102a of the second lead frame 102 at portions corresponding to the solder fillet 51a formed on the edge of the semiconductor chip 21 adjacent to the semiconductor chip 22 and the solder fillet 51d formed on the edges of the semiconductor chip 21 adjacent to the lateral ends E2 and E4 of the first lead frame 101. The recess 102b may be formed on the inner surface 102a of the second lead frame 102 at portions adjacent to the edges of the semiconductor chips 22 and 23 and the lateral ends E1 and E2 or E2 and E3 of the first lead frame. First exemplary modification of the sixth embodiment

[0098] Fig. 13 is a diagram of a first exemplary modification of the Fig. 12 shown sixth embodiment.

[0099] In Fig. 13 are the Fig. 12 are grouped in two rows. In the first exemplary modification of the sixth embodiment shown in Fig. 13, the relationship between the distances a to d between the adjacent semiconductor chips 21 to 23 or the relationship between the distances a to d between the semiconductor chips 21 to 23 and the lateral ends E1 to E4 of the first lead frame 101 in both the first and second rows is the same as in the Fig. 12. The relationship between the lengths of the solder fillets (51a to 51d, 52a, 53b and the like) formed on four edges of each of the semiconductor chips 21 to 23 is also the same in both the first and second rows as in the sixth embodiment shown in Fig. 12. Thus, the first exemplary modification also produces the effect similar to the effect of the sixth embodiment shown in Fig. 12 shown sixth embodiment.

[0100] It should be noted that the semiconductor chips 21 to 23 may also be formed in three or more rows. The number of semiconductor chips 21 to 23 arranged in each row may be four or more. Second exemplary modification of the sixth embodiment

[0101] Fig. 14 is a diagram of a second exemplary modification of the Fig. 12 shown sixth embodiment.

[0102] In addition, Fig. 14 which in Fig. 12 are grouped in two rows. Unlike the first exemplary modification shown in Fig. 13, however, the semiconductor chips 21 to 23 in the second row are arranged upside down with respect to the semiconductor chips 21 to 23 in the first row.

[0103] In the second exemplary modification of the sixth embodiment shown in Fig. 14, the relationship between the distances a to d between the adjacent semiconductor chips 21 to 23 or the relationship between the distances a to d between the semiconductor chips 21 to 23 and the lateral ends E1 to E4 of the first lead frame 101 in both the first and second rows is the same as in the Fig. 12. The relationship between the lengths of the solder fillets (51a to 51d, 52a, 53b and the like) formed on four edges of each of the semiconductor chips 21 to 23 is also the same in both the first and second rows as in the sixth embodiment shown in Fig. 12. As a result, the second exemplary modification also produces the effect similar to the effect of the sixth embodiment shown in Fig. 12 shown sixth embodiment.

[0104] It is pointed out that in Fig. 14, a configuration may be possible in which the semiconductor chips 21 to 23 are provided in three or more rows by alternately adding the arrangement of the semiconductor chips 21 to 23 in the first and second rows. The number of semiconductor chips 21 to 23 arranged in each row may be four or more. Seventh embodiment

[0105] Fig. 15 is a schematic plan view of a seventh embodiment of the present invention, showing the mounting structure of semiconductor chips provided on a power module.

[0106] Similar to the fifth embodiment, a power module 100 according to the seventh embodiment includes three semiconductor chips 21 to 23 grouped linearly. The semiconductor chips 21 to 23 are arranged almost at the center of the first soldering point 50 in the lateral and vertical directions. However, the first soldering points 50 that solder the semiconductor chips 21 to 23 are rectangular in shape, with the length in the lateral direction being longer than the length in the vertical direction.

[0107] In other words, when the distances a to d are defined similarly to the fifth embodiment, the seventh embodiment has the following configurations.

[0108] The distance from the edge of the semiconductor chip 21 adjacent to the semiconductor chip 22 to the edge of the semiconductor chip 22 adjacent to the semiconductor chip 21 is almost equal to the distance b from the edge of the semiconductor chip 21 adjacent to the semiconductor chip 23 to the edge of the semiconductor chip 23 adjacent to the semiconductor chip 21. The distance d from the edge of the semiconductor chip 21 adjacent to a lateral end E2 of the first lead frame 101 to the lateral end E2 of the first lead frame 101 is almost equal to the distance c from the edge of the semiconductor chip 21 adjacent to a lateral end E4 of the first lead frame 101 to the lateral end E4 of the first lead frame 101. The distances c and d are formed shorter than the distances a / 2 and b / 2.

[0109] The lengths of the solder fillets 51a and 52a of the semiconductor chips 21 and 22, formed on the edges adjacent to the other semiconductor chips 21 and 22, are almost equal to the lengths of the solder fillets 51b and 53b of the semiconductor chips 21 and 22, formed on the edges adjacent to the other semiconductor chips 21 and 23. The lengths of the solder fillets 51c and 51d, formed on the edges of the semiconductor chip 21 adjacent to the lateral ends E4 and E2 of the first lead frame 101, are almost equal to each other. The solder fillets 51a, 51b, 52a, and 53b are formed longer than the solder fillets 51c and 51d.

[0110] Thus, in the seventh embodiment, the solder of the solder fillets 51a, 51b, 52a, and 53b overflows from the solder fillet formation regions more easily than the solder of the solder fillets 51c and 51d. As a result, the overflow of solder from the formation regions of the solder fillets 51c and 51d to the two lateral ends E2 and E4 of the first lead frame 101 is suppressed.

[0111] It should be noted that similar to the fourth embodiment (see Fig. 9) In the seventh embodiment, a recess 102c may be formed on an inner surface 102a of a second lead frame 102. In other words, the recess 102c may be formed on the inner surface 102a of the second lead frame 102 at portions corresponding to the solder fillets 51a, 51b, 52a, and 53b of the semiconductor chips 21 to 23 formed on the edges adjacent to the other semiconductor chips 21 to 23. Exemplary modification of the seventh embodiment

[0112] Fig. 16 is a diagram of an exemplary modification of the Fig. 15 shown seventh embodiment.

[0113] In the Fig. In the exemplary modification shown in Figure 16, the semiconductor chips 21 to 23 are grouped in two rows.

[0114] The relationship between the lengths of the solder fillets 51a to 51d formed on the edges of the semiconductor chip 21 arranged in two rows is the same as that shown in Fig. 15. Thus, the exemplary modification of the seventh embodiment produces the effect similar to that of the seventh embodiment.

[0115] The semiconductor chips 21 to 23 may also be formed in three or more rows.

[0116] The number of semiconductor chips 21 to 23 arranged in each row may be four or more. Confirmation of the effects

[0117] The following are specific examples of the effects of the present invention using examples. Example 1

[0118] Fig. 17 is a graph of a first effect of the present invention, showing the frequency of occurrence of short circuits between semiconductor chips according to Example 1 of the present invention.

[0119] Example 1 has a soldering structure of a first lead frame 101, a second lead frame 102 and the semiconductor chips 11 to 14, which are shown in the Fig. 3 and Fig. 4 as the first embodiment. Specifically, the first and second lead frames 101 and 102 were formed of copper plates. Four protrusions 103 were formed on the second lead frame 102, and the four semiconductor chips 11 to 14 were mounted corresponding to the protrusions 103. The semiconductor chips 11 to 14 have a rectangular parallelepiped shape of a size of 10 mm square. The distances (a, b, and the like) between the adjacent semiconductor chips 11 to 14 were set to 1.0 mm. The distances (c, d, and the like) from the semiconductor chips 11 to 14 to the lateral ends E1 to E4 of the first lead frame 101 were set to 2.0 mm.

[0120] The lengths of the solder fillets (51a, 51b, 52a, 53b, and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 were set to 0.3 mm. The lengths of the solder fillets (51c, 51d, and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to the lateral ends E1 to E4 of the first lead frame 101 were set to 1.0 mm. A foil of Sn3Ag0.5Cu solder was used as the solder 50. A vacuum reflow device was used for reflow and bonded using a temperature profile with a tip at a temperature of 250°C.

[0121] As Comparative Example 1, a soldering structure shown below was prepared from a first lead frame 101, a second lead frame 102, and semiconductor chips 11 to 14.

[0122] The lengths of the solder fillets (51a, 51b, 52a, 53b, and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 were set to 0.3 mm. The lengths of the solder fillets (51c, 51d, and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to the lateral ends E1 to E4 of the first lead frame 101 were set to 0.3 mm. In other words, all the lengths of the solder fillets formed on four edges of each of the semiconductor chips 11 to 14 were all set to 0.3 mm.

[0123] The configurations other than the above configurations are all similar to the configurations of Example 1.

[0124] Example 1 and Comparative Example 1 were each prepared for 20 devices. On Example 1 and Comparative Example 1, the number of occurrences of short circuits between the semiconductor chips 11 to 14 and the number of occurrences of solder overflow from the fillet formation regions to the lateral ends of the first lead frame 101 in the semiconductor chips 11 to 14 were checked. The result is shown in Fig. 17 shown.

[0125] In Comparative Example 1, that is, in the mounting structure in which the lengths of the solder fillets formed on four edges of each of the semiconductor chips 11 to 14 were all formed in 0.3 mm, a short circuit occurred between the semiconductor chips 11 to 14 in seven out of 20 devices.

[0126] On the other hand, in Example 1, that is, in the mounting structure in which the lengths of the solder fillets (51a, 51b, 52a, 53b, and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 were set to 0.3 mm and the lengths of the solder fillets (51c, 51d, and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to the lateral ends of the first lead frame 101 were set to 1.0 mm, no short circuit occurred between the semiconductor chips 11 to 14 in zero out of 20 devices.

[0127] It is noted that in both Example 1 and Comparative Example 1, the number of occurrences of overflow of solder from the solder fillets on the semiconductor chips 11 to 14 to the side ends E1 to E4 of the first lead frame 101 was zero out of 20 devices.

[0128] From the above description, according to Example 1 of the present invention, it was confirmed that overflow of solder from the formation regions of the solder fillets of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 was suppressed and short circuit between the semiconductor chips 11 to 14 could be prevented. Example 2

[0129] Fig. 18 is a graph of a second effect of the present invention, showing the frequency of occurrence of short circuits between semiconductor chips according to Example 2 of the present invention.

[0130] Example 2 has a soldering structure of the first and second lead frames 101 and 102 and the semiconductor chips 11 to 14 of the second embodiment shown in the Fig. 6 and Fig. 7. Specifically, the first and second lead frames 101 and 102 were formed of copper plates. Four protrusions 103 were formed on the second lead frame 102, and the four semiconductor chips 11 to 14 were mounted corresponding to the protrusions 103. The semiconductor chips 11 to 14 have a rectangular parallelepiped shape of a size of 10 mm square. The distances (a, b, and the like) between the adjacent semiconductor chips 11 to 14 were set to 3.0 mm. The distances (c, d, and the like) from the semiconductor chips 11 to 14 to the lateral ends E1 to E4 of the first lead frame 101 were set to 1.0 mm.

[0131] The lengths of the solder fillets (51a, 51b, 52a, 53b, and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 were set to 1.0 mm. The lengths of the solder fillets (51c, 51d, and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to the lateral ends E1 to E4 of the first lead frame 101 were set to 0.3 mm. A foil of Sn3Ag0.5Cu solder was used as the solder 50. A vacuum reflow device was used for reflow and bonded using a temperature profile with a tip at a temperature of 250°C.

[0132] As Comparative Example 2, a solder structure shown below was prepared from a first lead frame 101, a second lead frame 102, and semiconductor chips 11 to 14.

[0133] The lengths of the solder fillets (51a, 51b, 52a, 53b, and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 were set to 0.3 mm. The lengths of the solder fillets (51c, 51db, and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to the lateral ends E1 to E4 of the first lead frame 101 were set to 0.3 mm. In other words, all the lengths of the solder fillets formed on four edges of each of the semiconductor chips 11 to 14 were all set to 0.3 mm.

[0134] The configurations other than the above configurations are all similar to the configurations of Example 2.

[0135] Example 2 and Comparative Example 2 were each prepared for 20 devices. On Example 2 and Comparative Example 2, the number of occurrences of short circuits between the semiconductor chips 11 to 14 and the number of occurrences of solder overflow from the fillet formation regions to the lateral ends of the first lead frame 101 in the semiconductor chips 11 to 14 were checked. The result is shown in Fig. 18 shown.

[0136] In Comparative Example 2, that is, in the mounting structure in which the lengths of the solder fillets formed on four edges of each of the semiconductor chips 11 to 14 were set to 0.3 mm, solder overflowed from the formation regions of the solder fillets formed on the semiconductor chips 11 to 14 to the side ends E1 to E4 of the first lead frame 101 in Fig. 11 out of 20 devices.

[0137] On the other hand, in Example 2, that is, in the mounting structure in which the lengths of the solder fillets of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 were set to 1.0 mm and the lengths of the solder fillets formed on the edges of the semiconductor chips 11 to 14 adjacent to the lateral ends E1 to E4 of the first lead frame 101 were set to 0.3 mm, no solder overflowed from the formation regions of the solder fillets formed on the semiconductor chips 11 to 14 to the lateral ends E1 to E4 of the first lead frame 101 in zero out of 20 devices.

[0138] It is noted that in both Example 2 and Comparative Example 2, the number of occurrences of faults that are short circuits between the semiconductor chips 11 to 14 was zero.

[0139] From the above description, according to Example 2 of the present invention, overflow of solder from the formation regions of the solder fillets formed on the edges of the semiconductor chips 11 to 14 adjacent to the lateral ends E1 to E4 of the first lead frame 101 to the lateral ends E1 to E4 of the first lead frame 101 can be suppressed.

[0140] Note that in Example 1, an example was shown in which the lengths of the solder fillets (51a, 51b, 52a, 53b, and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 were set to 0.3 mm, and the lengths of the solder fillets (51c, 51d, and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to the lateral ends E1 to E4 of the first lead frame 101 were set to 1.0 mm. However, the lengths of the solder fillets are examples. The lengths of the solder fillets (51a, 51b, 52a, 53b, and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 may be shorter than 0.3 mm or longer than 0.3 mm. The lengths of the solder fillets (51a, 51b, and the like) formed on two opposite sides of the adjacent semiconductor chips 11 to 14 may be different from each other.Similarly, the lengths of the solder fillets (51c, 51d, and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to the lateral ends E1 to E4 of the first lead frame 101 may be longer than 1.0 mm or shorter than 1.0 mm. The lengths of the solder fillets (51c, 51d, and the like) formed on two edges of the semiconductor chips 11 to 14 adjacent to the lateral ends E1 to E4 of the first lead frame 101 may be different from each other.

[0141] In Example 2, an example was shown in which the lengths of the solder fillets (51a, 51b, 52a, 53b, and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 were set to 1.0 mm, and the lengths of the solder fillets (51c, 51d, and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to the lateral ends E1 to E4 of the first lead frame 101 were set to 0.3 mm. However, the lengths of the solder fillets are examples. The lengths of the solder fillets (51a, 51b, 52a, 53b, and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 may be shorter than 1.0 mm or longer than 1.0 mm. The lengths of the solder fillets (51a, 51b, and the like) formed on edges of the semiconductor chips 11 to 14 adjacent to the edges of the other semiconductor chips 11 to 14 may be different from each other.Similarly, the lengths of the solder fillets (51c, 51d, and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to the lateral ends E1 to E4 of the first lead frame 101 may be shorter than 0.3 mm or longer than 0.3 mm. The lengths of the solder fillets (51c, 51d, and the like) formed on two edges of the semiconductor chips 11 to 14 adjacent to the lateral ends of the first lead frame 101 may be different from each other.

[0142] As a method for reliably adjusting the lengths of the solder fillets formed on the edges of the semiconductor chips 11 to 14 and 21 to 23, a solder wetting prevention structure for preventing solder wetting may be formed around the areas where solder fillets are formed. The solder wetting prevention structure may be formed, for example, by coating with a solder resist, by recessing, by oxidation treatment using a laser, and the like, or by chemical roughening, and the like.

[0143] In the above embodiments, examples of structures were described in which the semiconductor chips 11 to 14 and 21 to 23 were soldered to the first and second lead frames 101 and 102 with the solder pads 50 and 60. However, the embodiments are applicable to structures without a second lead frame 102.

[0144] In the above embodiments, examples of structures were described in which the protrusions 103 were provided on the second lead frame 102, to which the semiconductor chips 11 to 14 and 21 to 23 were soldered with the solder joint 60. However, structures in which no protrusions 103 are formed on the second lead frame 102 may be provided.

[0145] In the above embodiments, examples of structures were described in which the semiconductor chips 11 to 14 and 21 to 23 were soldered to the first and second lead frames 101 and 102 with the solder pads 50 and 60. However, instead of the first and second lead frames 101 and 102, molded products such as aluminum molded products and sintered compacts such as ceramics may also be used.

[0146] The first to seventh embodiments may be selectively combined.

[0147] Other than the above configurations, the present invention is applicable to various modifications and variations within the scope of the present invention. In short, the power module only needs to have a configuration according to the features of independent claim 1. List of reference symbols 11 to 14 semiconductor chips 21 to 23 semiconductor chip 50 first solder joint 51a, 51b, 51c, 51d solder fillet 52a, 52c solder fillet 53a, 53b solder fillet 60 second solder joint 61 soldering fillet 100 power modules 101 first lead frame (base plate) 102 second management frame 102a inner surface 102b, 102c recess 103 lead 111 Line 210 module housings 304B flange 305 Rib 307 Heat dissipation base 350 primary sealing material 351 secondary sealing material a to d distance E1, E2, E3, E4 side end

Claims

[1] Performance module that includes: a base plate (101); a first semiconductor chip (11; 21) having four edges, the first semiconductor chip (11; 21) being soldered to the base plate (101); a second semiconductor chip (12; 22) having four edges, one of the four edges being arranged adjacent to a first edge of the first semiconductor chip (11; 21), the second semiconductor chip (12; 22) being soldered to the base plate (101); and a third semiconductor chip (13; 23) having four edges, one of the four edges being arranged adjacent to a second edge of the first semiconductor chip (11; 21), the third semiconductor chip (13; 23) being soldered to the base plate (101), wherein a third edge or a fourth edge of the first semiconductor chip (11; 21) is arranged adjacent to an associated lateral end (E1; E2; E4) of the base plate (101) or a third edge and a fourth edge of the first semiconductor chip (11; 21) are each arranged adjacent to a respective associated lateral end (E1, E2; E4, E2) of the base plate (101), and at half a distance (a / 2) from the first edge of the first semiconductor chip (11; 21) to one edge of the second semiconductor chip (12; 22), half a distance (b / 2) from the second edge of the first semiconductor chip (11; 21) to one edge of the third semiconductor chip (13; 23) and a distance (c; d) from the third edge or from the fourth edge of the first semiconductor chip (11; 21), which is arranged adjacent to the associated lateral end (E1; E2; E4) of the base plate (101), to the associated lateral end (E1; E2; E4) of the base plate (101) of solder fillets (51a, 51b, 51c; 51a, 51b, 51d) formed on these edges of the first semiconductor chip (11; 21), the length (I) of a solder fillet among these solder fillets (51a, 51b, 51c; 51a, 51b, 51d) formed on an edge of the first semiconductor chip (11; 21) at a shorter distance, is formed in a shorter length and the length (I) of the solder fillet among these solder fillets (51a, 51b, 51c;51a, 51b, 51d) formed on the edge of the first semiconductor chip (11; 21) at the shortest distance, in the shortest length; [2] Power module according to claim 1, wherein half a distance (a / 2) from the first edge of the first semiconductor chip (11; 21) to the one edge of the second semiconductor chip (12; 22) and half a distance (b / 2) from the second edge of the first semiconductor chip (11; 21) to the one edge of the third semiconductor chip (13; 23) are shorter than the distance (c; d) from the third edge or from the fourth edge of the first semiconductor chip (11; 21), which is arranged adjacent to the associated lateral end (E1; E2; E4) of the base plate (101), to the associated lateral end (E1; E2; E4) of the base plate (101), and the lengths of the solder fillets (51a, 51b) formed on the first edge and on the second edge of the first semiconductor chip (11; 21) are each formed shorter than the length of the solder fillet (51c; 51d) formed on the third edge or on the fourth edge of the first semiconductor chip (11; 21) adjacent to the associated lateral end (E1; E2; E4) of the base plate (101). [3] The power module according to claim 2, wherein the first edge and the second edge of the first semiconductor chip (11) are adjacent edges to each other, the third edge and the fourth edge of the first semiconductor chip (11) are adjacent edges to each other, the third edge of the first semiconductor chip (11) is arranged adjacent to a first lateral end (E1) of the base plate (101), and the fourth edge of the first semiconductor chip (11) is arranged adjacent to a second lateral end (E2) of the base plate (101), and the lengths of the solder fillets (51a, 51b) formed on the first edge and on the second edge of the first semiconductor chip (11) are each formed shorter than each of the lengths of the solder fillets (51c, 51d) formed on the third edge and on the fourth edge of the first semiconductor chip (11). [4] The power module according to claim 2, wherein the first edge and the second edge of the first semiconductor chip (21) are a pair of opposite edges, the third edge or the fourth edge of the first semiconductor chip (21) is arranged adjacent to the associated lateral end (E4; E2) of the base plate (101), or the third edge and the fourth edge of the first semiconductor chip (21) are each arranged adjacent to the associated lateral end (E4; E2) of the base plate (101), and the lengths of the solder fillets (51a, 51b) formed on the first edge and on the second edge of the first semiconductor chip (21) are each formed shorter than the length of the solder fillet (51c; 51d) formed on the third edge or on the fourth edge of the first semiconductor chip (21) arranged adjacent to the associated lateral end (E4; E2) of the base plate (101). [5] Power module according to claim 4, wherein the third edge and the fourth edge of the first semiconductor chip (21) are each arranged adjacent to the associated lateral ends (E4, E2) of the base plate (101), and the lengths of the solder fillets (51a, 51b) formed on the first edge and on the second edge of the first semiconductor chip (21) are each formed shorter than each of the lengths of the solder fillets (51c, 51d) formed on the third edge and on the fourth edge of the first semiconductor chip (21). [6] The power module of claim 4, further comprising: a fourth semiconductor chip arranged adjacent to the third edge of the first semiconductor chip (21), wherein the fourth edge of the first semiconductor chip (21) is arranged adjacent to the associated lateral end (E2) of the base plate (101), and the lengths of the solder fillets (51a, 51b) formed on the first edge and on the second edge of the first semiconductor chip (21) are each formed shorter than each of the lengths of the solder fillets (51c, 51d) formed on the third edge and on the fourth edge of the first semiconductor chip (21). [7] Power module according to claim 1, wherein the first edge and the second edge of the first semiconductor chip (21) are a pair of opposite edges, the third edge and the fourth edge of the first semiconductor chip (21) are a further pair of opposite edges, the third edge or the fourth edge of the first semiconductor chip (21) is arranged adjacent to the associated lateral end (E4; E2) of the base plate (101) or the third edge and the fourth edge of the first semiconductor chip (21) are each arranged adjacent to the respectively associated lateral end (E4; E2) of the base plate (101), and the length of the solder fillet (51a) formed on the first edge of the first semiconductor chip (21) is shorter than the length of the solder fillet (51b) formed on the second edge of the first semiconductor chip (21) and shorter than the length of the solder fillet (51c; 51d) formed on the third edge or on the fourth edge arranged adjacent to the associated lateral end (E4; E2) of the base plate (101). [8] Power module according to claim 1, wherein the first edge and the second edge of the first semiconductor chip (21) are a pair of opposite edges, the third edge and the fourth edge of the first semiconductor chip (21) are a further pair of opposite edges, the third edge or the fourth edge of the first semiconductor chip (21) is arranged adjacent to the associated lateral end (E4; E2) of the base plate (101) or the third edge and the fourth edge of the first semiconductor chip are each arranged adjacent to the respectively associated lateral end (E4; E2) of the base plate (101), the distance (c; d) from the third edge or from the fourth edge of the first semiconductor chip (21), which is arranged adjacent to the associated lateral end (E4; E2) of the base plate (101), to the associated lateral end (E4; E2) of the base plate (101) is shorter than half a distance (a / 2) from the first edge of the first semiconductor chip (21) to the one edge of the second semiconductor chip (22) and shorter than half a distance (b / 2) from the second edge of the first semiconductor chip (21) to the one end of the third semiconductor chip (23), and the length of the solder fillet (51c; 51d) of the first semiconductor chip (21) formed on the third edge or on the fourth edge of the first semiconductor chip (21) arranged adjacent to the associated lateral end (E4; E2) of the base plate (101) is formed shorter than each of the lengths of the solder fillets (51a, 51b) formed on the first edge and on the second edge of the first semiconductor chip (21). [9] Power module according to claim 8, wherein the third edge and the fourth edge of the first semiconductor chip (21) are each arranged adjacent to the associated lateral end (E4; E2) of the base plate (101), and the lengths of the solder fillets (51c, 51d) formed on the third edge and on the fourth edge of the first semiconductor chip (21) are each formed shorter than each of the lengths of the solder fillets (51a, 51b) formed on the first edge and on the second edge of the first semiconductor chip (21). [10] The power module of claim 9, further comprising: a fourth semiconductor chip arranged adjacent to the third edge of the first semiconductor chip (21), wherein the fourth edge of the first semiconductor chip (21) is arranged adjacent to the associated lateral end (E2) of the base plate (101), and the lengths of the solder fillets (51c, 51d) formed on the third edge and on the fourth edge of the first semiconductor chip (21) are each formed shorter than each of the lengths of the solder fillets (51a, 51b) formed on the first edge and on the second edge of the first semiconductor chip (21). [11] The power module according to any one of claims 1 to 10, wherein in the solder fillets (51a, 51b, 51c, 51d) formed on the four edges of the first semiconductor chip (11; 21), the lengths of the solder fillets formed on two edges of the first semiconductor chip (11; 21) are each formed shorter than each of the lengths of the solder fillets formed on the other two edges of the first semiconductor chip (11; 21). [12] The power module of claim 11, further comprising: a further base plate (102) arranged opposite the base plate (101), wherein the first semiconductor chip (11; 21), the second semiconductor chip (12; 22) and the third semiconductor chip (13; 23) each have an area (f L ) and one further area (f U ) opposite one surface (f L ) and in the first semiconductor chip (11; 21), the second semiconductor chip (12; 22) and the third semiconductor chip (13; 23) each have one area (fL ) is soldered to the base plate (101) and each further surface (f U ) is soldered to the further base plate (102), and a recess (102b; 102c) is formed on an inner surface (102a) of the further base plate (102), the inner surface (102a) of the further base plate (102) being opposite the base plate (101), and the recess (102b; 102c) being formed opposite at least the longest of the solder fillets (51a, 51b, 51c, 51d) formed on the edges of the first semiconductor chip (11; 21).

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