Semiconductor device manufacturing process

Abstract

A method for manufacturing a semiconductor device, comprising the steps of: Forming an impurity diffusion region (3, 4, 5 / 12) in a semiconductor layer (2); Forming an insulating layer (6) having a thickness of 0.5 µm or greater on the semiconductor layer (2); Forming an etching mask (102 / 104) on the insulation layer (6); and Forming an opening, which reaches an upper surface of the semiconductor layer (2) and has a dimension of 2 mm × 2 mm or larger in a plan view, in the insulating layer (6) by etching using the etching mask (102 / 104) as a mask to expose at least a part of the impurity diffusion region (3, 4, 5 / 12) from the insulating layer (6), wherein the step of forming the opening comprises the steps Removing the insulating layer (6) so that half or less of a thickness of the insulating layer (6) is not removed by dry etching by using the etching mask (102 / 104) as a mask, and Removing the insulation layer (6) until the opening reaches the upper surface of the semiconductor layer (2) by wet etching using the etching mask (102 / 104) as a mask, wherein the insulation layer (6) has a first insulation layer (61) composed of a silicon oxide layer, and a second insulation layer (62) composed of a silicon nitride layer disposed on the first insulation layer (61) and thicker than the first insulation layer (61), wherein the step of forming the opening is carried out by removing the second insulation layer (62) in the dry etching and by removing the first insulation layer (61) in the wet etching, wherein the second insulation layer (62) has a higher selectivity with respect to the etching mask (102 / 104) during dry etching than the first insulation layer (61), and wherein the first insulation layer (61) has a lower etching rate during wet etching than the second insulation layer (62).

Description

Technical area

[0001] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a technique of forming a pattern of an insulating layer on a semiconductor substrate. State of the art

[0002] Examples of elements used for power semiconductor devices such as inverters include Schottky barrier diodes (SBDs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and insulated-gate bipolar transistors (IGBTs). Power semiconductor devices, each using silicon (Si) as a semiconductor material, have gradually approached the limits of the theoretical physical properties of silicon in recent years. Therefore, attention is now being turned to compound semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN), which exceed the limits of the theoretical physical properties of silicon. Accordingly, power semiconductor devices using such semiconductor materials are being developed.

[0003] Some compound semiconductors have crystal lattice constants smaller than the crystal lattice constant (5.43 Å) of silicon (1 Å = 0.1 nm). Examples of such compound semiconductors include GaN (a = 3.189 Å, c = 5.185 Å), 3C-SiC (4.36 Å), 4H-SiC (a = 3.07 Å, c = 10.05 Å), and 6H-SiC (a = 3.08 Å, c = 15.1 Å). A semiconductor substrate with a small crystal lattice constant exhibits a low ion diffusion coefficient when doped; in addition, the semiconductor substrate must be subjected to a heat treatment at a high temperature of 1500°C or higher to activate the doped ions (activation annealing). Therefore, activation annealing must be performed before patterning an insulating layer (particularly a Si-based insulating layer) on the semiconductor substrate.Accordingly, the patterning of the insulating layer preferably has little effect on an impurity diffusion region that is previously formed.

[0004] For example, Patent Document 1 discloses a design of a field insulation layer formed on a SiC substrate and having a thickness ranging from about 100 to 600 nm, the design comprising the following processes: first, the field insulation layer is subjected to dry etching until it becomes several tens of nanometers thick; and then, the field insulation layer is subjected to wet etching. Prior art documentsPatent document

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2002-093742

[0006] JP 2002 093 742 A discloses a method for manufacturing a semiconductor device in which openings are formed in an insulation layer, wherein the insulation layer is a stack comprising a thermal oxide layer and a PSG film.

[0007] JP S63 - 19 823 A discloses a method for forming a thin film pattern by wet etching and dry etching.

[0008] US 4 676 869 A discloses a method for manufacturing a semiconductor device which includes wet etching and dry etching. SummaryProblem to be solved by the invention

[0009] A typical method for forming a Si-based insulation layer is dry etching or wet etching using an etching mask. In dry etching for forming the insulation layer, different locations are likely to have different etching amounts (removal amounts). Thus, variations in the removal amount of the semiconductor substrate surface cause an impurity concentration profile of the previously formed impurity diffusion region to vary, causing electrical properties of, for example, current paths or a voltage holding region to vary from location to location. This unfortunately degrades the reliability of the semiconductor device.A semiconductor device having a large area such as the power semiconductor device, particularly an element having a MOS structure with a channel arranged in an uppermost layer of a semiconductor substrate, clearly encounters such a problem.

[0010] In contrast, wet etching for the design of the insulation layer exhibits a high degree of isotropy. Thus, the side surfaces of the insulation layer recede significantly in a lateral direction during design. This makes it difficult to form a fine pattern. Furthermore, forming the pattern to reflect the receding pattern results in a large chip. A semiconductor device such as a power semiconductor device, which has a thick insulation layer, clearly encounters such a problem.

[0011] The present invention has been achieved to solve these problems. It is an object of the present invention to provide a method for manufacturing a semiconductor device that has a low impact on a semiconductor substrate and in which a fine pattern of an insulating layer is formed. Means of solving the problem

[0012] A method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming an impurity diffusion region in a semiconductor layer; forming an insulating layer having a thickness of 0.5 µm or greater on the semiconductor layer; forming an etching mask on the insulating layer; and forming an opening, which reaches the upper surface of the semiconductor layer and has a dimension of 2 mm × 2 mm or greater in a plan view, in the insulating layer by etching by using the etching mask as a mask to expose at least a part of the impurity diffusion region from the insulating layer.The opening forming step includes the steps of: removing the insulating layer such that half or less of the thickness of the insulating layer is not removed by dry etching using the etching mask as a mask; and removing the insulating layer until the opening reaches the upper surface of the semiconductor layer by wet etching using the etching mask as a mask. The insulating layer includes a first insulating layer composed of a silicon oxide layer and a second insulating layer composed of a silicon nitride layer disposed on the first insulating layer and thicker than the first insulating layer. The opening forming step is performed by removing the second insulating layer in the dry etching and by removing the first insulating layer in the wet etching. Effects of the invention

[0013] In the present invention, the step of forming the opening having a dimension of 2 mm × 2 mm or larger in the insulating layer having a thickness of 0.5 μm or larger is carried out by the following steps: removing the insulating layer so that half or less of the thickness of the insulating layer is not removed by dry etching, which has a high ability of regulating a dimension; and then removing the remainder of the insulating layer by wet etching, whereby the surface of the semiconductor substrate is not removed. Such an arrangement prevents variations in a removal amount of the surface of the impurity diffusion region under the opening while maintaining high dimensional accuracy of the opening. The high dimensional accuracy enables a fine pattern of the insulating layer, thereby contributing to downsizing of the semiconductor device.Furthermore, the removal rate of the impurity diffusion region surface is uniform. This reduces variations in the impurity concentration profile of the impurity diffusion region and enables improved reliability of the semiconductor device.

[0014] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. Short description of the drawings Fig. 1 is a process step diagram illustrating a method of manufacturing a semiconductor device according to a first example. Fig. 2 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the first example. Fig. 3 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the first example. Fig. 4 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the first example. Fig. 5 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the first example. Fig. 6 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the first example. Fig. 7 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the first example. Fig. 8 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the first example. Fig. 9 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the first example. Fig. 10 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the first example. Fig. 11 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the first example. Fig. 12 is a process step diagram illustrating a method of manufacturing a semiconductor device according to an embodiment. Fig. 13 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the embodiment. Fig. 14 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the embodiment. Fig. 15 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the embodiment. Fig. 16 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the embodiment. Fig. 17 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the embodiment. Fig. 18 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the embodiment. Fig. 19 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the embodiment. Fig. 20 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the embodiment. Fig. 21 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the embodiment. Fig. 22 is a process step diagram illustrating the method of manufacturing the semiconductor device according to the embodiment. Description of the embodiment(s)< First example>

[0015] The following describes a method of manufacturing a semiconductor device according to a first example. Fig. Figures 1 to 11 are process step diagrams illustrating the method for manufacturing the semiconductor device and are cross-sectional views of the semiconductor device in each process step. The first example illustrates an n-channel MOSFET as a power semiconductor device.

[0016] The initial step ( Fig. 1) is a preparation of an n-type semiconductor substrate 1 made of silicon carbide, which has a low resistance. The following step ( Fig. 2) is a growth of an epitaxial layer 2 (semiconductor layer) consisting of n-type silicon carbide on the semiconductor substrate 1.

[0017] The next step ( Fig. 3) is to form a photoresist 101 (injection mask) provided with openings over areas in which well regions of the MOSFET are to be formed, on the epitaxial layer 2 by using photolithography. The following step ( Fig. 4) is doping the epitaxial layer 2 with a p-type impurity by selective ion implantation using the photoresist 101 as a mask to form well regions 3, each being a p-type impurity diffusion region, in an uppermost layer of the epitaxial layer 2.

[0018] The next step ( Fig. 5) is to form source regions 4, each being an n-type impurity diffusion region, and contact regions 5, each being a p-type impurity diffusion region, in upper layers within the well regions 3 by selective ion implantation using a similar technique. Note that a portion in an uppermost layer of each well region 3 outside the source region 4 is intended to be a channel region of the MOSFET.

[0019] The subsequent step is an annealing process at a temperature of 1500°C or higher to activate the injected impurity in the well regions 3, the source regions 4 and the contact regions 5.

[0020] After annealing for activation, the next step is ( Fig. 6) Applying an insulating layer 6 composed of a silicon oxide layer to the surface of the epitaxial layer 2 so that it has a thickness of 0.5 µm or greater. The insulating layer 6 has a thickness of approximately 1200 nm.

[0021] The following step ( Fig. 7) Forming a photoresist 102 (etching mask) with an opening over a region where the MOSFET is to be formed on the insulating layer 6 by using photolithography. The opening of the photoresist 102 is set to have a dimension of 2 mm² or larger (2 mm × 2 mm or larger in one dimension) in a plan view. Then, the insulating layer 6 is subjected to etching by using the photoresist 102 as a mask to form an opening in the insulating layer that reaches the upper surface of the epitaxial layer 2. The etching of the insulating layer 6 is performed by a combination of a dry etching process and a wet etching process, the details of which will be described below.

[0022] The first step ( Fig. 8) is to remove the insulating layer 6 such that half or less of the thickness of the insulating layer 6 is not removed by dry etching using the photoresist 102 as a mask. Here, the insulating layer 6 is subjected to one-minute etching at an etching rate of 850 nm / min using a parallel plate dry etching device. As a result, an approximately 300 nm thick insulating layer 6 remains at the bottom of an opening formed in the insulating layer 6.

[0023] The second step ( Fig. 9) is to remove the insulating layer 6 remaining at the bottom of the opening by wet etching by using the same photoresist 102 used in the dry etching as a mask to cause the opening to reach the surface of the epitaxial layer 2. Here, the wet etching process with buffered hydrofluoric acid (BHF) lasts six minutes, where NH4F:HF=10:1. The wet etching exhibits a high degree of isotropy; in addition, the side surfaces of the insulating layer 6 are subjected to etching. Therefore, the side surfaces of the insulating layer 6 are each inclined, as shown in Fig. 9. Thus, the opening formed in the insulation layer 6 is shaped so that it is wide upwards.

[0024] When the opening formed in the insulating layer 6 reaches the surface of the epitaxial layer 2, the well regions 3, the source regions 4, and the contact regions 5, which are all impurity diffusion regions formed in the uppermost layer of the epitaxial layer 2, are exposed from the insulating layer 6. The exposed well regions 3 each comprise the channel region of the MOSFET.

[0025] The next step ( Fig. 10) involves removing the photoresist 102 by O2 plasma ashing, followed by forming gate insulation layers 7, each composed of a silicon oxide layer, and gate electrodes 8, each composed of polysilicon, on the epitaxial layer 2, followed by forming interlayer insulation layers 9 to cover the gate insulation layers 7 and the gate electrodes 8. The interlayer insulation layers 9 are each provided with a contact hole that reaches the source region 4 and the contact region 5.

[0026] The last step ( Fig. 11) is to form a source electrode 10 made of aluminum on the interlayer insulation layers 9, followed by forming a drain electrode 11 on the back surface of the semiconductor substrate 1. This completes the MOSFET.

[0027] As described above, in the first example, the step of forming the opening having a large width (2 mm × 2 mm or larger in dimension) in the thick (0.5 μm or larger in thickness) insulating layer 6 is performed by removing the insulating layer 6 such that half or less of the thickness of the insulating layer 6 is not removed by dry etching, which has a high ability of regulating a dimension, followed by removing the remainder of the insulating layer 6 by wet etching, whereby the surface of the semiconductor substrate is not removed. This prevents variations in a removal amount of the surface of the impurity diffusion region under the opening while maintaining high dimensional accuracy of the opening. The high dimensional accuracy provides a fine pattern with the insulating layer 6, thereby contributing to downsizing of the semiconductor device.Furthermore, the removal amount of the surface of the impurity diffusion region (well region 3, source region 4, and contact region 5) is uniform, thereby reducing variations in the impurity concentration profile of the impurity diffusion region and enabling improved reliability of the semiconductor device. Further, as a result of the wet etching process, the side surfaces of the insulating layer 6 are each inclined, thereby enabling the aluminum source electrode 10 to have improved coverage of the insulating layer 6. <Ausführungsform>

[0028] The following describes a method of manufacturing a semiconductor device according to an embodiment. Fig. Figures 12 to 22 are process step diagrams illustrating the method for manufacturing the semiconductor device and are cross-sectional views of the semiconductor device in each process step. The embodiment illustrates a pn junction diode as a power semiconductor device.

[0029] The initial step ( Fig. 12) is a preparation of the semiconductor substrate 1, which is made of silicon carbide, which has a low resistance. The following step ( Fig. 13) is a growth of the epitaxial layer 2 (semiconductor layer), which consists of n-type silicon carbide, on the semiconductor substrate 1.

[0030] The next step ( Fig. 14) is to form a photoresist 103 (injection mask) provided with an opening over a region in which an anode region of the diode is to be formed on the epitaxial layer 2 by using photolithography. The following step ( Fig. 15) is to dope the epitaxial layer 2 with a p-type impurity by selective ion implantation using the photoresist 103 as a mask to form an anode region 12, which is a p-type impurity diffusion region, in the uppermost layer of the epitaxial layer 2.

[0031] The next step ( Fig. 16) is a removal of the photoresist 103, followed by an annealing process at a temperature of 1500°C or higher to activate the injected impurity in the anode region 12.

[0032] After the activation annealing, the next step is to form the insulating layer 6 to have a thickness of 0.5 μm or greater on the surface of the epitaxial layer 2. The second embodiment illustrates that the insulating layer 6 is a stack of a first insulating layer 61 and a second insulating layer 62 disposed thereon. The second insulating layer 62 is set to be thicker than the first insulating layer 61; that is, the second insulating layer 62 is set to have a thickness such that the second insulating layer 62 occupies one-half or more of the thickness of the insulating layer 6. Further, with respect to a photoresist 104 used in a dry etching process described below, the second insulating layer 62 preferably has a higher selectivity than the first insulating layer 61.Furthermore, the first insulation layer 61 preferably has a lower etching rate in a wet etching process, which is described below, than the second insulation layer 62. Here, the insulation layer 6 is formed by applying the first insulation layer 61, which is composed of a 300 nm thick silicon oxide layer (. Fig. 17), on the epitaxial layer 2 and applying the second insulation layer 62, which is made up of a 1200 nm thick silicon nitride layer ( Fig. 18), formed on the first insulation layer 61.

[0033] The next step ( Fig. 19) is to form a photoresist 104 (etching mask) having an opening over a region where the diode is to be formed on the insulating layer 6 by using photolithography. The opening of the photoresist 104 is set to have a dimension of 2 mm² or larger (2 mm × 2 mm or larger in one dimension) in a plan view. Then, the insulating layer 6 is subjected to etching by using the photoresist 104 as a mask to form an opening in the insulating layer 6 that reaches the upper surface of the epitaxial layer 2. The etching of the insulating layer 6 is performed by a combination of a dry etching process and a wet etching process, the details of which will be described below.

[0034] The first step ( Fig. 20) is to remove the second insulating layer 62 by dry etching by using the photoresist 104 as a mask. The first insulating layer 61 is not removed at the bottom of the opening by one-half or less of the thickness of the insulating layer 6 (300 nm). Here, the insulating layer 6 is subjected to etching for three minutes at an etching rate of 400 nm / min using a parallel plate dry etching device. Since the second insulating layer 62 has higher selectivity with respect to the photoresist 104 in the dry etching process than the first insulating layer 61, an over-etching process in this process step hardly removes the upper surface of the first insulating layer 61. This reduces variations in the removal amount of the insulating layer 6 as a result of the dry etching process.

[0035] The second step ( Fig. 21) is to remove the first insulating layer 61, which remains at the bottom of the opening, by wet etching by using the same photoresist 104 as that used for dry etching the second insulating layer 62 as a mask, thus causing the opening to reach the surface of the epitaxial layer 2. Here, the wet etching process with buffered hydrofluoric acid (BHF) lasts six minutes, where NH4F:HF=10:1. The wet etching exhibits a high degree of isotropy; in addition, the side surfaces of the insulating layer 6 (first insulating layer 61 and second insulating layer 62) are subjected to etching. Therefore, the side surfaces of the insulating layer 6 are each inclined, as shown in Fig.9. Thus, the opening formed in the insulation layer 6 is shaped to be wide upwards. Meanwhile, the first insulation layer 61 has a lower etching rate than the second insulation layer 62 during the wet etching process. Therefore, the side surfaces of the second insulation layer 62 have a relatively smaller amount of inclination. This maintains high dimensional accuracy at the bottom of the opening of the insulation layer 6.

[0036] When the opening formed in the insulating layer 6 reaches the surface of the epitaxial layer 2, the anode region 12, which is the impurity diffusion region formed in the uppermost layer of the epitaxial layer 2, is exposed from the insulating layer 6. Then, the photoresist 104 is removed by O2 plasma ashing, an aluminum anode electrode (not shown) is formed on the epitaxial layer 2, and a aluminum cathode electrode (not shown) is formed on the back surface of the semiconductor substrate 1. This completes the diode.

[0037] In the embodiment, the step of forming the opening having a large width (2 mm × 2 mm or larger in dimension) in the thick (0.5 μm or larger in thickness) insulating layer 6 is performed by removing the second insulating layer 62 so that the first insulating layer 61 is not removed by a half or less of the thickness of the insulating layer 6 by dry etching, which has a high ability of dimensional regulation, followed by removing the remainder of the second insulating layer 62 by wet etching, which does not remove the surface of the semiconductor substrate. This prevents variations in the removal amount of the surface of the impurity diffusion region under the opening while maintaining the high dimensional accuracy of the opening. The high dimensional accuracy provides a fine pattern with the insulating layer 6, thereby contributing to downsizing of the semiconductor device.Furthermore, the removal amount of the surface of the impurity diffusion region (anode region 12) is uniform, thereby reducing variations in the impurity concentration profile of the impurity diffusion region. Furthermore, the side surfaces of the insulating layer 6 are each inclined as a result of the wet etching process, thereby enabling the aluminum anode electrode to have improved coverage of the insulating layer 6.

[0038] In the description, the first example describes the MOSFET as an example of the semiconductor device, and the embodiment describes the pn junction diode. The present invention is widely applicable to a method of manufacturing a semiconductor device, the method comprising the step of forming a pattern of an insulating layer on a semiconductor substrate having an impurity diffusion region disposed in an uppermost layer of the semiconductor substrate. Furthermore, although the above descriptions employ SiC as a material of the semiconductor substrate, a material such as GaN, which has a crystal lattice constant similar to that of Si, achieves a similar effect.

[0039] It should be noted that in the present invention, the individual embodiments can be freely combined or appropriately modified and omitted within the scope of the invention.

[0040] Although the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations may be devised without departing from the scope of the invention. Explanation of reference symbols

[0041] 1 semiconductor substrate, 2 epitaxial layer, 3 well region, 4 source region, 5 contact region, 6 insulation layer, 61 first insulation layer, 62 second insulation layer, 7 gate insulation layer, 8 gate electrode, 9 interlayer insulation layer, 10 source electrode, 11 drain electrode, 12 anode region, and 101 to 104 photoresist.

Claims

[1] A method of manufacturing a semiconductor device, comprising the steps of: Forming an impurity diffusion region (3, 4, 5 / 12) in a semiconductor layer (2); Forming an insulating layer (6) having a thickness of 0.5 µm or greater on the semiconductor layer (2); Forming an etching mask (102 / 104) on the insulation layer (6); and Forming an opening, which reaches an upper surface of the semiconductor layer (2) and has a dimension of 2 mm × 2 mm or larger in a plan view, in the insulating layer (6) by etching using the etching mask (102 / 104) as a mask to expose at least a part of the impurity diffusion region (3, 4, 5 / 12) from the insulating layer (6), wherein the step of forming the opening comprises the steps Removing the insulating layer (6) so that half or less of a thickness of the insulating layer (6) is not removed by dry etching by using the etching mask (102 / 104) as a mask, and Removing the insulation layer (6) until the opening reaches the upper surface of the semiconductor layer (2) by wet etching using the etching mask (102 / 104) as a mask, wherein the insulation layer (6) has a first insulation layer (61) composed of a silicon oxide layer, and a second insulation layer (62) composed of a silicon nitride layer disposed on the first insulation layer (61) and thicker than the first insulation layer (61), wherein the step of forming the opening is carried out by removing the second insulation layer (62) in the dry etching and by removing the first insulation layer (61) in the wet etching, wherein the second insulation layer (62) has a higher selectivity with respect to the etching mask (102 / 104) during dry etching than the first insulation layer (61), and wherein the first insulation layer (61) has a lower etching rate during wet etching than the second insulation layer (62). [2] A method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the opening, the impurity diffusion region (3, 4, 5 / 12) exposed from the insulating layer (6) comprises a channel region of a transistor. [3] A method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer (2) is made of a material having a crystal lattice constant smaller than a crystal lattice constant of silicon. [4] A method of manufacturing a semiconductor device according to claim 3, wherein the semiconductor layer (2) is made of silicon carbide or gallium nitride.

Images