Method for lapping a semiconductor wafer

Abstract

A method for lapping a semiconductor wafer (W), wherein, while a solution containing abrasive grains is supplied to a gap between an upper plate (10A) and a lower plate (10B) facing each other, a carrier plate (20) on which a plurality of semiconductor wafers including the semiconductor wafer (W) are loaded is caused to perform a planetary motion, thereby lapping a front surface and a rear surface of the semiconductor wafer (W), and comprising: a start step of initiating the lapping of the semiconductor wafer (W); a stop step of stopping the lapping of the semiconductor wafer (W); a reversal step of reversing the surfaces of the semiconductor wafer (W) facing the upper plate (10A) and the lower plate (10B) after the stop step;and a continuation step of continuing the lapping of the semiconductor wafer (W) after the reversal step, while maintaining the reversal of the surfaces facing the plates (10A, 10B), wherein a diameter of the upper plate (10A) and the lower plate (10B) is greater than a diameter of the semiconductor wafer (W), and wherein the reversal step is performed when a lapping quantity is 40% or more and 60% or less with respect to a target lapping quantity.

Description

TECHNICAL FIELDThis disclosure relates to a method of lapping a semiconductor wafer.BACKGROUNDSilicon wafers and compound semiconductor wafers made of GaAs, etc. are known as semiconductor wafers. Semiconductor wafers are typically obtained by performing a cutting step of cutting a single crystal ingot into thin disk-shaped wafers using a wire saw, a lapping step of causing flat front and back surfaces and a predetermined thickness of the disk-cut wafer, and a polishing step of performing mirror polishing for eliminating irregularities on the surfaces of the wafer after lapping to achieve high flatness. It is noted that a double-wheel grinding step of the mechanical grinding may be performed instead of or in addition to the lapping step.In recent years, "nanotopography" which is a parameter of wavy components on a surface of a wafer (SEMI Standard M43) has been given importance particularly for semiconductor wafers having large diameters. Nanotopography refers to signs of irregularities observed on a surface of a semiconductor wafer having spatial wavelength components of approximately 0.2 mm to 20 mm, and this is expressed using the height difference in a range of a predetermined size. The nanotopography of a semiconductor wafer is obtained by optical measurement using optical interferometry in a state where the semiconductor wafer has been mirror polished. It is considered that corrugations caused due to machining in, for example, the above-described cutting step, lapping step, and double-disc grinding step may deteriorate the nanotopography of the semiconductor wafer.Here, a typical process of lapping a semiconductor wafer according to conventional techniques will be described with reference to FIG. 1. As schematically illustrated in FIG. 1, a semiconductor wafer W is loaded into a mounting hole 20 aof each carrier plate 20. The support plates 20 are placed between an upper plate 10A and a lower plate 10B placed to face each other and rotated in opposite directions. The shapes of gears are not shown in the drawing for brevity; an external gear 20b of each carrier plate meshes with a sun gear 11 and an internal gear 12. Due to the meshing of the gears, when the lower plate 10B is rotated while each carrier plate 20 is revolving around the sun gear 11, the carrier plate 20 itself is rotated, thus achieving planetary motion accordingly. Further, while supplying a solution (not shown) containing abrasive grains, the semiconductor wafers W are compressed by the upper plate 10A and the lower plate 10B, thus lapping the front and back surfaces of the semiconductor wafers W accordingly. Note that the lapping is usually finished after lapping is performed for a predetermined time or after it is confirmed that removal of a target amount of material by lapping is achieved by, for example, measuring the thickness of the semiconductor wafer.For example, JP 2001-260 015 A discloses a method of lapping a semiconductor wafer, including a step of preparing a base plate having a thickness approximately equal to a predetermined thickness of a lapped semiconductor wafer and a step of ending lapping of the semiconductor wafer when contact of the top plate and the base plate is detected. The lapping method disclosed in JP 2001-260 015 A can further increase (i.e., further smoothen) flatness of a semiconductor wafer that has been lapped.CN 1 787 181 A discloses a method of lapping a semiconductor wafer with a carrier plate which performs a planetary motion and a reversing step.Further methods for processing semiconductor wafers are known from JP 2011-009 735 A, JP 2010-010 358 A, JP 2002-280 332 A and JP 2006-100 799 A.SUMMARY(Technical Problem)In evaluating a nanotopography map obtained by measuring the nanotopographys of a surface of a silicon wafer prepared by slicing, lapping, and polishing, the inventors of this disclosure have confirmed that an annular pattern has been observed in the periphery of the silicon wafer (see FIG. 2A ). The nanotopography map represented in FIG. 2A was obtained using WaferIght 3 manufactured by KLA-Tencor Corporation. In the nanotopography map in FIG. 2A, bright regions correspond to raised regions and dark regions correspond to recessed regions. In the example of FIG. 2A, an annular recessed pattern is observed in the periphery of approximately 20 mm to 30 mm from the wafer edge to the wafer center. A schematic cross-sectional view of a silicon wafer corresponding to the nanotopography map shown in FIG. 2A is shown in FIG. 2B. On the other hand, the inventors have found that there were cases where an annular raised pattern was found in the periphery of a similar region in a nanotopography map, in contrast to the example of FIG. 2A.The inventors have conducted diligent studies to find the cause of formation of such a ring pattern in a nanotopography map. As a result, it was found that the geometric profile of a semiconductor wafer that was polished has a strong correlation with the profile of the nanotopography of the wafer that was polished after the lapping. The present inventors have focused on this fact. They have studied the effects of machining lapping on the nanotopography profile. Note that the geometric profile of a semiconductor wafer here refers to the height profile of the central position in the thickness of the semiconductor wafer in the radial direction of the semiconductor wafer (silicon wafer) (a broken line in FIG. 2B ) with respect to a reference plane as illustrated in FIG. 2. In the example of FIG. 2B, the semiconductor wafer is curved upward in such a direction that the center of the wafer is increased as a whole; however, the thickness of the semiconductor wafer is constant in the radial direction. Inflection points are found in the geometric profile of the semiconductor wafer near the edges of the semiconductor wafer.Here, FIGS. 3A to 4B are schematic views illustrating the arrangement of the plates, support plates and semiconductor wafers in lapping the lapping process described with reference to FIG. 1. FIGS. 3A and 3B are schematic views of a state in which the semiconductor wafers W are farthest from the center of the plates (the upper plate 10A and the lower plate 10B), and FIGS. 4A and 4B are schematic views of a state in which the semiconductor wafers W are closest to the center of the plates (the upper plate 10A and the lower plate 10B). Note that FIGS. 3A and 4A are plan views in which the upper plate is imaginaryly removed. FIG. 3B is a cross-sectional view corresponding to FIG. 3A taken along line I-I, and FIG. 4B is a cross-sectional view corresponding to FIG. 4A taken along line II-II.The upper plate 10A and the lower plate 10B are originally flat when installed in a lapping apparatus. However, the inventors found that the shapes of the upper plate 10A and the lower plate 10B were deformed after the lapping of semiconductor wafers was repeated. The shapes of the upper plate 10A and the lower plate 10B that have been deformed are schematically illustrated in FIGS. 3B and 4B. For the upper plate 10A, in the radial cross-sectional view thereof, a central part between the sun gear 11 side and the internal gear 12 side (see also FIG. 1 ) has a recessed shape, and locally raised regions are formed on both the sun gear 11 side and the internal gear 12 side. In contrast to the upper plate 10A, for the lower plate 10B, in the radial cross-sectional view thereof, a central part between the sun gear 11 side and the internal gear 12 side has an elevated shape, and recessed portions are formed on both the sun gear 11 side and the internal gear 12 side. The irregularities of the upper plate 10A and the lower plate 10B substantially match each other.The upper plate 10A and the lower plate 10B are deformed into shapes as schematically illustrated in FIGS. 3B and 4B. Accordingly, as illustrated in FIG. 3B, when the semiconductor wafers W are away from the center of the plates (i.e., when the wafers are closer to the internal gear) while a relatively strong pressing force F S is applied to portions of the plates on the internal gear 12 side, a relatively weak pressing force F W is applied to portions of the plates on the sun gear 11 side. Further, as illustrated in FIG. 4B, when the semiconductor wafers W are closer to the center of the plates (i.e., when the wafers are closer to the sun gear) while a relatively weak pressing force F W is applied to portions of the plates on the internal gear 12 side, a relatively strong pressing force F S is applied to portions of the plates on the sun gear 11 side.During lapping, such unbalanced compressive forces are applied to the semiconductor wafers. Therefore, undulations caused due to machining are left on the semiconductor surfaces and the undulations cannot be sufficiently removed even by the subsequent polishing step. The inventors have considered that this results in the ring-shaped raised pattern or the recessed pattern observed when the nanotopography map was obtained. In conventional techniques, it has been considered that undulations caused due to machining by lapping are sufficiently removed by a polishing step performed after a lapping step. However, the nanotopography quality is attracting more attention in recent years, and there will be an increased demand for semiconductor wafers for which neither an annular recessed pattern nor an increased pattern is observed in the evaluation using a nanotopography map.Under these circumstances, it may be helpful to provide a method of lapping a semiconductor wafer that can suppress formation of an annular pattern in a nanotopography map.(Solution of Problem)With a view to achieving the above object, the inventors have intensively studied. The inventors have considered reversing the plate-facing surfaces of semiconductor wafers while temporarily stopping lapping to reduce undulations caused due to the shape of the plates. The inventors have accordingly found that, in semiconductor wafers subjected to such inversion, formation of an annular pattern in a nanotopography map after polishing can be suppressed. The discovery has led to this disclosure.In particular, we propose the following features. (1) A method for lapping a semiconductor wafer in which, while supplying a solution containing abrasive grains to a gap between an upper plate and a lower plate placed facing each other, a support plate on which a plurality of semiconductor wafers including the semiconductor wafer are loaded is caused to perform planetary motion, thereby lapping a front surface and a back surface of the semiconductor wafer includes:a start step of starting lapping of the semiconductor wafer;a stopping step of stopping lapping of the semiconductor wafer;a reversing step of reversing surfaces of the semiconductor wafer facing the upper plate and the lower plate after the stopping step; anda continuing step of continuing lapping of the semiconductor wafer after the reversing step while maintaining the reversal of the plate facing surfaces,wherein the reversing step is performed when a lapping amount is 40% or more and 60% or less with respect to a target lapping amount. (2) The method for lapping a semiconductor wafer according to (1) above, wherein the semiconductor wafer is a silicon wafer.Thereby, a mirror-polished semiconductor wafer not claimed per se can be produced for which neither an annular recessed pattern nor an annular raised pattern is observed on a surface of the semiconductor wafer by nanotopography map evaluation.The term "nanotopography map evaluation" herein refers to an evaluation of whether an annular recessed pattern or raised pattern is observed in the periphery of a semiconductor wafer in a nanotopography map obtained by measuring the height profile (height difference) of a mirror-finished surface of the semiconductor wafer with the use of a flatness measurement system using optical interferometry (WaferIght 3, manufactured by TLA-Tencor Corporation). Specifically, long wavelength components are removed from a measurement result of the height of a semiconductor wafer which has been mirror-polished by filtering using a double Gaussian filter having a cut-off wavelength of 20 mm, and it is then determined whether an annular pattern is formed from a nanotopography map in which the measurement results of a nanotopography are graphically expressed as light and shadows. In this nanotopography map, darker colors indicate lower heights and the darkest part corresponds to -20 nm from the central height, whereas the lighter colors correspond to higher heights and the brightest part corresponds to +20 nm from the central height. Accordingly, the height difference between the lowest height and the highest height is 40 nm. Note that when the nanotopography map is to be obtained, the front and back surfaces of the semiconductor wafer are held to be vertical surfaces, and three given points are fixed in the periphery of the semiconductor wafer to measure the semiconductor wafer surfaces. Accordingly, the nanotopography map represents the height difference of a surface of a semiconductor wafer that is not held by suction. Specifically, in a cross section of a nanotopography map, a ring pattern is not observed when the difference between the average height of a surface center region of a semiconductor wafer and the average height of a surface periphery region of the semiconductor wafer surrounding the surface center region is 1 nm or less.A diameter of the semiconductor wafer may be 300 mm or more.The semiconductor wafer may be a silicon wafer.(Advantageous Effect)This disclosure provides a method for lapping a semiconductor wafer that can suppress formation of an annular pattern in a nanotopography map.BRIEF DESCRIPTION OF THE DRAWINGSIn the accompanying drawings, the following applies: FIG. 1 is a schematic view illustrating a method of lapping a semiconductor wafer according to conventional techniques; FIG. 2A is a diagram illustrating an example of a nanotopography map of a silicon wafer observed by the inventors, and FIG. 2B is a schematic cross-sectional view corresponding to the nanotopography map presented in FIG. 2A, along the radial direction of the silicon wafer; FIGS. 3A and 3B are schematic views illustrating the arrangement of upper and lower plates, support plates and semiconductor wafers when the semiconductor wafers are lapped, the arrangement having been studied by the inventors, wherein FIG. 3A is a plan view and FIG. 3B is a cross-sectional view thereof taken along the line I-I; FIGS. 4A and 4B are schematic views illustrating the arrangement of upper and lower plates, support plates and semiconductor wafers when the semiconductor wafers are lapped, the arrangement having been studied by the inventors, wherein FIG. 4A is a plan view and FIG. 4B is a cross-sectional view thereof taken along the line II-II; FIG. 5 is a process flow diagram illustrating a method of lapping a semiconductor wafer according to an embodiment of the disclosure; FIG. 6 represents graphs illustrating the geometric wafer profile and the nanotopography profile and nanotopography maps of Conventional Example 1, Examples 1, and 2 in EXAMPLES; and FIG. 7 represents graphs illustrating the geometric wafer profile and the nanotopography profile and nanotopography maps of Examples 3 to 5 in EXAMPLES.DETAILED DESCRIPTIONA method of lapping a semiconductor wafer according to an embodiment of this disclosure will now be described with reference to the drawings. Note that the thickness of each component in the drawings is exaggerated for convenience of description, and the thickness ratio of the illustrated components does not correspond to the actual thickness ratio.(Method of Lapping a Semiconductor Wafer)In a method for lapping a semiconductor wafer according to an embodiment of this disclosure, as schematically illustrated in FIG. 1, while supplying a solution (not shown) containing abrasive grains to a gap between the upper plate 10A and the lower plate 10B placed facing each other, the support plates 20 on which the semiconductor wafers W are loaded are caused to perform planetary motion, thereby lapping the front and back surfaces of each semiconductor wafer W. Further, as illustrated in FIG. 5, the method for lapping a semiconductor wafer according to this embodiment includes: a start step of starting lapping the semiconductor wafer W (step 5A of FIG. 5 ); a stop step of stopping lapping the semiconductor wafer W (step 5B of FIG. 5 ); a reversal step of reversing surfaces of the semiconductor wafer W facing the upper plate 10A and the lower plate 10B after the stop step (step 5C of FIG. 5 ); and a continuation step of continuing lapping the semiconductor wafer W after the reversal step while maintaining the reversal of the plate-facing surfaces (step 5D of FIG. 5 ). Accordingly, formation of an annular pattern in a nanotopography map can be suppressed. Note that FIG. 5 illustrates only the upper plate 10A, the lower plate 10B, and the semiconductor wafer W in the above steps. These steps are described in detail below in sequence.First, the start step of starting lapping of the semiconductor wafer W (step 5A of FIG. 5 ) is performed. In this starting step, as schematically illustrated in FIG. 1, the semiconductor wafer W is loaded into the mounting hole 20 aof each carrier plate 20 as in the conventional techniques. The support plates 20 on which the semiconductor wafers W are loaded are placed between the upper plate 10A and the lower plate 10B placed facing each other. The upper plate 10A and the lower plate 10B are rotated in opposite directions, and when the carrier plate external gear 20 bis meshed with the sun gear 11 and the internal gear 12 while the carrier plate 20 is revolving around the center of the carrier plate 20 (hereinafter referred to as "revolution"), the carrier plate 20 is rotated around the center of the upper plate 10A and the lower plate 10B around the sun gear 11 (hereinafter referred to as "rotation"). Such a revolving and rotating movement of the carrier plates 20 is referred to as planetary movement. In this step, while causing the support plate 20 itself to perform planetary motion, a solution (not shown) containing abrasive grains is supplied and the semiconductor wafer W is compressed by the upper plate 10A and the lower plate 10B to start lapping the front and back surfaces of the semiconductor wafer W. Note that the amount of material removed by lapping increases with lapping time after the start of lapping.Next, the stopping step of stopping lapping of the semiconductor wafer W (step 5B of FIG. 5 ) is performed. For example, when the supply of the abrasive grain-containing solution is stopped, the rotation of the upper plate 10A and the lower plate 10B can be stopped in the same manner as the stopping of lapping in the conventional lapping method. The time from the previous start step (step 5A of FIG. 5 ) to the stop of lapping in this step (step 5B of FIG. 5 ) can be arbitrarily determined, and the stop step, the reversal step, and the continuation step of this embodiment are sequentially performed, whereby the advantageous effects of this disclosure can be obtained accordingly.In this embodiment, the reversing step is preferably performed when the amount of material removed by lapping (hereinafter referred to as "lapping amount") is 40% or more and 60% or less with respect to a target lapping amount. Note that here, the "target lapping amount" corresponds to the total amount of material to be removed by the lapping method of this embodiment. Here, the stopping step after the starting step is preferably performed when a lapping amount of 40% or more and 60% or less with respect to the target lapping amount is achieved, more preferably when a lapping amount of 45% or more and 55% or less with respect to the target lapping amount is achieved. In this way, the reversing step can be performed immediately after the stopping step when a desired lapping amount is reached. When the target lapping amount is controlled by one lapping time, the stopping step may be performed after elapse of 40% or more and 60% or less of the total lapping time, or the stopping step may be performed after elapse of 45% or more and 55% or less of the total lapping time. Accordingly, as described with reference to FIGS. 3A to 4B, machining effects caused due to the shape of the upper plate 10A and the lower plate 10B and the planetary motion of the semiconductor wafers W loaded on the carrier plates 20 can be more reliably reduced. Accordingly, a peak-to-valley (P-V) value of the wafer shape in the radial direction of the semiconductor wafer W in a state after lapping before performing polishing may be 0.51 μm or less, or the P-V value may be even 0.26 μm or less. The P-V value of the wafer shape in the radial direction means the difference between the maximum value (peak) and the minimum value (valley) of the geometric profile of the semiconductor wafer W obtained when the semiconductor wafer W is scanned from one end to the other end in the diameter direction.After stopping lapping of the semiconductor wafer W, the reversing step of reversing the surfaces of the semiconductor wafer W (surfaces Wa and Wb) facing the upper plate 10A and the lower plate 10B (step 5C of FIG. 5 ) is performed as described above. This reversing step will be described more specifically with reference to Figs. 5A to 5C. As illustrated in FIGS. 5A and 5B, after starting lapping until stopping lapping, the surface of the semiconductor wafer W facing the upper plate 10A is the surface Wa and the surface of the semiconductor wafer W facing the lower plate 10B is the surface Wb. In this step, the surface Wa and the surface Wb are reversed with respect to the upper plate 10A and the lower plate 10B. Accordingly, this step makes the surface of the semiconductor wafer W facing the upper plate 10A the surface Wb and makes the surface of the semiconductor wafer W facing the lower plate 10B the surface Wa.In this reversing step, the surfaces of the semiconductor wafer W facing the wafers can be reversed by a given method. For example, the semiconductor wafer W loaded on the carrier plate 20 may be lifted using a known holding mechanism such as a suction pad or a vacuum pad, the surfaces facing the plates may be reversed as described above, and the semiconductor wafer W may be loaded on the carrier plate 20 again.Finally, the continuing step of continuing lapping of the semiconductor wafer W while maintaining the inversion of the plate-facing surfaces (FIG. 5 ) is performed. In continuing the lapping, the lapping can be performed in the same manner as in the starting step. The lapping can be finished after the total of the lapping amount after continuation in this step and the lapping amount previously obtained by the start step and the stop step reaches the target lapping amount. Further, when the target lapping amount of material removed by lapping is controlled by lapping time, lapping can be finished after elapse of a remaining time determined from the total lapping time of lapping after continuation of lapping.As described above, effects of the pressing force for the resulting semiconductor wafer W due to the shape of the upper plate 10A and the lower plate 10B are reduced. Accordingly, effects of machining of lapping on semiconductor wafer surfaces can be reduced. Further, when a polishing step is performed on a semiconductor wafer subjected to lapping of this embodiment, an annular pattern is prevented from being formed when a nanotopography map is obtained.It is noted that the nanotopography can be measured using a measurement system commercially available from KLA-Tencor Corporation, RAYTEX CORPORATION, ADE Corporation, etc., according to SEMI standards M43 and M78. Further, in measuring the nanotopography, the polishing conditions for the polishing step performed after the lapping may be typical conditions. Further, in measuring nanotopography, cleaning and / or etching of semiconductor wafer surfaces and any other given steps between lapping and polishing may be performed. In addition, in this embodiment, after the start step, the stop step, the reversal step, and the continuation step may be repeated a plurality of times in this order, and lapping may be finished thereafter. In this case, the timing at which lapping is finished may be set appropriately depending on a target lapping amount.Specific aspects of this embodiment are described below; however, this disclosure is not limited to the specific examples described below.The lapping method of this embodiment can be applied to any given semiconductor wafer W and can be applied to a thin disk-shaped wafer obtained by slicing a single crystal ingot of, for example, silicon or a compound semiconductor such as GaAs using a wire saw. The lapping method of this embodiment is preferably applied to a silicon wafer for which excellent topography is necessary as the semiconductor wafer W.Although the size of the semiconductor wafer W is not limited, the lapping method of this embodiment is preferably applied to a large-diameter wafer. For example, the lapping method is preferably applied to a silicon wafer having a diameter of 300 nm or more, and more preferably applied to a silicon wafer having a diameter of 450 nm or more. Even for such a large-diameter silicon wafer, an annular pattern can be prevented from being formed in a nanotopography map after polishing by applying the lapping method of this embodiment.For the upper plate 10A, the lower plate 10B, and the support plates 20, those plates typically used for lapping can be used. For a abrasive grain-containing solution used for lapping, for example, a water-soluble solution obtained by mixing abrasive grains free from small particles, alumina-zirconium, etc. and a liquid such as water containing a use agent can be used.Further, although in FIGS. 1 to 4B, examples using five support plates are illustrated, the number of support plates is not particularly limited. In FIGS. 1 to 4B, a semiconductor wafer W is loaded on a carrier plate; alternatively, a plurality of semiconductor wafers W may be loaded on a carrier plate.In addition, drive units such as a motor and control units not shown may be naturally used.(Semiconductor wafer)A semiconductor wafer according to this disclosure is a mirror-polished semiconductor wafer, and neither an annular recessed pattern nor an annular raised pattern is observed on a surface of the semiconductor wafer by nanotopography map evaluation. A semiconductor wafer according to this embodiment can be produced by the above embodiment of a lapping process followed by mirror polishing using an ordinary method. For a semiconductor wafer according to conventional techniques, when nanotopography map evaluation is performed after mirror polishing, an annular recessed pattern or raised pattern is observed in a surface of the semiconductor wafer. However, using the lapping method of the above embodiment, a semiconductor wafer for which no ring-shaped pattern is observed by nanotopography map evaluation can be produced.Further, in a cross section of a nanotopography map of a mirror-polished semiconductor wafer, the difference between the average height of a surface center portion of a semiconductor wafer and the average height of a surface periphery portion of the semiconductor wafer surrounding the surface center portion is preferably 1 nm or less, in which case it is ensured that no ring pattern is observed. Here, the regions of the surface center region and the surface periphery region are described more specifically for illustration. When the diameter of a semiconductor wafer is 450 mm (radius 225 mm), a region extending 160 mm from the center of the semiconductor wafer is regarded as a surface center region, and a region 160 mm to 200 mm from the center of the semiconductor wafer is regarded as a surface peripheral region of the semiconductor wafer.Further, the semiconductor wafer preferably has a diameter of 300 mm or more, and more preferably has a diameter of 450 mm or more. In addition, the semiconductor wafer is preferably a silicon wafer. Even in the case of a large-diameter silicon wafer, a silicon wafer for which no ring-shaped pattern is observed by nanotopography map evaluation can be obtained using the lapping method of the above embodiment.EXAMPLESNext, examples are given below to clarify the effects of this disclosure; however, this disclosure is in no way limited to those examples.(Example 1)A 450 nm diameter silicon wafer was lapped according to the above-described structure of Fig. 1 and the process flow chart presented in Fig. 5. Specifically, silicon wafers having a diameter of 450 nm obtained by slicing a single crystal silicon ingot were loaded on each support plate, and the support plates were placed between an upper plate and a lower plate of a lapping apparatus. The total lapping time by which a target lapping amount should be achieved was previously determined.First, lapping of the silicon wafer was started and lapping was stopped after a lapse of 35% of the total lapping time. After stopping lapping, the silicon wafer was removed from the support plate using a suction pad, the surfaces of the silicon wafer facing the upper plate and the lower plate were reversed, and the silicon wafer was loaded on the support plate. In other words, the reversing step was performed when the lapping amount was 35% with respect to the target lapping amount. Next, lapping was continued and lapping was finished after a lapse of a remaining time determined from the total lapping time (i.e., 65% of the total lapping time).(Examples 2 to 5)Silicon wafers having a diameter of 450 mm were lapped in the same manner as in Example 1, except that the lapping time from the start of lapping until lapping should be stopped was changed to 40%, 50%, 60%, and 65% of the total lapping time. Accordingly, in Examples 2 to 5, a reverse step was performed when the lapping amount had reached 40%, 50%, 60%, and 65% with respect to the target lapping amount, respectively.(Conventional Example 1)A silicon wafer having a diameter of 450 mm was lapped in the same manner as in Example 1 except that lapping was finished after a lapse of the total lapping time without stopping lapping. Accordingly, inversion of the silicon wafer and continuation of lapping were not performed in the conventional example 1.< 1: Geometric Evaluation>Silicon wafers subjected to lapping in Examples 1 to 5 and Conventional Example 1 were subjected to alkali etching (hereinafter abbreviated as "alkali ET") under the same conditions. Thereafter, graphs of the geometric profile in the radial direction of the silicon wafers (the direction indicated by the arrow in each nanotopography map corresponding to a cross section in the wire running direction, which prevents the effects of undulations caused by slicing) were obtained using a capacitive profile measurement system (SBW-451 / R manufactured by KOBELCO RESEARCH INSTITUTE, INC.). The results are presented in Figures 6 and 7. The P-V values of the geometric profiles are given in Table 1. In the graphs in FIGS. 6 and 7, the horizontal axis corresponds to the distance from the center of the wafer, and the height represents the relative values (a.u.). It is noted that the alkali ET mainly aims to clean the silicon wafers subjected to lapping and does not affect the P-V values of the geometrical profile of the silicon wafers subjected to measurements using the capacitive profile measurement system.< 2: Nanotopography Evaluation>The silicon wafers subjected to the lapping of Examples 1 to 5 and Conventional Example 1 were subjected to an alkali ET performed in Evaluation 1 above under the same conditions, and then were subjected to double-side polishing followed by mirror-polishing under the same conditions. The silicon wafers subjected to mirror polishing were subjected to measurement using a nanotopography measurement system (WaferIght 3, manufactured by KLA-Tencor Corporation) to obtain nanotopography maps of the wafer surfaces. Further, the nanotopography profiles in the radial direction (the direction indicated by the arrow in each nanotopography map corresponding to a cross section in the wire running direction, which prevents the effects of undulations caused by slicing) were also obtained. The results are presented in Figures 6 and 7. In the graphs in FIGS. 6 and 7, the horizontal axis corresponds to the distance from the center of the wafer. The height difference in nanotopography (NT) in the radial direction (the difference between the average height of a surface center portion and the average height of a surface periphery portion) is given in Table 1. Here, the surface center region refers to a region extending 160 mm from the center of each silicon wafer, and the surface periphery region is a region extending 160 mm to 200 mm from the center of each semiconductor wafer. [Table 1] Table 1] [Table 1] Table 1]Conventional Example 10,823,88No stopping and no reversingExample 10,512,61Stop and Reverse after 35% of the total lapping timeExample 20,260,80Stop and Reverse after 40% of the total lapping timeExample 30,190,39Stop and Reverse after 50% of the total lapping timeExample 40,210,43Stop and Reverse after 60% of the total lapping timeExample 50,341,92Stop and Reverse after 65% of the total lapping timeFIGS. 6 and 7 indicate that formation of an annular pattern in the nanotopography map in Examples 1 to 5 was suppressed as compared with Conventional Example 1. In particular, in Examples 2 to 4, no ring-shaped pattern was observed by nanotopography map evaluation. Further, it was confirmed that formation of an annular pattern in the nanotopography is suppressed more reliably when the P-V value of the geometric profile after the alkali ET was 0.3 μm or less (specifically, 0.26 μm or less). In other words, it is ensured that no ring-shaped pattern is observed in the nanotopography map when the height difference of the NT in the cross section after polishing is 1 nm or less (specifically, 0.80 nm or less).INDUSTRIAL APPLICABILITYThis disclosure provides a method for lapping a semiconductor wafer that can suppress formation of a ring-shaped pattern in a nanotopography map, which is useful in the semiconductor industry.LIST OF REFERENCE CHARACTERS10A upper plate 10B lower plate 11 sun gear 12 internal gear 20 carrier plate W semiconductor wafer

Claims

A method for lapping a semiconductor wafer (W) in which, while a solution containing abrasive grains is supplied to a gap between an upper plate (10A) and a lower plate (10B) placed facing each other, a carrier plate (20) on which a plurality of semiconductor wafers including the semiconductor wafer (W) are loaded is caused to perform planetary motion, thereby lapping a front surface and a back surface of the semiconductor wafer (W), and comprising: a start step of starting lapping the semiconductor wafer (W); a stop step of stopping lapping the semiconductor wafer (W); a reversing step of reversing surfaces of the semiconductor wafer (W) facing the upper plate (10A) and the lower plate (10B) after the stopping step; and a continuing step of continuing lapping of the semiconductor wafer (W) after the reversing step while maintaining the reversal of the surfaces facing the plates (10A, 10B), wherein a diameter of the upper plate (10A) and the lower plate (10B) is larger than a diameter of the semiconductor wafer (W), and wherein the reversing step is performed when a lapping amount is 40% or more and 60% or less with respect to a target lapping amount.The method for lapping a semiconductor wafer (W) according to claim 1, wherein the semiconductor wafer (W) is a silicon wafer.

Images