Protective passivation layer for magnetic tunnel transitions

Abstract

Magnetic device comprising the following: (a) a magnetic tunnel junction, MTJ (11a) having a side wall (11s1) extending from its top (11t1) to its bottom, the bottom contacting a lower electrode (10a) and the top contacting an upper electrode (14a); (b) a passivation layer (12) which is non-magnetic and has a double-layer or other multi-layer configuration comprising: (1) a lower layer which contacts the MTJ sidewall between the upper electrode and the lower electrode and comprises B, C or Ge; (2) a second layer formed on the lower layer comprising an alloy containing a first element that is one of B, C or Ge and at least one second element that is not the same as the first element; and (c) a dielectric layer (13) formed on the non-magnetic passivation layer, wherein the dielectric layer electrically insulates the MTJ from neighboring MTJs; where the bottom layer is B, C or Ge and the second layer is a BX, CX or GeX alloy, where X is one of B, C, Ge, Si, Al, P, Ga, In, Tl, Mg, Hf, Zr, Nb, V, Ti, Cr, Mo, W, Sr and Zn, such that a B / BX, C / CX or Ge / GeX double layer configuration is obtained for the passivation layer, or where the bottom layer is B, C or Ge and the second layer is oxygen, nitrogen or includes both oxygen and nitrogen, and has a BO, CO, GeO, BN, CN, GeN, BON, CON, or GeON composition, such that a B / BO, B / BN, C / CO, C / CN, Ge / GeO, Ge / GeN, B / BON, C / CON, or Ge / GeON bilayer configuration is obtained for the passivation layer; or the second layer further contains oxygen, nitrogen, or both oxygen as also includes nitrogen and has a BXO, CXO, GeXO, BXN, CXN, GeXN, BXON, CXON or GeXON composition, such that a B / BXO, C / CXO, Ge / GeXO, B / BXN, C / CXN, Ge / GeXN, B / BXON, C / CXON or Ge / GeXON bilayer configuration is obtained for the passivation layer; or The device further comprises a third layer, which is located on top of the second layer. is formed, and the third layer has a BXO, CXO, GeXO, BXN, CXN, GeXN, BXON, CXON or GeXON composition, such that a B / BX / BXO, C / CX / CXO, Ge / GeX / GeXO, B / BX / BXN, C / CX / CXN, Ge / GeX / GeXN, B / BX / BXON, C / CX / CXON or a Ge / GeX / GeXON three-layer configuration for the passivation layer is obtained.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to magnetic tunnel junctions (MTJs) in magnetic direct access memory (MRAM), spin-torque MRAM, and other spintronic devices, and more particularly relates to protecting MTJ sidewalls during processing steps including the deposition of an insulating dielectric layer separating adjacent MTJs and during a high-temperature anneal at about 400°C, as is common in complementary metal oxide semiconductor (CMOS) manufacturing. BACKGROUND

[0002] An MTJ is a key component in MRAM, spin-torque MRAM, and other spintronic devices. It comprises a stack with a tunneling barrier layer, such as a metal oxide, sandwiched between two magnetic layers, creating a tunneling magnetoresistance (TMR) effect. One of the magnetic layers is a free layer and acts as a sensing layer by switching the direction of its magnetic moment in response to external fields, while the second magnetic layer has a fixed magnetic moment and serves as a reference layer. The electrical resistance through the tunneling barrier layer (insulator layer) varies with the relative orientation of the free layer moment compared to the reference layer moment, thereby generating an electrical signal representative of a magnetic state in the free layer.In an MRAM, the MTJ is formed between a top conductor and a bottom conductor. When a current is passed through the MTJ, a lower resistance is detected when the magnetization directions of the free layer and the reference layer are in a parallel state, and a higher resistance is detected when they are in an antiparallel state. Since MTJ elements are often integrated into CMOS devices, the MTJ must be able to withstand annealing temperatures of approximately 400°C for approximately 30 minutes, which is commonly used to improve the quality of CMOS devices for semiconductor applications.

[0003] MTJ elements in which the free layer (FL) and reference layer (RL) exhibit perpendicular magnetic anisotropy (PMA) are preferred over their counterparts using in-plane anisotropy because a PMA MTJ offers the advantage of lower write current while maintaining thermal stability and better scalability. In MTJs with PMA, the FL has two preferred magnetization orientations perpendicular to the physical plane of the layer. Without external influence, the magnetic moment of the free layer aligns in one of the two preferred directions, representing the information "1" or "0" in the binary system.For memory applications, the FL magnetization direction is expected to be maintained during a read operation and idle state, but to reverse during a write operation if the new information to be stored differs from its current storage state. CoFeB or the like is commonly used as the FL and RL, and MgO is preferred as the tunneling barrier for generating PMA along the RL / MgO and MgO / FL interfaces in an RL / MgO / FL stack.

[0004] Spin-torque (STT) MRAM-based technologies are suitable for non-volatile memory applications. However, achieving low critical dimensions below 100 nm, consistent with those found in dynamic random access memory (DRAM), presents a challenge. MTJs are highly susceptible to sidewall damage, both chemical and physical, caused by etching and deposition processes and exacerbated by the CMOS process requirement of 400 °C annealing.

[0005] During the fabrication of a conventional STT-MRAM device, where a dielectric layer is deposited on MTJ sidewalls to isolate the MTJs from neighboring MTJs in the STT-MRAM array, the MTJ sidewalls are often damaged. Damage can occur, for example, due to oxygen diffusion through an MTJ sidewall during the deposition of an oxide dielectric layer, causing a significant portion of the MTJs to become oxidized. In some cases, metal from an MTJ cap layer can be redeposited on MTJ sidewalls to create a shunt around the tunnel junction or electrical shorts. As a result, device performance degrades; significant inter-bit non-uniformity develops, resulting in an unnecessarily large distribution of critical data; and device production yield decreases.Reducing sidewall damage is particularly important at the CoFeB / MgO (RL / tunnel barrier and tunnel barrier / FL) interfaces, which generate interfacial PMA. Furthermore, it is well known that the fragile nature of the MgO tunnel barrier layer results in poor corrosion properties and rapid degradation when exposed to the atmosphere during deposition of the insulating dielectric layer.

[0006] Although methods are available to remove sidewall damage caused by ion bombardment and atmospheric exposure during dielectric layer deposition, these methods are generally time-consuming and expensive. Furthermore, some sidewall damage may be prohibitively expensive to repair. There is a need to prevent MTJ sidewall damage by providing a means to protect the MTJ element during subsequent processing steps in memory device fabrication.

[0007] US 2016 / 0 163 971 A1 describes a method for manufacturing a magnetic memory device having a lower magnetic layer, a tunnel barrier, and an upper magnetic layer on a substrate. A magnetic tunnel junction pattern is formed by etching a stacked structure including the lower magnetic layer, the tunnel barrier, and the upper magnetic layer, a boron absorption layer is formed covering the magnetic tunnel junction pattern, and a heat treatment process is performed so that boron contained in the upper and lower magnetic layers can be absorbed by the boron absorption layer. The heat treatment process can be performed in a gaseous atmosphere containing at least one of hydrogen, oxygen, and nitrogen.

[0008] US 2013 / 0 001 652 A1 describes a magnetoresistive element comprising a storage layer with a variable and perpendicular magnetization, a tunnel barrier layer on the storage layer, a reference layer with a fixed and perpendicular magnetization on the tunnel barrier layer, a hard mask layer on the reference layer, and a sidewall spacer layer on the sidewalls of the reference layer and the hard mask layer. The sidewall spacer layer contains a material selected from a group consisting of diamond, DLC, BN, SiC, B4C, Al2O3, and AlN.

[0009] US Pat. No. 9,166,151 B2 describes a magnetoresistive element comprising a magnetic layer, an insulating layer, and a magnetic layer laminated onto a base electrode, wherein sidewalls of the magnetic layers are formed when the magnetic layers are processed. At least one element selected from the group consisting of He, C, N, O, F, Ne, Ti, V, Cu, Al, Si, P, S, Cl, Ar, Ge, As, Kr, Zr, In, Sn, Sb, Pb, and Bi is injected into the sidewalls and edge portions of the magnetic layers to improve the magnetic properties of the magnetic layers.

[0010] US 2016 / 0 013 397 A1 discloses a magnetoresistive effect element comprising: a recording layer having magnetic anisotropy and a variable magnetization direction, a reference layer having magnetic anisotropy and a fixed magnetization direction, an intermediate layer between the recording layer and the reference layer, an underlayer containing scandium (Sc) and arranged on a surface side of the recording layer opposite to a surface side on which the recording layer is arranged, and a sidewall layer containing an oxide of Sc and arranged on side surfaces of the recording layer and the intermediate layer. SHORT DESCRIPTION

[0011] An object of the present disclosure is to substantially improve the resistance of an MTJ to sidewall damage during etch, deposition and anneal processes in the fabrication of memory devices.

[0012] A second object of the present disclosure is to provide a method for achieving MTJ integrity improvement according to the first object that is compatible with Back End Of Line (BEOL) CMOS processes.

[0013] Provides a magnetic device according to claim 1, and a method according to claim 4. Embodiments are specified in the dependent claims.

[0014] According to the invention, the deposition of a protective passivation layer on an MTJ sidewall during the fabrication of a memory device is provided. The passivation layer can be sputtered using an RF magnetron or can be formed by an atomic layer deposition (ALD) technique, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process. According to a preferred embodiment, the passivation layer is a single layer of B, C, or Ge sputtered using an RF power of about 100 to 1000 watts in the absence of reactive species such as nitrogen- and oxygen-containing gases and plasmas. The passivation layer has a thickness of at least 0.3 nm (3 angstroms) to enable continuous deposition. Preferably, the passivation layer is amorphous rather than crystalline to prevent diffusion of reactive materials between crystals in a lattice.

[0015] In another embodiment, an oxidation process such as natural oxidation (NOX) is used to partially or completely oxidize a B layer to a BO passivation layer, a C layer to a CO passivation layer, or a Ge layer to a GeO passivation layer. Alternatively, a B, C, or Ge layer is deposited in a first step and is then subjected to a nitriding or oxynitriding process to form a BN, CN, GeN, BON, CON, or GeON passivation layer, respectively, having a non-stoichiometric or stoichiometric N content. Depending on the conditions used in the previous oxidation process, a B / BO bilayer, a C / CO bilayer, or a Ge / GeO bilayer may be formed.In another embodiment, a B, C, or Ge passivation layer reacts with oxygen species during the deposition of a dielectric layer and is partially or completely oxidized to a BO, CO, or GeO passivation layer.

[0016] In another embodiment, a passivation layer comprising an alloy can be produced by a two-step deposition sequence. In particular, an alloy having a BX, CX, or GeX composition is formed by a first step of depositing a B, C, or Ge layer followed by a second step of depositing an X element, where X is one of B, C, Ge, Si, Al, P, Ga, In, Tl, Mg, Hf, Zr, Nb, V, Ti, Cr, Mo, W, Sr, and Zn, and where X is different from the other element in the alloy. In other words, the initially deposited B, C, or Ge layer serves as a sacrificial material and is completely resputtered during X deposition, combining with the X element to form an alloy. Preferably, B in BX, C in CX, and Ge in GeX have a content of at least 10 atomic %.

[0017] According to another embodiment, the previously described two-step deposition follows. However, during the second step, which includes the X-deposition, only an upper (outer) portion of the first B, C, or Ge passivation layer is re-sputtered to form a second passivation layer comprising BX, CX, or GeX, respectively, thereby creating a B / BX, C / CX, or Ge / GeX bilayer structure as a composite passivation layer. Here, the duration of the second deposition is shortened, or the process conditions during the X-deposition can be adjusted to, for example, use a weaker RF power to prevent the entire B, C, or Ge layer from being re-sputtered.

[0018] A two-step deposition process is advantageous in that the first step of depositing a B, C, or Ge layer effectively protects the MTJ sidewalls from reactive species such as oxygen. The second step of depositing an X-material to form either a bilayer or a single alloy layer serves primarily to prevent damage to the MTJ sidewalls by high-energy ions during subsequent processes, including the deposition of a dielectric layer.

[0019] In a further embodiment where two deposition steps are used to form a passivation layer, one or both of oxygen and nitrogen may be incorporated into the second deposition step. Thus, the present disclosure contemplates the formation of a bilayer such as B / BXO, C / CXO, Ge / GeXO, B / BXN, C / CXN, Ge / GeXN, B / BXON, C / CXON, or Ge / GeXON when an X-layer is deposited on a B, C, or Ge layer in the presence of a reactive species comprising one or both of an oxygen species and a nitrogen species. Furthermore, the oxide, nitride, and oxynitride layers may be a composite such that, for example, a BXO layer comprises BO and BX, BXN comprises BN and BX, or BXON comprises BON and BX.

[0020] In the completed memory structure, which may be an MRAM, STT-MRAM, or spin-torque oscillator (STO), there is an array of MTJ elements formed in multiple rows and columns on a substrate. In an MRAM or STT-MRAM application, the substrate includes a bottom electrode layer, wherein there are multiple lines, such that a bottom surface of each MTJ contacts a line. Each MTJ has a sidewall that, according to an embodiment described herein, is covered with a protective passivation layer. Furthermore, there is a dielectric layer that contacts a top surface of the passivation layer and fills the spaces between adjacent MTJ elements. The dielectric layer may comprise one or more oxides, nitrides, oxynitrides, or carbides used in this technical field for the purpose of electrical insulation, and may have a top surface that is coplanar with a top surface of the MTJ.An upper electrode layer comprising a plurality of lines is formed on the array of MTJ elements such that each MTJ is formed between a lower electrode and an upper electrode.

[0021] In an STO device, the substrate may be a main pole layer serving as a bottom electrode, and the top electrode may be, for example, a back shield. A passivation layer is formed on a side of the STO layer stack facing away from an air-bearing surface (ABS). BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a memory structure having a passivation layer comprising a single element formed on MTJ sidewalls and with an overlying dielectric layer according to an embodiment of the present disclosure. Fig. 2-5 are cross-sectional views illustrating a sequence of steps for forming a memory structure having multiple MTJ elements with a single passivation layer, according to an embodiment of the present disclosure. Fig. 6-7 are cross-sectional views of a process that deposits the passivation layer in Fig. 3 into an oxide, nitride or oxynitride passivation layer, according to an embodiment of the present disclosure. Fig. 8-9 are cross-sectional views of a process, where an element X is in contact with the passivation layer in Fig. 3 to form a single alloy passivation layer, according to an embodiment of the present disclosure. Fig. 10-11 are cross-sectional views of a process where the single alloy passivation layer is Fig. 9 is subjected to an oxidation, nitriding or oxynitriding process, according to an embodiment of the present disclosure. Fig. 12 is a cross-sectional view of an embodiment described herein, wherein the process in Fig. 6 forms a two-layer structure for the passivation layer. Fig. Figure 13 is a cross-sectional view of an embodiment described herein, wherein the process in Fig. 8 forms a two-layer structure for the passivation layer. Fig. Figure 14 is a cross-sectional view of an embodiment described herein, wherein the two-layer structure in Fig. 13 is subjected to an oxidation, nitriding or oxynitriding process. Fig. 15-16 are cross-sectional views of an embodiment described herein wherein an element X in the presence of one or both of an oxygen and a nitrogen species is deposited onto the single passivation layer in Fig. 3 is sputtered to form a passivation layer with a two-layer structure. Fig. Figure 17 is a cross-sectional view of a passivation layer having a three-layer structure formed by the process in Fig. 14 is formed, according to an embodiment of the present disclosure. Fig. 18 is a plan view of the memory structure in Fig. 1, which includes a plurality of MTJ elements formed in rows and columns between a lower electrode layer and an upper electrode layer. Fig. 19 is a cross-sectional view of another embodiment of the present disclosure, wherein a memory structure includes a passivation layer formed on MTJ sidewalls, and the passivation layer has a dual-layer configuration. Fig. 20 is a cross-sectional view of another embodiment of the present disclosure, wherein a memory structure includes a passivation layer formed on MTJ sidewalls, and the passivation layer has a three-layer configuration. Fig. 21 is a cross-sectional view of another embodiment of the present disclosure wherein an STO device has a sidewall protected by a passivation layer and a dielectric layer is formed on the passivation layer. Fig. 22 is a graph of the magnetoresistive ratio (dR / R) as a function of MTJ size, showing a comparison of MTJs that do not have a protective passivation layer with MTJs that have a protective B passivation layer and are formed according to an embodiment of the present disclosure. Fig. 23 is a graph showing Hc as a function of MTJ size for MTJs that do not have a protective passivation layer and for MTJs that have a protective B passivation layer and are formed in accordance with an embodiment of the present disclosure. Fig. 24 is a graph showing tilt as a function of MTJ size for MTJs that do not have a protective passivation layer and for MTJs that have a protective B passivation layer and are formed according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] The present disclosure relates to the improved structural integrity of MTJ elements, particularly during processes involving deposition of dielectric layers between MTJ sidewalls and exposure to high temperatures of approximately 400°C. The MTJ elements can be formed in a variety of different memory devices, including, for example, MRAM, spin-torque MRAM, and other spintronic devices such as a spin-torque oscillator (STO). In the drawings, a thickness of a layer runs in the z-axis direction, a width runs in the x-axis direction, and a length runs in the y-axis direction. The terms "dielectric" and "insulation" may be used interchangeably.

[0023] As previously discussed, many memory devices today are integrated into CMOS platforms to achieve higher performance. However, we observe significantly more defects and degraded device performance when dielectric layers are deposited directly on MTJ sidewalls using conventional techniques and the resulting device is annealed at temperatures of approximately 400°C, as required in CMOS processing. This motivated us to implement a means of protecting MTJ elements to achieve higher performance and higher production yields for memory applications.

[0024] We turn Fig. 1, where a first embodiment of the present disclosure is shown, wherein a memory device comprises a plurality of MTJs, including MTJ-11a and MTJ-11b, which have sidewalls 11s1 and 11s2, respectively, and are protected by a passivation layer 12. MTJ-11a is formed between a bottom electrode 10a and a top electrode 14a, while MTJ-11b lies between the bottom electrode 10a and the top electrode 14b. In an MRAM or STT-MRAM embodiment, the bottom electrode is a line extending along the x-axis, and the top electrodes are lines extending in the y-axis direction. The bottom and top electrodes typically comprise one or more metals or one or more alloys to ensure excellent electrical conductivity and oxidation resistance. There is an insulating layer 15 formed on a substantial portion of the top surface 13t of the dielectric layer.Within the insulating layer, an upper electrode layer comprises a plurality of upper electrodes, including the upper electrodes 14a, 14b. Note that each of the upper electrodes may have a width w1 that is greater than a width of the upper surfaces 11t1 and 11t2. In other words, an inner portion of the upper electrodes may overlie the passivation layer 12 and an outer portion of the upper surface 13t that is close to the passivation layer.

[0025] It is understood that typically millions of MTJs are aligned in rows and columns in a memory array on a substrate, and each MTJ is formed between a bottom electrode and a top electrode. However, the number of Fig. 1 is limited to two to simplify the drawing. The MTJs can have a variety of different configurations, but each MTJ has at least one tunnel barrier layer formed between a reference layer (RL) and a free layer (FL) in an RL / tunnel barrier / FL or FL / tunnel barrier / RL stack on a substrate (not shown), which is, for example, a seed layer.

[0026] Preferably, the passivation layer 12 has a uniform thickness and not only contacts the MTJ sidewalls 11s1 and 11s2 and other MTJ sidewalls not shown, but also borders portions of the top surfaces of lower electrodes, such as the top surface 10t of the lower electrode 10a, that are not covered by MTJs. In one aspect, the passivation layer is non-magnetic and is a single layer with a thickness of at least 0.3 nm (3 angstroms) to enable continuous coating. In a preferred embodiment, the passivation layer is amorphous and non-crystalline to prevent diffusion of reactive materials between crystals in a lattice and may be a single layer of B, C, or Ge. A carbon passivation layer may have a diamond-like structure or a high degree of sp3 bonding deposited by a CVD or PVD process.We discovered that the maximum benefit of more uniform coercivity (Hc) across a range of MTJ sizes is minimized for a B-passivation layer thickness of approximately 0.5 nm (5 angstroms) and decreases slightly as the thickness is increased to 1 nm (10 angstroms) or more. Furthermore, a key feature of all the passivation layers disclosed herein is the ability to protect MTJ sidewalls from attack by reactive species during processes involving the deposition of a dielectric layer between MTJ elements.

[0027] The present disclosure also includes a method for forming a single passivation layer on the MTJ sidewalls. First, a method for fabricating multiple MTJs is described. In Fig. 2, an MTJ layer stack is formed on a bottom electrode layer containing a bottom electrode 10a. All layers in the MTJ stack can be deposited in a DC sputtering chamber of a sputtering system, such as an Anelva C-7100 sputter deposition system, which includes ultra-high vacuum DC magnetron sputtering chambers with multiple targets and at least one oxidation chamber to form a tunnel barrier, such as MgO, from a Mg layer and thereby generate a TMR effect. Typically, the sputter deposition processes for various layers involve an inert gas, such as Ar, and a base pressure between 5 × 10 -8 × 133 Pa and 5 × 10 -9 × 133 Pa (Torr).

[0028] A photoresist layer is formed on the MTJ layer stack and is patterned using a well-known photolithography technique to create multiple islands, including photoresist islands 30a, 30b, each having a width w. Subsequently, a conventional reactive ion etch (RIE) or ion beam etch (IBE) process is performed to remove regions of the MTJ layer stack not protected by a photoresist island. Note that the photolithography process yields an array of photoresist islands arranged in rows and columns, such that each island serves as an etch mask, and the RIE or IBE process generates an MTJ under each etch mask. Thus, MTJ 11a and MTJ 11b are formed with sidewalls 11s1 and 11s2, respectively, under the islands 30a and 30b, and there are openings 50 on each side of the MTJs exposing portions of the top surface 10t of the lower electrode.In the exemplary embodiment, the RIE or IBE process forms non-vertical sidewalls 11s1 and 11s2 such that a bottom surface of each MTJ at the top surface 10t has a width greater than w. .

[0029] However, depending on the etching conditions, essentially vertical MTJ sidewalls can also be formed.

[0030] We turn Fig. 3, where a conventional process is used to remove the photoresist islands 30a, 30b. Then, a single passivation layer 12 of B, C, or Ge is deposited on the top surface 10t and on the array of MTJs, including the top surfaces 11t1 and 11t2, and on the sidewalls 11s1 and 11s2 of the MTJs 11a and 11b, respectively. Accordingly, each opening 50 shrinks to an opening 50a. A magnetron sputtering process, PVD, CVD, or an atomic layer deposition (ALD) process can be used to deposit the passivation layer. In a preferred embodiment, the deposition process is carried out in the absence of reactive species, including nitrogen-containing and oxygen-containing gases and plasmas. In addition, the passivation layer can be deposited with an RF power in the range of 100 to 1000 watts and with a chamber pressure of 6.7 mPa to 2.7 Pa (0.05 to 20 mTorr) to prevent erosion of MTJ sidewalls.

[0031] Preferably, the passivation layer is conformally deposited with a thickness on the sidewalls 11s1 and 11s2 that substantially corresponds to a thickness on the top surface 10t of the bottom electrode. Although it is difficult to measure thin passivation layer thicknesses on the order of 0.5 to 1 nm (5-10 angstroms) during device fabrication, an independent experiment can be conducted wherein a substantially thicker film of, for example, B is deposited on a planar (off-product) substrate for a period of time "d." Once the thickness "t" of the B film has been measured using a transmission electron microscope (TEM) technique, a deposition rate "t / d" in angstroms per minute is determined for the deposition process.Then, the deposition rate is used to calculate a deposition time significantly shorter than “d” to produce a thin passivation layer with a thickness of about 0.5 to 1 nm (5-10 Ångstroms) on substrates comprising MTJs 11a, 11b.

[0032] We turn Fig. 4, where a dielectric layer 13 is deposited on the passivation layer 12 by a conventional method to a level that fills the openings 50a. Although the dielectric layer deposition typically contains reactive oxygen or nitrogen species, the MTJ sidewalls 11s1, 11s2 are protected from the reactive species by the presence of the passivation layer. The dielectric layer may comprise one or more oxides, nitrides, oxynitrides, or carbides used in the art for electrical insulation purposes and is typically deposited using a physical vapor deposition (PVD) or plasma-enhanced chemical vapor deposition (PECVD) technique.

[0033] According to a Fig. In the embodiment shown in Figure 5, a well-known chemical mechanical polishing (CMP) process is performed to remove a top portion of dielectric layer 13 such that the partially formed memory device has a top surface along plane 22-22 that includes top surface 13t and top surfaces 11t1 and 11t2 of MTJ 11a and MTJ 11b, respectively, of the dielectric layer. In some embodiments, the top MTJ layer is a hard mask, such as MnPt with a top surface that is 11t1 or 11t2. In other embodiments, the top MTJ layer is, for example, a cap layer, such as Ru, or has a Ru / Ta / Ru configuration.

[0034] We return to Fig. 1. This is followed by a sequence of steps that are well known in the art. These include photoresist patterning and etching processes used to form a top electrode layer having top electrodes 14a, 14b within the insulating layer 15, with top electrode 14a adjacent to the top surface of MTJ 11a and top electrode 14b contacting the top surface of MTJ 11b. As previously discussed, the top electrode layer typically includes multiple top electrodes formed, for example, in an array of parallel lines, but in the exemplary embodiment, only two top electrodes are shown. The insulating layer may include silicon oxide or aluminum oxide, or other dielectric materials used in the art to electrically isolate adjacent conductive elements.

[0035] It is understood that the passivation layer 12 in Fig. 1 can be replaced by the passivation layer 12x, the passivation layer 12y or the passivation layer 12z, which in the embodiments relating to Fig. 7, Fig. 9 or Fig. 11 are described.

[0036] According to another single layer embodiment described in Fig. 6, the passivation layer 12, which was previously applied with reference to Fig. 3, is subjected to an oxidation process, such as natural oxidation (NOX) with an oxygen species 24. The NOX process may include an oxygen flow rate of 1 to 10 standard cubic centimeters per minute (sccm) for a period of 10 to 600 seconds. In an alternative embodiment, nitriding is performed using the nitrogen species 24 on a single passivation layer comprising B, C, or Ge. Furthermore, the species 24 may contain both a reactive oxygen species and a reactive nitrogen species in an oxynitriding process. It is important that the oxidation and nitriding conditions be sufficiently mild to prevent oxygen or nitrogen species from penetrating the passivation layer and reacting with the MTJ sidewalls 11s1, 11s2.As a result, essentially the entire B passivation layer can be converted into a BO, BN or BON layer, a C passivation layer can be converted into a CO, CN or CON layer, and a Ge passivation layer can be converted into a GeO, GeN or GeON layer.

[0037] The present disclosure also includes an embodiment in which a BN, BO, BON, CN, CO, CON, GeN, GeO, or GeON target is used to deposit a single passivation layer 12x on MTJ sidewalls 11s1, 11s2, as shown in Fig. 7. For example, a BN, CN, or GeN target can be sputtered in the presence of an inert gas but without a reactive nitrogen species to form a BN, CN, or GeN passivation layer, respectively. Similarly, a BO, CO, or GeO target can be used with an inert gas in the absence of a reactive oxygen species to form a BO, CO, or GeO passivation layer, respectively, on MTJ sidewalls.

[0038] As in Fig. 7, the initially deposited passivation layer 12 reacts with one or both of a reactive oxygen and nitrogen species 24 in Fig. 6 and is thereby converted to the passivation layer 12x. In one aspect, only a portion of the B, C, or Ge passivation layer is converted to an oxide, nitride, or oxynitride thereof, while a certain number of B, C, or Ge atoms remain, thus creating a non-stoichiometric oxidation state and / or a non-stoichiometric nitriding state in the passivation layer 12x. Depending on the length of the oxidation, nitriding, or oxynitriding process and the concentration of oxygen or nitrogen species in the reaction chamber, the passivation layer 12 can be completely converted to an oxide, nitride, or oxynitride in the passivation layer 12x to form a so-called stoichiometric oxidation or stoichiometric nitriding state.The present disclosure also includes an embodiment wherein a B, C, or Ge passivation layer 12 reacts with an oxygen species, nitrogen species, or both species during subsequent processing when a dielectric oxide, nitride, or oxynitride layer 13 is deposited on the passivation layer 12. As a result, the initially deposited B, C, or Ge passivation layer is converted to an oxide, nitride, or oxynitride passivation layer 12x having a non-stoichiometric or stoichiometric oxidation state or nitridation state, respectively, such that the passivation layer 12 is in . Fig. 1 is replaced by the passivation layer 12x.

[0039] According to another embodiment of the present disclosure, which is set forth in the Fig. 8-9, two deposition steps are performed to obtain a single passivation layer having a BX, CX, or GeX alloy composition. In particular, the passivation layer 12 is formed as previously described with reference to Fig. 3. After that, an X-element 25 is Fig. 8 is sputtered onto the B, C, or Ge layer, where X is one of B, C, Ge, Si, Al, P, Ga, In, Tl, Mg, Hf, Zr, Nb, V, Ti, Cr, Mo, W, Sr, and Zn, and where X is not equal to the other element in the alloy. In other words, the initially deposited B, C, or Ge layer serves as a sacrificial material and is completely re-sputtered during X deposition, combining with the X element to form an alloy passivation layer 12y in Fig. 9. Preferably, B in a BX alloy, C in a CX alloy, and Ge in a GeX alloy have a content of at least 10 atomic %. As in previous embodiments, the passivation layer has a minimum thickness of 0.3 nm (3 angstroms) and a maximum thickness of about 1 to 2 nm (10-20 angstroms) and preferably forms a conformal layer on MTJ sidewalls 11s1, 11s2, on MTJ top surfaces 11t1, 11t2, and on exposed regions of the bottom electrode top surface 10t. Depending on the composition of the passivation layer, the optimal benefits of the present disclosure are achieved with a passivation layer thickness of 0.5 to 1 nm (5 to 10 angstroms).

[0040] Another embodiment with a single passivation layer is shown in the Fig. 10-11 shown. In Fig. 10, the BX, CX or GeX alloy passivation layer 12y is Fig. 9 treated with a species 24 comprising a reactive oxygen and / or a reactive nitrogen species. Fig. 11 shows that the process in Fig. 10 provides an oxide, nitride, or oxynitride passivation layer 12z, which may have a stoichiometric or non-stoichiometric oxidation or nitridation state. Thus, the oxidized alloy BXO, CXO, or GeXO, or the nitrided alloy BXN, CXN, or GeXN, or the oxynitrided alloy BXON, CXON, or GeXON may have a certain number of unreacted BX, CX, or GeX alloy molecules in the passivation layer 12z. However, substantially the entire alloy layer 12y may be oxidized, nitrided, or oxynitrided under certain conditions such that no BX, CX, or GeX alloy remains in the passivation layer 12z.

[0041] We turn Fig. 12. The present disclosure also includes an embodiment in which a passivation layer having a two-layer structure is formed before or during the deposition of the dielectric layer 13. For example, the conditions used in the oxidation, nitriding, or oxynitriding process in Fig. 6, comprising reactive species 24, can be controlled such that only an upper portion of the passivation layer 12 is converted to an oxide, nitride, or oxynitride passivation layer 12x. Optionally, the reactive species 24 are supplied during deposition of the dielectric layer. In any case, a bilayer is formed with a lower passivation layer 12 bordering MTJ sidewalls 11s1, 11s2 and MTJ tops 11t1, 11t2 and an upper passivation layer 12x on the surface of the lower passivation layer to obtain a B / BO, C / CO, Ge / GeO, B / BN, C / CN, Ge / GeN, B / BON, C / CON, or Ge / GeON configuration. The two-layer regime is advantageous over a single layer of B, C, or Ge in that an oxide or nitride passivation layer 12x generally has better adhesion to the subsequently deposited dielectric layer 13 than the passivation layer 12.

[0042] Another embodiment of the present disclosure is described in Fig. 13. There is a two-layer structure for the passivation layer, which includes a lower passivation layer 12 and an upper passivation layer 12y on top of the lower passivation layer. This two-layer regime results from the Fig. 8, in which the deposition of the X element is controlled to such an extent that only an upper portion of the passivation layer 12 is re-sputtered to form the BX, CX, or GeX alloy passivation layer 12y. This bilayer regime is represented by a B / BX, C / CX, or Ge / GeX configuration. The opening 50b is smaller than the opening 50a because the bilayer stack 12 / 12y has a greater thickness than the single passivation layer 12 in Fig. 3.

[0043] As in Fig. 14, the present disclosure assumes an oxidation, nitriding or oxynitriding process with species 24 after the bilayer stack 12 / 12y in Fig. 13 was formed. In one embodiment, the passivation layer 12y is partially or fully oxidized (or nitrided or oxynitrided) to form the two-layer stack 12 / 12z, wherein the passivation layer 12z has a BXO, CXO, GeXO, BXN, CXN, GeXN, BXON, CXON, or GeXON composition, which in Fig. 16. In other words, the oxidation and nitriding process conditions are sufficiently mild to leave a continuous passivation layer 12 on the MTJ sidewalls and top surfaces, and only the outer layer 12y reacts with species 24 to form layer 12z.

[0044] Fig. Figure 15 shows an alternative method for forming the passivation layer that connects the two-layer stack 12 / 12z in Fig. 16. It should be noted that during the deposition of the X-element 25 on the passivation layer 12, the species 24 may be contained in the reaction chamber. Furthermore, the deposition conditions are controlled such that only an upper region of the passivation layer 12 is re-sputtered to obtain a B / BXO, C / CXO, or Ge / GeXO bilayer through an oxidation process, a B / BXN, C / CXN, or Ge / GeXN bilayer through a nitriding process, or a B / BXON, C / CXON, or Ge / GeXON bilayer through an oxynitriding process.

[0045] As in Fig. 17, the present disclosure includes an embodiment in which a three-layer stack is formed as a passivation layer. According to one embodiment, the Fig. 14 can be controlled so that only an upper portion of the BX, CX, or GeX layer 12y is oxidized, nitrided, or oxynitrided to form a top passivation layer 12z. Thus, a B / BX / BXO, C / CX / CXO, or Ge / GeX / GeXO triple layer is produced when the species 24 in Fig. 14 represent an oxidation process. Alternatively, a B / BX / BXN, C / CX / CXN or Ge / GeX / GeXN triple layer is formed when species 24 in Fig. 14 is used in a nitriding process, or a B / BX / BXON, C / CX / CXON or Ge / GeX / GeXON triple layer is formed by an oxynitriding process.

[0046] We turn Fig. 18, where a top view of the memory structure in Fig. 1. Level 20-20 indicates the position where the cross-sectional view in Fig. 1. In the exemplary embodiment in which two additional MTJs 11 cand 11d between a second lower electrode 10b and upper electrodes 14a and 14b, respectively, the width w1 of the upper electrodes is preferably greater than the width w of the MTJs 11a-11d. Furthermore, a length b of the lower electrodes 10a, 10b in the y-axis direction is typically greater than the length c of the MTJs. The MTJs have a substantially circular shape, which may be a circle or an ellipse. In other embodiments, the MTJs may have a polygonal shape, such as a square or a rectangle.

[0047] We turn Fig. 19, where a modification of the storage device in Fig. 1, in which all layers were retained except that the passivation layer 12 was replaced by a two-layer structure. In the exemplary embodiment, the bilayer has a stack 12 / 12y, as previously described with reference to Fig. 13. However, the bilayer can also have a stack 12 / 12x, as in Fig. 12, or a 12 / 12z configuration, as shown in Fig. 16 shown.

[0048] We turn Fig. 20, where a modification of the storage device in Fig. 1, in which all layers were retained except that the passivation layer 12 was replaced by a three-layer structure. In the exemplary embodiment, the triple layer has a stack 12 / 12y / 12z, as previously described with reference to Fig. 17 explained.

[0049] In Fig. Figure 21 shows another embodiment of the present disclosure in which the previously described passivation layer 12 may be used as a protective measure in an STO device. An STO device 40 is formed between a main pole layer 17 and the back shield 18. In this case, a DC current (100% duty cycle) or pulsed current I flows from a source 35 through a lead 36 to the main pole 17 and then flows through the STO 40 and the back shield 18 before exiting through the lead 37. The pulsed current may be "on" on the order of 0.1 ns, followed by an off period of a fraction of a nanosecond to several nanoseconds.The STO 40 may have a bottom spin valve configuration in which a seed layer 41, a spin polarization (SP) layer 42, a non-magnetic spacer 43, an oscillation (OL) layer 44, and a cap layer 45 are formed sequentially on the main pole, such that a bottom surface of the seed layer contacts the main pole and a top surface of the cap layer contacts the rear shield. One or both of the layers 41, 43 are a metal oxide to create perpendicular magnetic anisotropy (PMA) 46 in the SP layer. The z-axis is the medium movement direction and is the down-track direction.

[0050] During a write process, a magnetic flux 8 passes through the ABS 33-33 and traverses the magnetic medium 7 and the soft underlayer 6, and the flux 8a re-enters the write head through the rear shield 18. Under a gap field 8b of several thousand Oe (1 Oe corresponds to 79.5775 A / m) and a DC bias on the STO, the write process is assisted by a spin-polarized current flowing from the SP layer 42 to the OL 44 with sufficient magnitude (critical current density) to induce a large-angle oscillation 47 with a specific amplitude and frequency in the OL, which generates an RF field 49 at the medium bit 9. The combined effect of the RF field and the magnetic field 8 makes it possible to alternate the magnetization 5 in the bit with a weaker magnetic field than if only the magnetic field 8 were applied.

[0051] The STO device 40 is considered an MTJ, where the SP layer 42 serves as a reference layer, the non-magnetic spacer 43 is a tunnel barrier, and the OL layer 44 is virtually a free layer. The composition of layers 41-45 is described in detail in related U.S. Patent 9,230,571. A key feature of the present disclosure is that the passivation layer 12 is formed on a backside 17t of the main pole and on a sidewall 40s of the STO 40, thereby protecting the sidewall during the deposition of the dielectric layer 13 formed between the main pole layer 17 and the back shield 18. As a result, the STO device maintains its structural integrity during subsequent manufacturing steps, unlike the prior art where the STO sidewall is susceptible to damage from reactive gases used in the deposition of the dielectric layer.

[0052] We turn Fig. 22, where an experiment was conducted to demonstrate the improved performance achieved by implementing a protective passivation layer on MTJ sidewalls according to an embodiment of the present disclosure. A series of MTJ elements were fabricated in a circular shape (w = c in Fig. 18), with the diameter w varying from approximately 20 nm to 40 nm. For each MTJ size, half of the specimens were not protected with a passivation layer, and half of the specimens were protected by a 0.5 nm (5 angstroms) thick B passivation layer deposited in an Anelva sputter deposition chamber under the following conditions: 600 watts of RF power; an Ar flow rate of 150 standard cubic centimeters per minute (sccm); and a B target-to-substrate distance of 240 mm to obtain a B deposition rate of 0.018 nm (0.18 angstroms) / s (according to TEM analysis). Thus, several different MTJ sizes were fabricated, and for each, a TMR ratio (dR / R) was measured at 25 °C using an Accretech UF300A prober. The TMR ratio is also expressed as (Rp-Rap) / Rp × 100, where Rp and Rap are the resistances in parallel and antiparallel configurations for the reference layer and the free layer in an MTJ element, respectively.Each MTJ batch was annealed at 400 °C for 2.5 hours prior to TMR measurement.

[0053] The results in Fig. 22 show that MTJs with a protective B-passivation layer had a higher dR / R ratio than MTJs fabricated by a process of record (POR) that does not involve deposition of a passivation layer on MTJ sidewalls, especially for MTJ diameters between 20 nm and 35 nm.

[0054] In Fig. Figure 23 plots the coercivity (Hc) in kOe (1 kOe corresponds to 79.5775 kA / m) as a function of the MTJ diameter, which ranges from 50 to 300 nm. Again, MTJs with a protective B passivation layer (0.5 nm or 5 angstroms thick) were found to have higher performance (a larger Hc) than POR MTJs, especially for the smaller MTJ sizes from 50 nm to 250 nm. In this case, the results were measured at 125 °C using an Accretech UF300A prober.

[0055] We turn Fig.24. We found that, compared to reference POR MTJs without a passivation layer, tilting is significantly improved when a 0.5 nm (5 Ångström) thick protective passivation layer is formed on MTJ sidewalls. Tilt results were also determined at 125 °C using the Accretech UF300A probe. Tilt values ​​on the y-axis refer to the parallelism of the magnetic moments of the AP1 and AP2 sublayers in an MTJ where the reference layer has a synthetic anti-parallel (SyAP) configuration, represented by AP2 / coupling layer / AP1 layer stack. Ideally, the middle antiferromagnetic coupling layer results in AP2 and AP1 layers with magnetic moments aligned essentially parallel to each other—either in a perpendicular to the plane or in an in-plane direction.However, certain factors disrupt a perfectly parallel relationship (y-axis value = 1), so that the magnetic moments of the AP1 and AP2 layers approach an orthogonal alignment to each other (y-axis value approximately 0). In real practice, a tilt value > 0.9, indicating a substantially parallel alignment of the AP1 and AP2 magnetic moments, is required for high performance in an MTJ. In contrast to the reference POR MTJs, where all tilt values ​​are below 0.9, most MTJs meet or exceed the minimum tilt value required for optimal performance when their sidewalls border a 0.5 nm (5 angstroms) thick B passivation layer formed according to an embodiment of the present disclosure.

[0056] The one or more additional deposition steps and minimal costs required to form a protective passivation layer described herein are considered insignificant compared to the significant costs associated with attempting to repair a POR MTJ damaged during dielectric layer deposition and the scrap (reduced production yield) associated with POR MTJs that are so severely damaged that they cannot be repaired. The protective passivation layers of the present disclosure can be deposited using conventional tools and materials used in the art.

Claims

[1] Magnetic device comprising: (a) a magnetic tunnel junction, MTJ (11a) having a sidewall (11s1) extending from its top surface (11t1) to its bottom surface, the bottom surface contacting a lower electrode (10a) and the top surface contacting an upper electrode (14a); (b) a passivation layer (12) which is non-magnetic and has a bilayer or other multilayer configuration comprising: (1) a bottom layer contacting the MTJ sidewall between the top electrode and the bottom electrode and comprising B, C, or Ge; (2) a second layer formed on the lower layer and comprising an alloy containing a first element which is one of B, C or Ge and at least one second element which is different from the first element; and (c) a dielectric layer (13) formed on the non-magnetic passivation layer, the dielectric layer electrically isolating the MTJ from adjacent MTJs; where the lower layer is B, C or Ge and the second layer is a BX, CX or GeX alloy, where X is one of B, C, Ge, Si, Al, P, Ga, In, Tl, Mg, Hf, Zr, Nb, V, Ti, Cr, Mo, W, Sr and Zn, so that a B / BX, C / CX or Ge / GeX bilayer configuration is obtained for the passivation layer, or where the lower layer is B, C or Ge and the second layer is oxygen, nitrogen or comprises both oxygen and nitrogen, and has a BO, CO, GeO, BN, CN, GeN, BON, CON or GeON composition, so that a B / BO, B / BN, C / CO, C / CN, Ge / GeO, Ge / GeN, B / BON, C / CON or Ge / GeON bilayer configuration is obtained for the passivation layer; or wherein the second layer further comprises oxygen, nitrogen or both oxygen and also comprises nitrogen and has a BXO, CXO, GeXO, BXN, CXN, GeXN, BXON, CXON or GeXON composition, so that a B / BXO, C / CXO, Ge / GeXO, B / BXN, C / CXN, Ge / GeXN, B / BXON, C / CXON or Ge / GeXON bilayer configuration is obtained for the passivation layer; or the device further comprises a third layer deposited on the second layer is formed, and the third layer has a BXO, CXO, GeXO, BXN, CXN, GeXN, BXON, CXON or GeXON composition, so that a B / BX / BXO, C / CX / CXO, Ge / GeX / GeXO, B / BX / BXN, C / CX / CXN, Ge / GeX / GeXN, B / BX / BXON, C / CX / CXON or a Ge / GeX / GeXON three-layer configuration is obtained for the passivation layer. [2] The magnetic device of claim 1, wherein the MTJ is part of an MRAM, spin torque MRAM, or spin torque oscillator structure. [3] A magnetic device according to claim 1, wherein the B in BX, the C in CX and the Ge in GeX comprise at least 10 atomic% of the alloy. [4] A method of forming a magnetic device comprising: (a) providing a substrate having a top surface; (b) forming a plurality of magnetic tunnel junctions, MTJs (11a), on the substrate top surface, each MTJ having a sidewall (11s1) extending from its top surface to its substrate top surface; (c) depositing a passivation layer (12) which is non-magnetic and is one of B, C or Ge on the MTJ sidewalls and top surfaces and on exposed portions of the substrate top surface; (d) depositing a dielectric layer (13) on the passivation layer, the dielectric layer electrically isolating each of the plurality of MTJs; and Depositing Si or an X element on the passivation layer prior to depositing the dielectric layer such that an upper portion of the passivation layer is re-sputtered to form a second layer on the passivation layer, wherein the second layer is an alloy comprising BSi, GeSi, BX, CX, or GeX, where X is one of B, C, Ge, Al, P, Ga, In, Tl, Mg, Hf, Zr, Nb, V, Ti, Cr, Mo, W, Sr, and Zn, to obtain a B / BX, C / CX, or Ge / GeX bilayer configuration for the passivation layer, and the B in BSi and BX, the C in CX, and the Ge in GeSi and GeX comprise at least 10 atomic percent of the alloy; and Subjecting the second layer to an oxidation, nitriding, or oxynitriding process such that an upper portion of the second layer is converted to a third layer that is an oxide, nitride, or oxynitride of BX, CX, or GeX to obtain a three-layer configuration that is one of B / BX / BXO, C / CX / CXO, Ge / GeX / GeXO, B / BX / BXN, C / CX / CXN, Ge / GeX / GeXN, B / BX / BXON, C / CX / CXON, or Ge / GeX / GeXON for the passivation layer. [5] The method of claim 4, further comprising: (a) performing a chemical mechanical polishing process to form a top surface (13t) on the dielectric layer that is coplanar with the top surface on each of the plurality of MTJs; and (b) Carrying out an annealing process at a temperature of approximately 400 °C. [6] The method of claim 4 or 5, wherein the substrate comprises a bottom electrode layer which is a bottom electrode (10a) in an MRAM or spin torque MRAM, or a main pole layer in a spin torque oscillator. [7] A method according to any one of claims 4 to 6, wherein the passivation layer has a thickness of about 0.3 to 1 nm. [8] A method according to any one of claims 4 to 7, further comprising: Depositing an X element on the passivation layer prior to depositing the dielectric layer, wherein the initially deposited B, C, or Ge passivation layer serves as a sacrificial material and is completely re-sputtered to form a single passivation layer that is an alloy having a BSi, GeSi, BX, CX, or GeX composition, where X is one of B, C, Ge, Al, P, Ga, In, Tl, Mg, Hf, Zr, Nb, V, Ti, Cr, Mo, W, Sr, and Zn, and the B in BX, the C in CX, and the Ge in GeX comprise at least 10 atomic percent of the alloy. [9] A method according to any one of claims 4 to 8, further comprising: Subjecting the passivation layer to an oxidation process prior to deposition of the dielectric layer to form a BO, CO, or GeO layer having a non-stoichiometric or stoichiometric oxidation state. [10] The method of claim 9, wherein the BO, CO or GeO layer is a second layer formed on a portion of the passivation layer that remains unoxidized to obtain a B / BO, C / CO or Ge / GeO bilayer configuration for the passivation layer. [11] A method according to any one of claims 4 to 10, further comprising: Subjecting the passivation layer, which is one of B, C, or Ge, to a nitriding process prior to depositing the dielectric layer to form a BN, CN, or GeN layer having a non-stoichiometric or stoichiometric nitriding state. [12] The method of claim 11, wherein the BN, CN or GeN layer is a second layer formed on a portion of the passivation layer that is not converted to a nitride to obtain a B / BN, C / CN or Ge / GeN bilayer configuration for the passivation layer. [13] The method of claim 12, further comprising: Exposing the BSi, BX, CX, GeSi or GeX layer to an oxidation, nitriding or oxynitriding process such that the passivation layer is completely converted to an oxide, nitride or oxynitride of BSi, BX, CX, GeSi or GeX. [14] A method according to any one of claims 4 to 13, further comprising: Subjecting the second layer to an oxidation, nitriding, or oxynitriding process such that the entire second layer is converted to an oxide, nitride, or oxynitride of BX, CX, or GeX to obtain a bilayer configuration that is one of B / BXO, C / CXO, Ge / GeXO, B / BXN, C / CXN, Ge / GeXN, B / BXON, C / CXON, or Ge / GeXON for the passivation layer. [15] The method of any one of claims 4 to 14, wherein depositing the passivation layer comprises a sputter deposition process with an RF power of about 100 to 1000 watts and a chamber pressure of about 6.7 mPa to 2.7 Pa. [16] The method of claim 15, wherein the oxidation process comprises natural oxidation at an oxygen flow rate of 1 to 10 standard cubic centimeters per minute (sccm) for a period of 10 to 600 seconds.

Images