MAGNETIC TUNNEL junction (MTJ) device comprising a dielectric encapsulation layer and method for forming the same using high-frequency (HF) sputters

Abstract

Magnetic device comprising: (a) several vertically magnetized MTJs (11a, 11b), each of which has a side wall extending from an upper surface to a lower surface, the lower surface contacting a lower electrode (10a) and the upper surface contacting an upper electrode (14a, 14b) on a first plane parallel to the lower surface; (b) an encapsulation layer (12, 13) which adjoins the side wall from the upper surface to the lower surface of each perpendicularly magnetized MTJ and has an upper surface on the first plane, wherein the encapsulation layer has: (1) a first dielectric layer (12) comprising a lower layer (12-1) containing B or Ge, which contacts the perpendicularly magnetized MTJ side wall, and an upper layer (12-3) comprising one or more SiO Y N Z , AIO Y N z TiO Y N z , SiC y Nz or MgO, where y + z > 0; and (2) a second dielectric layer (13) formed on an upper surface of the first dielectric layer and having a composition comprising one of metal oxide, metal nitride, metal carbide, metal oxynitride or metal cyanide nitrogen or combinations thereof.

Description

TECHNICAL AREA

[0001] The present disclosure relates to magnetic tunnel junctions (MTJs) in magnetic random access memory (MRAM), spin-torque MRAM and other spintronic devices, and in particular to protective MTJ sidewalls during processing steps including the deposition of an insulating dielectric layer separating adjacent MTJs, and during high-temperature annealing of approximately 400 °C, which is common in complementary metal oxide semiconductor (CMOS) fabrication. GENERAL STATE OF THE ART

[0002] An MTJ is a key component in MRAM, spin-torque MRAM, and other spintronic devices. It comprises a stack with a tunnel barrier layer, such as a metal oxide formed between two magnetic layers, which provides a tunnel magnetoresistance (TMR) effect. Since MTJ elements are frequently integrated into CMOS devices, the MTJ must be thermally resistant to withstand annealing temperatures of approximately 400 °C for up to several hours. These temperatures are commonly used to improve the quality of CMOS devices for semiconductor applications.

[0003] Perpendicularly magnetized MTJs (p-MTJs), in which the free layer (FL) and the reference layer (RL) exhibit perpendicular magnetic anisotropy (PMA), are preferred over their counterparts that use in-plane anisotropy because a p-MTJ offers the advantage of lower write current with comparable thermal resistance and better scalability. p-MTJs are an emerging major technology for use in embedded magnetic random access memory (MRAM) applications, including spin-torque (STT) MRAM, and in stand-alone MRAM applications. An STT MRAM, which uses spin torque to write memory bits, was described by Slonczewski, JC: Current-driven excitation of magnetic multilayers. In: Journal of Magnetism and Magnetic Materials, 159, 1996, SI1 - I.7., and is highly competitive with existing semiconductor memory technologies such as SRAM, DRAM, and flash memory.p-MTJs have a general structure in which an insulating tunnel barrier is placed between two magnetic layers. One of the magnetic layers is called the reference layer and has, for example, a magnetization fixed in an out-of-plane direction in the (+y) direction. The second magnetic layer, called the free layer, has a magnetization that is also out-of-plane, but can be changed from a (+y) direction in a parallel state or P-state to a (-y) direction in an antiparallel or AP-state, or vice versa. When a current is sent through the p-MTJ in a direction perpendicular to the plane, the difference in resistance between the P-state (Rp) and AP-state (Rap) can be characterized by the equation (Rap - Rp) / Rp, also known as the DRR value or magnetoresistive (MR) ratio.It is important that p-MTJ devices have a large DRR value, as this property is directly related to the read margin for the memory bit or the ease of distinguishing between the P state (0-bit) and AP state (1-bit).

[0004] Spin-transfer-torque (STT) MRAM-based technologies are desirable for non-volatile memory applications. However, to compete with embedded high-speed SRAM technologies, p-MTJs must be fabricated in high-density arrays with single bits capable of high-speed (<100 ns) write currents. To achieve the goal of low write currents, the overall free-layer volume must be reduced, most easily accomplished by reducing the p-MTJ dimensions. However, as the dimensions decrease, the effect of electrical conductivity through the edge or sidewall regions of the p-MTJ device becomes more pronounced. p-MTJs are highly susceptible to sidewall damage, both chemical and physical, caused by etching and deposition processes. This is exacerbated by the CMOS process requirement of annealing at 400 °C.Accordingly, these boundary regions are of particular importance, as crystal structure damage from etching, encapsulation and tempering processes can greatly influence the p-MTJ properties, including the free layer coercivity (Hc), DRR and resistivity area product (RA).

[0005] Typically, encapsulation with a dielectric layer is used to isolate p-MTJ devices from each other in an STT-MRAM arrangement. The dielectric layer is deposited using a chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or reactive physical DC sputtering vapor deposition (PVD) process that involves reactive gases, radicals, ions, or other excited elements with a tendency to attack p-MTJ sidewalls and damage the magnetic layers within.

[0006] Sidewall damage leads to a reduction in device performance and significant inconsistency between bits, resulting in an undesirable wider distribution of key metrics and lower device yields. It is important that the encapsulation layer forms a thermodynamically stable interface with p-MTJ sidewalls to prevent, for example, oxygen diffusion through a p-MTJ sidewall during oxide dielectric layer deposition or mixing of the dielectric layer with one or more p-MTJ layers, which also results in a degradation of device performance.

[0007] Although methods exist to eliminate sidewall damage caused by ion bombardment and atmospheric exposure during dielectric layer deposition, these methods are generally time-consuming and costly. Furthermore, p-MTJ sidewall damage can be too extensive to repair. There is a need to improve the encapsulation process to prevent parallel conduction along p-MTJ sidewalls and avoid device damage by depositing an encapsulation layer that forms a thermodynamically stable interface with the p-MTJ and increases the DRR.

[0008] Publication US 2016 / 0268499A1 describes a method for forming a magnetoresistive random access memory (MRAM) device with a perpendicular MTJ (magnetic tunnel junction). A magnetic tunnel junction is formed over a lower electrode layer. An upper electrode layer is formed over an upper surface of the MTJ, and a hard mask is formed over an upper surface of the upper electrode layer. An initial etch is performed through the upper electrode layer, through areas of the MTJ not masked by the hard mask, to form an upper electrode and an etched MTJ. Sidewall spacers are formed, extending from an upper surface of the hard mask or the upper electrode along sidewalls of the upper electrode and the etched MTJ to a point below or approximately level with an upper surface of the lower electrode.

[0009] Document US 8,796,814 B2 describes a semiconductor substrate device. Several memory elements are formed on the top surface of a semiconductor substrate. Interlayer insulating films are embedded between adjacent memory elements. A protective film is formed on the sides of each memory element and on the top surface of the semiconductor substrate between adjacent memory elements. Contacts are formed in the interlayer insulating films. The protective film comprises a first protective film formed on the sides of each memory element and on the top surface of the semiconductor substrate between adjacent memory elements, and a second protective film formed on top of the first protective film. The first protective film is formed of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The second protective film is formed of a boron film or a boron nitride film. SUMMARY

[0010] One objective of the present disclosure is essentially to improve the resistance of a p-MTJ to sidewall damage during encapsulation and tempering processes in storage device manufacturing, thereby improving DRR and device yield.

[0011] A second objective of the present disclosure is to provide an improved method for encapsulating a p-MTJ device that enables heat resistance up to 400 °C in order to be compatible with back-end-of-line (BEOL) CMOS processes.

[0012] The tasks are solved by the magnetic device according to claim 1 and the method according to claim 13. Further embodiments are set out in the dependent claims.

[0013] According to one embodiment of the present disclosure, these objectives are achieved by a two-step encapsulation process, wherein the first step comprises the deposition of a first dielectric layer on a p-MTJ sidewall by a PVD process in which a first dielectric is RF sputtered using inert gas. A key feature is that an RF sputtering process is employed under conditions that localize ionized elements in the plasma to a region around the target cathode using inert process gases, so that reactive species do not attack the p-MTJ sidewall. During the first step, the p-MTJ sidewall is completely covered and forms a thermodynamically stable interface with the first dielectric layer. The first dielectric layer can have a two-layer configuration with a lower layer contacting the p-MTJ sidewall and an upper layer with a top surface.Subsequently, a second dielectric layer is deposited on the upper surface of the first dielectric layer by a PVD, PECVD, or CVD process, whereby reactive gases, plasmas, or radicals can impinge on the first dielectric layer but cannot reach the p-MTJ sidewall. The second dielectric layer is preferably thicker than the first dielectric layer to ensure that openings between adjacent p-MTJs are completely filled.

[0014] According to one embodiment, the first dielectric layer is made of SiO Y N Z , AlOyNz, TiO Y N z , SiC y N zor MgO or any combination of the aforementioned materials, where y + z > o. In other embodiments, the first dielectric layer may comprise BX or GeX, where XO, N, B, C, Ge, Si, Al, P, Ga, In, TI, Mg, Hf, Zr, Nb, V, Ti, Cr, Mo, W, Sr, or Zn. In embodiments where the first dielectric layer has a two-layer configuration, a B / BX or Ge / GeX stack may be formed, or the lower layer may be one of B, Ge, BX, or GeX, while the upper layer may be one of SiO. Y N Z , AIO Y N Z , TiO Y N z , SiC y N z or MgO. In a three-layer configuration, an upper layer consisting of SiO₂ is used. Y N Z , AIOYNz, TiO Y N z , SiC y N z or MgO is formed on a lower layer with a B / BX or Ge / GeX stack.

[0015] The second dielectric layer is typically a metal oxide, metal carbide, metal nitride, metal oxynitride or metal carbonitride with a thickness of up to 200.0 nm and can be made of SiO₂ Y N Z , AIO Y N z , TiO Y N z , SiC y N z or MgO, where y + z > 0. The second dielectric layer also serves as an insulating layer to electrically isolate p-MTJs from each other.

[0016] In the completed memory structure, which can be an MRAM, STT-MRAM, embedded flash, or spin-torque oscillator (STO), there is an array of p-MTJ elements arranged in multiple rows and columns on a substrate. In an MRAM or STT-MRAM application, the substrate includes a bottom electrode layer containing multiple first conductive lines, such that the bottom face of each p-MTJ contacts a first conductive line. Each p-MTJ has a side wall that is protected by the first dielectric layer, while the second dielectric layer is an insulating layer. An upper electrode layer consisting of multiple second conductive lines is formed on the array of p-MTJ elements such that each p-MTJ is sandwiched between a first conductive line and a second conductive line.

[0017] In an STO device, the substrate can be a main pole layer serving as a bottom electrode, and the top electrode can be, for example, a rear shield. An encapsulation layer formed by a method described herein is formed on one side of the STO layer stack facing away from an air-supported surface (ABS). BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a cross-sectional view showing a storage structure with an encapsulation layer forming a thermodynamically stable interface with adjacent p-MTJ sidewalls according to an embodiment of the present disclosure. Fig. Figure 2 is a cross-sectional view showing a structuring step forming multiple p-MTJs from a p-MTJ layer stack according to an embodiment of the present disclosure. The Fig. Figures 3 to 4 are cross-sectional views of a PVD process consisting of RF sputtering, which, according to an embodiment of the present disclosure, forms a first dielectric layer on p-MTJ sidewalls. The Fig. Figures 5 to 6 are cross-sectional views of a process in which an upper dielectric layer is deposited on top of the first dielectric layer in Fig. 4 is deposited to form a first dielectric layer with a two-layer configuration according to an embodiment of the present disclosure. Fig. Figure 7 is a cross-sectional view of an embodiment of the present disclosure in which the first dielectric layer has a three-layer configuration. Fig. Figure 8 is a cross-sectional view showing a second dielectric layer formed on a first dielectric layer in order to provide an encapsulation layer according to an embodiment of the present disclosure. Fig. 9 is a cross-sectional view showing the partially formed storage structure in Fig. Figure 8 shows the result after a chemical-mechanical polishing process was used to form a planar top surface on the p-MTJs. Fig. Figure 10 is a top view of a completed MRAM arrangement with multiple p-MTJs protected by an encapsulation layer and formed according to an embodiment of the present disclosure. Fig. Figure 11 is a cross-sectional view of an STO device, wherein a side wall is protected by an encapsulation layer formed according to an embodiment of the present disclosure. Fig. Figure 12 is a representation of the DRR against parallel state resistance for p-MTJ devices with an encapsulation layer formed according to prior art methods and by a method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The present disclosure relates to an improved p-MTJ encapsulation layer and a method for forming it, wherein an interface between the encapsulation layer and the p-MTJ sidewalls is produced that is stable at high temperatures of approximately 400 °C. The p-MTJ elements can be formed in a variety of memory devices, including, but not limited to, MRAM, e-Flash, spin-torque MRAM, and other spintronic devices such as a spin-torque oscillator (STO). The drawings illustrate the thickness of a layer in the z-axis direction and the plane or top surface of each p-MTJ layer in the x- and y-axis directions. The terms "dielectric" and "insulation," as well as "passivation" and "encapsulation," may be used interchangeably.

[0019] As previously mentioned, many memory devices are now being incorporated into CMOS platforms to provide higher performance. However, significantly more defects and degraded device performance are observed when dielectric layers are deposited directly onto p-MTJ sidewalls using conventional methods and the resulting device is annealed at temperatures of approximately 400 °C, which are required in CMOS processing. Therefore, we were motivated to implement a means of protecting p-MTJ elements to provide higher performance and yields in memory applications.

[0020] In the related publication US 2018 / 0269385A1, it was disclosed how the deposition of passivation layer materials such as B, C, and Ge in the absence of reactive oxygen and nitrogen elements is effective in protecting p-MTJ sidewalls from damage during subsequent deposition of a dielectric layer that acts as an insulating layer between p-MTJs. We have now discovered a process that allows a wide variety of encapsulation layer materials to be formed on a p-MTJ sidewall, thereby providing a thermodynamically stable interface with the sidewall and improving the p-MTJ integrity.

[0021] With reference to Fig. Figure 1 shows a first embodiment of the present disclosure, in which a storage device comprises several p-MTJs, including p-MTJ 11a and p-MTJ 11b, which have sidewalls 11s1 and 11s2 respectively and are protected by the first dielectric layer 12. p-MTJ 11a is formed between a lower electrode 10a and an upper electrode 14a, while p-MTJ 11b is located between the lower electrode 10a and the upper electrode 14b. The second dielectric layer 13 is formed on top of the first dielectric layer and fills the gaps between adjacent p-MTJ elements. The stack of first and second dielectric layers is considered an encapsulation layer. The lower electrode is a conductor extending along the x-axis, and the upper electrodes are conductors extending in the y-axis direction in an MRAM or STT-MRAM configuration.The lower and upper electrodes typically consist of one or more metals or alloys to ensure excellent electrical conductivity and oxidation resistance. An insulating layer 15 is formed on a substantial portion of the second upper dielectric layer surface 13t. Within the insulating layer is an upper electrode layer consisting of several upper electrodes, including 14a and 14b. It is important to note that each of the upper electrodes can have a width w1 that is greater than the width of upper p-MTJ surfaces 11t1 and 11t2. In other words, a substantial portion of each upper electrode lies above a p-MTJ layer 11a or 11b, and an outer portion is formed on the second upper dielectric layer surface 13t, which is close to the first dielectric layer. Portions of the upper surface of the lower electrode 10t coincide with a lower surface of the p-MTJs 11a and 11b.

[0022] It should be self-evident that typically millions of p-MTJs are aligned in rows and columns in a memory block on a substrate, with each p-MTJ formed between a lower electrode and an upper electrode. The number of p-MTJs that are in Fig. The number of p-MTJs shown in Figure 1 is limited to two for the sake of simplicity. The p-MTJs can have different configurations, but each p-MTJ, including 11a and 11b, has at least one tunnel barrier formed between a reference layer (RL) and a free layer (FL) in an RL / tunnel barrier / FL or FL / tunnel barrier / RL stack on a bottommost layer (not shown), which may be, for example, a seeding layer. Preferably, the first dielectric layer 12 has a substantially uniform thickness and contacts not only the p-MTJ sidewalls 11s1 and 11s2 and other MTJ sidewalls not shown, but also bounds sections of the upper surface 10t of the lower electrode 10a that are not covered by p-MTJs.

[0023] According to one embodiment, the first dielectric layer 12 is a single D-layer with a thickness of 0.3 to 40.0 nm, wherein D is one of SiO₂ Y N Z , AIOY N z TiO Y N z , SiC y N zor MgO or any combination of the materials described above, where y + z > 0. In embodiments where MgO or another metal oxide is co-deposited with a nitride such as SiNz, the content of the oxide (MgO) is, for example, 0.1 to 10 wt.% in the nitride matrix. Although not bound by theory, it is assumed that MgO separates at least partially from the SiNz during deposition to form a thin oxide layer at an interface with the p-MTJ sidewall, which is more stable than an interface with silicon nitride. However, the present disclosure anticipates that the first dielectric layer may comprise other metal oxides, metal carbides, metal nitrides, metal oxynitrides, or metal carbonitrides used in the field.Preferably, the first dielectric layer is amorphous and non-crystalline to prevent diffusion of reactive materials between crystals in a lattice structure during subsequent processes.

[0024] In another embodiment, the first dielectric layer 12 is a single layer comprising, but not limited to, one of B and Ge, or comprising B, Ge, BX, or GeX, where X is one of O, N, B, C, Ge, Si, Al, P, Ga, In, Ti, Mg, Hf, Zr, Nb, V, Ti, Cr, Mo, W, SR, and Zn, and where X is unlike the other element in the alloy. It is important that the first dielectric layer be at least 0.3 nm thick to provide a continuous film on the p-MTJ sidewalls 11s1, 11s2.

[0025] In a second embodiment, which is shown in the intermediate structure, which is in Fig. As shown in Figure 6, the first dielectric layer 12 has a two-layer configuration, in which a lower layer 12-1 contacts the p-MTJ sidewalls 11s1, 11s2, and an upper layer 12-2 has a top surface on which the second dielectric layer 13 is subsequently deposited. There is usually an opening 50b above the first dielectric layer and between adjacent p-MTJs 11a, 11b before the second dielectric layer is deposited. In some embodiments, the lower layer 12-1 is B or Ge, and the upper layer 12-2 is one of BX or GeX. In other embodiments, the lower layer has a B, Ge, BX, or GeX composition, while the upper layer is the D layer described above. The two-layer configuration has a minimum thickness of 0.3 nm, while a maximum thickness for the first dielectric layer 12 is 40.0 nm.

[0026] According to a third embodiment in Fig. 7 The first dielectric layer has a three-layer configuration represented by B / BX / D or Ge / GeX / D, where B or Ge is the lower layer 12-1, contacting the p-MTJ sidewalls 11s1, 11s2, and BX or GeX forms a middle layer 12-2 on the lower layer. The upper layer 12-3 has the D-layer composition, and the second dielectric layer is subsequently deposited on top of it. The total thickness of the first dielectric layer 12 is in the range of 0.3 to 40.0 nm. The openings 50c are formed above the first dielectric layer and between adjacent p-MTJs.

[0027] With renewed reference to Fig. 1 is the second dielectric layer 13 typically a metal oxide, metal carbide, metal nitride, metal oxynitride or metal carbonitride such as SiO Y N Z , AlOyNz, TiO Y N z , SiC y N zor MgO, where y + z > 0, or any combination of the materials described above. The second dielectric layer has a thickness of up to approximately 200.0 nm and is typically thicker than the first dielectric layer. As described below, the second dielectric layer usually has a faster deposition rate than the first dielectric layer and is relied upon to fill gaps between adjacent p-MTJs that remain after the first dielectric layer has formed. A PVD-HF sputtering process is used to deposit the first dielectric layer and prevent exposure of p-MTJ sidewalls to reactive gases during the deposition of the dielectric layers 12, 13. However, the PVD-HF sputtering process has a relatively slow deposition rate compared to PECVD or CVD processes.Therefore, in order to increase throughput, the first dielectric layer thickness is limited to a maximum value of approximately 40.0 nm to minimize processing time.

[0028] A key feature of the present disclosure is a process flow for forming the encapsulation layer, consisting of the dielectric layers 12, 13, on p-MTJ sidewalls. First, a method for fabricating multiple p-MTJs is described. Fig. 2. A p-MTJ layer stack is formed on a lower electrode layer, which includes the lower electrode 10a. All layers in the MTJ stack can be deposited in a DC sputtering chamber of a sputtering system such as an Anelva C-7100 sputtering system, which includes multi-target ultra-high vacuum DC magnetron sputtering chambers and at least one oxidation chamber to form a tunnel barrier such as MgO from a Mg layer, thereby providing a TMR effect. Typically, the sputtering processes for different layers involve an inert gas such as Ar and a base pressure between 6.7 × 10⁻⁶. -8 and 6.7 × 10 -9 mbar (5 × 10 -8 and 5 × 10 -9 Torr) one.

[0029] A photoresist layer is formed on the MTJ stack and structured using a well-known photolithography technique to create several islands, including photoresist islands 30a and 30b, each with a width w. Subsequently, a conventional reactive ion etching (RIE) or ion beam etching (IBE) process is performed to remove regions of the p-MTJ stack not protected by a photoresist island. Note that the photolithography process produces an array of photoresist islands arranged in rows and columns such that each island acts as an etch mask, and the RIE or IBE process creates a p-MTJ beneath each etch mask. Therefore, the p-MTJs 11a and 11b with the side walls 11s1 and 11s2 are formed accordingly under the islands 30a and 30b and there are openings 50 on each side of the MTJs that expose sections of the upper surface of the lower electrode 10t.Each p-MTJ has a top surface on plane 22-22. In the embodiment, the RIE or IBE process forms the non-vertical sidewalls 11s1 and 11s2, such that a bottom surface of each MTJ has a greater width than w on the top surface 10t. However, depending on the etching conditions, essentially vertical MTJ sidewalls can be produced, resulting in a width w on the top and bottom p-MTJ surfaces.

[0030] With reference to Fig. 3. A conventional process is used to remove the photoresist islands 30a, 30b. Then, a first deposition step is performed to deposit the first dielectric layer onto the array of p-MTJs, including p-MTJ 11a and p-MTJ 11b. Crucially, the dielectric material 24 is formed in a PVD process that includes radiofrequency (RF) sputtering using an RF magnetron source. The elements 24 are oriented at an angle > 0 degrees with respect to the z-axis, ensuring adequate coverage of the resulting first dielectric layer 12 on the p-MTJ sidewalls 11s1, 11s2. An inert gas such as Ar, Kr, Ne, or Xe is used for the sputtering process, and the PVD RF sputtering conditions are configured to localize ionized elements from the plasma to the target cathode.In a preferred embodiment, the RF power is in the range of 300 to 1500 watts with an inert gas pressure of 6.67 × 10. -5 mbar up to 27 × 10 -3 mbar (0.05 to 20 mTorr) maintained at room temperature during the deposition of the first dielectric layer, which may have a D-layer composition or, as previously described, is one of B, Ge, BX or GeX.

[0031] In an alternative embodiment, the deposition of a BX or GeX layer as the first dielectric layer 12 can comprise two steps, as described in the related publication US 2018 / 0269385A1. For example, a B or Ge layer can be deposited on the p-MTJ sidewalls 11s1, 11s2 by PVD RF sputtering in a first step. Then, in a second step, the X layer is deposited on the B layer by PVD RF sputtering and, under certain conditions, re-sputters the B or Ge layer to produce a single BX or GeX layer. Furthermore, the B or Ge layer initially deposited by RF sputtering can be subjected to oxidation, such as natural oxidation or nitride formation, to form a first BO, GeO, BN, or GEN dielectric layer, respectively.

[0032] With reference to Fig. 4 shrinks each opening 50 ( Fig. 2) between adjacent p-MTJs with an opening 50a after the first dielectric layer 12 has been deposited. Preferably, a substantially uniform thickness of at least 3 angstroms exists on the upper surfaces 11t1, 11t2 and on the sidewalls 11s1, 11s2 of p-MTJ 11a and p-MTJ 11b. As a result of the PVD-HF sputtering process, the interface between the p-MTJ sidewalls and the first dielectric layer is thermodynamically stable with substantially no attack or damage on the sidewalls or upper surfaces by the elements 24 in the first embodiment, wherein the first dielectric layer 12 in Fig. 1 is a single layer.

[0033] The present disclosure also anticipates embodiments in which the first dielectric layer has a B / BX or Ge / GX configuration, or a B / D, BX / D, Ge / D, or GeX / D configuration. Accordingly, the PVD RF sputtering process described above, which involves an RF power of 300 to 1500 watts and an inert gas pressure of 6.67 × 10⁻⁵ mbar to 27 × 10⁻³ mbar (0.05 to 20 mTorr), can be repeated. In particular, a first PVD RF sputtering step comprises the deposition of a B, Ge, BX, or GeX layer. Then, a second PVD RF sputtering step is used to deposit a D layer on top of the B, Ge, BX, or GeX layer.

[0034] With reference to Fig. 5. A second deposition step is carried out, which involves the reactive elements 25 during the formation of an upper layer 12-2 on a lower layer 12-1 to form a two-layer stack for the first dielectric layer 12. The second deposition step can include the same PVD RF sputtering conditions as the first deposition, which involves the reactive elements 24. In some embodiments, during the second deposition step according to the second embodiment of the present disclosure, a BX layer is deposited on a B layer, a GeX layer is deposited on a Ge layer, or a D layer is deposited on a B, BX, Ge, or GeX layer.

[0035] In Fig. Figure 6 shows the upper layer 12-2 on an upper surface of the lower layer 12-1 as a product of the second deposition step. Here, the first dielectric layer 12 comprises Fig. 1 the two-layer stack 12-1 / 12-2. The openings 50b are formed above the top layer and between adjacent p-MTJs 11a, 11b.

[0036] According to the third embodiment, which is in Fig. As shown in Figure 7, a third deposition step is performed on the intermediate structure using the previously defined PVD-HF sputtering conditions. Fig. 6. As a result, a different intermediate structure is generated, wherein the first dielectric layer 12 has a three-layer configuration, with an upper layer 12-3 formed on a two-layer stack 12-1 / 12-2. The upper layer can, for example, be a D-layer, while 12-1 is B or Ge, and the middle layer 12-2 is BX or GeX.

[0037] According to one embodiment, which is in Fig. As shown in Figure 8, the second dielectric layer 13 is deposited on the first dielectric layer 12 by a PVD, PECVD or CVD process to form the openings 50a in the embodiment of Fig. 4 or the openings 50b in the embodiment of Fig. 6 or the openings 50c in the embodiment of Fig. 7 to fill. The PVD, PECVD, or CVD process can involve a temperature in the range of 200 °C to 400 °C to improve the deposition rate and reduce the processing time. The second dielectric layer preferably has a minimum thickness h of substantially greater than 0 over the 22-22 plane. The second dielectric layer can be an oxide such as Al2O3 or SiO2, but other oxides, nitrides, oxynitrides, or carbonitrides can be used, such as one of the D-layer materials.

[0038] In Fig. 9 A well-known chemical-mechanical polishing (CMP) process is carried out to remove an upper portion of the second dielectric layer 13 such that the partially formed storage device has an upper surface along the plane 22-22, which accordingly comprises the second upper dielectric layer surface 13t, the first upper dielectric layer surface 12t, and the upper surfaces 11t1 and 11t2 of p-MTJ 11a and p-MTJ 11b. The plane 22-22 is parallel to the upper surface of the lower electrode 10t. In some embodiments, the uppermost p-MTJ layer (not shown) is a hard mask such as MnPt, Ta, TaN, Ti, TiN, or W with an upper surface that is 11t1 or 11t2. In other embodiments, the uppermost p-MTJ layer is a capping layer such as Ru, or it has, for example, a Ru / Ta / Ru configuration.

[0039] With renewed reference to Fig. 1 follows a sequence of steps that are well known in the prior art and includes the deposition of the insulating layer 15 on level 22-22 in Fig. 9 and photoresist structuring and etching processes are used to form an upper electrode layer with upper electrodes 14a, 14b within the insulating layer. The upper electrode 14a is adjacent to the upper surface of the p-MTJ 11a, and the upper electrode 14b contacts the upper surface of the p-MTJ 11b. As mentioned previously, the upper electrode layer typically comprises several upper electrodes, formed, for example, in an arrangement of parallel conductors, but only two upper electrodes are shown in the embodiment. The insulating layer can be silicon oxide or aluminum oxide, or other dielectrics used in the field to electrically insulate adjacent conductive traces.

[0040] With reference to Fig. Figure 10 is a top view of the storage structure in Fig. Figure 1 shows the location where the cross-sectional view is shown. Level 20-20 indicates the location where the cross-sectional view is shown in Fig. 1. In the embodiment in which two additional p-MTJs 11c and 11d are shown between a second lower electrode 10b and the upper electrodes 14a, 14b, the width w1 of the upper electrodes is preferably larger than the width w of the p-MTJs 11a-11d. Furthermore, the length b of the lower electrodes 10a, 10b in the y-axis direction is typically greater than the length c of the p-MTJs. The p-MTJs have a substantially circular shape, which can be a circle or an ellipse. In other embodiments, the p-MTJs can have a polygonal shape, such as a square or a rectangle.

[0041] In Fig. Figure 11 shows a further embodiment of the present disclosure in which the encapsulation layer consisting of the dielectric layers 12, 13 described above can be used as a protective coating in an STO device. An STO device 40 is formed between a main pole layer 17 and a rear shield 18. In this case, a direct current (100% duty cycle) or pulsed current i flows from a source 35 through the conductor 36 to the main pole 17 and then passes through the STO 40 and the rear shield 18 before exiting through the conductor 37. The pulsed current can be on for a duration of approximately 0.1 ns followed by an off-time of a fraction of a nanosecond up to several nanoseconds.The STO 40 can have a bottom spin valve configuration in which a seeding layer 41, spin polarization (SP) layer 42, non-magnetic spacer element 43, oscillation layer (OL) 44, and capping layer 45 are sequentially formed on the main pole, such that a lower surface of the seeding layer contacts the main pole and an upper surface of the capping layer contacts the rear shield. One or both layers 41 and 43 can incorporate a metal oxide to induce perpendicular magnetic anisotropy (PMA) 46 in the SP layer. The z-axis is the direction of medium movement, and the down-track direction is [missing information].

[0042] During a write process, the magnetic flux 8 passes through ABS 33-33 and traverses the magnetic medium 7 and the soft sublayer 6, and the flux 8a re-enters the write head through the rear shield 18. Under a gap field 8b of several thousand Oe and a dc bias across the STO, the write process is assisted by a spin-polarized current passing from the SP layer 42 to the OL 44 with a sufficient magnitude (critical current density) to cause a large angular oscillation 47 with a specific amplitude and frequency in the OL, which imparts an RF field 49 to the medium bit 9. The combined effect of the RF field and the magnetic field 8 enables the magnetization 5 in the bit to be switched with a lower magnetic field than if only the magnetic field 8 were applied.

[0043] The STO device 40 is considered a p-MTJ, wherein the SP layer 42 serves as a reference layer, the non-magnetic spacer element 43 is a tunnel barrier, and the OL layer 44 is effectively a free layer. The composition of layers 41-45 is described in detail in connection with US patent 9,230,571 B1. A key feature of the present disclosure is that the encapsulation layer 12 is formed on an exit side 17t of the main pole and on a side wall 40s of the STO 40, thereby protecting the side wall during the deposition of the insulating layer 13, which is formed between the main pole layer 17 and the rear shield 18. As a result, the STO device retains its structural integrity during subsequent manufacturing steps, in contrast to the prior art, where the STO sidewall is susceptible to damage from reactive gases used in the deposition of the dielectric layer.

[0044] With reference to Fig. 12. An experiment was conducted to demonstrate the improved performance achieved by implementing an encapsulation layer on p-MTJ sidewalls according to an embodiment of the present disclosure. A series of p-MTJs with a CoFeB / MgO / CoFeB reference layer / tunnel barrier / free layer stack was encapsulated with a circular shape (w = c in Fig. 10) fabricated, varying the diameter w from approximately 30 nm to 450 nm. The parallel-state resistance varied from approximately 102 ohms for the largest p-MTJ size to approximately 104 ohms for the smallest size. An initial sample set was fabricated by depositing a first reference encapsulation layer onto a first group of p-MTJs using a conventional process. The process involved depositing a first Si3N4 dielectric layer 20.0 nm thick using a PECVD process. Subsequently, PECVD was used to deposit a second Si3N4 dielectric layer 200.0 nm thick onto the first Si3N4 dielectric layer using the same process conditions as for the first layer. The results are shown as curve 60.

[0045] A second comparison encapsulation layer was deposited on a second group of p-MTJs using a different conventional process. In this case, the 20.0 nm thick Si3N4 layer was deposited on the p-MTJ sidewalls using PVD-DC sputtering with Ar and N2 plasma. Subsequently, a second Si3N4 dielectric layer with a thickness of 200.0 nm was deposited by the same PECVD process as described above. The results are shown in curve 61.

[0046] A third sample set was produced by depositing an encapsulation layer onto a third group of p-MTJs according to an embodiment of the present disclosure. In particular, a first dielectric layer with a Si3N4 / MgO (2 wt%) composition and a thickness of 20.0 nm was deposited from a single target by PVD RF sputtering using a process involving RF power and an Ar volume flow. Subsequently, a second dielectric layer with a Si3N4 composition and a thickness of 200.0 nm was formed by the PECVD process used to deposit the second Si3N4 layer in the preceding two sample sets. The results are shown in curve 62, where point 62a represents the smallest p-MTJ size and point 62b represents the largest p-MTJ size in the third sample set. Therefore, several different p-MTJ sizes were produced for each of the three sample sets, and an encapsulation layer was formed on each p-MTJ.All samples were tempered at 400 °C for the same period of time.

[0047] The TMR ratio (dR / R) was measured at 25 °C for each sample using an Accretech UF300A analyzer. Note that DRR is plotted on the y-axis in Fig. Figure 12 shows the AR / R ratio, where 0.8 can alternatively be expressed as 80%, 1.2 as 120%, and so on. In general, DRR is substantially increased for each p-MTJ size, particularly as the size decreases to 100 nm and below, when an encapsulation layer deposited by a PVD-HF sputtering process disclosed herein is used to protect the p-MTJ.

Claims

[1] Magnetic device comprising: (a) several vertically magnetized MTJs (11a, 11b), each of which has a side wall extending from an upper surface to a lower surface, the lower surface contacting a lower electrode (10a) and the upper surface contacting an upper electrode (14a, 14b) on a first plane parallel to the lower surface; (b) an encapsulation layer (12, 13) which adjoins the side wall from the upper surface to the lower surface of each perpendicularly magnetized MTJ and has an upper surface on the first plane, wherein the encapsulation layer has: (1) a first dielectric layer (12) comprising a lower layer (12-1) containing B or Ge, which contacts the perpendicularly magnetized MTJ side wall, and an upper layer (12-3) comprising one or more SiO Y N Z , AIO Y N z TiO Y N z , SiC y Nz or MgO, where y + z > 0; and (2) a second dielectric layer (13) formed on an upper surface of the first dielectric layer and having a composition comprising one of metal oxide, metal nitride, metal carbide, metal oxynitride or metal cyanide nitrogen or combinations thereof. [2] Magnetic device according to claim 1, wherein each vertically magnetized MTJ is part of an MRAM, spin-torque MRAM, e-flash or spin-torque oscillator structure. [3] Magnetic device according to claim 1, wherein the first dielectric layer has a two-layer configuration with a thickness of approximately 0.3 to 40 nm. [4] Magnetic device according to claim 1, wherein the lower layer in the first dielectric layer is one of B, BX, Ge or GeX, wherein X is one of N, O, B, C, Ge, Al, P, Ga, In, TI, Mg, Hf, Zr, Nb, V, Ti, Cr, Mo, W, Sr or Zn. [5] Magnetic device according to claim 1, wherein the lower layer in the first dielectric is B or Ge and the first dielectric layer further comprises a middle layer (12-2) between the lower layer and the upper layer and the middle layer has a BX or GeX configuration, wherein X is one of N, O, B, C, Ge, Al, P, Ga, In, TI, Mg, Hf, Zr, Nb, V, Ti, Cr, Mo, W, Sr or Zn. [6] Magnetic device according to claim 5, wherein the first dielectric layer has a thickness of approximately 0.3 to 40 nm. [7] Magnetic device according to claim 1, wherein the second dielectric layer is made of SiO Y N Z , AlOyNz, TiO Y N z , SiC y N z or MgO or combinations thereof, where y + z > 0. [8] Magnetic device according to claim 1, wherein the first dielectric layer contains 0.1 to 10 wt.% of a metal oxide in a metal nitride matrix. [9] Magnetic device according to claim 8, wherein each vertically magnetized MTJ is part of an MRAM, spin-torque MRAM or spin-torque oscillator structure. [10] Magnetic device according to claim 8, wherein the first dielectric layer contains MgO formed in a silicon nitride matrix. [11] Magnetic device according to claim 8, wherein the first dielectric layer has a thickness of approximately 0.3 to 40 nm. [12] Magnetic device according to claim 8, wherein the second dielectric layer is made of SiO Y N Z , AlOyNz, TiO Y N z , SiC y N z or MgO or combinations thereof, where y + z > 0. [13] Method for forming a magnetic device comprising: (a) Providing several vertically magnetized MTJs (11a, 11b) separated by openings (50) on an upper surface of a substrate (10a), each vertically magnetized MTJ having a side wall extending from an upper surface to the upper substrate surface, and each upper vertically magnetized MTJ surface being located on a first plane; (b) Deposition of a first dielectric layer (12) on each perpendicularly magnetized MTJ sidewall using a physical vapor deposition process comprising RF sputtering, wherein the first dielectric layer is composed of SiO Y N Z , AlOyNz, TiO Y N z , SiC y N z or contains MgO or combinations thereof, where y + z > 0; and (c) Deposition of a second dielectric layer (13) on the first dielectric layer, wherein the second dielectric layer fills the openings between the perpendicularly magnetized MTJs and has a thickness substantially greater than 0 above the first plane, wherein the second dielectric layer contains a metal oxide, metal nitride, metal carbide, metal oxynitride or metal cyanide nitrogen or combinations thereof. [14] The method of claim 13, further comprising: (a) Performing a chemical-mechanical polishing process to form a top surface on the second dielectric layer that is coplanar with the top surface on each of the multiple perpendicularly magnetized MTJs; and (b) Carrying out a tempering process at a temperature of approximately 400 °C. [15] Method according to claim 13, wherein the substrate is a lower electrode (10a) in an MRAM or a spin-torque MRAM or a main pole layer in a spin-torque oscillator. [16] Method according to claim 13, wherein the first dielectric layer has a thickness of approximately 0.3 to 40 nm. [17] Method according to claim 13, wherein the first dielectric layer contains B, Ge, BX or GeX, wherein X is one of N, O, B, C, Ge, Si, Al, p, Ga, In, Ti, Mg, Hf, Zr, Nb, V, Ti, Cr, Mo, W, Sr and Zn. [18] The method of claim 13, wherein the physical vapor deposition RF sputtering of the first dielectric layer comprises a first physical vapor deposition RF sputtering step to deposit a lower layer (12-1) that is one of B, BX, Ge or GeX, wherein X is one of N, O, B, C, Ge, Si, Al, P, Ga, In, Ti, Mg, Hf, Zr, Nb, V, Ti, Cr, Mo, W, SR and Zn, and then performing a second physical vapor deposition RF sputtering step to deposit an upper layer (12-3) on the lower layer, wherein the upper layer is SiO Y N Z , AlOyNz, TiO Y N z , SiC y N z or MgO or combinations thereof, where y+z > 0. [19] The method of claim 13, wherein the physical vapor deposition RF sputtering of the first dielectric layer comprises a first physical vapor deposition RF sputtering step to deposit a lower layer that is B or Ge, a second physical vapor deposition RF sputtering step to deposit a middle layer (12-2) of BX or GeX, wherein X is one of N, O, B, C, Ge, Si, Al, P, Ga, In, Ti, Mg, Hf, Zr, Nb, V, Ti, Cr, Mo, W, Sr and Zn, and a third physical vapor deposition RF sputtering step to deposit a top layer on the middle layer, wherein the top layer is SiO Y N Z , AIO Y N z TiO Y N z , SiC y N z or MgO or combinations thereof, where y + z > 0. [20] Method according to claim 13, wherein the second dielectric layer is deposited by a chemical vapor deposition, physical vapor deposition or plasma-assisted CVD process. [21] Method according to claim 13, wherein the physical vapor deposition RF sputtering process uses an RF power of 300 to 1500 watts and an inert gas pressure between 6.67 × 10 -5 mbar and 27 × 10 -3 mbar and an inert gas that is one of Ar, Kr, Xe and Ne. [22] Method according to claim 13, wherein the first dielectric layer consists of a metal oxide formed in a metal nitride matrix. [23] Method according to claim 22, wherein the first dielectric layer has a composition comprising 0.1 to 10 wt.% of MgO in a silicon nitride matrix.

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