Methods for manufacturing multiple semiconductor chips and semiconductor chips

Abstract

A method for fabricating multiple semiconductor chips (100), comprising the steps: A) providing a semiconductor substrate (1) with multiple integrated electronic circuits (2) on a top side (10) of the semiconductor substrate (1); B) applying a sacrificial layer (3) to one side of the semiconductor substrate (1); C) introducing holes (30) into the sacrificial layer (3) such that at least one hole (30) is formed over each electronic circuit (2); D) bonding the semiconductor substrate (1) sacrificial layer (3) forward onto a support (5), wherein an adhesive layer (4) is used between the sacrificial layer (3) and the support (5), and wherein the adhesive layer (4) fills the holes (30) so that retaining elements (40) of the adhesive layer (4) are formed in the holes (30); E) thinning the semiconductor substrate (1);F) Creating separation trenches (6) between the electronic circuits (2), extending from a side of the electronic circuits (2) facing away from the substrate (5) to the sacrificial layer (3) and penetrating the thinned semiconductor substrate (1); G) Removing the sacrificial layer (3) in the area between the electronic circuits (2) and the substrate (5) so that the electronic circuits (2) are held on the substrate (5) by the retaining elements (40).

Description

A method for producing a plurality of semiconductor chips is specified. Furthermore, a semiconductor chip is specified.From the documents US 2017 / 0 133 356 A1, US 2019 / 0 115 274 A1 and US 2014 / 0 196 850 A1, methods for producing a plurality of semiconductor chips and a semiconductor chip are known.One object to be achieved is to specify a method which enables parallel mounting of a plurality of semiconductor chips. A further object to be achieved is to specify a semiconductor chip produced by this method.These objects are achieved, among other things, by the method and the subject matter of the independent claims. Advantageous embodiments and developments are the subject matter of the dependent patent claims.The method comprises a step A) in which a semiconductor substrate with a plurality of integrated electronic circuits is provided on a top side of the semiconductor substrate.The semiconductor substrate preferably extends along a main extension plane. The top side of the semiconductor substrate may extend substantially parallel to the main extension plane. The semiconductor substrate is, for example, a silicon substrate. On the top side, the electronic circuits are arranged next to one another.Each electronic circuit may include one or more electronic components interconnected with each other. For example, an electronic circuit comprises one or more transistors and / or one or more diodes and / or one of the plurality of resistors and / or one or more capacitances. The transistors may be field effect transistors or bipolar transistors.The electronic circuits are integrated into the semiconductor substrate. That is, the electronic components of the electronic circuits are partially integrated into the semiconductor substrate. In each electronic circuit, a region of the semiconductor substrate, in particular the region directly below the top side, forms a functional constituent part of at least one electronic component. During the intended operation of the electronic circuits, a current flow or charge carrier transport therefore occurs in this region of the semiconductor substrate. In particular, the semiconductor substrate may comprise n-doped regions and / or p-doped regions below the top side, which are for example constituents of transistors or diodes.The semiconductor substrate can be formed continuously, preferably simply continuously. It spans a plurality of electronic circuits and connects the electronic circuits to one another. In other words, the electronic circuits are provided in wafer assemblage.The lateral extent of the semiconductor substrate, measured parallel to the main plane of extent, is, for example, between 100 mm and 500 mm inclusive.The electronic circuits in particular each comprise a wiring layer formed on the upper side of the semiconductor substrate. Each wiring layer comprises, for example, an electrically insulating material, such as an oxide, in particular silicon oxide. Conductor tracks, in particular metallic conductor tracks, are embedded in the electrically insulating material (ILD: interlayer dielectric). The conductive tracks can be electrically connected to the semiconductor substrate. Portions of the conductive traces and the semiconductor substrate may form the transistors or diodes or resistors in the electronic circuit. Capacitances in the electronic circuit are formed, for example, within the wiring layer by interconnects spaced apart from one another. The wiring layer is, for example, between 3 μm and 15 μm thick.The wiring layers of the electronic circuits may initially be contiguous, i.e. form a contiguous wiring layer on the upper side of the semiconductor substrate. In the region between the electronic circuits, the contiguous wiring layer is then preferably free of the conductor tracks. For example, the wiring layer is formed exclusively by electrically insulating material there.Alternatively, the continuous wiring layer may be formed of a metal such as aluminum or titanium or copper or tungsten in a region between the electronic circuits. This metal is then preferably electrically insulated from the conductor tracks of the electronic circuit. Preferably, the continuous wiring layer in this region is formed of a metal over its entire thickness.The method comprises a step B) in which a sacrificial layer is applied to one side of the semiconductor substrate. For example, the sacrificial layer may be deposited on the electronic circuits. Alternatively, the sacrificial layer may be applied to a bottom side of the semiconductor substrate opposite the electronic circuits.The sacrificial layer comprises, for example, silicon or silicon oxide or consists of one of these materials. The sacrificial layer is preferably applied as a continuous, in particular simply continuous, layer which extends over a plurality of the electronic circuits or over all the electronic circuits. A thickness of the sacrificial layer is, for example, between 100 nm and 1 μm inclusive.The method comprises a step C) in which a plurality of holes are introduced into the sacrificial layer, so that at least one hole is formed above each electronic circuit. The holes preferably completely penetrate the sacrificial layer. The holes can be introduced, for example, with the aid of a photolithography mask and an etching method. For example, exactly one hole or a plurality of holes, for example at most 20 holes or at most 10 holes, are introduced in the region of each electronic circuit.In a step D), the semiconductor substrate is bonded to a carrier together with the electronic circuits and with the sacrificial layer in front, wherein an adhesive layer is used between the sacrificial layer and the carrier, and wherein the adhesive layer fills the holes, so that retaining elements made of the adhesive layer are produced in the holes. The adhesive layer can be introduced first onto the sacrificial layer and into the holes. The adhesive layer is applied to a side of the sacrificial layer facing away from the electronic circuits. The adhesive layer is preferably formed continuously.The dimensions of the retaining elements substantially correspond to the dimensions of the holes in the sacrificial layer. For example, the holding elements each have a diameter, measured along the main extension plane, of at most 10 μm or at most 5 μm or at most 3 μm. Alternatively or additionally, the diameter of each retaining element is at least 0.5 μm or at least 1 μm. The holding elements are, for example, cylindrical. The height of each holding element, measured as an extension perpendicular to the main extension plane of the semiconductor substrate, is, for example, between 100 nm and 1 μm inclusive.The adhesive layer comprises, for example, benzocyclobutene, BCB for short, and / or an epoxy-based adhesive. Alternatively, the adhesive layer may be made of one of these materials. The epoxy-based adhesive preferably has a glass transition temperature of at least 250° C. The semiconductor substrate is bonded to the carrier by a material bond via the adhesive layer. For this purpose, the adhesive layer is cured, for example.The carrier may comprise or consist of a semiconductor material or a glass. The lateral extent of the carrier is preferably at least as large as the lateral extent of the semiconductor substrate, such that the semiconductor substrate can be placed on the carrier over the full surface. The lateral extent is defined as an extent parallel to the respective main extension plane of the semiconductor substrate or carrier.The method comprises a step E) in which the semiconductor substrate is thinned, i.e. reduced in thickness. For example, the semiconductor substrate is ground and / or polished and / or etched for this purpose. For example, the semiconductor substrate is thinned to a target thickness between 3 μm and 30 μm, inclusive. Before this, the thickness of the semiconductor substrate is, for example, at least 100 μm or at least 500 μm.The method comprises a step F) in which separation trenches are introduced between the electronic circuits. The separating trenches extend from a side of the electronic circuits facing away from the carrier as far as the sacrificial layer and penetrate the thinned semiconductor substrate. In the region of the separating trenches, the sacrificial layer is exposed. The separating trenches can be introduced, for example, in the form of a grid network, such that each electronic circuit is surrounded completely by a contiguous separating trench laterally, that is to say along the main extension plane. The width of the separating trenches is, for example, between 1 μm and 20 μm inclusive.In particular, the separating trenches define the size of the semiconductor chips produced by means of the method. For example, the lateral extent of each semiconductor chip or the lateral extent of the mesh surrounding a separating trench is at least 10 μm or at least 50 μm. Alternatively or additionally, the lateral extent is at most 1000 μm or at most 300 μm or at most 200 μm. Each semiconductor chip or each mesh surrounding the separating trenches may have an area of at least 10 μm×10 μm and / or of at most 1000 μm×10000 μm.The separating trenches extend in particular through the thinned semiconductor substrate and through the contiguous wiring layer, so that after the introduction of the separating trenches, the electronic circuits are no longer connected to one another via the semiconductor substrate or the contiguous wiring layer. The electronic circuits are then preferably connected to one another exclusively via the second carrier.By introducing the separating trenches, the contiguous semiconductor substrate with the contiguous wiring layer applied thereon is therefore singulated into a plurality of semiconductor chips. Each semiconductor chip then comprises an electronic circuit with a part of the semiconductor substrate and a wiring layer.The method comprises a step G) in which the sacrificial layer is removed in the region between the electronic circuits and the carrier, so that the electronic circuits are held on the second carrier via the holding elements, in particular exclusively via the holding elements. The sacrificial layer is removed, for example, to an extent of at least 80% or at least 90% or at least 99% from the region between the electronic circuits and the carrier.The holding elements form selective mechanical supports underneath each electronic circuit. In the region next to the holding elements, the electronic circuits are not connected to the carrier, so that the electronic circuits in these regions are arranged freely suspended over the carrier without mechanical support. In other words, the electronic circuits are mechanically connected to the carrier via the holding elements only over a small area proportion, for example of at most 10% of the total area of the electronic circuit. This allows easy detachment of the electronic circuits from the carrier. However, until the electronic circuits are detached from the carrier, they remain interconnected in their original configuration by virtue of the carrier.The removal of the sacrificial layer is effected in particular by etching away the sacrificial layer. For this purpose, an etchant can reach the sacrificial layer via the separating trenches.In at least one embodiment, the method for manufacturing a plurality of semiconductor chips comprises a step A) in which a semiconductor substrate having a plurality of integrated electronic circuits is provided on a top side of the semiconductor substrate. In a step B), a sacrificial layer is applied to one side of the semiconductor substrate. In a step C), holes are introduced into the sacrificial layer, so that at least one hole is formed above each electronic circuit. In a step D), the semiconductor substrate is bonded to a carrier with the sacrificial layer first, wherein an adhesive layer is used between the sacrificial layer and the carrier, and wherein the adhesive layer fills the holes, so that retaining elements made of the adhesive layer are produced in the holes. In a step E), the semiconductor substrate is thinned. In a step F), separating trenches are introduced between the electronic circuits, which extend from a side of the electronic circuits facing away from the carrier as far as the sacrificial layer and penetrate the thinned semiconductor substrate. In a step G), the sacrificial layer in the region between the electronic circuits and the carrier is removed, so that the electronic circuits are held on the carrier via the holding elements.The use of a sacrificial layer patterned with holes and the filling of these holes with an adhesive layer, so that retaining elements are produced, leads after the removal of the sacrificial layer to the electronic circuits only being fastened to the carrier via the retaining elements. The holding elements thus form supports or pillars between the carrier and the electronic circuits. For detaching the electronic circuits from the carrier, therefore, only a very small amount of force is required. Until detachment, however, the electronic circuits are arranged in their original configuration, that is to say in their original order and with their original distances from one another. Thus, a plurality of electronic circuits can be mounted or printed in parallel, with easy detachment from the substrate being guaranteed.According to at least one embodiment, steps A) to G) are performed as separate steps in succession and in the order indicated.According to at least one embodiment, after step G), a contact area between the holding elements and an electronic circuit is at least 0.1% or at least 1% of the total surface of the electronic circuit facing the carrier. Alternatively or additionally, the contact surface amounts to at most 10% or at most 8% or at most 5% of the total surface of the electronic circuit facing the carrier. The rest of the surface facing the carrier is arranged suspended above the carrier and is not mechanically connected to the carrier. Such a small proportion of the contact area on the total area of the electronic circuit guarantees an easy detachment of the electronic circuit from the carrier.According to at least one embodiment, an intermediate step F 1) is carried out in order to carry out step F), in which an photoresist layer is applied to the side of the electronic circuits facing away from the carrier. The photoresist layer may be a positive or negative photoresist.According to at least one embodiment, an intermediate step F 2) is carried out in order to carry out step F), in which intermediate step the photoresist layer is patterned with trenches, the trenches being formed where the separating trenches are intended to be produced later. The trenches in the photoresist layer completely penetrate the photoresist layer and define the position of the separating trenches to be formed later. In particular, the trenches in the photoresist layer are therefore also formed circumferentially around the electronic circuits and form a grid network, for example.According to at least one embodiment, an intermediate step F 3) is carried out in order to carry out step F) by applying an etching method for producing the separating trenches in the region of the trenches. For example, a dry chemical or wet chemical etching process is used. The etchant then passes through the trenches to the materials connecting the electronic circuits and can etch isolation trenches into this material.According to at least one embodiment, steps F 1), F 2), and F 3) are performed in the order indicated.According to a first embodiment, the support is a transparent support, for example a glass support. "Transparent" here means transparent to visible light. The transparent carrier can advantageously be used to identify structures of the electronic circuits. Such structures can be, for example, metallic contact structures or markings. These structures can serve for the adjustment of the separating trenches or trenches. For example, a system with rear side adjustment is used for this purpose.Alternatively, however, it is also possible for the carrier to be formed from a non-transparent material, such as silicon. The position of the structures through the material of the semiconductor substrate or through the material of the carrier can then be determined by means of an IR camera and the alignment for the separating trenches or trenches can be carried out on the basis of said position. In this case, a system with front-side adjustment can be used.According to at least one embodiment, an anisotropic, fluorine-based etching process is carried out in step F) in order to produce the separating trenches. The etching process may be dry chemical, for example. Such an etching process is suitable in particular for the penetration of the semiconductor substrate. Here, for example, a fluorine-containing gas such as SF 6, is used. Such an etching process is also known as a Bosch process. Fluoropolymers are formed in the region of the penetrated semiconductor substrate, which form a lateral etch stop layer. Such an etching process can produce separating trenches with particularly steep side flanks.In order to penetrate the continuous wiring layer in the areas between the electronic circuits with the separating trenches, another etchant such as hydrofluoric acid may be used. It is particularly advantageous if, as already explained above, the contiguous wiring layer is formed from a metal in the region between electronic circuits and where the separating trenches are to be formed. Namely, the separation trenches may then be formed through the metal. Metal is often easier to etch than, for example, oxide. Suitable metals are, for example, aluminum or titanium. The metal may then be selectively etched to the surrounding oxide of the contiguous interconnect layer.According to at least one embodiment, a dry chemical etching method is used for removing the sacrificial layer in step G). For example, the same anisotropic fluorine-based etching process as in step F) may be used to remove the sacrificial layer. For example, SF 6 or XeF 2 is used as the etchant.According to at least one embodiment, in step G) the etchant used reaches the sacrificial layer via the separating trenches. The etchant removes, for example, at least 80% or at least 90% or at least 99% of the sacrificial layer in the region between the electronic circuits and the carrier.According to at least one embodiment, isolation trenches extend between two, in particular between two, electronic circuits and / or in the region of the electronic circuits from the top side of the semiconductor substrate as far as into the semiconductor substrate. The isolation trenches protrude, for example, at least 3 μm or at least 4 μm or at least 5 μm deep into the semiconductor substrate. Alternatively or additionally, the depth of the insulation trenches is at most 10 μm or at most 9 μm or at most 8 μm. The width of the isolation trenches is, for example, between 1 μm and 3 μm inclusive. The isolation trenches preferably project deeper into the semiconductor substrate than electronically functional regions of the electronic circuits, in particular as n- and / or p-doped regions of the semiconductor substrate. Such isolation trenches are also referred to as deep trench isolation.In the region of the electronic circuits, for example between two adjacent transistors of an electronic circuit, the isolation trenches can also be formed to be less deep. Such so-called shallow trench isolations have depths of at most 3 μm or at most 2 μm, for example.The isolation trenches may laterally run completely around the electronic circuits and define the lateral extension of an electronic circuit.According to at least one embodiment, the isolation trenches are filled with an electrically insulating material, such as silicon oxide. For example, the electrically insulating material of the wiring layer fills the isolation trenches.According to at least one embodiment, in step E) the semiconductor substrate is thinned until the isolation trenches, in particular the electrically insulating material of the isolation trenches, are exposed. The exposed isolation trenches can then serve as landmarks for the alignment of the isolation trenches.In addition to acting as landmarks, the isolation trenches may also provide electrical isolation between electronic devices within an electronic circuit. For example, the distance of an insulation trench from an electronic component is at least 5 μm or at most 8 μm.In order to make the isolation trenches or the electrically insulating material visible within the isolation trenches after thinning the semiconductor substrate, a further etchant may be used which has different etching rates for the electrically insulating material and the material of the semiconductor substrate.According to at least one embodiment, in step F) the separating trenches are formed through the exposed insulating trenches. Advantageously, etching does not then have to be carried out through the semiconductor material of the semiconductor substrate, but only through an electrically insulating material, such as silicon oxide.According to at least one embodiment, two isolation trenches are formed between two electronic circuits, in particular between two electronic circuits each, which laterally delimit a separation region of the semiconductor substrate. In particular, the separating region is separated from the electronic circuits on both sides by the insulation trenches. For example, after thinning the semiconductor substrate, the separating region is electrically insulated from the remaining regions of the semiconductor substrate by the insulation trenches.According to at least one embodiment, in step F) the separation trenches are formed through the separation region. The isolation trenches can delimit the isolation trenches in their width when forming the isolation trenches, since the material in the isolation trenches is not attacked, or is attacked to a lesser extent, by the etchant used, for example, than the semiconductor material in the isolation regions.According to at least one embodiment, each electronic circuit has a first contact structure arranged above the upper side for electrically contacting the electrical circuit. "Above the upper side" means here that the contact structure is arranged outside the semiconductor substrate. The first contact structure is formed, for example, in the wiring layer of the electronic circuit. The first contact structure is preferably metallic. The first contact structure may be electrically insulated and spaced apart from the top side of the semiconductor substrate by a layer of electrically insulating material. This electrically insulating layer is formed in particular from an oxide, preferably silicon oxide. The thickness of the electrically insulating layer is, for example, at most 1 μm.According to at least one embodiment, the method comprises a step E 1) following the step E), in which contact holes are introduced into the thinned semiconductor substrate, such that the first contact structures are exposed. The contact holes are introduced, for example, from a side of the thinned semiconductor substrate facing away from the electronic circuits and completely penetrate the thinned semiconductor substrate. The contact holes can be introduced, for example, by means of an etching process. For this purpose, for example, an etching mask produced via a lithography process is used. The diameter of the contact holes is, for example, between 2 μm and 10 μm inclusive.After the contact holes are formed through the semiconductor substrate, the optional electrically insulating layer can also be etched through between the first contact structure and the top side. For this purpose, a different etchant can be used than for the etching through of the semiconductor substrate.According to at least one embodiment, the method comprises a step E 2) following the step E), in which an electrically conductive material, in particular a metal, is introduced into the contact holes. The electrically conductive material is preferably brought into direct electrical and mechanical contact with the first contact structures. The electronic circuits can then be electrically contacted via the electrically conductive material from a side of the thinned semiconductor substrate facing away from the electronic circuits.Before the introduction of the electrically conductive material, the inner walls of the contact holes can be passivated with a passivation layer. In a base region, the passivation layer is then removed again, so that the first contact structures are exposed. Only then is the electrically conductive material filled into the contact holes.Preferably, steps E1) and E2) are carried out before step F).According to at least one embodiment, the semiconductor substrate comprises in the region below the first contact structures in each case a first contact region which is laterally surrounded by an electrically insulating delimiting trench. The contact region comprises or consists of the semiconductor material of the semiconductor substrate. Each boundary trench may laterally completely surround the associated contact region. Each boundary trench may be formed continuously. The delimiting trenches are filled, for example, with an electrically insulating material, such as an oxide, in particular silicon oxide. The boundary trenches extend from the top side of the semiconductor substrate into the semiconductor substrate. The depths and widths of the delimiting trenches can be selected here like the depths and widths of the insulation trenches defined above. In particular, the delimiting trenches are likewise so-called deep trench isolations.According to at least one embodiment, in step E) the semiconductor substrate is thinned until the delimiting trenches and the contact regions surrounding it are exposed. In a plan view of the underside of the thinned semiconductor substrate facing away from the electrical circuits, each contact region is then surrounded by a continuous path of a delimiting trench. The contact region seen in the plan view of the underside has, for example, a diameter of at most 50 μm or at most 30 μm.According to at least one embodiment, the method comprises a step E3) following the step E), in which an electrically conductive material is applied to the thinned semiconductor substrate in the contact regions. On the underside of the thinned semiconductor substrate facing away from the electrical circuits, the contact region is thus electrically conductively connected to the electrically conductive material. At the top side, the contact region is electrically conductively connected to the first contact structure. As a result, the first contact structures can be contacted via the underside of the thinned semiconductor substrate. The delimiting trenches ensure electrical insulation between the contact regions and the remaining semiconductor material of the semiconductor substrate.In order to increase the electrical conductivity of the contact region from the bottom side to the top side of the thinned semiconductor substrate, metal vias, for example made of tungsten or aluminum, can be introduced or introduced into the contact regions. The metallic vias through the thinned semiconductor substrate are then laterally surrounded completely by the delimiting trench. The diameter of such a metallic through-contact is, for example, between 1 μm and 10 μm inclusive. It can be produced, for example, by a CVD method.Preferably, step E3) is carried out before step F).According to at least one embodiment, the method comprises a step E4) following step E), in which optoelectronic components are applied to the underside of the thinned semiconductor substrate facing away from the electrical circuits. In this case, the optoelectronic components are electrically conductively connected to the electronic circuits via the electrically conductive material. The optoelectronic component can be, for example, LED chips or laser diode chips. The lateral extent of the component is, for example, between 10 μm and 80 μm inclusive. Step E4) is preferably carried out before step F).According to at least one embodiment, after step A) and before step B), the semiconductor substrate with the electronic circuits is first applied to an auxiliary carrier. After the application, the electronic circuits are preferably arranged between the auxiliary carrier and the semiconductor substrate. Step E) is then carried out. Only after step E) are steps B), C), D), F) and G) then carried out, in particular, in this sequence. The sacrificial layer and the adhesive layer are preferably applied to a side of the thinned semiconductor substrate facing away from the auxiliary carrier.According to at least one embodiment, after step D) and preferably before step F), the auxiliary carrier is removed again.According to at least one embodiment, each electronic circuit comprises a region of the semiconductor substrate or of the thinned semiconductor substrate and an electronic component formed with this region of the semiconductor substrate. In particular, each electronic circuit comprises at least one, preferably a plurality of such electronic components.According to at least one embodiment, each electronic circuit includes a wiring layer on the semiconductor substrate. The wiring layer serves for contacting the electronic component. A wiring layer comprises, for example, a plurality of conductor tracks embedded in an electrically insulating material.According to at least one embodiment, each electronic circuit comprises a second contact structure on a side of the wiring layer facing away from the semiconductor substrate. The electronic circuit is electrically contactable via the second contact structure. The second contact structure comprises or consists of Al, for example.According to at least one embodiment, the wiring layers of the electronic circuits are contiguous in step A) and form a contiguous wiring layer.According to at least one embodiment, the contiguous wiring layer is metallic in the region of the separating trenches to be formed.According to at least one embodiment, in step F), the separation trenches are formed through the contiguous wiring layer.According to at least one embodiment, after step C), a dielectric layer is introduced between the sacrificial layer and the adhesive layer. The dielectric layer is preferably simply contiguous. The dielectric layer comprises, for example, Al 2 O 3 or SiO 2 or SiN x or consists of one of these materials.According to at least one embodiment, the dielectric layer partially fills the holes and separates the holding elements from the semiconductor substrate. When the electronic circuits are detached from the holding elements, the boundary surface between the dielectric layer and the holding elements then preferably tears open. This is gentler for the electronic circuits.Preferably, a second, in particular simply contiguous, dielectric layer is formed between the sacrificial layer and the semiconductor substrate. In the region of the holes, the dielectric layer can then directly border the second dielectric layer. The second dielectric layer preferably comprises a different material than the dielectric layer.According to at least one embodiment, the method comprises a step H), which preferably follows the step G) and in which the electronic circuits are detached from the carrier, so that individual semiconductor chips separated from one another are produced. Each semiconductor chip comprises one, preferably exactly one, electronic circuit.Furthermore, a semiconductor chip is specified. The method described here is suitable in particular for producing such a semiconductor chip. That is, all features disclosed in connection with the semiconductor chip are also disclosed for the method and vice versa.The semiconductor chip comprises a semiconductor substrate having an integrated electronic circuit on a top side of the semiconductor substrate.The electronic circuit includes a wiring layer on the top surface of the semiconductor substrate.The electronic circuit includes a first contact structure in the wiring layer.The first contact structure is electrically conductively connected to a contact region of the semiconductor substrate. The contact region preferably comprises or consists of the semiconductor material of the semiconductor substrate.The contact region extends completely from the upper side through the semiconductor substrate as far as a lower side of the semiconductor substrate opposite the upper side.The contact region is electrically conductively connected on the underside to an electrically conductive material, preferably a metallic material.The contact region is laterally surrounded completely by an electrically insulating delimiting trench which extends from the top side to the bottom side of the semiconductor substrate. The delimiting trench is filled, for example, with an electrically insulating material, such as oxide, in particular silicon oxide. The delimiting trenches may be formed from deep trench isolations.The semiconductor chip comprises an optoelectronic component on the underside of the semiconductor substrate. The optoelectronic component is electrically conductively connected to the electronic circuit via the electrically conductive material and the contact region. Along the main extension plane of the semiconductor substrate, the electronic component overlaps with the electronic circuit.A method described here for producing a plurality of semiconductor chips and a semiconductor chip described here are explained in more detail below with reference to drawings on the basis of exemplary embodiments. Identical reference numerals indicate identical elements in the individual figures. However, no references to scale are shown here; rather, individual elements may be represented with exaggerated size for better understanding.The following are shown: FIGS. 1A to 1G show different positions in a first exemplary embodiment of the method, FIGS. 2A to 2C show different positions in a second exemplary embodiment of the method, FIGS. 3A to 3E show different positions in a third exemplary embodiment of the method, FIGS. 4A to 4E show different positions in a fourth exemplary embodiment of the method, FIGS. 5A and 5B are perspective views of an embodiment of the semiconductor chip, FIGS. 6A to 6G show different positions in a fifth exemplary embodiment of the method, FIG. 7 shows a position in a sixth exemplary embodiment of the method.FIG. 1A shows a first position in a first exemplary embodiment of the method. A semiconductor substrate 1 having a top surface 10 is provided. On or on the top side 10, a plurality of laterally adjacently arranged integrated electronic circuits 2 is formed. The electronic circuits 2 are integrated in places into the semiconductor substrate 1. In particular, the electronic circuits 2 comprise electronic components 201, such as transistors and / or diodes, which are partially formed by n-doped and or p-doped regions below the top side 10 of the semiconductor substrate 1. The semiconductor substrate 1 is, for example, a silicon substrate.Each electronic circuit 2 further comprises a wiring layer 202 on the top side 10 of the semiconductor substrate 1. Each wiring layer 202 comprises an electrically insulating material 204, for example silicon oxide, in which a plurality of conductor tracks 205 is embedded. On the side facing away from the semiconductor substrate 1, each electronic circuit 2 comprises a second contact structure 203. The electronic circuit 2 can be contacted externally via this. In the region between two electronic circuits 2, the wiring layers 202 are connected to one another by the electrically insulating material 204.FIG. 1B illustrates a second position in the method, in which a sacrificial layer 3, for example made of silicon, is applied to the sides of the electronic circuits 2 facing away from the semiconductor substrate 1. The sacrificial layer 3 is penetrated by a plurality of holes 30. In this case, at least one such hole 30 is provided in the sacrificial layer 3 in the region of each electronic circuit 2.In FIG. 1C, a third position of the method is shown. An adhesive layer 4, for example made of BCB, is applied to the side of the sacrificial layer 3 facing away from the semiconductor substrate 1. The adhesive layer 4 fills the holes 30 in the sacrificial layer 3, whereby retaining elements 40 made of the material of the adhesive layer 4 are produced in the holes 30. The semiconductor substrate 1 with the electronic circuits 2 is bonded to a carrier 5 by means of the adhesive layer 4. The carrier 5 is made of glass, for example.In the fourth position of the method shown in FIG. 1D, the semiconductor substrate 1 is thinned. For this purpose, the semiconductor substrate 1 was ground or polished or etched, for example, from a side facing away from the carrier 5. For example, the semiconductor substrate 1 is thinned to a target thickness between 5 μm and 20 μm, inclusive. In FIG. 1D, the carrier 5 is the component stabilizing the electronic circuits 2.FIG. 1E shows a fifth position of the method. A photoresist layer 7 is applied to a side of the electronic circuits 2 facing away from the carrier 5. The photoresist layer 7 is patterned with trenches 70. The trenches 70 are formed in the region between the electronic circuits 2. Furthermore, a respective isolation trench 6 is formed between the electronic circuits 2. For the purpose of separating the semiconductor substrate 1, an anisotropic, dry chemical and fluorine-based etching process using the patterned photoresist layer 7 as an etching mask was used, for example. In order to penetrate the material connecting the wiring layer 202 to the separation trenches 6, for example, another etchant was used.It can be seen in FIG. 1E that the separating trenches 6 extend as far as the sacrificial layer 3, so that the sacrificial layer 3 is exposed in the region of the separating trenches 6.FIG. 1F shows a sixth position of the method in which the sacrificial layer 3 is removed in the region below the electronic circuits 2. The holding elements 40 are left over, via which the electronic circuits 2 are fastened to the carrier 5. The contact area between an electronic circuit 2 and the holding elements 40 arranged beneath it is, for example, at most 10% of the total area of the electronic circuit 2 facing the carrier 5.For the removal of the sacrificial layer 3, an anisotropic etching process was again used, for example. The etchant used for this purpose can have reached the sacrificial layer 3 via the separating trenches 6. The etchant has removed at least 99% of the sacrificial layer 3 in the area below the electronic circuits 2.In FIG. 1G, a seventh position of the method is shown. The electronic circuits 2 are detached from the carrier 5. Individual semiconductor chips 100 remain. These each comprise a section of the thinned semiconductor substrate 1 having an electronic circuit 2 integrated therein. The electronic circuits 2 each comprise a wiring layer 202 and a plurality of electronic components 201. A side of the thinned semiconductor substrate 1 facing away from the wiring layer 202 forms a bottom side 17 of the semiconductor chip 100.FIG. 2A shows a first position of a second exemplary embodiment of the method. As in FIG. 1A, a semiconductor substrate 1 is shown having a plurality of electronic circuits 2 formed on the top side 10. From the top side 10, insulation trenches 11 extend into the semiconductor substrate 1. The isolation trenches 11 are filled with an electrically insulating material, in particular the electrically insulating material 204 of the wiring layer 202.The isolation trenches 11 are formed on the one hand in the region between two transistors 201 of the electronic circuit 2 and electrically isolate the transistors 201 from one another. On the other hand, the isolation trenches 11 are formed in the region between two electronic circuits 2 each. In the present case, two insulation trenches 11 spaced apart from one another are respectively formed between two electronic circuits 2. A separating region 16 made of the material of the semiconductor substrate 1 is provided between the two insulation trenches 11.The isolation trenches 11 have, for example, a depth between 5 μm and 8 μm inclusive, a width between 2 μm and 3 μm inclusive, and a distance from the nearest transistors 201 or the nearest electronic circuits 2 between 5 μm and 8 μm inclusive.In the second position of the method illustrated in FIG. 2B, the semiconductor substrate 1 with the electronic circuits 2 is again applied to a carrier 5. Between the carrier 5 and the semiconductor substrate 1, a sacrificial layer 3 and an adhesive layer 4 are formed. Furthermore, the semiconductor substrate 1 is thinned again. In this case, the semiconductor substrate 1 was thinned until the isolation trenches 11 were exposed and the electrically insulating material in the isolation trenches 11 became visible on an underside 17 of the semiconductor substrate 1 facing away from the carrier 5. Optionally, a deco etching method can also be used which has a different etching rate for the electrically insulating material in the region of the isolation trenches 11 than for the semiconductor material of the semiconductor substrate 1. As a result, a visible height difference can be generated between the insulation trenches 11 and the semiconductor substrate 1 on the underside 17.FIG. 2C shows a third position of the method. A photoresist layer 7 patterned with trenches 70 was used as an etching mask to form isolation trenches 6 between the electronic circuits 2. The exposed isolation trenches 11 may serve as landmarks for positioning the trenches 70.In the present case, the separating trenches 6 are formed through the insulating trenches 11. This has prevented the semiconductor material of the thinned semiconductor substrate 1 from being etched through and risking damage to the semiconductor substrate 1. Alternatively, however, it would also be possible to form the separating trenches 6 between the insulating trenches 11 and through the separating regions 16. Then, only the semiconductor material of the semiconductor substrate 1 would be etched for forming the separating trenches 6. The isolation trenches 11 would constitute lateral passivations for protecting the electronic circuits 2 from the etchant.FIG. 3A shows a first position of a third exemplary embodiment of the method. A semiconductor substrate 1 having an electronic circuit 2 formed on the upper surface 10 is provided. The electronic circuit 2 comprises a first contact structure 200 in the region above the top side 10, that is to say within the wiring layer 202. This is electrically insulated from the semiconductor substrate 1 by an insulating layer, such as a field oxide layer, for example.FIG. 3B shows a second position of the method in which the semiconductor substrate 1 is mounted on a carrier 5, and a sacrificial layer 3 and an adhesive layer 4 are formed between the carrier 5 and the semiconductor substrate 1. The semiconductor substrate 1 is thinned to a target thickness.FIG. 3C shows a third position of the method. Contact holes 12 are made in the thinned semiconductor substrate 1. The contact holes 12 are located in particular in the region of the semiconductor substrate 1 above the first contact structures 200. The first contact structures 200 are exposed in the contact holes 12.FIG. 3D shows a fourth position of the method. An electrically conductive material 13 in the form of a metallic layer is introduced into the contact holes 12. The electrically conductive material 13 is in direct contact with the first contact structures 200. Furthermore, the electrically conductive material 13 extends from the first contact structures 200 as far as a bottom side 17 of the thinned semiconductor substrate 1 opposite the top side 10. A passivation layer 130 is formed between the electrically conductive material 13 and the semiconductor material of the semiconductor substrate 1.FIG. 3E shows a fifth position of the method. Again, with the aid of a photoresist layer 7 and trenches 70 in the photoresist layer 7, separating trenches 6 have been formed between the electronic circuits 2. The sacrificial layer 3 is removed below the electronic circuits 2, so that the electronic circuits 2 are held on the carrier 5 only via the holding elements 40.FIG. 4A shows a first position of a fourth exemplary embodiment of the method. Again, an electronic circuit 2 comprises first contact structures 200 over the top side 10 of the semiconductor substrate 1. contact regions 14 of the semiconductor substrate 1 are formed below the first contact structures 200. That is, the contact regions 14 consist of the semiconductor material of the semiconductor substrate 1. the contact regions 14 are laterally each completely surrounded by a delimiting trench 15. The delimiting trenches 15 extend from the top side 10 into the semiconductor substrate 1 and are filled with an electrically insulating material such as silicon oxide.FIG. 4B shows a second position of the method, in which the semiconductor substrate 1 is mounted again on a carrier 5 by means of an adhesive layer 4. Between the adhesive layer 4 and the electronic circuits 2, a sacrificial layer 3 is formed.FIG. 4C shows a third position of the method in which the semiconductor substrate 1 is thinned to such an extent that the delimiting trenches 15 and the contact regions 14 enclosed by them are exposed. An electrically conductive material 13 in the form of a metallic layer is again applied to the underside 17 of the thinned semiconductor substrate 1. The metallic layer is in electrically conductive contact with the contact regions 14. The contact regions 14 thus form vias through the semiconductor substrate 1, which vias are respectively insulated from the remaining semiconductor material of the semiconductor substrate 1 by the insulating delimiting trenches 5. The electronic circuits 2 can be contacted from the bottom side 17 via the electrically conductive material 13 and the contact regions 14. Except in the region of the contact regions 14, the electrically conductive material 13 is electrically insulated from the semiconductor material of the semiconductor substrate 1 by a passivation layer 130.FIG. 4D shows a fourth position of the method. Optoelectronic components 8, for example LED chips 8, are applied to the underside 17. The optoelectronic components 8 are each connected to an electronic circuit 2 via the electrically conductive material 13 and the contact region 14. The optoelectronic components 8 each comprise a semiconductor layer sequence 80 which emits radiation during operation.FIG. 4E shows a fifth position of the method. Separating trenches 6 are again formed in the region between the electronic circuits 2. The sacrificial layer 3 below the electronic circuit 2 can then be removed again with the aid of the separating trenches 6.FIGS. 5A and 5B show an exemplary embodiment of a semiconductor chip 100 in a perspective illustration. The semiconductor chip 100 can be produced by the method described in connection with FIGS. 4A to 4E. For this purpose, in particular the electronic circuit 2 with the optoelectronic component 8 applied thereon was removed from the carrier 5. The semiconductor chip 100 comprises a plurality of optoelectronic components 8 which are arranged on an electronic circuit 2 and are electrically conductively connected to the electronic circuit 2. As a result of the detachment of the electronic circuit 2 from the carrier 5, the second contact structures 203 of the electronic circuit 2 are exposed and can be used for the electrical contacting of the semiconductor chip 100.FIG. 6A shows a first position of a fifth exemplary embodiment of the method. The semiconductor substrate 1 with the electronic circuits 2 applied thereon corresponds to that of FIG. 1A.In the second position of the method illustrated in FIG. 6B, the semiconductor substrate 1 is applied to an auxiliary carrier 9 with the electronic circuits 2 first. The auxiliary carrier 9 is made of silicon, for example. The semiconductor substrate 1 is temporarily fastened to the auxiliary carrier 9 by means of a further adhesive layer 90, for example a thermal release layer or a UV release layer or a BCB layer with a laser release sacrificial layer, such as SiN x.FIG. 6C shows a third position of the method. The semiconductor substrate 1 is thinned to a target thickness. An oxide layer 31 is applied to the side of the thinned semiconductor substrate 1 facing away from the auxiliary carrier 9. On the oxide layer 31, a sacrificial layer 3 with holes 30 formed therein is formed again.FIG. 6D shows a fourth position of the method. The auxiliary carrier 9 with the electronic circuits 2 and the thinned semiconductor substrate 1 situated thereon is applied to a carrier 5. Between the electronic circuits 2 and the carrier 5, a sacrificial layer 3 and an adhesive layer 4 with holding elements 40 are again formed.FIG. 6E shows a fifth position of the method. The auxiliary carrier 9 is detached. The electronic circuits 6 are supported by the carrier 5.In the sixth position of the method shown in FIG. 6F, separating trenches 6 are again introduced between the electronic circuits 2 with the aid of a patterned photoresist layer 7.In the seventh position of the method shown in FIG. 6G, the sacrificial layer 3 below the electronic circuits 2 is removed.In the methods described in connection with FIGS. 1 to 4, the thinned semiconductor substrate 1 is always facing away from the carrier 5. With the method of FIG. 6, the thinned semiconductor substrate 1 faces the carrier 5. Depending on the method used, the electronic circuits 2 can thus be printed or mounted with the thinned semiconductor substrate 1 in front or the wiring layer 202 in front.FIG. 7 shows a position of a seventh exemplary embodiment. This position corresponds to that of FIG. 6D, for example. Here, a dielectric layer 32 is introduced between the sacrificial layer 3 and the adhesive layer 4. The dielectric layer 32 is in the present case simply contiguous and comprises, for example, Al 2 O 3 or SiO 2 or SiN x or consists of one of these materials. The dielectric layer 32 partially fills the holes 30 and separates the holding members 40 from the semiconductor substrate 1. This is gentler for the electronic circuits 2.Such a dielectric layer 32 may be used in any of the described embodiments.This patent application claims priority to German patent application 10 2017 125 276.2, the disclosure of which is hereby incorporated by reference.The invention is not limited to the exemplary embodiments by the description on the basis of the exemplary embodiments. Rather, the invention comprises any novel feature and any combination of features, which includes in particular any combination of features in the patent claims, even if this feature or this combination itself is not explicitly stated in the patent claims or exemplary embodiments.List of reference characters1 Semiconductor substrate 2 electronic circuit 3 sacrificial layer 4 adhesive layer 5 carrier 6 isolation trench 7 photoresist layer 8 optoelectronic component 9 auxiliary carrier 10 upper side 11 isolation trench 12 contact hole 13 electrically conductive material 14 contact region 15 boundary trench 16 isolation region 17 underside 30 hole in the sacrificial layer 3 31 oxide layer 32 dielectric layer 40 retaining elements 70 further adhesive layer 80 semiconductor layer sequence 100 semiconductor chip 130 passivation layer 200 first contact structure 201 transistor 202 wiring layer 203 second contact structure 204 electrically insulating material 205 conductor track

Claims

Method for producing a plurality of semiconductor chips (100), comprising the steps: A) providing a semiconductor substrate (1) with a plurality of integrated electronic circuits (2) on a top side (10) of the semiconductor substrate (1); B) applying a sacrificial layer (3) to one side of the semiconductor substrate (1); C) introducing holes (30) into the sacrificial layer (3) such that at least one hole (30) is produced above each electronic circuit (2); D) adhering the semiconductor substrate (1) with the sacrificial layer (3) first onto a carrier (5), wherein an adhesive layer (4) is used between the sacrificial layer (3) and the carrier (5) and wherein the adhesive layer (4) fills the holes (30) such that retaining elements (40) are produced from the adhesive layer (4) in the holes (30); E) thinning the semiconductor substrate (1); F) Introduction of separating trenches (6) between the electronic circuits (2), which extend from a side of the electronic circuits (2) facing away from the carrier (5) as far as the sacrificial layer (3) and penetrate the thinned semiconductor substrate (1); G) Removal of the sacrificial layer (3) in the region between the electronic circuits (2) and the carrier (5), so that the electronic circuits (2) are held on the carrier (5) via the holding elements (40).Method according to claim 1, wherein after step G) a contact area between the holding elements (40) and an electronic circuit (2) is at least 0.1% and at most 10% of the total surface of the electronic circuit (2) facing the carrier (5).Method according to Claim 1 or 2, wherein the following intermediate steps are carried out in order to carry out step F): F1) applying a photoresist layer (7) to that side of the electronic circuits (2) which faces away from the carrier (5); F2) structuring the photoresist layer (7) with trenches (70), wherein the trenches (70) are formed where the separating trenches (6) are intended to be produced later; F3) applying an etching method for producing the separating trenches (6) in the region of the trenches (70).Method according to one of the preceding claims, wherein the carrier (5) is a transparent carrier.Method according to one of the preceding claims, wherein an anisotropic, fluorine-based etching process is carried out in step F) in order to produce the separating trenches (6).Method according to one of the preceding claims, wherein - a dry chemical etching method is used in step G) to remove the sacrificial layer (3), - the etchant used for this purpose reaches the sacrificial layer (3) via the separating trenches (6).Method according to one of the preceding claims, wherein - isolation trenches (11) extend between two electronic circuits (2) and / or in the region of the electronic circuits (2) from the top side (10) into the semiconductor substrate (1), - the isolation trenches (11) are filled with an electrically insulating material, - in step E) the semiconductor substrate (1) is thinned until the isolation trenches (11) are exposed.Method according to Claim 7, wherein - an insulation trench (11) is formed between two electronic circuits (2), - in step F) the separation trenches (6) are formed through the exposed insulation trenches (11).Method according to Claim 7, wherein - two isolation trenches (11) are formed between two electronic circuits (2), said isolation trenches laterally delimiting a separation region (16) of the semiconductor substrate (1), - in step G), the isolation trenches (6) are formed through the separation region (16).Method according to one of the preceding claims, wherein - each electronic circuit (2) has a first contact structure (200) arranged above the top side (10) for electrically contacting the electrical circuit (2), - the method further comprises the steps following the step E): E1) introducing contact holes (12) into the thinned semiconductor substrate (1) such that the first contact structures (200) are exposed, E2) introducing an electrically conductive material (13) into the contact holes (12).Method according to one of Claims 1 to 9, wherein - each electronic circuit (2) has a first contact structure (200) arranged above the top side (10) for electrically contacting the electrical circuit (2), - in the region below the first contact structures (200), the semiconductor substrate (1) in each case comprises a contact region (14) which is laterally surrounded by an electrically insulating delimiting trench (15), - in step E) the semiconductor substrate (1) is thinned until the delimiting trenches (15) and the contact regions (14) are exposed, - the method further comprises the step following step after step E): E3) applying an electrically conductive material (13) to the thinned semiconductor substrate (1) in the contact regions (14).Method according to either of Claims 10 and 11, further comprising a step following step E): E4) applying optoelectronic components (8) to an underside (17) of the thinned semiconductor substrate (1) facing away from the electronic circuits (2), wherein the optoelectronic components (8) are electrically conductively connected to the electronic circuits (2) via the electrically conductive material (13).Method according to one of the preceding claims, wherein - after step A) and before step B) the semiconductor substrate (1) with the electronic circuits (2) is firstly applied to an auxiliary carrier (9) and step E) is subsequently carried out, - after step D) the auxiliary carrier (9) is removed again.Method according to one of the preceding claims, wherein each electronic circuit (2) comprises: - a region of the semiconductor substrate (1) and an electronic component (201) formed with this region of the semiconductor substrate (1), - a wiring layer (202) on the semiconductor substrate (1) for contacting the component (201), - a second contact structure (203) on a side of the wiring layer facing away from the semiconductor substrate (1), wherein the electronic circuit (2) can be electrically contacted via the second contact structure (203).Method according to Claim 14, wherein - the wiring layers (202) of the electronic circuits (2) are contiguous in step A) and form a contiguous wiring layer, - the contiguous wiring layer is formed metallically in the region of the separating trenches (6) to be formed, - in step F) the separating trenches (6) are formed through the contiguous wiring layer.Method according to one of the preceding claims, wherein - after step C) a dielectric layer is introduced between the sacrificial layer (3) and the adhesive layer (4), - the dielectric layer partially fills the holes (30) and separates the holding elements (40) from the semiconductor substrate (1).Method according to one of the preceding claims, further comprising the step: H) detaching the electronic circuits (2) from the carrier (5) so that individual semiconductor chips (100) separated from one another are produced.Semiconductor chip (100) comprising: - a semiconductor substrate (1) with an integrated electronic circuit (2) on a top side (10) of the semiconductor substrate (1), wherein - the electronic circuit (2) comprises a wiring layer (202) on the top side (10) of the semiconductor substrate (1) and a first contact structure (200) in the wiring layer (202), - the first contact structure (200) is electrically conductively connected to a contact region (14) of the semiconductor substrate (1), - the contact region (14) extends completely from the top side (10) through the semiconductor substrate (1) as far as a bottom side (17) of the semiconductor substrate (1) opposite the top side (10), - the contact region (14) is electrically conductively connected to an electrically conductive material (13) on the bottom side (17), - the contact region (14) is laterally completely surrounded by an electrically insulating delimiting trench (15), which extends from the top side (10) to the bottom side (17) of the semiconductor substrate (1), and - the semiconductor chip (100) further comprises an optoelectronic component (8) on the bottom side (17) of the semiconductor substrate (1), wherein the optoelectronic component (8) is electrically conductively connected to the electronic circuit (2) via the electrically conductive material (13) and the contact region (14).

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