Semiconductor unit and method for manufacturing a semiconductor unit

Abstract

Semiconductor unit comprising the following: - a substrate (1) formed by integrating an insulating element and a cooling fin (1a); - a plate interconnecting element (5); and - a semiconductor element (3) whose back side is bonded with a first solder to an interlink structure formed on the insulating elements of the substrate (1), and whose front side is bonded with a second solder to the plate interlink element (5) such that the plate interlink element (5) corresponds to the semiconductor element (3), - wherein the first lot mainly contains Sn, 0.3 wt.% to 3 wt.% Ag and 0.5 wt.% to 1 wt.% Cu and - wherein the second solder mainly contains Sn, 0.3 wt.% to 2 wt.% Ag and 0.5 wt.% to 1 wt.% Cu and a metal layer of Al is formed on the front side of the semiconductor element (3).

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device having a structure such that a board interconnection member is soldered to a chip, and relates to a method for manufacturing such a semiconductor device. STATE OF THE ART

[0002] In power semiconductor devices, thermal resistance is reduced by soldering a semiconductor chip directly to an insulating substrate integrated with a cooling fin. Furthermore, the dimensions of a semiconductor module are reduced by using a structure such that interconnections on the chip are created by soldering a lead instead of wire bonding.

[0003] Patent Document 1 discloses a module structure that enables a greater reduction in thermal resistance by mounting the chip on an insulating substrate integrated with a cooling fin, rather than mounting it on a substrate in contact with a fin via grease, thereby enabling a reduction in size. Patent Documents 1 and 2 disclose module structures that enable a greater increase in current density by forming interconnections on the chip using soldering of a board interconnector, compared to a case where they are formed by wire bonding, thereby enabling a reduction in size. Furthermore, Patent Documents 2 and 3 disclose a module in which an Sn-Ag-Cu-based solder is used for bonding the chip to the substrate and leads to the chip.

[0004] Patent Document 4 describes a semiconductor module including a heat sink having a mounting surface and a heat dissipation surface opposite to the mounting surface, a fin provided in a central region of the heat dissipation surface, an insulating member provided on the mounting surface of the heat sink, an electrically conductive member provided on the insulating member, a semiconductor chip bonded to the electrically conductive member by means of an electrically conductive bonding material such as solder, and a metal frame bonded to the semiconductor chip.

[0005] Patent Document 5 relates to a semiconductor module including a metal block, a semiconductor device mounted on a surface of the metal block via a solder layer in a semiconductor device mounting area, and a molded portion formed by molding a resin on the metal block and the semiconductor device.

[0006] Patent Document 6 discloses a lead-free solder alloy consisting essentially of 0.1-1.5% Ag, 2.5-5.0% Bi, 0.5-1.0% Cu, optionally 0.015-0.035% Ni and / or 0.0005-0.01% Ge and / or Ga, and Sn as the balance.

[0007] Patent Document 7 describes a semiconductor device including a semiconductor substrate, a support member, a tin-based solder layer, a first metal layer, and a first alloy layer. Alloys of tin, silver, and copper, among others, are mentioned for the solder layer. PRIOR ART DOCUMENTSPatent documents Patent Document 1: JP 6 065 973 B2 (paragraphs

[0012] to

[0015] and Fig. 1) Patent Document 2: JP 2007- 157 863 A (paragraphs

[0012] to

[0013] and Fig. 1) Patent Document 3: JP 2005- 183 568 A (para.

[0008] and Fig. 1) Patent document 4: DE 11 2013 007 047 T5 Patent document 5: DE 10 2012 100 137 A1 Patent document 6: US 2011 / 0 204 121 A1 Patent document 7: DE 10 2005 042 780 A1 BRIEF DESCRIPTION OF THE INVENTION Problem to be solved by the invention

[0008] However, when the structures disclosed in Patent Documents 1 to 3 are employed, shrinkage voids sometimes occur in the solder between the chip and the insulating substrate integrated with a cooling fin, since the cooling rate when the chip is soldered to the insulating substrate is reduced more than in a case where the cooling fin is a flat plate due to a high heat capacity due to the cooling fin and a reduced contact area with a cooling plate due to the cooling fin, thus posing a problem of deterioration of heat dissipation.

[0009] The present application aims to solve the problem described above and to provide a semiconductor device whose dimensions can be reduced without impairing heat dissipation and a method for manufacturing such a semiconductor device. Means of solving the problem

[0010] According to one aspect disclosed herein, a semiconductor device comprises: a substrate formed by integrating an insulating member and a cooling fin; a plate interconnection member; and a semiconductor element, the back surface of which is bonded to an interconnection structure formed on the insulating members of the substrate with a first solder, and the front surface of which is bonded to the plate interconnection member with a second solder such that the plate interconnection member corresponds to the semiconductor element, wherein the first solder predominantly contains Sn, 0.3 wt% to 3 wt% Ag, and 0.5 wt% to 1 wt% Cu, and wherein the second solder predominantly contains Sn, 0.3 wt% to 2 wt% Ag, and 0.5 wt% to 1 wt% Cu, and a metal layer of Al is formed on the front surface of the semiconductor element.

[0011] According to another aspect disclosed herein, a semiconductor device comprises: a substrate formed by integrating an insulating member and a cooling fin, a plate inter-connection member; and a semiconductor element, the back surface of which is bonded to an interconnection structure formed on the insulating member of the substrate 1 with a first solder, and the front surface of which is bonded to the plate inter-connection member with a second solder such that the plate inter-connection member corresponds to the semiconductor element, wherein the first solder predominantly contains Sn, 0.3 wt% to 2 wt% Ag, and 0.5 wt% to 1 wt%% Cu, and the substrate is provided with a metal layer formed on the interconnection structure on the insulating member, which is bonded to the back surface of the semiconductor element with the first solder via the metal layer, and the semiconductor element 3 is provided with a metal layer formed on the back surface, which is bonded to the insulating member with the first solder via the metal layer, and wherein at least one of the metal layer on the back surface of the semiconductor element and the metal layer on the interconnection structure on the insulating member is formed of Ag or Cu.

[0012] According to another aspect disclosed herein, a method for manufacturing a semiconductor device comprises bonding the back surface of a semiconductor element with a first solder by a first reflow process to an interconnection structure on an insulating member of a substrate formed by integrating the insulating member and a cooling fin; and bonding a plate inter-connection member to a front surface of the semiconductor element with a second solder by a second reflow process such that the plate inter-connection member corresponds to the semiconductor element 3, wherein the second solder predominantly contains Sn, 0.3 wt% to 3 wt% Ag, and 0.5 wt% to 1 wt% Cu, and wherein the second solder predominantly contains Sn, 0.3 wt% to 2 wt% Ag, and 0.5 wt% to 1 wt% Cu, and forming a metal layer of Al over the front surface of the semiconductor element.

[0013] According to another aspect disclosed herein, a method for manufacturing a semiconductor device comprises: bonding a metal layer formed on back surfaces of a semiconductor element with a first solder by a first reflow process to a metal layer formed on an interconnection structure on an insulating member of a substrate formed by integrating the insulating member and a cooling fin;and bonding a metal layer formed over the front side of the semiconductor element with a second solder to a board interconnection element by a second reflow process such that the board interconnection element corresponds to the semiconductor element, wherein at least one of the metal layer on the back side of a semiconductor element and the metal layer formed on the interconnection structure on the insulating member of the substrate is formed of Ag, and a solder predominantly containing Sn and 0.5 wt% to 1 wt% Cu is used as the first solder, such that the first solder becomes a solder predominantly containing Sn, 0.3 wt% to 3 wt% Ag, and 0.5 wt% to 1 wt% Cu during the first reflow process in the step of bonding with the first solder;

[0014] According to yet another aspect disclosed herein, a method for manufacturing a semiconductor device comprises: bonding a metal layer formed on the back surface of a semiconductor element with a first solder by a first reflow process to a metal layer formed on an interconnection structure on an insulating member of a substrate formed by integrating an insulating member and a cooling fin;and bonding a plate interconnection element with a second solder by a second reflow process to a metal layer formed over the front surface of the semiconductor element such that the plate interconnection element corresponds to the semiconductor element, wherein at least one of the metal layer on the back surface of a semiconductor element and the metal layer formed on the interconnection structure on the insulating member of the substrate is formed of Cu, and a solder predominantly containing Sn and 0.3 wt% to 3 wt% Ag is used as the first solder, such that the first solder becomes a solder predominantly containing Sn and 0.3 wt% to 3 wt% Ag and 0.5 wt% to 1 wt% Cu during the first reflow process in the step of bonding with the first solder;

[0015] According to another aspect disclosed herein, a semiconductor device comprises: a substrate formed integrally with an insulating member and a cooling fin; a plate inter-connection member; and a semiconductor element, the back surface of which is bonded to an interconnection structure formed on the insulating member of the substrate with a first solder, and the front surface of which is bonded to the plate inter-connection member with a second solder such that the plate inter-connection member corresponds to the semiconductor element, wherein the first solder predominantly contains Sn, 0.3 wt% to 2 wt% Ag, and 0.5 wt% to 1 wt% Cu, and a metal layer of Al is formed on the back surface of the semiconductor element. Advantageous effect of the invention

[0016] According to the present application, occurrence of shrinkage cavities can be prevented by using a solder containing predominantly Sn and 0.3 wt% to 3 wt% Ag and 0.5 wt% to 1 wt% Cu for bonding the semiconductor element, thus enabling a reduction in the dimensions of a semiconductor module without impairing heat dissipation. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The figures show: Fig. 1 is a schematic plan view showing a configuration of the main portion of a semiconductor unit according to Embodiment 1; Fig. 2 is a schematic cross-sectional view showing the configuration of the main portion of the semiconductor unit of Embodiment 1; Fig. 3 is a schematic cross-sectional view showing a chip configuration of the semiconductor unit of Embodiment 1; Fig. 4 is a schematic plan view illustrating a shape of a shrinkage void in a solder used in a conventional semiconductor device; Fig. 5 is a diagram for explaining basic composition of a solder used for a semiconductor device according to Embodiment 1; Fig. 6 is a flowchart showing a causal relationship in a case where a solder having a different composition from that of a solder used for the semiconductor device according to Embodiment 1 is used; Fig. 7 is a flowchart showing a causal relationship in a case where a solder having a different composition from that of the solder used for the semiconductor device according to Embodiment 1 is used; Fig. 8 is a flowchart showing a causal relationship in a case where a solder having a different composition from that of the solder used for the semiconductor device according to Embodiment 1 is used; Fig. 9 is a flowchart showing a causal relationship in a case where a solder having a different composition from that of the solder used for the semiconductor device according to Embodiment 1 is used; Fig. 10 is a graph showing a relationship between a Cu concentration and a thickness of a solder alloy layer for explaining a situation in a case where a solder having a different composition from that of the solder used for the semiconductor device according to Embodiment 1 is used; Fig. 11 is a binary phase diagram of an Sn-Cu solder for explaining the composition of the solder used for the semiconductor device according to Embodiment 1; Fig. 12 is a graph showing a relationship between temperature and Vickers hardness for explaining the composition of the solder used for the semiconductor device according to Embodiment 1; Fig. 13 are ternary phase diagrams of a Sn-Ag-Cu solder for explaining a composition of the solder used for the semiconductor device according to Embodiment 1; Fig. 14 is a graph for explaining the state of a shrinkage void depending on an Ag concentration in the solder used for the semiconductor device according to Embodiment 1; Fig. 15 is a graph for explaining a condition for the main stress of the metal layer depending on an Ag concentration in the solder used for the semiconductor device according to Embodiment 1; Fig. 16A to 16C are schematic cross-sectional views illustrating steps for manufacturing the semiconductor device according to Embodiment 1; Fig. 17A and Fig. 17B is a schematic plan view and a cross-sectional view showing another configuration of the main portion of the semiconductor unit according to Embodiment 1; Fig. 18A and Fig. 18B is a schematic plan view and a cross-sectional view showing still another configuration of the main portion of the semiconductor unit according to Embodiment 1; Fig. 19 is a schematic plan view showing a configuration of a main portion of a semiconductor unit according to Embodiment 3; Fig. 20 is a schematic cross-sectional view showing a configuration of the main portion of the semiconductor unit according to Embodiment 3. EMBODIMENTS FOR REALIZING THE INVENTION Embodiment 1

[0018] With reference to the drawings, a configuration of a semiconductor device according to Embodiment 1 will be described. Note that the same or similar components are assigned the same reference numerals in each drawing. The illustrated dimensions of each corresponding component and the scale of each corresponding configuration in the various figures are independent of each other; for example, in the various cross-sections showing a portion of a configuration that is changed or not changed, the illustrated dimensions of the same components and the scale of the same configurations may differ from each other.

[0019] Furthermore, although the semiconductor device includes a plurality of components in an actual configuration, only components necessary for description are illustrated for the sake of simplicity, and other components (such as an external terminal) are omitted from the illustration. Furthermore, although the same components are connected in parallel in an actual configuration, or the switching elements are connected in series with rectifying elements such as diodes, these are also omitted from the illustration for the sake of simplicity.

[0020] Fig. 1 is a top plan view of the semiconductor device 101 according to Embodiment 1. Fig. 2 is a cross-sectional view in the direction of the arrows on a line AA according to Fig. 1. As in the Fig. 1 and Fig. 2, the semiconductor unit 101 includes an insulating substrate 1 integrated with a cooling fin 1a, chips 3, board interconnectors 5 for electrically connecting the chips 3 to external wires 8, and a resin sealing portion 9 encapsulating the connecting portions of the chips 3 in a case 7.

[0021] The insulating substrate 1 includes a ceramic base plate 1b made of AlN (dimensions: 100 mm long × 100 mm wide and 0.6 mm thick) as an insulating member and a cooling fin 1a made of Al formed together with the ceramic base plate 1b made of AlN on the back side thereof, and is provided with an electrode structure 1c made of Al as an interconnection structure on the front side thereof. The ceramic base plate 1b and the cooling fin 1a are integrally formed by molding. The front side of the electrode structure 1c is coated with a metal layer 1d made of Ni with a thickness of 5 µm to ensure good bonding with a solder 4 on the chip bottom side as a first solder.

[0022] Fig. Figure 3 shows a cross-sectional view of chip 3. Chip 3 has a metal layer 3c made of Al on the front surface of a semiconductor element 3a, and the metal layer 3c made of Al is coated with a metal layer 3d made of Ni to ensure good bonding to the board interconnection element 5 with a solder 6 on the top surface of the chip as a second solder. The back surface of the semiconductor element is also coated with a metal electrode layer 3b made of Ni to ensure good bonding to the insulating substrate 1 with the solder 4 on the bottom surface of the chip.

[0023] A Si insulated gate bipolar transistor (IGBT; dimensions: 15 mm long x 15 mm wide and 100 µm thick) is used as the semiconductor element 3c. Al wire spacers 2 (100 µm diameter) are arranged at the four corners on the electrode structure 1c of the substrate 1 to position the chip 3. The plurality of chips 3 are attached to the spacers by substrate bonding with solder 4 on the chip bottom surface (Sn, 0.3 wt% to 2 wt% Ag, and 0.5 wt% to 1 wt% Cu).

[0024] The plate interconnection member 5 is formed of a Cu plate electrode (thickness 1 mm) and bonded to the metal layer 3d as the front-side electrode of each chip 3 with the solder 6 on the chip top side (Sn, 0.3 wt% to 2 wt% Ag, and 0.5 wt% to 1 wt% Cu). The end of the plate interconnection member 5 not connected to the chip 3 serves as an external electrode. Although the plate interconnection member 5 is used for the interconnection on the chip 3 from the viewpoint of reducing the size of the module according to Embodiment 1, a wire bond may also be used as the interconnection on the chip 3.

[0025] The housing 7 is made of polyphenylene sulfide (PPS) resin and is formed in a box shape. The bottom of the housing 7 is bonded to the insulating substrate 1, such as with an adhesive. The housing 7 is provided with a Cu terminal connected to an external terminal, and the chip 3 is electrically connected to it via Al wires 8 (diameter 200 µm). The housing 7 is potted with an encapsulating resin (an epoxy resin).

[0026] The resin sealing portion 9, which is formed by molding the epoxy resin in the package 7, seals and insulates the front side of the insulating substrate 1, the chips 3, the interconnection elements 5, the wires 8, and the solder 4 on the chip bottom side and the solder 6 on the chip top side.

[0027] Manufacturing the insulating substrate 1 by integrating the ceramic base plate 1b and the cooling fin 1a enables a greater reduction in thermal resistance than in a case where the fin is brought into contact with the substrate via a grease, thus reducing the dimensions of the module. Compared with a case where a ceramic base plate is soldered to a cooling fin, as in Fig. As shown in Fig. 3 of JP 2007-157 863 A, by molding together with an insulating material or integrating the insulating substrate and the cooling fin in advance by brazing or the like, the thermal resistance can be further reduced and thereby the module dimension can be reduced.

[0028] A soldering process can sometimes cause voids and shrinkage cavities in the solder layer. Since thermal resistance increases significantly when these occur, the occurrence of such voids and shrinkage cavities must be considered for a large module. Furthermore, by forming the interconnection on the chip 3 by soldering the board interconnect element 5, the current density can be increased, and the dimensions of the module can be reduced compared to a case where wire bonding is used.

[0029] When the insulating substrate formed by integrating the ceramic base plate 1b and the cooling fin 1a is used, good thermal conductivity is exhibited; however, the cooling rate decreases compared with a case where an insulating substrate with a flat back surface without fins is used, because the cooling fin reduces the contact area with a cooling plate used for cooling after a reflow process for substrate bonding of the chip 3. A slow cooling rate tends to cause shrinkage cavities due to volume shrinkage during solder solidification. Although the cooling rate can be increased by combining the use of contact cooling and blowing nitrogen or the like onto the fin, such cooling cannot achieve a cooling rate as high as that achieved by bringing the entire bottom surface of a module without fins into contact with a cooling plate.

[0030] Fig. 4 shows a shape of a shrinkage void that has developed in the solder 4 at the chip bottom side. It is preferable that a shrinkage void 11 does not occur in the solder 4 at the chip bottom side, since if it does occur, it raises concerns about a reduction in heat dissipation.

[0031] As a result, the inventors found that the occurrence of shrinkage voids can be prevented for the configuration of Embodiment 1 by using the solder 4 on the chip bottom side with a composition containing Sn, 0.3 wt% to 2 wt% Ag, and 0.5 wt% to 1 wt% Cu. Furthermore, the presence of the wire spacers 2 in the solder 4 on the chip bottom side ensures a minimum solder thickness and prevents deterioration of heat dissipation through a thick portion due to the occurrence of a thickness variation in the solder.

[0032] In summary, since shrinkage voids tend to occur in a thick portion of the solder, by using the solder 4 on the chip bottom surface with a composition containing Sn, 0.3 wt% to 2 wt% Ag, 0.5 wt% to 1 wt% Cu and disposing the spacers, the solder thickness can be controlled, and the formation of a thick portion due to the occurrence of thickness variation can be prevented, so that occurrence of shrinkage voids can be more strongly suppressed.

[0033] Fig. Fig. 5 shows guidelines for determining the composition of the solder 4 on the chip bottom side used for the semiconductor device 101 according to Embodiment 1, with Sn, 0.3 wt% to 2 wt% Ag and 0.5 wt% to 1 wt% Cu. Fig. 6 to 9 are flowcharts showing causal relationships in cases where a solder having a different composition from that of the solder 4 used for the semiconductor device according to Embodiment 1 is used.

[0034] In a case where the Cu concentration with respect to the solder 4 with the composition Sn, 0.3 wt% to 2 wt% Ag, 0.5 wt% to 1 wt% Cu (range S in Fig. 5) is less than 0.5 wt.% (area A in Fig. 5), there are concerns that the Ni metal layers 1d and 3b, which are formed to ensure good bonding of the chip 3 to the electrode structure 1c of the insulating substrate 1, may diffuse (state S61) or be lost (state S62) during the melting of the solder 4 at the chip bottom in the temperature cycle, as shown in the flowchart according to Fig. 6 shown.

[0035] Fig. Figure 10 shows the dependence of the thickness of a resulting solder alloy layer on the Cu concentration. The thickness of the alloy layer increases with decreasing Cu concentration when the Cu concentration is less than 0.5 wt.%. This indicates that Ni diffuses into the alloy layer and is lost. The loss of Ni can sometimes cause separation (condition S63). Therefore, the Cu concentration is preferably 0.5 wt.% or higher, and more preferably 0.6 wt.% or higher, considering composition variation during solder preparation.

[0036] The semiconductor device 101 requires a plurality of board interconnectors 5 in a case where a plurality of chips 3 are mounted. Using the plurality of board interconnectors integrally bonded in advance with the resin bonding members 5a allows for compaction of the positioning pins required for the respective board interconnectors, thus reducing the size of the semiconductor device. The board interconnectors and the bonding members 5a are bonded by, for example, insert molding.

[0037] In a case where the Cu concentration is higher than 1 wt.% (area B in Fig. 5), however, the melting point of solder 4 on the chip bottom and solder 6 on the chip top exceeds 280 °C (state S71), as shown in the binary phase diagram for the Sn-Cu solder (see Fig. 11), and since this temperature is higher than the melting point of the PPS connecting element 5a, there are concerns about melting of the resin connecting elements 5a connecting the board intermediate connecting elements during soldering, as shown in the flow chart according to Fig. 7 shown.

[0038] Since the temperature is inevitably increased during a reflow process (condition S72), heating and cooling take a long time, meaning the process time in the reflow steps becomes long, thus reducing productivity (deterioration of cycle time; condition S73). Consequently, the Cu concentration is preferably 1 wt% or less.

[0039] If the heat capacity of the semiconductor unit 101 is high, the Cu concentration is preferably 0.8 wt% or less, since the reflow process is necessarily performed after the solder has fully reached its melting temperature and at a temperature at which the resin connecting element 5a does not melt. Incidentally, it is known that the Vickers hardness of the Ni plating, which is coated on the chip and serves for soldering, increases by annealing at 300°C or higher, as shown in Fig. 12 shown.

[0040] The increase in hardness is due to crystallization. However, the increase in hardness causes the Ni plating to become brittle and prone to cracking, raising concerns about reduced reliability. Therefore, even if soldering can be completed without the resin fasteners, it is not desirable for the solder melting temperature to increase.

[0041] When the Ag concentration is 0.3 wt% to 3 wt%, the Fig. 13, it is considered that Sn crystallizes first, followed by Cu6Sn5 and Ag3Sn in this order, and since solidification proceeds gradually in a low-flow state, it is considered that shrinkage voids hardly occur. When the Ag concentration is less than 0.3 wt% (area C in Fig. 5), Cu6Sn5 crystallizes, and when the Ag concentration is higher than 3 wt.%, Ag3Sn and Sn crystallize simultaneously.

[0042] As a result, it is considered that the duration of the low-flow condition (condition S81) is short and there is a tendency for shrinkage cavities to occur (condition S82), as shown in Fig. 8. In the inventors' experimental results regarding actual substrate bonding of the chip 3 to the insulating substrate 1 at a temperature profile of a chip cooling rate of 0.5 K / sec, many shrinkage voids occurred when the Ag concentration was less than 0.3 wt.%, and the occurrence of shrinkage voids could be prevented when the Ag concentration was in a range of 0.3 wt.% to 3 wt.%, as shown in Fig. 14 shown.

[0043] Since shrinkage voids often occur when the Ag concentration is less than 0.3 wt.%, the Ag concentration is preferably 0.3 wt.% or higher. For a power semiconductor device capable of outputting high current, such as a current higher than 600 A, the cooling rate is expected to further decrease because the module has a large size to ensure insulation clearance, and its heat capacity increases with increasing size. In this case, it is also preferable to contain 0.5 wt.% or more of Ag.

[0044] The metal layer 3c of Al is arranged between the semiconductor element 3a of Si and the metal layer 3d of Ni to bond the chip 3 with the solder 6 on the chip top side. Fig. Figure 15 shows a calculation result for the principal stress occurring in the Al metal layer 3c when varying the Ag concentration contained in the solder 4 on the bottom surface of the chip and the solder 6 on the top surface of the chip. The calculation was performed assuming that the Al metal layer 3c and the Ni metal layers 3b and 3d each had a thickness of 5 µm, and the 0.2% yield strength of the solder was 20 MPa to 35 MPa, calculated from an actual measurement value.

[0045] Since the solder is at an Ag concentration of more than 2 wt.% (area D in Fig. 5) is hardened (condition S91) and the 0.2% yield strength of solder 4 on the chip bottom and solder 6 on the chip top exceeds that of Al, the stress increases rapidly, as indicated by point P in Fig. 15. The occurrence of thermal stress (state S92) causes cracks to form in the Al metal layer 3c in front of the solder materials. This raises concerns about chip 3 breaking (state S93).

[0046] Since the Ag concentration is higher than 2 wt.%, the use of Al for the metal layer 3c on the front side of the chip 3 may cause cracks in the Al metal layer 3c, the Ag concentration is therefore preferably 2 wt.% or lower. Considering a variation in the 0.2% yield strength of the solder materials, the Ag concentration is preferably 1.2 wt.% or lower, thereby stably providing a semiconductor device with even more excellent reliability.

[0047] It should be noted that if Al is not used for the metal layer 4c on the front side of the chip 3 or a material having a 0.2% yield strength lower than that of the solder is not used, the Ag concentration can be kept in a range of 3 wt% or less, at which the occurrence of shrinkage voids can be prevented.

[0048] Using solder 4 on the chip bottom and solder 6 on the chip top, both of which have the same composition containing Sn, 0.3 wt% to 2 wt% Ag, and 0.5 wt% to 1 wt% Cu, prevents not only shrinkage voids but also separation due to loss of Ni during thermal cycling, as well as preventing stress acting on the Al metal layer 3c, thus providing a module with excellent reliability and reduced dimensions due to low thermal resistance. Furthermore, using solder 4 on the chip bottom and solder 6 on the chip top, which have the same composition, makes manufacturing control easy.

[0049] Furthermore, since both solder materials have the same melting point, the components on and below the chip can be bonded using the same soldering fixture with the same temperature profile.

[0050] Next, a method for manufacturing the semiconductor device 101 according to Embodiment 1 will be described. Fig. 16A, Fig. 16B and Fig. 16C are cross-sectional views for explaining a manufacturing process for the semiconductor unit 101.

[0051] First, the insulating substrate 1 integrated with the cooling fin 1a is prepared, and then the spacers 2 made of an Al wire are arranged at the four corners of a surface for disposing the chip 3 on the electrode structure 1c of the insulating substrate 1, as shown in Fig. 16A. Then, the solder 4 on the chip bottom side (Sn, 0.3 wt% to 2 wt% Ag, and 0.5 wt% to 1 wt% Cu) and the chip 3 are arranged, and bonding is performed by means of a reflow process.

[0052] Subsequently, the solder 6 on the chip top side (Sn, 0.3 wt% to 2 wt% Ag and 0.5 wt% to 1 wt% Cu) and the plate interconnection element 5 are arranged on the chip 3, as shown in Fig. 16B, and then bonded by a reflow process. In a case where a plurality of chips 3 are mounted, a plurality of board interconnecting members 5 integrally bonded with the resin connecting members 5a in advance may be used.

[0053] Next, the package 7 is attached with an adhesive so as to surround the chip 3 attached to the insulating substrate 1 by substrate bonding, and thereafter, the wires 8 are connected as signal lines by wire bonding between the chip 3 and the externally connected terminal (not shown) on the package 7, as shown in Fig. 16C. Furthermore, the bonding of the housing 7 is completed by heating during the reflow process.

[0054] The bonding of the housing 7 to the insulating substrate 1 can be completed by the reflow process for the solder 4 or the solder 6 simultaneously, or can be completed in a further step that is different from the reflow step for the solder. By using the solder 4 on the chip bottom side and the solder 6 on the chip top side, both containing Sn, 0.3 wt% to 3 wt% Ag, and 0.5 wt% to 1 wt% Cu, it is possible to perform the solder bonding at a temperature at which the housing 7 does not melt, and it is possible to perform the soldering and bonding of the housing 7 at the same time.

[0055] The use of such a solder is preferable because the bonding process can be simplified. Furthermore, the use of such a solder is also preferable in a case where the plurality of inter-board connecting members 5 are connected to each other in advance, because the solder can be melted at a temperature lower than the upper temperature limit for the resin connecting members 5a.

[0056] Finally, the sealing resin is poured into the housing to form the resin sealing region 9 by subsequent curing. This completes the semiconductor unit 101, as shown in, for example, Fig. 2 shown.

[0057] Although AlN is used for the ceramic base plate of the insulating substrate 1, Al2O3, Si3N4 ceramic, or the like can also be used as long as they ensure insulation, and their dimensions and thickness are not limited to those described above. Although an Al wire is used as the wire spacer 2, a Cu wire or other wire can also be used. Furthermore, while the spacers 2 have a diameter of 100 µm, the diameter can be less than the thickness of the solder.

[0058] Furthermore, a solder containing Ni balls can be used because the minimum thickness of the solder can be ensured. Although the insulating substrate 1 is formed by pre-integrating the ceramic base plate 1b and the cooling fin 1a by molding, the ceramic base plate and the cooling fin can also be pre-integrated by brazing or soldering. Integration by molding or brazing is preferable because it eliminates the use of solder with low thermal conductivity, and thermal resistance can be reduced.

[0059] Furthermore, the material for the insulating member is not limited to ceramic, but can also be any other material as long as it ensures insulation. For example, a laminated resin sheet can be used. Therefore, the insulating substrate 1 can also be formed by integrating the cooling fin 1a and an insulating member, such as an insulating sheet or an insulating layer.

[0060] Although the metal layers 3b and 3d are arranged with a thickness of 5 µm on the surfaces to be soldered of the chip 3 to ensure solderability, metal layers made of Au or Ti, for example, can also be used, and their thickness is not limited to these as long as soldering can be performed. Furthermore, the metal layers 3b and 3d can each be formed in one region or two or more regions on the chip 3.

[0061] Although an IGBT is used as the semiconductor element 3a, the element may also be an integrated circuit (IC), a thyristor, or a metal-oxide-semiconductor field-effect transistor (MOSFET). Furthermore, the element may be composed of a rectifying element such as a Schottky barrier diode (SBD) or a junction barrier Schottky diode (SBJ), and it may also be applied to a semiconductor package other than a semiconductor unit. Furthermore, the dimensions and thickness of the semiconductor element are not limited to those of the aforementioned IGBT. As shown in the Fig. 17A and Fig. 17B, ​​the semiconductor device may comprise a chip and accordingly comprise an interconnect element.

[0062] Although the semiconductor element 3a is made of Si, a so-called wide-bandgap semiconductor material, such as a silicon carbide (SiC), gallium nitride (GaN), or diamond-based material, which has a larger bandgap than silicon, may also be used for the semiconductor element. When the semiconductor unit 101 includes the semiconductor elements formed of such a wide-bandgap semiconductor material and capable of high-current operation and high-temperature operation, it exhibits a particularly remarkable effect in the above operation.

[0063] Since the power loss of a switching element and a rectifier element formed from a wide-bandgap semiconductor element is lower than that of such an element formed from silicon, the switching element and the rectifier element can achieve increased efficiency, and, by extension, a power semiconductor device using the element can achieve high efficiency. Since wide-bandgap switching and rectifier elements have a high breakdown voltage and also a high allowable current density, their dimensions can be reduced.

[0064] Accordingly, the use of these small-sized switching elements and rectifying elements enables the power semiconductor device to be made compact or to operate at even higher currents. Furthermore, since they have high thermal resistance, high-temperature operation is possible, and this allows for a reduction in the size of a radiating fin (a cooling device) mounted in a heat sink. Furthermore, switching from a water cooling device to an air cooling device allows for a further reduction in the size of the power semiconductor device, and enables high-current operation.

[0065] Although the plate interconnection 5 is formed of Cu, another material such as Al may also be used. A plating material formed by bonding multiple metals, such as Invar and the like, may also be used. The plate interconnection may be coated with a metal layer such as Ni or Au, and its thickness is not limited to 1 mm.

[0066] Although the connecting element 5a is formed from PPS, a material such as polybutylene terephthalate (PBT) can also be used if the material is not deformed during the high-temperature reflow process. If the intermediate connecting elements 5 can be integrally connected, the connecting elements 5a can be arranged at one location or at multiple locations between the plurality of plate intermediate connecting elements 5.

[0067] Although the interconnecting elements are positioned using the positioning pins, the electrode structure 1c of the insulating substrate 1 can also be used instead of the pins. Although the interconnecting elements 5a are formed by insert molding, they can also be formed using a method in which they are integrally bonded by pressing a metal into a molded resin.

[0068] Although the plurality of intermediate connecting elements 5 are connected to the connecting elements 5a into one piece, the housing 7 is formed as shown in the Fig. 18A and Fig. 18B, it has a structure that also serves as a connecting member for the intermediate interconnection elements 5 to fix the external electrodes 5b of the intermediate interconnection elements 5. This enables a further reduction in the number of parts.

[0069] The housing 7 can be formed from polybutylene terephthalate (PBT) or the like if it is not deformed during the high-temperature reflow process. Although the housing is formed by insert molding, it can also be formed using a method of integrally bonding a metal into a molded resin.

[0070] The wire 8 is not limited to gate wiring, but can also be used for wiring an emitter sensing or a temperature sensing diode. Its material is not limited to Al, but can be another material, such as Cu. Furthermore, the diameter of the wires 8 is not limited to 200 µm. Furthermore, it is possible to solder a board-to-board interconnection element as the wires 8, rather than a single wire.

[0071] Although the resin sealing portion 9 is formed from an epoxy resin, the resin material is not limited to epoxy resin; silicone gel or the like can also be used as long as it ensures insulation. Bonding using solder 4 on the bottom side of the chip and solder 6 on the top side of the chip is performed by a simultaneous reflow process.

[0072] As described above, the semiconductor device 101 according to Embodiment 1 includes the insulating substrate 1 formed by integrating the ceramic base plate 1b and the cooling fin 1a; the plurality of plate interconnectors 5 connected to each other with the resin interconnectors 5a; and the plurality of semiconductor elements 3a, one side of which is bonded to the ceramic base plate 1b of the insulating substrate 1 with the solder 4 on the bottom side of the chip, and the other side of which is bonded to the corresponding plurality of plate interconnectors 5 with the solder 6 on the top side of the chip. The solder 4 on the bottom side of the chip and the solder 6 on the top side of the chip both predominantly contain Sn and 0.3 wt% to 3 wt% and 0.3 wt% to 2 wt% of Ag, respectively, and 0.5 wt% to 1 wt% of Cu.

[0073] This prevents the occurrence of shrinkage cavities and reduces the dimensions of the semiconductor device without compromising heat dissipation. Furthermore, since separation due to Ni loss during thermal cycling can be prevented and stress acting on the Al metal layer can be prevented, the module exhibits excellent reliability and low thermal resistance, thus providing a module with reduced dimensions.

[0074] By using solder 4 on the bottom of the chip and solder 6 on the top of the chip, which have the same composition, it becomes easier to control the manufacturing process. Furthermore, the components on and under the chip can be bonded using the same soldering equipment at the same temperature profile, since both solder materials have the same melting point.

[0075] Furthermore, since the insulating substrate 1 is formed by integrating the ceramic base plate 1b and the cooling fin 1a, the thermal resistance can be reduced more than in a case where the fin is brought into contact with the substrate via grease, thereby reducing the size of the module. Furthermore, since the interconnection on the chip 3 is formed by soldering the board interconnector 5, the current density can be increased and the size of the module can be reduced compared to a case where wire bonding is used.

[0076] Furthermore, since the plurality of inter-board connecting members are integrally connected in advance with the resin connecting members 5a, the number of positioning pins can be reduced, and the dimensions can be reduced accordingly. Furthermore, since the insulating substrate 1 and the semiconductor element 3a are soldered with the spacers 2 interposed between them, the minimum solder thickness can be ensured, and deterioration of heat dissipation due to the occurrence of solder thickness unevenness can be prevented.

[0077] Furthermore, in a case where Al is used for the metal layer on the front side of the chip 3, the same effect as above can be achieved because the solder containing predominantly Sn and 0.3 wt% to 2 wt% Ag and 0.5 wt% to 1 wt% Cu is used for the solder 6 on the chip top side. Similarly, in a case where Al is used for the metal layer on the back side of the chip 3, the same effect as above can be achieved because the solder containing predominantly Sn and 0.3 wt% to 2 wt% Ag and 0.5 wt% to 1 wt% Cu is used for the solder 4 on the chip bottom side. Embodiment 2

[0078] Although Embodiment 1 describes the manufacture of the semiconductor device using the solder 4 on the chip bottom side and the solder 6 on the chip top side, which predominantly contain Sn and 0.3 wt% to 3 wt% Ag and 0.5 wt% to 1 wt% Cu, Embodiment 2 describes the manufacture of a semiconductor device using a solder that predominantly contains Sn and only 0.5 wt% to 1 wt% Cu.

[0079] A semiconductor device 102 according to Embodiment 2 is fabricated using a solder containing predominantly Sn and 0.5 wt% to 1 wt% Cu for both the solder 4 on the chip bottom side and the solder 6 on the chip top side. Furthermore, a metal layer made of Ag is used for the metal layer 3d over the front side of the chip 3 and the metal layer 3b on the back side thereof, or the metal layer 1d on the front side of the electrode structure 1c of the insulating substrate 1.

[0080] The configuration of the manufactured semiconductor device of Embodiment 2 is the same as that of the semiconductor device of Embodiment 1 except for the metal layer 3d and the metal layer 3b or the metal layer 1d; therefore, the drawings used in Embodiment 1 are adopted in Embodiment 2, and the description of the same portions is omitted.

[0081] When the solder materials in a process for manufacturing a semiconductor device according to embodiment 2 are heated during the Fig. 16B, Ag is dissolved from the metal layers 3b bonded to the solder 4 on the chip bottom side therein and is dissolved from the metal layers 3d or 1d bonded to the solder 6 on the chip top side therein, so that the Ag concentrations in both the solder 4 on the chip bottom side and the solder 6 on the chip top side thereby become equal to 0.3 wt% to 2 wt%.

[0082] A manufacturing method for the semiconductor unit 102 according to Embodiment 2 is the same as that for the semiconductor unit 101 according to Embodiment 1 in other steps; therefore, the drawings used in Embodiment 1 are adopted, and the description of the same steps is omitted.

[0083] As described above, the method for manufacturing the semiconductor unit 102 according to Embodiment 2 includes a step of bonding the metal layers 3b on the back surfaces of the plurality of semiconductor elements 3a to the metal layers 1d on the front surfaces of the electrode patterns 1c on the front surface of the ceramic base plate 1b of the insulating substrate 1 formed by integrating the ceramic base plate 1b and the cooling fin 1a by the first reflow process with the solder 4 on the chip bottom side, and a step of bonding the plurality of plate interconnecting members 5 each corresponding to the semiconductor elements 3a to the metal layers 3d formed over the front surfaces of the plurality of semiconductor elements 3a by the second reflow process with the solder 6 on the chip top side.

[0084] By using the solder 4 on the chip bottom side and the solder 6 on the chip top side, both of which predominantly contain Sn and 0.5 wt% to 1 wt% Cu, and by forming the Ag of the metal layers 3d over the front sides of the plurality of semiconductor elements 3a and by forming the Ag either of the metal layers 3b on the back sides of the plurality of semiconductor elements 3a or of the metal layers 1d on the front side of the electrode structures 1c on the front side of the ceramic base plate 1b of the insulating substrate 1, both the solder 4 on the chip bottom side and the solder 6 on the chip top side are each converted into a solder that predominantly contains Sn and 0.3 wt% to 3 wt% Ag and 0.5 wt% to 1 wt% Cu through the reflow steps. This not only enables the manufactured semiconductor device to have the same effect as in Embodiment 1, but also enables the solder materials to be obtained at low cost.

[0085] Furthermore, in a case where the metal layer 3d and the metal layer 3b or the metal layer 1d, each formed of Ag, are exchanged or replaced with those formed of Cu, using a solder containing predominantly Sn and 0.3 wt% to 2 wt% Ag as both the solder 4 on the chip bottom side and the solder 6 on the chip top side can bring about the same effect.

[0086] Furthermore, the metal layer 3d and the metal layer 3b or the metal layer 1d, each formed of Ag or Cu, may be in the form of a plating or either a powder or a paste, thereby also bringing about the same effect.

[0087] In a case where the metal layer on the front side of the chip 3 is formed of Al, the same effect can be achieved because a solder containing predominantly Sn and 0.3 wt% to 2 wt% Ag and 0.5 wt% to 1 wt% Cu is used as solder 6 on the chip top side. Similarly, in a case where the metal layer on the back side of the chip 3 is formed of Al, the same effect can also be achieved because a solder containing predominantly Sn and 0.3 wt% to 2 wt% Ag and 0.5 wt% to 1 wt% Cu is used as solder 4 on the chip bottom side.

[0088] Metal layers 3b and 3d are not necessarily both made of Ag. It is also possible for only metal layer 3b to be made of Ag, or for only metal layer 3d to be made of Ag. Similarly, metal layers 3b and 3d are not necessarily both made of Cu. It is also possible for only metal layer 3b to be made of Cu, or for only metal layer 3d to be made of Cu. Embodiment 3

[0089] Although Embodiment 2 describes the case where the semiconductor element is directly disposed on the electrode structure 1c of the substrate 1 to be bonded with the solder 4 on the chip bottom side and the solder 6 on the chip top side, which predominantly contain Sn and 0.3 wt% to 2 wt% of Ag, Embodiment 3 describes a case where a resist is formed over a region on the electrode structure 1c different from the region for disposing the semiconductor element 3a.

[0090] Fig. 19 is a top plan view of a semiconductor device 103 according to Embodiment 3. Fig. 20 is a cross-sectional view in the direction of arrows BB in Fig. 19. As in the Fig. 19 and Fig.20, the semiconductor element 3a in the semiconductor unit 103 is bonded with the solder 4 at the chip bottom after the resist 10 made of polyimide or the like is formed over the area other than the area for disposing the semiconductor element 3a on the metal layer 1d on the front surface of the electrode pattern 1c in the case of those in Embodiment 2 in which the metal layer 1d made of Cu is formed on the front surface of the electrode pattern 1c on the ceramic base plate 1b of the insulating substrate and in which the solder 4 containing predominantly Sn and 0.3 wt% to 2 wt% Ag is used at the chip bottom.

[0091] The other configuration of the semiconductor unit 103 according to Embodiment 3 and the manufacturing method thereof are the same as the configuration of the semiconductor unit 102 according to Embodiment 2 and the manufacturing method thereof in the case where the metal layer 1d made of Cu is formed on the electrode structure 1c; therefore, the drawings used in Embodiment 2 are adopted, and the description of the same portions is omitted.

[0092] As described above, in the case where the metal layer 1d on the front side of the electrode structure 1c is formed of Cu, the semiconductor device manufactured according to the manufacturing method for the semiconductor device 103 of Embodiment 3 not only has the same effect as that of Embodiment 1, but also can prevent the wetting area of ​​the solder on the chip bottom from spreading because the bonding with the solder 4 on the chip bottom is performed after the resist 10 is formed over the area different from that for disposing the semiconductor element 3a on the metal layer 1d on the front side of the electrode structure 1c.

[0093] Although the above embodiments use a cooling fin 1a made of Al, the cooling fin is not limited to this. For example, using a cooling fin made of Cu can improve heat dissipation.

[0094] Although the interconnect element is bonded to the chip top surface using solder during the second reflow process, soldering can also be performed by local heating using a laser. Although the chip and substrate are coated with a metal layer, such as Ni, to ensure good solderability, a metal such as Ni diffuses into the solder during the melting of the solder.

[0095] Excessive diffusion of a metal such as Ni during the second reflow process changes the solder composition to one that is ineffective in preventing shrinkage voids. In contrast, localized heating using a laser can prevent such diffusion because the solder at the bottom of the chip does not melt. Furthermore, although a void may sometimes be formed due to proximity to an open end portion of a shrinkage void that occurred during the first reflow process, no such void is formed because the solder at the bottom of the chip does not melt.

[0096] Since localized laser heating prevents remelting of the solder on the chip bottom surface, defects such as voids and shrinkage cavities can be inspected under conditions where the interconnection element is not present. When the interconnection element is made of Cu, a CT scan or visual observation is required for inspection because its X-ray transmittance is substantially the same as that of the solder, and the inspection is performed under conditions where the Cu interconnection elements are soldered. On the other hand, performing the inspection under conditions where the interconnection elements are not yet soldered can reduce the inspection time because a conventional X-ray machine can be used.

[0097] Rapid heating can sometimes damage a chip confined to a soldering temperature by a soldering process due to thermal stresses caused by the difference between the linear expansion coefficients of the substrate and the chip. Since localized laser heating only heats the area to be bonded to the top of the chip using solder, the influence of thermal stresses due to a difference in the linear expansion coefficients between the substrate and the chip can be reduced, thus preventing chip breakage.

[0098] If it is possible to heat only a soldering area of ​​the solder on the chip top side and the interconnect element, contacting a heated metal, such as soldering iron, can be used as a bonding method. REFERENCE SYMBOL 1 insulating substrate; 1a cooling fin; 1b ceramic base plate; 1c Electrode structure; 1d metal layer; 2 spacers; 3 chips; 3a semiconductor element; 3b, 3c, 3d metal layer; 4 solder on the bottom of the chip; 5 intermediate connection(s) 6 solder on the top of the chip; 10 Resist; and 101 semiconductor unit 102, 103 semiconductor unit

Claims

[1] Semiconductor device comprising: - a substrate (1) formed by integrating an insulating member and a cooling fin (1a); - a plate intermediate connecting element (5); and - a semiconductor element (3), the back side of which is bonded with a first solder to an interconnection structure formed on the insulating elements of the substrate (1), and the front side of which is bonded with a second solder to the plate interconnection element (5) such that the plate interconnection element (5) corresponds to the semiconductor element (3), - the first solder predominantly contains Sn, 0.3 wt% to 3 wt% Ag and 0.5 wt% to 1 wt% Cu and - wherein the second solder predominantly contains Sn, 0.3 wt% to 2 wt% Ag and 0.5 wt% to 1 wt% Cu and a metal layer of Al is formed on the front side of the semiconductor element (3). [2] A semiconductor device according to claim 1, wherein the first solder predominantly contains Sn, 0.3 wt% to 2 wt% Ag and 0.5 wt% to 1 wt% Cu and a metal layer of Al is formed on the back side of the semiconductor element (3). [3] Semiconductor device comprising: - a substrate (1) formed by integrating an insulating member and a cooling fin (1a); - a plate intermediate connecting element (5); and - a semiconductor element (3), the back side of which is bonded with a first solder to an interconnection structure formed on the insulating element of the substrate (1), and the front side of which is bonded with a second solder to the plate interconnection element (5) such that the plate interconnection element (5) corresponds to the semiconductor element (3), - the first solder contains predominantly Sn, 0.3 wt% to 2 wt% Ag and 0.5 wt% to 1 wt% Cu, - wherein the substrate (1) is provided with a metal layer formed on the interconnection structure on the insulating member, which is bonded to the back side of the semiconductor element with the first solder via the metal layer, and the semiconductor element (3) is provided with a metal layer formed on the back side, which is bonded to the insulating member with the first solder via the metal layer, and -wherein at least one of the metal layer on the back side of the semiconductor element (3) and the metal layer on the interconnection structure on the insulating member is formed of Ag or Cu. [4] A semiconductor device according to claim 3, wherein the second solder predominantly contains Sn, 0.3 wt% to 3 wt% Ag and 0.5 wt% to 1 wt% Cu. [5] A semiconductor device according to claim 3 or 4, wherein the semiconductor element (3) is provided with a metal layer formed on the front surface of the semiconductor element (3), which is bonded to the board interconnection member (5) with the second solder via the metal layer, and the metal layer on the front surface of the semiconductor element (3) is formed of Ag or Cu. [6] A semiconductor device according to any one of claims 1 to 5, wherein the substrate (1) and the semiconductor element (3) are bonded with a spacer sandwiched between the substrate (1) and the semiconductor element (3). [7] The semiconductor unit according to any one of claims 1 to 6, wherein the semiconductor unit comprises a plurality of semiconductor elements (3), each being the semiconductor element (3), a plurality of board interconnection members (5), each being the board interconnection member (5), formed to correspond to the plurality of semiconductor elements (3), and a first board interconnection member (5) and a second board interconnection member (5), which are the board interconnection members (5), are joined to each other with a resin joining member. [8] A semiconductor device according to any one of claims 1 to 7, wherein the substrate (1) is formed by integrating the insulating member and the cooling fin (1a) by means of molding. [9] A semiconductor device according to any one of claims 1 to 8, wherein the substrate (1) is formed by integrating the insulating member and the cooling fin (1a) by brazing. [10] A semiconductor device according to any one of claims 1 to 9, wherein the semiconductor element (3) is formed of a semiconductor material having a large band gap, either a silicon carbide-based material, a gallium nitride-based material or a diamond-based material. [11] A method for manufacturing a semiconductor device, comprising the following steps: - bonding the back side of a semiconductor element (3) with a first solder by a first reflow process to an interconnection structure on an insulating element of a substrate (1) formed by integrating the insulating element and a cooling fin (1a); and - bonding a plate interconnection element (5) with a second solder by a second reflow process to a front side of the semiconductor element (3) such that the plate interconnection element (5) corresponds to the semiconductor element (3), - the first solder predominantly contains Sn, 0.3 wt% to 3 wt% Ag and 0.5 wt% to 1 wt% Cu and - wherein the second solder predominantly contains Sn, 0.3 wt% to 2 wt% Ag and 0.5 wt% to 1 wt% Cu and a metal layer of Al is formed over the front side of the semiconductor element (3). [12] The method according to claim 11, wherein the first solder predominantly contains Sn, 0.3 wt% to 2 wt% Ag and 0.5 wt% to 1 wt% Cu and a metal layer of Al is formed on the back side of the semiconductor element (3). [13] Method for producing a semiconductor device, which includes the following steps: - bonding a metal layer formed on the back side of a semiconductor element (3) with a first solder by a first reflow process to a metal layer formed on an interconnection structure on an insulating member of a substrate (1) formed by integrating the insulating member and a cooling fin (1a); and - bonding a metal layer formed over the front side of the semiconductor element (3) with a second solder to a plate interconnection element (3) by a second reflow process such that the plate interconnection element (5) corresponds to the semiconductor element (3), wherein at least one of the metal layer on the back surface of a semiconductor element (3) and the metal layer formed on the interconnection structure on the insulating member of the substrate (1) is formed of Ag, and a solder predominantly containing Sn and 0.5 wt% to 1 wt% Cu is used as the first solder, so that the first solder becomes a solder predominantly containing Sn, 0.3 wt% to 3 wt% Ag, and 0.5 wt% to 1 wt% Cu during the first reflow process in the step of bonding with the first solder. [14] Method for producing a semiconductor device, which includes the following steps: - bonding a metal layer formed on the back side of a semiconductor element (3) with a first solder by a first reflow process to a metal layer formed on an interconnection structure on an insulating member of a substrate (1) formed by integrating an insulating member and a cooling fin (1a); and - bonding a plate interconnection element (5) with a second solder by a second reflow process to a metal layer formed over the front side of the semiconductor element (3) such that the plate interconnection element (5) corresponds to the semiconductor element (3), wherein at least one of the metal layer on the back surface of a semiconductor element (3) and the metal layer formed on the interconnection structure on the insulating member of the substrate (1) is formed of Cu, and a solder predominantly containing Sn and 0.3 wt% to 3 wt% Ag is used as the first solder, so that the first solder becomes a solder predominantly containing Sn, 0.3 wt% to 3 wt% Ag, and 0.5 wt% to 1 wt% Cu during the first reflow process in the step of bonding with the first solder. [15] The method according to any one of claims 11 to 14, wherein the semiconductor unit comprises a plurality of semiconductor elements (3), each being the semiconductor element (3), a plurality of board interconnection members (5), each being the board interconnection member (5), are formed to correspond to the plurality of semiconductor elements (3), and a first board interconnection member (5) and a second board interconnection member (5), which are the board interconnection members (5), are bonded to each other with a resin bonding member. [16] A method according to any one of claims 11 to 15, wherein the step of bonding with the first solder and the step of bonding with the second solder are carried out at the same time. [17] A method according to any one of claims 11 to 16, wherein the step of bonding with the first solder is performed simultaneously with a step of bonding a package to the substrate (1). [18] The method according to any one of claims 11 to 17, wherein the bonding in the step of bonding with the second solder is performed by local heating using a laser instead of bonding by the second reflow process. [19] Semiconductor device comprising: - a substrate (1) formed by integrating an insulating member and a cooling fin (1a); - a plate intermediate connecting element (5); and - a semiconductor element (3), the back side of which is bonded with a first solder to an interconnection structure formed on the insulating element of the substrate (1), and the front side of which is bonded with a second solder to the plate interconnection element (5) such that the plate interconnection element (5) corresponds to the semiconductor element (3), wherein the first solder predominantly contains Sn, 0.3 wt% to 2 wt% Ag and 0.5 wt% to 1 wt% Cu and a metal layer of Al is formed on the back side of the semiconductor element (3).

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