Semiconductor device

Abstract

Semiconductor device in which a main current flows in a thickness direction of a semiconductor substrate (1), the semiconductor substrate comprising: an active region (AR) in which the main current flows; and a termination region (2) located on an outside of the active region; the semiconductor device comprising: a first main electrode (3) arranged on the active region (AR); a second main electrode (19) arranged on a side of the semiconductor substrate (1) opposite the first main electrode (3); and a protective film (4) covering at least the termination region (2).and a non-electrolytic plating layer (8) arranged on the first main electrode (3) not covered by the protective film (4), the first main electrode (3) comprising a central electrode (3a) in a central part and an outer peripheral electrode (3b) arranged along the central electrode (3a) so that it is separated from the central electrode (3a), the protective film (4) arranged so that it extends from the termination region (2) to an end edge region of the outer peripheral electrode (3b), the central electrode (3a) and the outer peripheral electrode (3b) comprising: a first metal layer (6); and an aluminium-containing second metal layer (7) arranged on the first metal layer (6), and at least the outer peripheral electrode (3b) has a hole portion (9, 91, 92) that penetrates the second metal layer (7) to reach the first metal layer (6).

Description

Technical FieldThe present invention relates to a semiconductor device, and more particularly to a semiconductor device in which an external electrode electrically connected to an external component and a main electrode of the semiconductor device are bonded with a solder.Background ArtIn a conventional semiconductor device, for example, Patent Document 1 discloses a configuration of solder bonding a surface electrode and an external electrode to reduce the conduction resistance of the semiconductor device. In this configuration, there is a possibility that tensile stress occurs on the surface electrode due to a thermal cycle when current is applied, and a crack is generated in an end portion of the electrode. The crack expands from the electrode toward an inside of the semiconductor device, and the semiconductor device electrically collapses in some cases, and such a state is a problem in improving the thermal cycle compatible dose of products.There is a case where an alloy of a solder and the surface electrode advances due to the thermal cycle, so that the surface electrode needs to be thickened to secure the dose compatible with a thermal cycle. Accordingly, as disclosed in Patent Document 2, it is common to form an electrode using non-electrolytic plating of nickel (Ni).Prior Art DocumentsPatent DocumentsPatent Document 1: JP 2008-182 074 APatent Document 2: JP 2005-019 798 ASummaryProblem to be Solved by the InventionThere is a possibility that a crack occurs in an end portion of a surface electrode even when the surface electrode is thickened, and when the crack expands to reach an inner side of a semiconductor device, there is a possibility that the semiconductor device electrically breaks down.The present disclosure has therefore been made to solve problems as described above, and an object is to provide a semiconductor device in which tolerance to thermal cycles is improved.Means for Solving the ProblemA semiconductor device according to the present invention is a semiconductor device in which a main current flows in a thickness direction of a semiconductor substrate, the semiconductor substrate including: an active region in which the main current flows; and a termination region located on an outer side of the active region, the semiconductor device including: a first main electrode disposed on the active region; a second main electrode disposed on an opposite side of the semiconductor substrate from the first main electrode; a protection film covering at least the termination region; and a non-electrolytic plating layer disposed on the first main electrode not covered by the protective film, the first main electrode comprising a center electrode in a central part and an outer peripheral electrode disposed along the central electrode so as to be separated from the central electrode, the protective film being disposed so as to extend from the termination region to an end edge part region of the outer peripheral electrode, the central electrode and the outer peripheral electrode comprising: a first metal layer; and an aluminum-containing second metal layer disposed on the first metal layer, and at least the outer peripheral electrode having a hole part penetrating the second metal layer so as to reach the first metal layer.Effects of the InventionAccording to the semiconductor device according to the present invention, the hole part penetrating the second metal layer of the outer peripheral electrode is provided to reach the first metal layer, thereby reducing a contact area between the first metal layer and the second metal layer, so that peeling easily occurs at an interface between the first metal layer and the second metal layer. Accordingly, even in a case where a crack (interfacial detachment) occurs along the interface between the protective film and the non-electrolytic plating layer due to the thermal cycle, when the crack reaches the outer peripheral electrode, peeling in a horizontal direction expands at the interface between the first metal layer and the second metal layer, and a crack expanding in a vertical direction, that is, in a thickness direction, of the semiconductor device is suppressed, so that compatibility with thermal cycles is improved.Brief Description of the Drawings[FIG. 1 ] A plan view illustrating an upper surface configuration of a semiconductor device according to Embodiment 1.[FIG. 2 ] A partial cross-sectional view illustrating a configuration of the semiconductor device according to Embodiment 1.[FIG. 3 ] A partial cross-sectional view illustrating a configuration of the semiconductor device according to Embodiment 1.[FIG. 4 ] A partial enlarged view illustrating a configuration of the semiconductor device according to Embodiment 1.[FIG. 5 ] A cross-sectional view schematically illustrating a crack occurring when a thermal cycle caused by application of current is applied to the semiconductor device according to Embodiment 1.[FIG. 6 ] A partial cross-sectional view to describe a method of manufacturing the semiconductor device according to Embodiment 1.[FIG. 7 ] A partial cross-sectional view to describe a method of manufacturing the semiconductor device according to Embodiment 1.[FIG. 8 ] A partial cross-sectional view illustrating a configuration of a semiconductor device according to Embodiment 2.[FIG. 9 ] A partial cross-sectional view illustrating a configuration of a semiconductor device according to Embodiment 3.[FIG. 10 ] A partial cross-sectional view to describe a method of manufacturing the semiconductor device according to Embodiment 3.[FIG. 11 ] A partial cross-sectional view to describe a method of manufacturing the semiconductor device according to Embodiment 3.[FIG. 12] A partial cross-sectional view illustrating a configuration of a semiconductor device according to Embodiment 4.[FIG. 13 ] A partial cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment 5.[FIG. 14 ] A drawing to describe a relationship between a distance from a central emitter electrode to an outer peripheral emitter electrode and a thickness of a plating layer.Brief Description of the (of) Embodiment(s)<>>Hereinafter, in the description, "an active region" is a region in which a main current flows when a semiconductor device is in an ON state. Hereinafter, in the description, "an outer side" is a direction toward an outer periphery of the semiconductor device, and "an inner side" is a direction opposite to the outer side. Hereinafter, in the description, regarding a conductivity type of a impurity, an N type is generally defined as "a first conductivity type", and a P type that is a conductivity type opposite to the N type is defined as "a second conductivity type"; however, a reverse definition is also applicable.The drawings are schematically illustrated such that a size of an image and a mutual relationship of positions thereof are not necessarily accurately illustrated but can be appropriately changed. In the description hereinafter, the same reference numerals are assigned to the similar individual elements in the illustration, and the same applies to their names and functions. Thus, the detailed description thereof may be omitted in some cases. In the present description, when reference is made to "on... " and "cover... " this does not prevent the presence of an object located therebetween between the individual elements. For example, when "B disposed on A" or "A covered B" is mentioned, this may mean that the other single element C is disposed between A and B or is not disposed. In the description herein, terms each indicating a specific position and direction such as "top side", "bottom side", "lateral side", "bottom", "front side" and "back side" are used hereinafter; however, these terms are used for easier understanding of contents of the embodiments and do not refer to a direction in actual use.A term "MOS" has hitherto been used for a transition structure of a metal oxide semiconductor and stands for the initials of "metal oxide semiconductor". However, especially in a field effect transistor having a MOS structure (hereinafter, simply referred to as "the MOS transistor"), materials of a gate insulating film and a gate electrode are improved from the viewpoint of recent integration and improvement of a manufacturing process.For example, in the MOS transistor, from the viewpoint of mainly forming a source and a drain in a self-aligned form, polycrystalline silicon is adopted as a material of a gate electrode instead of a metal. From the viewpoint of improving electrical characteristics, a material having a high dielectric constant is adopted as the material of the gate insulating film; however, the material is not necessarily limited to an oxide.Accordingly, the term "MOS" is not necessarily used only for a lamination structure of a metal oxide semiconductor, and the present description is not based on such a premise. That is, in view of the technical common knowledge herein, "MOS" means not only an abbreviation derived from a word origin, but also broadly includes a lamination structure of conductor-insulator-semiconductor.An embodiment of a semiconductor device according to the present invention will be described hereinafter. An insulated gate bipolar transistor (IGBT) will be described hereinafter as an example of the semiconductor device.< 1><Konfiguration of Device>FIG. 1 is a plan view schematically illustrating an upper surface configuration of an IGBT 100 according to an embodiment 1 of the present invention. As illustrated in FIG. 1, the IGBT 100 is disposed on a semiconductor substrate 1 having a quadrangular shape in plan view, and a gate wiring 51 is disposed along the outer peripheral part thereof. A gate electrode pad 5 having a quadrangular shape is disposed on a corner part of the IGBT 100, and the gate electrode pad 5 is surrounded by the gate wiring 51.An emitter electrode 3 (a first main electrode) is disposed on a substantially larger part of a main surface of the IGBT 100 than a part where the gate electrode pad 5 and the gate wiring 51 are provided.The emitter electrode 3 is disposed on an active region AR of the IGBT 100, and the emitter electrode 3 is divided into a central emitter electrode 3 ain a central part and an outer peripheral emitter electrode 3 bdisposed so as to surround an outer side of the central emitter electrode 3 a.A region on an outer side of an outer periphery of the gate wiring 51 is defined as a terminal region (terminal region) 2. An impurity region for holding a withstand voltage may be provided in the termination region 2; however, this is not illustrated. A protective film 4 is provided to cover at least the termination region 2 and the gate wiring 51.A cross-sectional view along an A-A line in an arrow direction in FIG. 1 is illustrated in FIG. 2, and a cross-sectional view along a B-B line in an arrow direction is illustrated in FIG. 3. As illustrated in FIGS. 2 and 3, in the IGBT 100, an N-type drift layer 15 is disposed on an upper main surface of an N-type buffer layer 16, and a P-type body layer 10 is disposed on an upper layer part of the N-type drift layer 15.A P-type collector layer 17 is disposed on a lower main surface of the buffer layer 16, a metal layer 18 made of an aluminum-silicon alloy (AISi) is disposed on a lower main surface of the collector layer 17, and a metal layer 19 made of Ni (Nil) is disposed on a lower main surface of the metal layer 18 to form a collector electrode (a second main electrode). The semiconductor substrate 1 includes the collector layer 17, the buffer layer 16, the drift layer 15, and the body layer 10.On an upper layer part of the body layer 10, a plurality of N-type emitter layers 12 are selectively disposed, and a plurality of electrodes 11 of trench gates penetrating the emitter layer 12 and the body layer 10 in the thickness direction to reach the drift layer 15 are disposed.An interlayer insulating film 13 is disposed on the drift layer 15 (on the body layer 10), and a plurality of contact electrodes 14 penetrating through the interlayer insulating film 13 in the thickness direction to reach the emitter layer 12 are disposed in the interlayer insulating film 13.The central emitter electrode 3 aand the outer peripheral emitter electrode 3 bhave a stack structure made up of a metal layer 6 (a first metal layer) disposed on the interlayer insulating film 13 so as to be in contact with the plurality of contact electrodes 14 and a metal layer 7 (a second metal layer) disposed on the metal layer 6, and a plating layer 8 is disposed on the metal layer 7. Herein, the metal layer 6 is, for example, a barrier metal of Ti / TiN in which titanium (Ti) is stacked on titanium nitride (TiN), the metal layer 7 is, for example, an aluminum layer, and the plating layer 8 is, for example, a non-electrolytic nickel plating layer (a non-electrolytic plating layer) of phosphorated nickel (NiP).A hole part 9 penetrating through the metal layer 7 in the thickness direction to reach an upper surface of the metal layer 6 is formed in the metal layer 7, and the hole part 9 is filled with the plating layer 8.The protective film 4 made of, for example, polyimide is provided to cover a region from a top surface of a peripheral portion of the gate electrode pad 5 to a top surface of an outer peripheral portion of the outer peripheral emitter electrode 3 bin FIG. 1 and a region from a top surface of an outer peripheral portion of the outer peripheral emitter electrode 3 bto a top surface of the gate electrode pad 5 in FIG. 2.In FIG. 4, an enlarged view of a region "X" in FIG. 2 is illustrated herein. FIG. 4 is a drawing illustrating in detail a trench gate electrode 11 and a contact electrode 14. As illustrated in FIG. 4, in the electrode 11 of a trench gate, a gate insulating film 111 is disposed to cover an outer surface of a gate trench 113 that penetrates the emitter layer 12 and the body layer 10 in the thickness direction to reach an inner side of the drift layer 15, and a gate electrode 112 is embedded in the gate trench 113 covered by the gate insulating film 111.A top surface of the trench gate electrode 11 is covered by the interlayer insulating film 13 and is electrically connected to the gate wiring 51 via an opening part of the interlayer insulating film 13 provided in a portion not illustrated in the drawings, thereby having a configuration in which a gate voltage is provided.The metal layer 6 is embedded in the contact electrode 14 in an opening part 131 that penetrates the interlayer insulating film 13 in the thickness direction to reach the emitter electrode 12. Moreover, a tungsten (W) layer 142 is embedded in an opening part 141 in the metal layer 6 embedded in the opening part 131, and the metal layer 6 and the tungsten layer 142 form the contact electrode 14.FIG. 5 is a cross-sectional view schematically illustrating a crack 21 occurring when a brazing metal layer 20 is bonded to the plating layer 8 and a thermal cycle induced by application of current is applied.As illustrated in FIG. 5, when the crack 21 occurring due to the thermal cycle expands along an interface between the protective film 4 and the plating layer 8 and contacts the metal layer 7, a crack (interface detachment) first occurs at the interface between the plating layer 8 and the metal layer 7. Subsequently, when the peeling reaches an upper surface of the metal layer 6, peeling occurs at an interface between the metal layer 7 and the metal layer 6 because a contact area between the metal layer 6 and the metal layer 7 is reduced by forming the hole part 9. As a result, the peeling expands in a horizontal direction, and expansion of the peeling in a vertical direction, that is, a thickness direction of the IGBT 100 is suppressed, so that breakdown of an element structure of the IGBT 100 is suppressed, and the lifetime of a device can be set longer than that before.The separation at the interface expands on the outer peripheral emitter electrode 3 b; however, the outer peripheral emitter electrode 3 band the central emitter electrode 3 aare separated from each other so that a crack expanding toward the central emitter electrode 3 ais suppressed.< Method>A method of manufacturing the IGBT 100 will be described next using FIGS. 6 and 7, which are cross-sectional views sequentially illustrating a manufacturing process. The configuration under the interlayer insulating film 13 is well known, and a known technique can be used for the manufacturing method thereof, so that the description is omitted.After the configuration is formed under the interlayer insulating film 13 using a conventional technique, for example, in a process illustrated in FIG. 6, the contact electrode 14 is formed in the interlayer insulating film 13, a barrier metal made of Ti / TiN is formed on the interlayer insulating film 13 to form the metal layer 6, and an aluminum layer is formed on the metal layer 6 to form the metal layer 7. The metal layer 7 may be an aluminum alloy layer.The metal layer 6 is formed on the active region but is not formed on a formation region of the gate electrode pad 5 and the gate wiring 51, and the stack structure of the metal layer 6 and the metal layer 7 is formed on the active region. It is also possible that the metal layer 6 is also formed in the formation region of the gate electrode pad 5 and the gate wiring 51 to form a stack structure with the metal layer 7.The stacked structure of the metal layer 6 and the metal layer 7 and the metal layer 7 are patterned by a photolithography process and an etching process, and a region where the protective film 4 contacts the interlayer insulating film 13 and a region separating the central emitter electrode 3 aand the outer peripheral emitter electrode 3 bare opened. The protective film 4 is selectively formed by polyimide, for example. A well-known etching process may be used for etching the metal layer 6 and the metal layer 7.Next, Al pitting corrosion is generated in the metal layer 7 by performing zincate processing as pre-processing before forming the plating layer 8 by performing non-electrolytic NiP plating on aluminum, and the plurality of hole parts 9 penetrating the metal layer 7 in the thickness direction are formed as illustrated in FIG. 7.Here, a depth of Al pitting corrosion by the zincate processing is approximately 0.5 μm to 1 μm, so that a thickness of the metal layer 7 is set to be equal to or greater than 0.5 μm and equal to or less than 1 μm, and more preferably is approximately 0.5 μm, so that the hole part 9 reliably penetrates the metal layer 7. A thickness of the metal layer 6 is approximately 0.1 μm, and a thickness of the plating layer 8 is approximately 5 μm.Subsequently, the plating layer 8 is formed by performing non-electrolytic NiP plating to obtain the IGBT 100 having the cross-sectional configuration illustrated in FIGS. 2 and 3.Al pitting corrosion performed by zincate processing is used as the hole part 9, so that processing treatment for forming the hole part 9 in the metal layer can be omitted. Accordingly, a process and a cost necessary for processing can be reduced, and a reduction in productivity can be suppressed by providing the hole part 9.<Ausführungsform 2>FIG. 8 is a cross-sectional view illustrating a configuration of an IGBT 200 of an embodiment 2 according to the present invention, and corresponds to a cross-sectional view along a B-B line in an arrow direction in FIG. 1 ; an upper surface configuration of the IGBT 200 is the same as a plan view of the IGBT 100 illustrated in FIG. 1.As illustrated in FIG. 8, in the IGBT 200, a hole part 91 in an outer peripheral emitter electrode 3 bis formed larger than the hole part 9 in the central emitter electrode 3 a. The hole part 91 in the outer peripheral emitter electrode 3 bis enlarged so that a crack (interfacial detachment) occurring when a thermal cycle is applied to the IGBT 200 can more reliably expand in a horizontal direction of the outer peripheral emitter electrode 3 band expansion of detachment in a vertical direction, that is, in a thickness direction of the IGBT 200 is suppressed, so that breakdown of an element structure of the IGBT 200 is suppressed and the lifetime of a device can be prolonged more than before.In order to form the hole part 91 in the outer peripheral emitter electrode 3 bto be larger than the hole part 9 in the central emitter electrode 3 aas described above, a process of forming a part to be the central emitter electrode 3 aand the gate electrode pad 5 (not illustrated) and a part to be the outer peripheral emitter electrode 3 bis performed separately, and in forming the metal layer 7 made of AISi, the part of the metal layer 7 to be the outer peripheral emitter electrode 3 bis formed by another film material so that the silicon concentration thereof is higher than that of the part of the metal layer 7 to be the central emitter electrode 3 aand the gate electrode pad 5.Normally, an Si content of AlSi is approximately 1%. Its content is increased to approximately 10%, so that a silicon bump (silicon segregation) is formed in large amounts in the metal layer 7. In the zincate processing before the formation of the plating layer 8, a silicon pad is also peeled from the metal layer 7, so that the hole part 91 larger than the hole part 9 in the central emitter electrode 3 ais formed in the part of the metal layer 7 to be the outer peripheral emitter electrode 3 b.A sputtering method is used to form the metal layer 7, and a sputtering target having a different Si composition ratio is used, so that a Si concentration in the part to be the central emitter electrode 3 aand the gate electrode pad 5 and the part to be the outer peripheral emitter electrode 3 bcan be set differently. That is, it is sufficient that when forming the part of the metal layer 7 to be the central emitter electrode 3 aand the gate electrode pad 5 (not illustrated), the sputtering target having a Si composition ratio of approximately 1% is used, and when forming the part to be the outer peripheral emitter electrode 3 b, the sputtering target having a Si composition ratio of approximately 10% is used.<Ausführungsform 3><Konfiguration of Device>FIG. 9 is a cross-sectional view illustrating a configuration of an IGBT 300 of an embodiment 3 according to the present invention, and corresponds to a cross-sectional view along an A-A line in an arrow direction in FIG. 1. A top surface configuration of the IGBT 300 is the same as a plan view of the IGBT 100 illustrated in FIG. 1.As illustrated in FIG. 9, in the IGBT 300, a hole part 92 in an outer peripheral emitter electrode 3 bis formed deeper and larger than the hole part 9 in the central emitter electrode 3 aand the gate electrode pad 5, and the hole part 92 in the outer peripheral emitter electrode 3 btransfiltrates the metal layer 7 to reach an upper surface of the metal layer 6; however, the hole part 9 in the central emitter electrode 3 aand the gate electrode pad 5 does not permeate the metal layer 7.The hole part 92 in the outer peripheral emitter electrode 3 btransfiltrates the metal layer 7 to reach the top surface of the metal layer 6, so that a crack (interfacial detachment) occurring when a thermal cycle is applied to the IGBT 300 can expand in the horizontal direction of the outer peripheral emitter electrode 3 band expansion of the detachment in a vertical direction, that is, in a thickness direction of the IGBT 300 is suppressed, so that breakdown of an element structure of the IGBT 300 is suppressed, and the lifetime of a device can be prolonged more than before.The hole part 92 in the outer peripheral emitter electrode 3 bis herein a hole selectively formed by etching, and the hole part 9 in the central emitter electrode 3 aand the gate electrode pad 5 is formed by Al pitting corrosion by zincate processing before the formation of the plating layer 8, and is a non-selectively formed hole.< Method>A method of manufacturing the IGBT 300 will be described next using FIGS. 10 and 11 which are cross-sectional views sequentially illustrating a manufacturing process. The configuration under the interlayer insulating film 13 is well known, and a known technique can be used for the manufacturing method thereof, so that the description is omitted.After the configuration is formed under the interlayer insulating film 13 using a conventional technique, for example, the contact electrode 14 is formed in the interlayer insulating film 13, a barrier metal made of Ti / TiN is formed on the interlayer insulating film 13 to form the metal layer 6, and an aluminum layer is formed on the metal layer 6 to form the metal layer 7. The metal layer 6 is formed on the active region but is not formed on a formation region of the gate electrode pad 5 and the gate wiring 51, and the stack structure of the metal layer 6 and the metal layer 7 is formed on the active region. It is also possible that the metal layer 6 is also formed in the formation region of the gate electrode pad 5 and the gate wiring 51 to form a stack structure with the metal layer 7.The stacked structure of the metal layer 6 and the metal layer 7 and the metal layer 7 are patterned by a photolithography process and an etching process, and a region where the protective film 4 contacts the interlayer insulating film 13 and a region separating the central emitter electrode 3 aand the outer peripheral emitter electrode 3 bare opened. The protective film 4 is selectively formed by polyimide, for example.Subsequently, after a rephotolithography process in a process illustrated in FIG. 10, on the part of the metal layer 7 to be the emitter outer peripheral electrode 3 b, a resist mask RM in which a part to be the hole part 92 becomes an opening part OP is disposed. The resist mask RM has no opening part other than the opening part OP, and the top surface of the part of the metal layer 7 to be the central emitter electrode 3 aand the gate electrode pad 5 is covered by the resist mask RM.Subsequently, the stacked structure of the metal layer 6 and the metal layer 7 is etched via the opening part OP by the etching process, so that the hole part 92 penetrating the metal layer 7 to reach the top surface of the metal layer 6 is formed.After the resist mask RM is removed, zincate processing is performed by means of non-electrolytic NiP plating on aluminum before the plating layer 8 is formed. Accordingly, as illustrated in FIG. 11, in the part of the metal layer 7 to be the central emitter electrode 3 aand the gate electrode pad 5, the Al pitting corrosion occurs, so that the hole part 9 is formed.The thickness of the metal layer 7 herein is equal to or greater than 1.5 μm, so that the hole part 9 cannot penetrate the metal layer 7 and does not reach the top surface of the metal layer 6 in the central emitter electrode 3 aand the gate electrode pad 5. The thickness of the metal layer 7 is preferably equal to or greater than 1.5 μm and equal to or less than 2 μm from the viewpoint of securing flatness of the plating layer 8.By the zincate processing, the Al pitting corrosion also occurs in the outer peripheral emitter electrode 3 b; however, the thickness of the metal layer 7 is equal to or greater than 1.5 μm, so that the hole part 9 cannot penetrate the metal layer 7 by the Al pitting corrosion, and illustration thereof is omitted.Subsequently, the plating layer 8 is formed by performing non-electrolytic NiP plating to obtain the IGBT 300 having the cross-sectional configuration illustrated in FIG. 9.The hole part 92 in the outer peripheral emitter electrode 3 bis formed by etching in this manner, and the size, shape, number, and arrangement pattern of the hole part 92 can be optionally set so that the expansion of the crack (interfacial detachment) at the interface between the metal layer 7 in the outer peripheral emitter electrode 3 band the metal layer 6 can be controlled and the crack can reliably expand in the horizontal direction.The hole part 9 in the central emitter electrode 3 aand the gate electrode pad 5 cannot penetrate the metal layer 7, so that contact between the metal layer 6 and the plating layer 8 with a large contact resistance can be avoided. Accordingly, a contact area between the metal layer 6 and the metal layer 7 having a low contact resistance is increased, and the resistance upon application of current is reduced, and an electrical performance of the IGBT 300 is improved.<Ausführungsform 4>FIG. 12 is a cross-sectional view illustrating a configuration of an IGBT 400 of an embodiment 4 according to the present invention, and corresponds to a cross-sectional view along a B-B line in an arrow direction in FIG. 1 ; an upper surface configuration of the IGBT 400 is the same as a plan view of the IGBT 100 illustrated in FIG. 1.As illustrated in FIG. 12, in the IGBT 400, the thickness of the metal layer 7 in the central emitter electrode 3 aand the gate wiring 51 (and the gate electrode pad 5) is larger than that of the metal layer 7 in the outer peripheral emitter electrode 3 b, and the hole part 9 in the central emitter electrode 3 adoes not penetrate the metal layer 7. Meanwhile, the hole part 9 in the outer peripheral emitter electrode 3 btransfiltrates the metal layer 7 to reach the top surface of the metal layer 6.In order to form the metal layer 7 in the central emitter electrode 3 aand the gate wiring 51 (and the gate electrode pad 5) to have the thickness larger than the metal layer 7 in the outer peripheral emitter electrode 3 bas described above, a process of forming the part to be the central emitter electrode 3 aand the gate wiring 51 (and the gate electrode pad 5) and the part to be the outer peripheral emitter electrode 3 bis performed separately in the formation of the metal layer 7.The thickness of the part of the metal layer 7 to be the central emitter electrode 3 aand the gate wiring 51 (and the gate electrode pad 5) is set to be equal to or greater than 1.5 μm, and the thickness of the part of the metal layer 7 to be the outer peripheral emitter electrode 3 bis set to be equal to or greater than 0.5 μm and equal to or less than 1 μm, and is more preferably approximately 0.5 μm, so that the hole part 9 reliably penetrates the metal layer 7. The thickness of the part of the metal layer 7 to be the central emitter electrode 3 aand the gate wiring 51 (and the gate electrode pad 5) is preferably equal to or greater than 1.5 μm and equal to or less than 2 μm from a viewpoint of securing flatness of the plating layer 8.According to such a configuration, in the outer peripheral emitter electrode 3 b, a crack (interfacial detachment) occurring when a thermal cycle is applied to the IGBT 400 can expand in the horizontal direction of the outer peripheral emitter electrode 3 band expansion of peeling in a vertical direction, that is, in a thickness direction of the IGBT 400 is suppressed, so that breakdown of an element structure of the IGBT 400 is suppressed and the lifetime of a device can be prolonged more than before.The hole part 9 in the central emitter electrode 3 aand the gate electrode pad 5 cannot penetrate the metal layer 7, so that contact between the metal layer 6 and the plating layer 8 with a large contact resistance can be avoided. Accordingly, a contact area between the metal layer 6 and the metal layer 7 having a low contact resistance is increased, and a resistance upon application of current is reduced, and an electrical performance of the IGBT 400 is improved.<Ausführungsform 5>FIG. 13 is a cross-sectional view illustrating a configuration of an IGBT 500 of an embodiment 5 according to the present invention, and corresponds to a cross-sectional view along a B-B line in an arrow direction in FIG. 1 ; an upper surface configuration of the IGBT 500 is the same as a plan view of the IGBT 100 illustrated in FIG. 1.As illustrated in FIG. 13, the IGBT 500 has a configuration in which the electrode 11 of a trench gate is not disposed in a lower part of the outer peripheral emitter electrode 3 b, that is, no unit cell is included as a minimum unit structure of the IGBT.By adopting such a configuration, the flatness of the metal layer 6 of the outer peripheral emitter electrode 3 bis improved, a crack (interfacial detachment) occurring when a thermal cycle is applied to the IGBT 500 can expand more reliably in the horizontal direction at the interface between the metal layer 7 and the metal layer 6 in the outer peripheral emitter electrode 3 b, and expansion of detachment in a vertical direction, that is, in a thickness direction of the IGBT 500 is suppressed, so that breakdown of an element structure of the IGBT 500 is suppressed, and the lifetime of a device can be set longer than that before.The trench gate electrode 11 is not disposed in the lower part of the outer peripheral emitter electrode 3 b, so that the number of unit cells in the IGBT 500 is reduced by the absence of the trench gate electrode 11. Accordingly, a length of the emitter outer peripheral electrode 3 bin the horizontal direction is reduced as much as possible to suppress the reduction of the unit cell, and is set to, for example, approximately 5 μm.<Beziehung Between Distance from Central Emitter Electrode to Outer Peripheral Emitter Electrode and Thickness of Plating Layer>FIG. 14 is a drawing for describing a relationship between a distance from a central emitter electrode to an outer peripheral emitter electrode and a thickness of a plating layer, and is a drawing based on a cross-sectional view along the B-B line in the arrow direction in FIG. 1. FIG. 14 illustrates a case where a relationship between a distance d and a thickness t is d>2t, where the distance from the central emitter electrode 3 ato the outer peripheral emitter electrode 3 bis d, and the thickness of the plating layer 8 is t.In this case, if the distance from the central emitter electrode 3 ato the outer peripheral emitter electrode 3 bis too large, there is a possibility that a solder layer 20 extends over only a top surface of the central emitter electrode 3 awhen the solder layer 20 is bonded to a top surface of the plating layer 8, and a crack occurs on the top surface of the central emitter electrode 3 awhen a thermal cycle is applied, and the device lifetime is reduced.Meanwhile, the distance from the central emitter electrode 3 ato the outer peripheral emitter electrode 3 bis set such that the relationship between the distance d and the thickness t is expressed as d≤2 t, so that the plating layer 8 formed on the central emitter electrode 3 aand the outer peripheral emitter electrode 3 bexpands uniformly, and the solder layer 20 extends over an entire surface of the upper surface of the plating layer 8 on an upper surface of the central emitter electrode 3 aand the outer peripheral emitter electrode 3 b. Thus, a crack easily occurs when applying a thermal cycle on the emitter outer peripheral electrode 3 b.In the IGBTs 100 to 500 in Embodiments 1 to 5, the relationship between the distance d and the thickness t is set as expressed by d≤2 tsuch that the crack extends in the horizontal direction of the outer peripheral emitter electrode 3 b.< Application Example>In the examples described in Embodiments 1 to 5, a trench gate type IGBT is described; however, the configurations in Embodiments 1 to 5 may be adopted for a planar gate type IGBT or a MOS transistor, and may also be adopted for various diodes such as a PN junction diode. In particular, in a case of the planar gate type IGBT and the MOS transistor, the configuration in Embodiment 5 is particularly effective and the flatness of the metal layer 6 of the outer peripheral emitter electrode 3 bis significantly improved.In Embodiments 1 to 5 described above, a material of the semiconductor substrate is not particularly limited. The semiconductor substrate 1 may be made of silicon or SiC (silicon carbide), or may also be made of a wide band gap semiconductor other than silicon carbide such as gallium nitride (GaN), for example.In particular, SiC has a high dielectric breakdown strength of approximately ten times that of Si, and the thickness of the semiconductor layer can be reduced to approximately 1 / 10. Thus, a SiC semiconductor device can achieve a low ON voltage and can operate under high temperature, so that in the SiC semiconductor device, the size can be reduced and the efficiency can be increased compared with a Si device.

Claims

A semiconductor device in which a main current flows in a thickness direction of a semiconductor substrate (1), the semiconductor substrate comprising: an active region (AR) in which the main current flows; and a termination region (2) located on an outer side of the active region, the semiconductor device comprising: a first main electrode (3) disposed on the active region (AR); a second main electrode (19) disposed on an opposite side of the semiconductor substrate (1) from the first main electrode (3); a protective film (4) covering at least the termination region (2); and a non-electrolytic plating layer (8) disposed on the first main electrode (3) uncovered by the protective film (4), the first main electrode (3) includes a central electrode (3a) in a central part and an outer peripheral electrode (3b) disposed along the central electrode (3a) so as to be separated from the central electrode (3a), the protective film (4) is disposed so as to extend from the termination region (2) to an end edge portion of the outer peripheral electrode (3b), the central electrode (3a) and the outer peripheral electrode (3b) include: a first metal layer (6); and an aluminum-containing second metal layer (7) disposed on the first metal layer (6), and at least the outer peripheral electrode (3b) has a hole part (9, 91, 92) penetrating the second metal layer (7) to reach the first metal layer (6).The semiconductor device according to claim 1, wherein the hole part (9, 91) is a hole formed by pitting corrosion in a pre-processing before forming the non-electrolytic plating layer (8).The semiconductor device according to claim 2, wherein the second metal layer (7) is made of an aluminum-silicon alloy, and a silicon concentration of the second metal layer (7) of the outer peripheral electrode (3b) is higher than a silicon concentration of the second metal layer of the central electrode.The semiconductor device according to claim 1, wherein the hole part (92) is a selectively formed hole.The semiconductor device according to claim 2, wherein the central electrode (3a) has a hole part (9) of the central electrode (3a), and a thickness of the second metal layer (7) of the central electrode (3a) is set to be larger than a thickness of the second metal layer (7) of the outer peripheral electrode (3b) and large enough that the hole part (9) of the central electrode (3a) does not penetrate the second metal layer (7).The semiconductor device according to claim 1, wherein the active region (AR) does not have a unit cell as a minimum unit structure of the semiconductor device on a bottom surface of the outer peripheral electrode (3b).The semiconductor device according to claim 1, wherein a distance from the central electrode (3a) to the outer peripheral electrode (3b) is set to be smaller than a thickness of the non-electrolytic plating layer (8).The semiconductor device according to claim 2, wherein the thickness of the second metal layer (7) is set to be equal to or greater than 0.5 μm.The semiconductor device according to claim 4, wherein the thickness of the second metal layer (7) of the central electrode (3a) and the thickness of the second metal layer (7) of the outer peripheral electrode (3b) are set to be equal to or greater than 1.5 μm.The semiconductor device according to claim 5, wherein the thickness of the second metal layer (7) of the central electrode (3a) is set to be equal to or greater than 1.5 μm, and the thickness of the second metal layer (7) of the outer peripheral electrode (3b) is set to be equal to or greater than 0.5 μm.

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