Semiconductor component and method for manufacturing one

Abstract

Method for manufacturing a semiconductor component in which a semiconductor element which generates heat during operation is formed in an active region of a semiconductor substrate and in which a temperature-sensitive diode sensor is formed in a temperature-sensitive diode region of the semiconductor substrate which is configured to measure a temperature, wherein the method comprises the steps: Forming a polysilicon layer that forms the temperature-sensitive diode sensor in the temperature-sensitive diode area; Forming a mask comprising an element pattern with an element opening through which an area forming the semiconductor element in the active region is exposed, a diode pattern with a diode opening through which a section of the temperature-sensitive diode region is exposed, and a control pattern provided in the diode pattern with a size smaller than that of the diode opening; and Introducing contaminants through the mask into the semiconductor substrate and the polysilicon layer.

Description

Technical field

[0001] The present invention relates to a semiconductor component comprising a temperature-sensitive diode and a method for manufacturing the same. State of the art

[0002] A semiconductor component comprising a temperature-sensitive diode is disclosed, for example, in Japanese patent application JP 2017-103272A. The semiconductor component in Japanese patent application JP 2017-103272A comprises a temperature-sensitive diode consisting of a polysilicon diode on a semiconductor chip with an integrated power transistor. The forward voltage of the temperature-sensitive diode changes depending on the temperature of the semiconductor chip. It is therefore possible to detect the temperature of the semiconductor chip by monitoring the forward voltage. For example, anomalous heat generation can be detected using the temperature-sensitive diode. In response to the detection of anomalous heat generation, the power transistor can be switched off to prevent damage to the semiconductor component due to the anomalous heat generation. Summary of the invention: Technical problem

[0003] Temperature sensing using a temperature-sensitive diode depends on the forward characteristics of the diode. Therefore, it is necessary to integrate the diode in such a way that it exhibits the intended forward characteristics. If the diode does not have these characteristics, the semiconductor device is defective and cannot be sold. The integration accuracy of the temperature-sensitive diode thus impacts production yield.

[0004] A preferred embodiment of the present invention provides a method for manufacturing a semiconductor component with improved yield.

[0005] A preferred embodiment of the present invention provides a semiconductor component that has been demonstrably manufactured using a high-precision process. Solution to the problem

[0006] A preferred embodiment of the present invention provides a method for manufacturing a semiconductor device in which a semiconductor element that generates heat during operation is formed in an active region of a semiconductor substrate, and in which a temperature-sensitive diode sensor configured to detect a temperature is formed in a temperature-sensitive diode region of the semiconductor substrate. The method comprises the step of forming a polysilicon layer that forms the temperature-sensitive diode sensor in the temperature-sensitive diode region. The method also comprises the step of forming a mask. The mask comprises an element pattern with an element opening through which a region forming the semiconductor element is exposed in the active region.The mask comprises a diode pattern with a diode aperture through which a portion of the temperature-sensitive diode area is exposed. The mask includes a control pattern, provided within the diode pattern, with a size smaller than the diode aperture. The process includes the step of introducing impurities through the mask into the semiconductor substrate and the polysilicon layer.

[0007] A preferred embodiment of the present invention also provides a semiconductor component. The semiconductor component comprises a semiconductor substrate. The semiconductor component includes a semiconductor element that is inserted into the active region of the semiconductor substrate and generates heat during operation. The semiconductor component includes a temperature-sensitive diode sensor that is inserted into a temperature-sensitive diode region of the semiconductor substrate and is configured to detect a temperature. The temperature-sensitive diode sensor comprises a polysilicon layer formed in the temperature-sensitive diode region. A diode is formed in the temperature-sensitive diode region. The diode comprises an anode region and a cathode region. The anode region can be a region in which p-type impurities are introduced into the polysilicon layer.The cathode region can be an area where n-type impurities are introduced into the polysilicon layer. In the temperature-sensitive diode region, a control impurity pattern is formed in the polysilicon layer, exhibiting a linewidth smaller than that of the anode or cathode region.

[0008] The aforementioned and further objects, features and effects of the present invention will be made clear by the following description of the preferred embodiments with reference to the accompanying drawings. Brief description of the drawings [ Fig. 1] Fig. Figure 1 is a top view of a semiconductor component according to a preferred embodiment of the present invention. [ Fig. 2] Fig. Figure 2 is an enlarged top view to illustrate a configuration example of a cell area of ​​the semiconductor component. [ Fig. 3] Fig. Figure 3 is a cross-sectional view along line III-III in Fig. 2. [ Fig. 4] Fig. Figure 4 is an enlarged top view to illustrate a configuration example of a temperature-sensitive diode area. [ Fig. 5] Fig. Figure 5 is an electrical circuit diagram showing an electrical configuration of the temperature-sensitive diode area. [ Fig. 6] Fig. Figure 6 is a cross-sectional view showing a structural example along line VI-VI in Fig. 4 shows. [ Fig. 7] Fig. Figure 7 is an enlarged top view of a diode formation area. [ Fig. 8] Fig. Figure 8 is an enlarged cross-sectional view of the diode formation area. [ Fig. 9] Fig. Figure 9 shows a sample photoresist mask used for p-type impurity ion implantation. [ Fig. 10] Fig. Figure 10 shows a sample photoresist mask used for n-type impurity ion implantation. [ Fig. 11A] Fig. Figure 11A is a cross-sectional view of a main section illustrating a method for manufacturing a semiconductor component. [ Fig. 11B] Fig. Figure 11B is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 11C] Fig. Figure 11C is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 11D] Fig. Figure 11D is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 11E] Fig. Figure 11E is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 11F] Fig. Figure 11F is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 11G] Fig. Figure 11G is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 11H] Fig. Figure 11H is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 11I] Fig. Figure 11I is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 11J] Fig. Figure 11J is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 11K] Fig. Figure 11K is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 11L] Fig. Figure 11L is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 11M] Fig. Figure 11M is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 12A] Fig. Figure 12A is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 12B] Fig. Figure 12B is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 12C] Fig. Figure 12C is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 12D] Fig. 12D is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 12E] Fig. Figure 12E is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 12F] Fig. Figure 12F is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 12G] Fig. Figure 12G is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 12H] Fig. Figure 12H is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 12I] Fig. Figure 12I is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 12 years] Fig. Figure 12J is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 12K] Fig. Figure 12K is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 12L] Fig. Figure 12L is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 12M] Fig. Figure 12M is a cross-sectional view of a main section illustrating the process for manufacturing a semiconductor component. [ Fig. 13A] Fig. Figure 13A is a schematic cross-sectional view to illustrate a pn transition shift in a state in which a photoresist mask is formed for p-type impurity ion implantation. [ Fig. 13B] Fig. Figure 13B is a schematic cross-sectional view to illustrate a pn transition shift in a state in which a photoresist mask is formed for n-type impurity ion implantation. [ Fig. 14] Fig. Figure 14 is a top view illustrating a configuration of a semiconductor component according to a further preferred embodiment of the present invention. Description of the embodiments

[0009] Fig. Figure 1 is a top view of a semiconductor component 1 according to a preferred embodiment of the present invention. In this preferred embodiment, the semiconductor component 1 is an electrical component comprising an IGBT (insulated-gate bipolar transistor). An IGBT is an example of a power supply device. The semiconductor component 1 is an example of a single component with a power supply device.

[0010] The semiconductor component 1 comprises a chip-shaped semiconductor layer 2. The semiconductor layer 2 comprises, in particular, a first main surface 2a on one side and a second main surface 2b on the other side (see Fig. 3) The first main surface 2a and the second main surface 2b are both flat surfaces. Fig. Figure 1 shows a configuration of the semiconductor device 1 in a top view in a direction perpendicular to the first main surface 2a. In this preferred embodiment, the first main surface 2a and the second main surface 2b have a four-sided shape, in particular a rectangular shape. The semiconductor layer 2 has side surfaces 2c, 2d, 2e, 2f (four side surfaces in this preferred embodiment) which connect the first main surface 2a and the second main surface 2b.

[0011] For simplicity, the direction perpendicular to the first main surface 2a and the second main surface 2b, i.e., the direction parallel to a normal line to the first main surface 2a and the second main surface 2b, will be referred to in the following descriptions as the "normal direction Z" of semiconductor layer 2. Furthermore, the view in the normal direction Z will be referred to as a "top view". Also for simplicity, the direction perpendicular to the normal direction Z and parallel to one (2c) of the side surfaces will be referred to as a "first direction X", while the direction perpendicular to both the normal direction Z and the first direction X (the direction parallel to the side surface 2d adjacent to the side surface 2c) will be referred to as a "second direction Y".

[0012] Semiconductor layer 2 comprises an active region 3 and an outer region 4 (peripheral region). The active region 3 and the outer region 4 are defined in the first main surface 2a of semiconductor layer 2.

[0013] The active region 3 is defined in a central section of the semiconductor layer 2 such that, in a top view, it is spaced inwards from the side surfaces 2c to 2f of the semiconductor layer 2. The active region 3 can be defined in a four-sided shape (in particular a rectangular shape) whose four sides, in a top view, are parallel to the respective four side surfaces 2c to 2f of the semiconductor layer 2.

[0014] The outer area 4 is outside the active area 3. In a plan view, the outer area 4 extends section by section along the perimeter edge of the active area 3. In a plan view, the outer area 4 surrounds the active area 3. In particular, the outer area 4 is defined as an endless shape (four-sided annular shape) that surrounds the active area 3 in a plan view.

[0015] An emitter-terminal electrode 5 in the form of a film is arranged such that it covers almost the entire active region 3. Fig. For simplicity, the emitter-terminal electrode 5 is shown in Figure 1 as having the same shape and size as the active region 3. A gate-terminal electrode 6, in the form of a film, is arranged in the outer region 4. The gate-terminal electrode 6 and the emitter-terminal electrode 5 are spaced apart and electrically insulated from each other. A gate wire 7 is electrically connected to the gate-terminal electrode 6. The gate wire 7 has an annular section 7A, which is formed in the outer region 4 such that it surrounds the active region 3. The gate wire 7 also includes a gate finger 7B, which is formed such that it extends from the annular section 7A to and across the active region 3. The gate wire 7 is configured to transmit a gate signal applied to the gate-terminal electrode 6 to the active region 3.Several gate fingers 7B are configured such that they extend region by region in the first direction X and are spaced apart from each other in the second direction Y within the active region 3. The gate fingers 7B are arranged beneath the emitter terminal electrode 5 in such a way that they are insulated from the emitter terminal electrode 5. A cell region 8 is arranged between each pair of adjacent gate fingers 7B. Power transistor cells 11 are located in the cell region 8 (see figure). Fig. 2) arranged. Each of the power transistor cells 11 is an example of a semiconductor element or semiconductor component that generates heat during operation.

[0016] A temperature-sensitive diode section 9 is further provided in the outer area 4. A temperature-sensitive diode sensor 41, consisting of a polysilicon diode, is located in the temperature-sensitive diode section 9 (see Fig. 4) arranged. An anode terminal electrode 37 and a cathode terminal electrode 38 of the temperature-sensitive diode sensor 41 (see Fig. 4) are also provided in the outdoor area 4.

[0017] Fig. Figure 2 is an enlarged top view illustrating a configuration example of a section of the active region 3, showing the detailed structure of the front surface (first main surface 2a) of the semiconductor layer 2 in each cell region 8. More precisely, Fig. 2 an enlarged top view with description of the emitter terminal electrode 5 as well as an intermediate layer insulating film etc. which are arranged on the first main surface 2a of the semiconductor layer 2, which is omitted.

[0018] In each cell region 8, several power transistor cells 11 are arranged in the first direction X, in which the gate fingers 7B extend. In particular, several trench-gate structures 10 are formed in the semiconductor layer 2. Each of the trench-gate structures 10 extends, for example, linearly in the second direction Y. The several trench-gate structures 10 are arranged parallel and spaced apart from each other in the first direction X. The power transistor cells 11 are each defined, for example, by a section that encompasses each of the trench-gate structures 10 within each cell region 8.

[0019] The end sections of each trench-gate structure 10 are each connected to a pair of outer trench-gate structures 12 ( Fig. Figure 2 shows only the outer trench-gate structures 12 on one side. This implies that the multiple trench-gate structures 10 within each cell region 8 are interconnected via the outer trench-gate structures 12. The outer trench-gate structures 12 extend linearly in the first direction X. The outer trench-gate structures 12 are electrically connected to the gate fingers 7B via gate-extending electrode layers 13, which consist of polysilicon films.

[0020] Fig. Figure 3 is a cross-sectional view along line III-III in Fig. Figure 2 shows an example of a cross-sectional structure near the trench-gate structures 10. The semiconductor layer 2 has a single crystal structure, which is an n -The semiconductor substrate 15 comprises a -type semiconductor substrate. The semiconductor substrate 15 can be a silicon FZ substrate formed using an FZ (floating zone) process. The n-type impurity concentration of the semiconductor substrate 15 can be equal to or greater than 4.0 × 10⁻⁶ 13 cm -3 , but equal to or less than 2.0 × 10 14 cm -3 The thickness of the semiconductor substrate 15 can be equal to or greater than 50 µm, but equal to or less than 200 µm. An example of n-type impurities includes phosphorus-containing, arsenic-containing, etc. impurities.

[0021] A collector electrode 16 is formed on the second primary surface 2b of the semiconductor layer 2. The collector electrode 16 is electrically connected to the second primary surface 2b of the semiconductor layer 2. The collector electrode 16 is in ohmic contact with the second primary surface 2b of the semiconductor layer 2. The collector electrode 16 is configured to transmit a collector signal to the active region 3.

[0022] A p-type collector region 17 is formed over the surface section of the second main surface 2b of the semiconductor layer 2. The p-type impurity concentration of the collector region 17 can be equal to or greater than 1.0 × 10⁻⁶ 15 cm -3 , equal to or less than 1.0 × 10 18 cm -3The collector region 17 is in ohmic contact with the collector electrode 16. The collector region 17 can be formed over the entire surface area of ​​the second main surface 2b. An example of p-type impurities includes boron.

[0023] An n-type buffer layer 18 is deposited on the collector region 17. The buffer layer 18 can be formed over the entire surface area of ​​the second main surface 2b of the semiconductor layer 2. The n-type impurity concentration of the buffer layer 18 is greater than the n-type impurity concentration of the semiconductor substrate 15.

[0024] Each of the trench-gate structures 10 comprises a gate trench 20, a gate insulating layer 21, and a gate electrode layer 22. The gate trench 20 is formed in the first main surface 2a of the semiconductor layer 2. In particular, the gate trench 20 is trenched from the first main surface 2a to a predetermined depth within the semiconductor layer 2 in order to extend in the direction (normal direction Z) perpendicular to the first main surface 2a.

[0025] The width perpendicular to the longitudinal direction of the gate trench 20 can be equal to or greater than 0.5 µm, but equal to or less than 3.0 µm (e.g., approximately 1.2 µm). The width of the gate trench 20 is defined as the width of the gate trench 20 in the first direction X. The width of the gate trench 20 can be equal to or greater than 0.5 µm, but equal to or less than 1.0 µm; equal to or greater than 1.0 µm, but less than 1.5 µm; equal to or greater than 1.5 µm, but equal to or less than 2.0 µm; equal to or greater than 2.0 µm, but equal to or less than 2.5 µm; or equal to or greater than 2.5 µm, but equal to or less than 3.0 µm.

[0026] The gate insulating layer 21 is formed as a film along the inner wall of the gate trench 20. The gate insulating layer 21 delimits a niche within the gate trench 20. In this preferred embodiment, the gate insulating layer 21 comprises a silicon oxide film. Alternatively or additionally to the silicon oxide film, the gate insulating layer 21 can comprise a silicon nitride film.

[0027] The gate electrode layer 22 is embedded in the gate trench 20, with the gate insulating layer 21 positioned between them. Specifically, the gate electrode layer 22 is embedded in the niche defined by the gate insulating layer 21 within the gate trench 20. A gate signal is transmitted to the gate electrode layer 22. This means that the gate electrode layer 22 is electrically connected to the gate terminal electrode 6 (see Fig. 1).

[0028] FET (field-effect transistor) structures 30 are formed on both sides of the trench-gate structure 10. Each of the FET structures 30 comprises a p-type body region 31 formed over a surface section of the first main surface 2a of the semiconductor layer 2. The p-type impurity concentration of the body region 31 can be equal to or greater than 1.0 × 10⁻⁶ 16 cm -3 , but equal to or less than 1.0 × 10 18 cm -3 The body region 31 is formed in a top view to extend along the trench-gate structure 10. The body region 31 is exposed through the side surfaces of the gate trench 20. The lower section of the body region 31 is located at a depth between the first main surface 2a of the semiconductor layer 2 and the bottom wall of the gate trench 20 in the direction (normal direction Z) perpendicular to the first main surface 2a.

[0029] The FET structure 30 comprises an n + -Type emitter region 32, which is formed over a surface section of body region 31. The n-type impurity concentration of the emitter region 32 can be equal to or greater than 1.0 × 10 19 cm -3 , but equal to or less than 1.0 × 10 21 cm -3 be.

[0030] The emitter region 32 is formed in a top view to extend along the trench-gate structure 10. The emitter region 32 is exposed by the first main surface 2a of the semiconductor layer 2. The emitter region 32 is further exposed by the side surface of the gate trench 20. The lower section of the emitter region 32 is located at a depth between the upper end section of the gate electrode layer 22 and the lower section of the body region 31 in the direction (normal direction Z) perpendicular to the first main surface 2a.

[0031] The FET structure 30 comprises a p + The p-type contact region 33 extends from the first main surface 2a of the semiconductor layer 2 through the emitter region 32 to the body region 31. The p-type impurity concentration of the contact region 33 is greater than the p-type impurity concentration of the body region 31. The p-type impurity concentration of the contact region 33 can be equal to or greater than 1.0 × 10 19 cm -3 , but equal to or less than 1.0 × 10 20 cm -3 be.

[0032] The contact area 33 is positioned such that it confines the emitter area 32 together with the trench-gate structure 10. The contact area 33 is exposed through the first main surface 2a of the semiconductor layer 2.

[0033] The FET structure 30 is configured such that the gate electrode layer 22 faces the body region 31 and the emitter region 32, with the gate insulating layer 21 in between. An IGBT channel is formed in a region of the body region 31 that faces the gate trench 20. The channel is OFF / OFF controlled by a gate signal.

[0034] A main surface insulating layer 25 is formed on the first main surface 2a of the semiconductor layer 2. The main surface insulating layer 25 is formed as a film extending along the first main surface 2a. The main surface insulating layer 25 continues to the gate insulating layer 21. In this preferred embodiment, the main surface insulating layer 25 comprises a silicon oxide film. Alternatively or additionally to the silicon oxide film, the main surface insulating layer 25 can comprise a silicon nitride film.

[0035] An insulating interlayer 26 is formed on the main surface insulating layer 25. The insulating interlayer 26 is formed as a film along the first main surface 2a of the semiconductor layer 2. The insulating interlayer 26 can comprise silicon oxide or silicon nitride. The insulating interlayer 26 can comprise PSG (phosphosilicate glass) and / or BPSG (borophosphosilicate glass) as an example of a silicon oxide. The insulating interlayer 26 can be a film in which a PSG layer and a BPSG layer are layered in that order, starting from the side of the first main surface 2a.

[0036] An emitter contact opening 35 is arranged in the insulating intermediate layer 26. The emitter region 32 and the contact region 33 are exposed through the emitter contact opening 35 between the adjacent trench-gate structures 10.

[0037] An emitter-terminal electrode 5 is arranged on the insulating intermediate layer 26. The emitter-terminal electrode 5 can consist of at least one type of material from aluminum, copper, Al-Si-Cu (aluminum-silicon-copper) alloy, Al-Si (aluminum-silicon) alloy, and Al-Cu (aluminum-copper) alloy. The emitter-terminal electrode 5 can have a single-layer structure comprising one type of conductive material. The emitter-terminal electrode 5 can have a layered structure in which at least two types of conductive materials are layered in any order.

[0038] The emitter terminal electrode 5 penetrates the emitter contact opening 35 from above the insulating intermediate layer 26. This means that the emitter terminal electrode 5 is electrically connected to the emitter area 32 and the contact area 33 in the emitter contact opening 35.

[0039] The gate terminal electrode 6, the anode terminal electrode 37 and the cathode terminal electrode 38, shown in Fig. 1, are also formed on the insulating intermediate layer 26. These can be formed with the same conductive materials as the emitter terminal electrode 5.

[0040] Fig. Figure 4 is an enlarged top view to illustrate a configuration example of the temperature-sensitive diode area 9 and Fig. Figure 5 is an electrical circuit diagram showing an electrical configuration of the temperature-sensitive diode area 9. Fig. Figure 6 is a cross-sectional view showing a structural example along line VI-VI in Fig. 4 shows.

[0041] The temperature-sensitive diode array 9 comprises a temperature-sensitive diode sensor 41 and a protective device or element 42. The temperature-sensitive diode sensor 41 comprises a first series circuit 81 consisting of a series of several first diodes 43 connected in series in the forward direction. Each of the first diodes 43 is an example of a sensor diode. The several first diodes 43 are arranged to form a linear series. The protective element 42 comprises a second series circuit 82 consisting of a series of several second diodes 44 connected in series in the forward direction. Each of the second diodes 44 is an example of a protective diode. The several second diodes 44 are arranged to form a linear series. The series of first diodes 43 and the series of second diodes 44 are parallel to each other.The temperature-sensitive diode sensor 41 and the protection element 42 are connected in parallel in reverse. Specifically, the first series connection 81 of the several first diodes 43, which form the temperature-sensitive diode sensor 41, and the second series connection 82 of the several second diodes 44, which form the protection element 42, are connected in parallel with the first diodes 43 and the second diodes 44 in mutually reversed directions. The parallel connection thus configured is connected to the anode terminal electrode 37 (see ). Fig. 1) connected by a first connecting wire 45 and to the cathode terminal electrode 38 (see Fig. 1) connected by a second connecting wire 46.

[0042] The temperature-sensitive diode section 9 further comprises blind diodes 47, 48, which are electrically isolated from the temperature-sensitive diode sensor 41 and the protective element 42. In this preferred embodiment, a first blind diode 47 and a second blind diode 48 are provided. The first blind diode 47 is arranged in a linear series together with the first diodes 43, which form the temperature-sensitive diode sensor 41. The first blind diode 47 is located at one end of the series. The second blind diode 48 is arranged in a linear series together with the second diodes 44, which form the protective element 42. The second blind diode 48 is located at one end of the series. In this preferred embodiment, the first blind diode 47 and the second blind diode 48 are arranged adjacent to each other.

[0043] The dummy diodes 47, 48 are primarily designed to fill the empty space within the temperature-sensitive diode area 9. The dummy diodes 47, 48 are therefore intended to allow the precise formation of the first diodes 43 and the second diodes 44, which form the temperature-sensitive diode sensor 41 and the protective element 42, respectively.

[0044] As in Fig. As shown in Figure 6, the temperature-sensitive diode sensor 41 comprises a polysilicon layer 50 formed on the first main surface 2a of the semiconductor layer 2. The temperature-sensitive diode sensor 41 is formed by selectively introducing n-type and p-type impurities into the polysilicon layer 50.

[0045] In particular, the polysilicon layer 50 is formed on the main surface insulating layer 25. The polysilicon layer 50 is electrically insulated from the semiconductor layer 2 by the main surface insulating layer 25. The thickness of the polysilicon layer 50 can be equal to or greater than 0.2 µm, but equal to or less than 1.0 µm.

[0046] As in Fig. As shown in Figure 4, in this preferred embodiment, the polysilicon layer 50 has a longitudinal rectangular shape extending in the first direction X. A first circuit formation area 51 and a second circuit formation area 52 are defined in the polysilicon layer 50. The first circuit formation area 51 and the second circuit formation area 52 are defined such that they are spaced apart from each other in the lateral direction of the polysilicon layer 50 and extend parallel in the longitudinal direction of the polysilicon layer 50.

[0047] In this preferred embodiment, the first circuit formation area 51 comprises several (four in this preferred embodiment) first diode formation areas 53 and a first blind diode formation area 55. The first diodes 43 are formed in the first diode formation areas 53. The first blind diode 47 is formed in the first blind diode formation area 55. The several first diode formation areas 53 and the first blind diode formation area 55 are defined such that they are spaced apart from each other in the longitudinal direction (in the first direction X in this preferred embodiment) of the polysilicon layer 50 (equally spaced in this preferred embodiment).

[0048] In this preferred embodiment, each of the first diode formation areas 53 and of the first blind diode formation area 55 is defined in a top view in a four-sided shape.

[0049] In this preferred embodiment, the second circuit formation area 52 comprises several (four in this preferred embodiment) second diode formation areas 54 and a second blind diode formation area 56. The second diodes 44 are formed in the second diode formation areas 54. The second blind diode 48 is formed in the second blind diode formation area 56. The several second diode formation areas 54 and the second blind diode formation area 56 are defined such that they are spaced apart from one another in the longitudinal direction (the first direction X in this preferred embodiment) of the polysilicon layer 50.

[0050] In this preferred embodiment, each of the second diode formation areas 54 and of the second blind diode formation area 56 is defined in a top view in a four-sided shape.

[0051] Fig. Figure 7 is an enlarged top view of the first blind diode 47 and some of the first diodes 43 and Fig. Figure 8 shows an enlarged cross-sectional structure along the line VIII-VIII in Fig. 7. Each of the first diode formation regions 53 and the first blind diode formation region 55 is formed with a p-type first anode region 61 and an n-type first cathode region 63. The first anode region 61 is formed in a central section of each of the first diode formation regions 53 and the first blind diode formation region 55. In this preferred embodiment, the first anode region 61 is exposed by a first surface 50a and a second surface 50b of the polysilicon layer 50.

[0052] In this preferred embodiment, the first anode region 61 is formed in an approximately rectangular shape in a top view. The first anode region 61 can have a planar shape. The first anode region 61 can be formed in a polygonal shape, such as a triangular or hexagonal shape, a circular shape, or an elliptical shape in a top view.

[0053] The first cathode region 63 is formed along the circumferential edge of the first anode region 61. In this preferred embodiment, the first cathode region 63 is formed in a C-shape or a U-shape, which surrounds the first anode region 61 in a top view. The first cathode region 63 can be formed in a ring-shaped form, which surrounds the entire first anode region 61. The first cathode region 63 is electrically connected to the first anode region 61.

[0054] In this preferred embodiment, the first cathode region 63 is exposed by a first surface 50a and a second surface 50b of the polysilicon layer 50. The first cathode region 63 is connected to the first anode region 61 through the entire thickness direction of the polysilicon layer 50. A pn ​​junction 60 is formed at an interface between the first cathode region 63 and the first anode region 61. In this preferred embodiment, the pn junction 60 also has a C-shape or a U-shape in a top view because the first cathode region 63 is formed in a C-shape or a U-shape, such that it surrounds the first anode region 61. If the first cathode region 63 surrounds the entire first anode region 61 in an annular manner and is in contact with it, the pn junction 60 accordingly has an annular shape in a top view.

[0055] A first diode 43 is therefore formed in each of the first diode formation regions 53, with the first anode region 61 serving as the anode and the first cathode region 63 as a cathode. Furthermore, the first blind diode 47 is formed in the first blind diode formation region 55 to provide the first anode region 61 and the first cathode region 63. It should be noted that the first blind diode 47 has no electrical function, as mentioned above.

[0056] The structure of the second diode training area 54 and the second reactive diode training area 56 is essentially the same as the structure of the first diode training area 53 and the first reactive diode training area 55. It should be noted here that, as in Fig. As can be seen in Figure 4, the second diode formation region 54 has a structure resulting from a mirror inversion of each first diode formation region 53 at a central section of a rectangular region encompassing the multiple first diode formation regions 53 in the direction (first direction X) in which the multiple first diodes 43 are arranged. Similarly, the second blind diode formation region 56 has a structure resulting from a mirror inversion of the first blind diode formation region 55 at a central section of the first blind diode formation region 55 in the direction (first direction X) in which the multiple first diodes 43 are arranged.

[0057] In particular, each of the second diode formation areas 54 and the second blind diode formation area 56 is configured with a p-type second anode area 62 and an n-type second cathode area 64. The second anode area 62 is formed in a central section of each of the second diode formation areas 54 and the second blind diode formation area 56. In this preferred embodiment, the second anode area 62 is exposed by a first surface 50a and a second surface 50b of the polysilicon layer 50.

[0058] In this preferred embodiment, the second anode region 62 is formed in an approximately rectangular shape in a top view. The second anode region 62 can have a planar shape. The second anode region 62 can be formed in a polygonal shape, such as a triangular or hexagonal shape, a circular shape, or an elliptical shape in a top view.

[0059] The second cathode region 64 is formed along the circumferential edge of the second anode region 62. In this preferred embodiment, the second cathode region 64 is formed in a C-shape or a U-shape, which surrounds the second anode region 62 in a top view. The second cathode region 64 can be formed in a ring-shaped form, which surrounds the entire second anode region 62. The second cathode region 64 is electrically connected to the second anode region 62.

[0060] In this preferred embodiment, the second cathode region 64 is exposed through the first surface 50a and the second surface 50b of the polysilicon layer 50. The second cathode region 64 is connected to the second anode region 62 through the entire thickness direction of the polysilicon layer 50. A pn ​​junction 60 is formed between the second cathode region 64 and the second anode region 62. In this preferred embodiment, the pn junction 60 also has a C-shape or a U-shape in a top view because the second cathode region 64 is formed in a C-shape or a U-shape, such that it surrounds the second anode region 62. If the second cathode region 64 surrounds the entire second anode region 62 in an annular manner and is in contact with it, the pn junction 60 accordingly has an annular shape in a top view.

[0061] Each of the second diodes 44 is therefore formed in every second diode formation area 54, with the second anode area 62 serving as an anode and the second cathode area 64 serving as a cathode. Furthermore, the second blind diode 48 is formed in the second blind diode formation area 56 to provide a second anode area 62 and a second cathode area 64. It should be noted that the second blind diode 48 has no electrical function, as mentioned above.

[0062] Referring to the Fig. 6 and Fig. 8, the above-mentioned insulating intermediate layer 26 covers the polysilicon layer 50. A first anode opening 65 and a first cathode opening 67 are formed in a section of the insulating intermediate layer 26, which covers each of the first diode formation areas 53.

[0063] The first anode region 61 is exposed through the first anode opening 65. The first anode opening 65 is formed in such a way that it penetrates the insulating intermediate layer 26. As shown in the Fig. 4 and Fig. As shown in Figure 7, in this preferred embodiment the first anode opening 65 is formed in an approximately rectangular shape in a top view. Of course, the first anode opening 65 can have a planar shape, not only a rectangular shape, but also a polygonal, circular, or elliptical shape. The first anode opening 65 can also extend along the circumferential edge of the first anode region 61 in a top view. In this case, the first anode opening 65 can have an annular shape, such as a circular, elliptical, or polygonal shape, in a top view. Furthermore, several first anode openings 65 can be formed such that they are spaced apart from one another in each of the first diode formation regions 53.

[0064] The first cathode region 63 of each first diode formation region 53 is exposed through the first cathode opening 67. The first cathode opening 67 is formed in such a way that it penetrates the insulating intermediate layer 26. As shown in the Fig. 4 and Fig. As shown in Figure 7, the first cathode opening 67 extends in a plan view along the circumferential edge of the first anode region 61. The first cathode opening 67 is formed in a C-shape or a U-shape in a plan view. The first cathode opening 67 can have a planar shape without being restricted to a C-shape or a U-shape. The first cathode opening 67 can be formed in a polygonal shape, such as a triangular, four-sided, or hexagonal shape, or in an elliptical shape in a plan view. Several first cathode openings 67 can also be formed in such a way that they are spaced apart from each other in each first diode formation region 53.

[0065] A second anode opening 66 and a second cathode opening 68 are formed in a section of the insulating intermediate layer 26, around which every second diode formation area 54 is covered.

[0066] The second anode region 62 is exposed through the second anode opening 66. The second anode opening 66 is shaped such that it penetrates the insulating intermediate layer 26. In this preferred embodiment, the second anode opening 66 is approximately rectangular in a top view. Of course, the second anode opening 66 can also have a planar shape, not only rectangular, but also polygonal, circular, or elliptical. The second anode opening 66 can also extend partially along the circumferential edge of the second anode region 62 in a top view. In this case, the second anode opening 66 can have an annular shape, such as circular, elliptical, or polygonal, in a top view.Furthermore, several second anode openings 66 can be designed in such a way that they are spaced apart from each other in each of the second diode formation areas 54.

[0067] The second cathode region 64 of every second diode formation region 54 is exposed by the second cathode opening 68. The second cathode opening 68 is configured to penetrate the insulating intermediate layer 26. In a top view, the second cathode opening 68 extends partially along the circumferential edge of the second anode region 62. In a top view, the second cathode opening 68 is configured in a C-shape or a U-shape. The second cathode opening 68 can have a planar shape without being restricted to a C-shape or a U-shape. In a top view, the second cathode opening 68 can be configured in a polygonal shape, such as a triangular, four-sided, or hexagonal shape, or in an elliptical shape. Multiple second cathode openings 68 can also be configured such that they are spaced apart from one another in every second diode formation region 54.

[0068] A first diode wire 71 is formed in a section of the insulating intermediate layer 26, which covers the first circuit formation area 51 (see Fig. 4) The first diode wire 71 connects the several first diodes 43 in series in the forward direction between a first terminal wire 45 and a second terminal wire 46. The first diode wire 71 has a lower end section that is connected to the first terminal wire 45 and the other end section that is connected to the second terminal wire 46.

[0069] The first diode wire 71 can comprise at least one type of material of aluminium, copper, Al-Si-Cu (aluminium-silicon-copper) alloy, Al-Si (aluminium-silicon) alloy and Al-Cu (aluminium-copper) alloy.

[0070] In particular, the first diode wire 71 comprises several first anode electrodes 73, several first cathode electrodes 75 and several first connecting electrodes 77.

[0071] Each of the first anode electrodes 73 is formed on a section of the insulating intermediate layer 26, which covers each first diode formation area 53. The first anode electrode 73 is formed in an approximately rectangular shape in a top view. The first anode electrode 73 has a planar shape. The first anode electrode 73 can be formed in a polygonal shape, such as a triangular, four-sided, or hexagonal shape, a circular shape, or an elliptical shape in a top view. The first anode electrode 73 penetrates the first anode opening 65 from above the insulating intermediate layer 26. The first anode electrode 73 is electrically connected to the first anode area 61 within the first anode opening 65.

[0072] Each of the first cathode electrodes 75 is formed in a section of the insulating intermediate layer 26, which covers each of the first diode formation areas 53. In a top view, the first cathode electrode 75 extends partially along the first anode electrode 73. In this preferred embodiment, the first cathode electrode 75 is formed in a C-shape or a U-shape in a top view. The first cathode electrode 75 can have a planar shape without being limited to a C-shape or a U-shape. The first cathode electrode 75 can be formed in a polygonal shape, such as a triangular, four-sided, hexagonal, circular, or elliptical shape, in a top view. The first cathode electrode 75 penetrates the first cathode opening 67 from above the insulating intermediate layer 26.The first cathode electrode 75 is electrically connected to the first cathode area 63 within the first cathode opening 67.

[0073] Each of the first connecting electrodes 77 is formed on a section of the insulating intermediate layer 26, which covers an area between a pair of mutually adjacent first diode formation areas 53. The first connecting electrode 77 extends from the first cathode electrode 75 of one of the first diode formation areas 53 and is connected to the first anode electrode 73 of the other first diode formation area 53. In this preferred embodiment, the first connecting electrode 77 is configured such that it extends in a top view in the longitudinal direction (the first direction X in this preferred embodiment) of the polysilicon layer 50. The first connecting electrode 77 can be guided linearly in an area between a pair of mutually adjacent first diode formation areas 53.

[0074] One of the first connecting electrodes 77, which is positioned in one end section side in the longitudinal direction of the polysilicon layer 50, is connected to the first connecting wire 45. One of the first connecting electrodes 77, which is positioned on the other end section side in the longitudinal direction of the polysilicon layer 50, is connected to the second connecting wire 46.

[0075] This requires that the first series circuit 81 comprises several (four in this preferred embodiment) first diodes 43 which are connected in series in the forward direction to be formed in a region between the first connecting wire 45 and the second connecting wire 46.

[0076] One of the first anode electrodes 73 and one of the first cathode electrodes 75 are also formed in the first blind diode formation area 55. However, these are not connected to other diodes or to the connecting wires 45, 46.

[0077] A second diode wire 72 is formed on a section of the insulating intermediate layer 26, which covers the second circuit formation area 52. The second diode wire 72 connects several second diodes 44 in series in the forward direction between a first terminal wire 45 and a second terminal wire 46. The second diode wire 72 has one end section connected to the first terminal wire 45 and another end section connected to the second terminal wire 46.

[0078] The second diode wire 72 can comprise at least one type of material of aluminium, copper, Al-Si-Cu (aluminium-silicon-copper) alloy, Al-Si (aluminium-silicon) alloy and Al-Cu (aluminium-copper) alloy.

[0079] In particular, the second diode wire 72 comprises several second anode electrodes 74, several second cathode electrodes 76 and several second connecting electrodes 78.

[0080] Each of the second anode electrodes 74 is formed on a section of the insulating intermediate layer 26, which covers every second diode formation area 54. The second anode electrode 74 is formed in an approximately rectangular shape in a top view. The second anode electrode 74 has a planar shape. The second anode electrode 74 can be formed in a polygonal shape, such as a triangular shape, a four-sided shape, a hexagonal shape, a circular shape, or an elliptical shape in a top view. The second anode electrode 74 penetrates the second anode opening 66 from above the insulating intermediate layer 26. The second anode electrode 74 is electrically connected to the second anode area 62 within the second anode opening 66.

[0081] Each of the second anode electrodes 76 is formed on a section of the insulating intermediate layer 26, which covers every second diode formation area 54. The second cathode electrode 76 extends, in a top view, partially along the second anode electrode 74. In this preferred embodiment, the second cathode electrode 76 is formed in a C-shape or a U-shape in a top view. The second cathode electrode 76 can have a planar shape without being limited to a C-shape or a U-shape. The second cathode electrode 76 can be formed in a polygonal shape, such as a triangular shape, a four-sided shape, a hexagonal shape, a circular shape, or an elliptical shape, in a top view. The second cathode electrode 76 penetrates the second cathode opening 68 from above the insulating intermediate layer 26.The second cathode electrode 76 is electrically connected to the second cathode area 64 within the second cathode opening 68.

[0082] Each of the second connecting electrodes 78 is formed on a section of the insulating intermediate layer 26, which covers an area between mutually adjacent second diode formation areas 54. The second connecting electrode 78 extends from the second cathode electrode 76 of one of the second diode formation areas 54 and is connected to the second anode electrode 74 of the other second diode formation area 54. In this preferred embodiment, the second connecting electrode 78 is configured such that, in a top view, it extends in a region along the longitudinal direction (the first direction X in this preferred embodiment) of the polysilicon layer 50. The second connecting electrode 78 can be guided linearly in a region between a pair of mutually adjacent second diode formation areas 54.

[0083] One of the second connecting electrodes 78, which is positioned on one end section side in the longitudinal direction of the polysilicon layer 50, is connected to the second connecting wire 46. One of the second connecting electrodes 78, which is positioned on the other end section side in the longitudinal direction of the polysilicon layer 50, is connected to the first connecting wire 45.

[0084] This requires that the second series circuit 82 comprises several (four in this preferred embodiment) second diodes 44 which are connected in series in the forward direction to be formed in a region between the first connecting wire 45 and the second connecting wire 46.

[0085] One of the second anode electrodes 74 and one of the second cathode electrodes 76 are also formed in the second blind diode formation area 56. However, these are not connected to other diodes or to connecting wires 45, 46.

[0086] How best to in the Fig. 7 and Fig. As shown in Figure 8, the pn junction 60 is formed between the approximately rectangular first anode region 61 and the first cathode region 63. This pn junction is shaped in a C-shape or a U-shape, surrounding the first anode region 61. The forward voltage of each first diode 43 depends on the junction length of the pn junction 60. Consequently, the forward voltage of the temperature-sensitive diode sensor 41 will deviate from an intended value if the junction length (formerly transition length) of the pn junction 60 of each first diode 43 is greater or less than the intended value. This can result in inaccurate temperature measurements.

[0087] One of the factors that causes the transition length of the pn junction 60 to deviate from a planned value is the accuracy of a mask used during ion implantation of p-type impurities into the polysilicon layer 50. In this case, the mask is typically a photoresist mask. The photoresist mask is formed by exposing a photoresist layer with an exposure machine and developing the exposed photoresist. A poor setting (e.g., an imprecise setting) of the exposure machine can cause a reduction in the accuracy of the photoresist mask. Even if the exposure machine is carefully set, the set state can vary, resulting in poor settings during mass production of semiconductor devices.

[0088] Fig. Figure 9 shows a model of a photoresist mask 90, which is used for p-type impurity ion implantation. The photoresist mask 90 has an opening in an area where p-type impurity ions are to be implanted. In particular, the photoresist mask 90 comprises a device pattern or element pattern 92, which has several device openings or element openings 91 that correspond to the p + -Type contact areas 33 in cell area 8 belong to the photoresist mask 90, which also includes a diode pattern 94 having several diode openings 93 belonging to the anode areas 61, 62 in the temperature-sensitive diode area 9. The p + -Type contact areas 33 and the anode areas 61, 62 are therefore formed simultaneously by a step which includes selective implantation of p-type impurities using the photoresist mask 90 as a mask.

[0089] Diode pattern 94 includes a sensor pattern 94S, which belongs to the first diodes 43 (sensor diodes). Diode pattern 94 also includes a protective pattern 94P, which belongs to the second diodes 44 (protective diodes). Diode pattern 94 further includes a dummy pattern 94D, which belongs to the dummy diodes 47 and 48.

[0090] The photoresist mask 90 has a pattern with a line width of approximately 1 µm in an area belonging to cell area 8. Each element opening 91, for example, has a zone-like shape belonging to each contact area 33. The line width of each element opening 91 corresponds to the line width of each contact area 33, which is, for example, approximately 1 µm.

[0091] On the other hand, the photoresist mask 90 has a pattern with a line width of approximately 100 µm to 200 µm in an area belonging to the temperature-sensitive diode region 9. For example, each of the diode openings 93 has a rectangular shape with a size corresponding to that of the anode regions 61, 62, where the long sides have a length of 150 µm to 200 µm (e.g., approximately 170 µm), while the short sides have a length of 120 µm to 170 µm (e.g., approximately 140 µm). Furthermore, the space between a pair of adjacent diode openings 93 in the first direction X is 50 µm to 100 µm (e.g., 70 µm). Furthermore, the space between a pair of diode openings 93, which are adjacent to each other in the second direction Y, is 50 µm to 110 µm (e.g. 85 µm).

[0092] There is therefore a 100- to 200-fold difference between the line width of the pattern belonging to cell region 8 and the line width of the pattern belonging to the temperature-sensitive diode region 9. It is therefore necessary to change magnification settings to detect the patterns in the respective regions using a scanning electron microscope (SEM).

[0093] Therefore, in this preferred embodiment, the photoresist mask 90 has a control pattern 95 within at least one of the several diode openings 93.

[0094] The control pattern 95 can be arranged within one of the diode openings 93, which belong to at least one of the first diodes 43. The control pattern 95 can be arranged within one of the diode openings 93, which belong to at least one of the second diodes 44. As in Fig. As shown in Figure 9, the control pattern 95 can be arranged within the diode opening 93 belonging to the first dummy diode 47. The control pattern 95 can be arranged within the diode opening 93 belonging to the second dummy diode 48. Several control patterns 95 can be formed within one of the diode openings 93 or can each be arranged in one of the several diode openings 93.

[0095] The control pattern 95 is preferably arranged at a position that is withdrawn inwards from the opening edge of the diode opening 93, so that the control pattern 95 does not affect the pn junction.

[0096] Control pattern 95 has an accuracy, in particular a line width, that is discernible at the same magnification as that of a scanning electron microscope used to detect the pattern in cell region 8. Specifically, control pattern 95 has a line width equal to that of the pattern in cell region 8, i.e., a line width of approximately 1 µm to 5 µm. In the example of Fig. The control pattern 95 comprises several linear sections 95L, which are designed to have the same width (e.g., approximately 1.2 µm) and a predetermined length (e.g., approximately 20 µm), and which are arranged parallel with the space between them (e.g., approximately 3 µm). Fig. Figure 9 shows an example in which the straight linear segments 95L extend in the second direction Y. The direction in which the straight linear segments 95L extend can be set arbitrarily within a surface that encompasses the first direction X and the second direction Y. For example, the linear segments 95L can extend in the first direction X.

[0097] The control pattern 95 can have any shape, not only a straight linear shape, but also a polygonal shape, a curved shape, a spiral shape, a character shape, etc. Several control patterns 95, each having different line widths, can also be formed within one of the diode openings 93 or can each be formed in the several diode openings 93.

[0098] Line width refers to the width of the linear segments of a photoresist pattern in the direction perpendicular to the direction in which the linear segments extend. If multiple parallel linear segments are formed, any of the widths of the linear photoresist segments and the space between adjacent linear segments can be a line width. That is, if a line-and-space mask is used as a control pattern, either the width of the line segments or the width of the space segments can be used as the line width.

[0099] Since the photoresist used to form the control pattern 95 blocks p-type impurities, a control impurity pattern 97, which has a shape following that of the control pattern 95, is formed in the polysilicon layer 50 below the control pattern 95, as shown in the Fig. 7 and Fig. 8. Control pattern 97 comprises a p-type impurity-non-implanted region in which no p-type impurity ions are implanted by the photoresist forming control pattern 95, and a p-type impurity-implanted region in which p-type impurity ions are implanted by the photoresist of control pattern 95. The p-type impurity-non-implanted region can disappear by a thermal spreading process after ion implantation (see Fig. 11K and Fig. 12K), or may remain as a trace even after the thermal spreading process to form the control contaminant pattern 97.

[0100] In an area belonging to element pattern 92, p + -Type contact areas 33 (see Fig. 3) formed at positions of the element openings 91. The contact areas 33 serve as an example of an element contamination pattern or a device contamination pattern.

[0101] Fig. Figure 10 shows a model of a photoresist mask 100 used for n-type impurity ion implantation. The photoresist mask 100 has an opening in a region where n-type impurity ions are implanted. In particular, the photoresist mask 100 comprises a device pattern or element pattern 102, which includes several device openings or element openings 101, which correspond to the n + -Type emitter areas 32 in cell area 8 belong to the photoresist mask 100, which also includes a diode pattern 104, which has several diode openings 103 belonging to the cathode areas 63, 64 in the temperature-sensitive diode area 9. The n +-Type emitter regions 32 and the cathode regions 63, 64 are therefore formed simultaneously by a step which includes selective implantation of n-type impurities using a photoresist mask 100 as a mask.

[0102] Diode pattern 104 includes a sensor pattern 104S, which belongs to the first diodes 43 (sensor diodes). Diode pattern 104 also includes a protective pattern 104P, which belongs to the second diodes 44 (protective diodes). Diode pattern 104 further includes a dummy pattern 104D, which belongs to the dummy diodes 47 and 48.

[0103] The photoresist mask 100 has a pattern with a line width of approximately 1 µm in an area belonging to cell region 8. Each element aperture 101, for example, has a zone-like shape belonging to emitter region 32. The line width of each element aperture 101 corresponds to the line width of each emitter region 32, which is, for example, approximately 1 µm.

[0104] On the other hand, the photoresist mask 100 has a pattern with a line width of approximately 100 µm to 200 µm in an area belonging to the temperature-sensitive diode region 9. For example, the diode openings 103 have a size and shape corresponding to that of the cathode regions 63, 64. That is, in this preferred embodiment, each of the diode openings 103 is in a zoned shape, having a C- or U-shaped profile. The zoned diode opening 103 has a width of 20 µm to 30 µm (e.g., 25 µm). Furthermore, the space between a pair of diode openings 103 that are adjacent to each other in the first direction X is 30 µm to 100 µm (e.g., 50 µm). Furthermore, the space between a pair of diode openings 93 that are adjacent to each other is in the second direction Y 25 µm to 50 µm (e.g. 35 µm).

[0105] There is therefore a 25- to 100-fold difference between the line width of the pattern belonging to cell region 8 and the line width of the pattern belonging to the temperature-sensitive diode region 9. It is therefore necessary to change the magnification settings to detect the patterns in the respective regions using a scanning electron microscope.

[0106] Therefore, in this preferred embodiment, the photoresist mask 100 has a control pattern 105 in an area surrounded by at least one of the several diode openings 103 (on three sides in this preferred embodiment). In other words, a control pattern 105 is provided within an area belonging to at least one of the several anode areas 61, 62.

[0107] The control pattern 105 can be formed within a region belonging to the first anode region 61 of at least one of the first diodes 43. The control pattern 105 can be formed within a region belonging to the second anode region 62 of at least one of the second diodes 44. As in Fig. As shown in Figure 10, the control pattern 105 can be formed within a region belonging to the first anode region 61 of the first dummy diode 47. The control pattern 105 can be formed within a region belonging to the second anode region 62 of the second dummy diode 48. Several control patterns 105 can be formed within a region belonging to one of the anode regions 61, 62, or can be formed within regions belonging to several anode regions 61, 62.

[0108] In this preferred embodiment, the control pattern 105 is formed outside the diode opening 103 and arranged at a position away from the opening edge of the diode opening 103, so that the control pattern 105 does not affect the pn junction. In particular, in the example of Fig. 10, the control pattern 105 is formed at a position that is withdrawn inwards from the outer edge of a region belonging to the anode regions 61, 62.

[0109] Control pattern 105 has an accuracy or line width that is discernible at the same magnification as that of a scanning electron microscope used to detect the pattern in cell region 8. Specifically, control pattern 105 has a line width equal to that of the pattern in cell region 8, i.e., a line width of approximately 1 µm to 5 µm. In the example of Fig. 10 The control pattern 105 comprises several linear opening sections 105L, which are designed to have the same width (e.g., approximately 1.2 µm) and a predetermined length (e.g., approximately 20 µm) and are arranged parallel in the space between them (e.g., approximately 3 µm). While Fig. As shown in Figure 10, where the straight linear opening sections 105L extend in the second direction Y, the direction in which the straight linear opening section 105L extends can be arbitrarily long within a plane that includes the first direction X and the second direction Y. For example, the linear opening sections 105L can extend in the first direction X.

[0110] The control pattern 105 can assume any shape, not only a straight linear shape, but also a polygonal shape, a curved shape, a spiral shape, a character-shaped shape (formerly character shape), etc. Several control patterns 105, each with different line widths, can also be formed within an area belonging to one of the anode areas 61, 62, or can be formed within areas belonging to the several anode areas 61, 62.

[0111] Since the linear opening sections 105L of the control pattern 105 allow n-type impurity ions to pass through, a control impurity pattern 107, which has a shape following that of the control pattern 105, is formed in the polysilicon layer 50 below the control pattern 105, as shown in the Fig. 7 and Fig. 8. The control impurity pattern 107 comprises an n-type impurity-implanted region, in which n-type impurity ions are implanted through the linear opening sections 105L of the control pattern 105, and an n-type impurity-not-implanted region, in which no n-type impurity ions are implanted through the photoresist between the opening sections. The n-type impurity-not-implanted region can disappear through thermal propagation processes after ion implantation ( Fig. 11K and Fig. 12K) or may remain as a trace, even after a thermal spreading process, to form the control contaminant pattern 107.

[0112] The control patterns 95, 105, which are provided in the respective photoresist masks 90, 100, may be formed in an overlapping position, but are preferably formed in positions that are separated from each other, with the control impurity patterns 97, 107 being individually confirmed if necessary.

[0113] In an area belonging to element pattern 102, n + -Type emitter regions 32 are formed at positions of the element openings 101. The emitter regions 32 serve as an example of an element contamination pattern or a device opening pattern.

[0114] The Fig. Figures 11A to 11M and 12A to 12M are cross-sectional views of a main section illustrating a method for manufacturing a semiconductor device. Fig. Figures 11A to 11M show a cross-sectional structure of a temperature-sensitive diode region 9 in several manufacturing steps and the Fig. Figures 12A to 12M show a cross-sectional structure of cell region 8, which belongs to the respective steps. It should be noted that the Fig. Figures 11A to 11M and 12A to 12M are not necessarily drawn to the same scale.

[0115] As in the Fig. 11A and Fig. As shown in Figure 12A, a p-type body region 31 is formed over a surface section of one side of a first main surface 2a of a semiconductor layer 2. In particular, the p-type body region 31 is formed by selective implantation of p-type impurity ions into the semiconductor layer 2 and subsequent thermal processing.

[0116] Next, as in the Fig. 11B and Fig. Figure 12B shows a hard mask 110, which has an opening belonging to the gate trench 20, formed on the first main surface 2a of the semiconductor layer 2. The hard mask 110 is formed by, for example, using a CVD (chemical vapor deposition) process and consists of a silicon oxide film.

[0117] Next, as in the Fig. 11C and Fig. Figure 12C shows that dry etching through the hard mask 110 is performed to open the gate trench 20. The hard mask 110 is then removed. The gate trench 20 can have an opening width of, for example, 1 µm to 2 µm (especially 1.2 µm).

[0118] Next, as in the Fig. 11D and Fig. Figure 12D shows the front surface of semiconductor layer 2 being thermally oxidized to form a gate insulating layer 21. The gate insulating layer 21 covers the first main surface 2a of semiconductor layer 2 and the inner wall surface of trench 20. The gate insulating layer 21 formed outside of trench 20, i.e., on the first main surface 2a, forms a main surface insulating layer 25.

[0119] Next, as in the Fig. 11E and Fig. Figure 12E shows a polysilicon film 85 being deposited onto the semiconductor layer 2 using a CVD process with the addition of n-type impurities such as phosphorus-like impurities. Simultaneously, the polysilicon, endowed with electrical conductivity by the n-type impurities, is embedded in the gate trench 20. The polysilicon film 85 on the first main surface 2a of the semiconductor layer 2 can have a thickness of, for example, 0.5 µm to 1 µm (particularly 0.6 µm). The formation of the polysilicon film 85 with a thickness half or greater than half the aperture width of the gate trench 20 allows the polysilicon to be embedded in the gate trench 20.

[0120] Next, as in the Fig. 11F and Fig. As shown in Figure 12F, a mask 111 (e.g., a photoresist mask) is formed, which covers the polysilicon film 85 of the temperature-sensitive diode region 9. The polysilicon film 85 is then etched back through this mask to remove unnecessary sections. This leaves a gate electrode layer 22 consisting of polysilicon within the gate trench 20. A section of the polysilicon film 85 of the electrode layer 13 leading to a gate (see Figure 12F) is then removed. Fig. 2) is also left on the main surface insulating layer 25 outside the gate trench 20. Furthermore, in the temperature-sensitive diode region 9, the polysilicon film 85 is left on the main surface insulating layer 25 to form a polysilicon layer 50, while the polysilicon film 85 is removed in the other regions.

[0121] Next, as in the Fig. 11G and Fig. Figure 12G shows a protective film 86 formed over the entire surface. The protective film 86 can be a silicon oxide film formed using a CVD process. The protective film 86 protects the front surface of the underlying layer during the implantation of contaminants as described below.

[0122] Next, as in the Fig. 11H and Fig. Figure 12H shows a photoresist mask 90 for p-type impurity ion implantation. The photoresist mask 90 has a shape described with respect to Fig. 9. This means that the photoresist mask 90 comprises several element openings 91 which are connected to p +-Type contact areas 33 in the cell area 8 and includes several diode openings 93 belonging to the anode areas 61, 62 in the temperature-sensitive diode areas 9. A control pattern 95 is then formed within a diode opening 93 belonging to each of the anode areas 61, 62 of one or both of the dummy diodes 47, 48, for example.

[0123] The formation of the photoresist mask 90 includes the steps of forming a photoresist layer, exposing the photoresist layer with an exposure machine, and developing the exposed photoresist layer.

[0124] The photoresist mask 90 is inspected using a semi-finished product in which the photoresist mask 90 is formed. Specifically, a scanning electron microscope is used to identify the cell region 8 and the temperature-sensitive diode region 9. This allows verification that the dimensions and arrangement of a mask pattern (element pattern 92) formed in the cell region 8 are within a predetermined tolerance range, and that the dimensions and line width of a mask pattern (diode pattern 94) formed in the temperature-sensitive diode region 9 are also within a predetermined tolerance range. If the dimensions or arrangement of the mask pattern in either of these regions are not within the prescribed tolerance range, the subsequent steps are omitted and the semi-finished product is rejected.

[0125] Cell region 8 and temperature-sensitive diode region 9 are observed using scanning electron microscopes with the same magnification. In this case, while observing temperature-sensitive diode region 9, control pattern 95 is observed with the scanning electron microscope, and its dimensions and arrangement are verified. A similar control pattern can be provided in cell region 8, and while inspecting cell region 8, the control pattern can also be examined with the scanning electron microscope.

[0126] After confirmation that the photoresist mask 90 is formed with adequate accuracy in both the cell area 8 and the temperature-sensitive diode area 9, the photoresist mask 90, as described in the Fig. 11I and Fig. Figure 12I shows the implantation of p-type impurity ions, such as boron. The photoresist mask 90 is then peeled off. The p-type impurity ion implantation can be a single-stage or multi-stage implantation.

[0127] Next, as in the Fig. 11 years and Fig. As shown in Figure 12J, a photoresist mask 100 for n-type impurity ion implantation was formed. The photoresist mask 100 has a shape described with respect to Fig. 10. This means that the photoresist mask has 100 element openings 101 belonging to n-type emitter regions 32 in cell region 8 and diode openings 103 belonging to cathode regions in temperature-sensitive diode region 9. A control pattern 105 is then provided at a position belonging to each of the anode regions 61, 62 of the dummy diodes 47, 48, e.g.

[0128] The formation of the photoresist mask 100 includes the steps of forming a photoresist layer, exposing the photoresist layer with an exposure machine and developing the exposed photoresist layer.

[0129] The photoresist mask 100 is inspected using a semi-finished product in which the photoresist mask 100 is formed. Specifically, a scanning electron microscope is used to examine cell region 8 and the temperature-sensitive diode region 9. This allows confirmation that the dimensions and arrangement of a mask pattern (element pattern 102) formed in cell region 8 are within a predetermined tolerance range, and that the dimensions and line width of a mask pattern (diode pattern 104) formed in the temperature-sensitive diode region 9 are also within a predetermined tolerance range. If the dimensions or arrangement of the mask pattern in either region are not within the predetermined tolerance range, the subsequent steps are omitted and the semi-finished product is rejected.

[0130] Cell region 8 and temperature-sensitive diode region 9 are observed using scanning electron microscopes with the same magnification. During the observation of temperature-sensitive diode region 9, control pattern 105 is observed with the scanning electron microscope, and its dimensions and arrangement are verified. A similar control pattern can be provided in cell region 8, and during the verification of cell region 8, the control pattern can also be observed with the scanning electron microscope.

[0131] After confirmation that the photoresist mask 100 is formed with adequate accuracy in both the cell area 8 and the temperature-sensitive diode area 9, the photoresist mask 100, as described in the Fig. 11 years and Fig. As shown in Figure 12J, n-type impurity ions, such as phosphorus-like, arsenic-like, etc., are implanted. The photoresist mask 100 is then peeled off. The n-type impurity ion implantation can be a single-stage or multi-stage implantation.

[0132] Next, as in the Fig. 11K and Fig. 12K shows a thermal processing “drive-in” (driving in) carried out, whereby impurity ions implanted in semiconductor layer 2 and impurity ions implanted in polysilicon layer 50 are spread. This results in p + -Type contact areas 33 and n +p-type emitter regions 32 are formed within the body region 31 of the semiconductor layer 2. Furthermore, p-type anode regions 61, 62 and n-type cathode regions 63, 64 are formed within the polysilicon layer 50, between which a pn junction 60 is formed.

[0133] Following this, as in the Fig. 11L and Fig. Figure 12L shows a photoresist mask 112 formed for separating the polysilicon layer 50. Etching through the photoresist mask 112 is carried out to separate the polysilicon layer 50 into two (it was called "into") areas of individual diodes 43, 44, 47, 48. The photoresist mask 112 is then peeled off.

[0134] Following this, as in the Fig. 11M and Fig. 12M shows an insulating intermediate layer 26 being formed, and an emitter contact opening 35, anode openings 65, 66, cathode openings 67, 68 etc. are formed in such a way that they penetrate the insulating intermediate layer 26 and the protective film 86.

[0135] Following this, as in the Fig. 3 and Fig. Figure 8 shows an electrode film 87 formed on the insulating intermediate layer 26 using, for example, a sputtering process. The electrode film 87 comprises, for example, a barrier film 88 and a main electrode film 89 layered on the barrier film 88. The electrode film 87 is etched to form a gate terminal electrode 6, an emitter terminal electrode 5, and diode wires 71, 72 (anode electrodes 73, 74, cathode electrodes 75, 76, and connecting electrodes 77, 78). The barrier film 88 can, for example, comprise titanium and / or titanium nitride. In particular, it can have a single-layer structure comprising a titanium layer or a titanium nitride layer, or a laminated (pre-layered) structure comprising a titanium layer and a titanium nitride layer.The main electrode film 89 can comprise at least one type of material of aluminium, copper, Al-Si-Cu (aluminium-silicon-copper) alloy, Al-Si (aluminium-silicon) alloy and Al-Cu (aluminium-copper) alloy.

[0136] Furthermore, p-type impurity ions are introduced into the back surface of the semiconductor substrate 15 and thermally spread to form a collector region 17. A collector electrode 16 in contact with the collector region 17 is then formed, for example, by a sputtering process. The material example for the collector electrode 16 can be the same as the material example mentioned above for the main electrode film 89.

[0137] Fig. Figure 13A is a schematic cross-sectional view illustrating a pn transition shift in a state where the photoresist mask 90 is formed. As shown in Fig. In 13A, the photoresist mask 90, which is used to implant p-type impurity ions, has diode openings 93 through which the anode regions 61, 62 are exposed. Each of the diode openings 93 has an opening edge at a position that is recessed inwards from the outer edge of the anode regions 61, 62, i.e., at the position where the pn junction 60 is formed at a predetermined distance (e.g., 0.5 µm to 1 µm). p-type impurity ions are implanted into a region belonging to such a diode opening 93. The implanted p-type impurity ions are then thermally treated so that they spread to the position of the outer edge of the anode regions 61, 62, i.e., to a predetermined pn junction position 115.

[0138] In an exposure step during the formation of the photoresist mask 90, the resulting photoresist mask 90 deteriorates if the exposure machine is poorly calibrated, for example, if it is out of focus. In particular, the opening edge of the diode aperture 93 may shift from a predetermined position and / or may have a blunt shape, as indicated by the alternating long and short dashed line. This consequently causes the area for the implantation of p-type impurities and its profile to vary. Accordingly, spreading due to thermal processing may cause the p-type impurities to either not spread to the predetermined pn transition position 115 or to spread beyond the predetermined pn transition position 115. If the pn transition position is shifted in this way, the transition length of the pn transition section 60 may deviate from a planned value.

[0139] As mentioned above, the resulting photoresist mask 90 can be verified by observing the line width of the control sample 95 with a scanning electron microscope. If the line width of the control sample 95 deviates from a predetermined value within a predetermined process tolerance (e.g., within ±1 µm and, in some cases, within ±0.1 µm) or more, it is determined that the control sample 95 has undergone a defective process. A necessary measure, such as adjusting the exposure machine, is then carried out.

[0140] Fig. Figure 13B is a schematic cross-sectional view illustrating a pn transition shift in a state where the photoresist mask 100 is formed. As in Fig. As shown in Figure 13B, the photoresist mask 100, which is used when implanting n-type impurity ions, has diode openings 103 through which the cathode regions 63, 64 are exposed. Each of the diode openings 103 has an opening edge at a position that is recessed inwards from the outer edge of the cathode regions 63, 64, i.e., at the position where the pn junction 60 is formed within a predetermined distance (e.g., 0.5 µm to 1 µm). n-type impurity ions are implanted into the region corresponding to such a diode opening 103. The implanted n-type impurity ions are then thermally treated so that they spread to the position of the outer edge of the cathode regions 63, 64, i.e. to a predetermined pn transition position 115.

[0141] In an exposure step, during the formation of the photoresist mask 100, the resulting photoresist mask 100 deteriorates if the exposure machine is poorly calibrated, for example, if it is out of focus. Specifically, the opening edge of the diode aperture 103 may shift from a predetermined position and / or may have a blunt shape, as indicated by the alternating long and short dashed line. This, in turn, causes the area for implantation of n-type impurities and its profile to vary. Consequently, propagation by thermal processing may cause the n-type impurities to fail to propagate to the predetermined pn transition position 115 or to propagate beyond it. If the pn transition position is shifted in this way, the transition length of the pn transition section 60 may deviate from a planned value.

[0142] As mentioned above, the resulting photoresist mask 100 can be verified by observing the line width of the control sample 105 with a scanning electron microscope. If the line width of the control sample 105 deviates from the predetermined value within a predetermined process tolerance (e.g., within ±1 µm and in some cases within ±0.1 µm) or more, it is determined that the control sample 105 has undergone a defective process. A necessary measure, such as adjusting the exposure machine, is then carried out.

[0143] The variation in the transition length of the pn junction 60 causes the forward voltage characteristics of each first diode 43, acting as a sensor diode, to vary, and consequently, the forward voltage characteristics of the temperature-sensitive diode sensor 41 also vary. For example, the forward voltage of the temperature-sensitive diode sensor 41 may deviate from a planned value by approximately ±5 mV, and the slope of the current-voltage characteristics (IV characteristics) may also deviate from a planned value. Therefore, the temperature-sensitive diode sensor 41 may detect the temperature inaccurately.

[0144] In this preferred embodiment, it is possible to fabricate the semiconductor component 1 while appropriately checking the setting state of the exposure machine, etc., since the resulting photoresist masks 90, 100 can be inspected in detail, even in the temperature-sensitive diode area 9. This allows the yield problem due to defective formation of a temperature-sensitive diode sensor 41 to be reduced.

[0145] Consequently, in the manufacturing process according to this preferred embodiment, power transistor cells 11, which are semiconductor elements or devices that generate heat during operation, are formed in the active region 3 of the semiconductor layer 2 (semiconductor substrate 15), and a temperature-sensitive diode sensor 41, configured to detect a temperature, is formed in the temperature-sensitive diode region 9 of the semiconductor layer 2 (semiconductor substrate 15). The manufacturing process comprises the step of forming a polysilicon layer 50 to form the temperature-sensitive diode sensor 41 in the temperature-sensitive diode region 9. The manufacturing process also comprises the step of forming a mask (photoresist mask 90) which is used when p-type impurities are introduced into the semiconductor layer 2 and the polysilicon layer 50.

[0146] The photoresist mask 90 has an element pattern 92. The photoresist mask 90 has a diode pattern 94. The photoresist mask 90 has a control pattern 95. The element pattern 92 has element openings 91 through which areas belonging to the power transistor cells 11 (semiconductor elements or devices) (areas belonging to the p) + -Type contact areas 33) in which the active area 3 is exposed. The diode pattern 94 has diode openings 93 through which a section of the temperature-sensitive diode area 9 (areas belonging to the anode areas 61, 62) is exposed. The control pattern 95 is provided within the diode pattern 94 with a size that is smaller than that of the diode openings 93. In particular, the control pattern 95 has a line width that is smaller than the line width of the diode openings 93.

[0147] The manufacturing process comprises the step of introducing p-type impurities (implanting ions in this preferred embodiment) into the semiconductor layer 2 and the polysilicon layer 50 through a photoresist mask 90 as described above.

[0148] The manufacturing process further includes the step of forming a mask (photoresist mask 100) which is used when n-type impurities are introduced into the semiconductor layer 2 and the polysilicon layer 50.

[0149] The photoresist mask 100 has an element pattern 102, a diode pattern 104, and a control pattern 105. The element pattern 102 has element openings 101 through which areas belonging to the power transistor cells 11 (semiconductor elements or devices) (areas belonging to the n) are located. +-Type emitter regions 32) are exposed in the active region 3. The diode pattern 104 has diode openings 103 through which a section of the temperature-sensitive diode region 9 (regions belonging to the cathode regions 63, 64) is exposed. The control pattern 105 is provided within the diode pattern 104 with a size that is smaller than that of the diode openings 103. In particular, the control pattern 105 has a line width that is smaller than the line width of the diode openings 103.

[0150] The manufacturing process comprises the step of introducing n-type impurities (implanting ions in this preferred embodiment) into the semiconductor layer 2 and the polysilicon layer 50 through a photoresist mask 100 as described above.

[0151] In the manufacturing process, it is possible to verify the resulting photoresist masks 90, 100 in the temperature-sensitive diode area 9 by observing the control patterns 95, 105 with an electron microscope, since the control patterns 95, 105 are formed within the diode patterns 94, 104 of the photoresist masks 90, 100. In particular, it is possible to observe the control patterns 95, 105 at the same magnification as the element patterns 92 of the photoresist mask 90, because the control patterns 95, 105 are smaller than the diode openings 93, 103 (especially with respect to line width). The following procedure can therefore be carried out after it has been quickly confirmed that the photoresist masks 90, 100 are formed with an accuracy within a required process tolerance in both the cell area 8 and the temperature-sensitive diode area 9.If the required procedural margin is not ensured in either cell area 8 or the temperature-sensitive diode area 9, an appropriate measure is taken, such as adjusting the exposure machine. This allows the number of defective products to be reduced and therefore the yield to be improved.

[0152] In this preferred embodiment, the control patterns 95, 105 have a line width that is discernible with an electron microscope having a magnification at which the line width of the element patterns 92, 102 can be observed. It is therefore possible to observe the element patterns 92, 102 and the control patterns 95, 105 with electron microscopes having the same magnification and thus to quickly check the photoresist masks 90, 100.

[0153] Furthermore, in this preferred embodiment, the control pattern 95 of the photoresist mask 90 is arranged within one of the diode openings 93. Since the control pattern 95 is thus located within an area belonging to a contamination area (e.g., anode areas 61, 62) that forms one of the diodes 43, 44, 47, 48 (e.g., dummy diodes 47, 48), it is possible to inspect the resulting photoresist mask 90 within the areas where the diodes 43, 44, 47, 48 are formed. It is therefore possible to install the diodes 43, 44, 47, 48 with a degree of accuracy.

[0154] Furthermore, in this preferred embodiment, the control pattern 105 of the photoresist mask 100 is arranged outside the diode openings 103. If the diode openings 103 are small, arranging the control pattern 105 outside the diode openings 103 reduces its influence. In particular, in this preferred embodiment, the cathode regions 63, 64, which correspond to the shape of the diode openings 103, are each partially C-shaped or U-shaped. The control pattern 105 is therefore arranged outside the diode openings 103. Specifically, it is arranged in a region belonging to one of the anode regions 61, 62, which have a relatively large area. This allows the control pattern 105 to be formed without affecting the cathode regions 63, 64 and without having a significant impact on the relatively large anode regions 61, 62.

[0155] In this preferred embodiment, the diodes 43, 44, 47, 48, which have the anode regions 61, 62 and the cathode regions 63, 64, are formed in the temperature-sensitive diode region 9. The control patterns 95, 105 are then arranged in regions belonging to the anode regions 61, 62. In particular, such an arrangement is advantageously used when the anode regions 61, 62 have a relatively large area.

[0156] The manufacturing process according to this preferred embodiment comprises the step of forming an anode terminal electrode 37 and a cathode terminal electrode 38, which are to be connected to the temperature-sensitive diode sensor 41. The first diodes 43, acting as sensor diodes, and the dummy diodes 47, 48 are formed in the temperature-sensitive diode region 9. The first diodes 43 (sensor diodes) are connected between the anode terminal electrode 37 and the cathode terminal electrode 38. The dummy diodes 47, 48 are not connected between the anode terminal electrode 37 and the cathode terminal electrode 38. That is to say, the dummy diodes 47, 48 essentially have no electrical function. The diode patterns 94, 104 have sensor patterns 94S, 104S, which belong to the first diodes 43 (sensor diodes) and blind patterns 94D, 104D, which belong to the blind diodes 47, 48.In this preferred embodiment, the blank patterns 94D, 104D have essentially the same shape and size as the sensor patterns 94S, 104S. The control patterns 95, 105 are inserted into the blank patterns 94D, 104D.

[0157] Since the control patterns 95, 105 are embedded in the dummy patterns 94D, 104D, which belong to the dummy diodes 47, 48, which essentially have no electrical function, it is possible to provide the control patterns 95, 105 in the temperature-sensitive diode area 9 without affecting the electrical characteristics of the first diodes 43 (sensor diodes).

[0158] The manufacturing process according to this preferred embodiment also includes the step of forming an anode terminal electrode 37 and a cathode terminal electrode 38, which are to be connected to the temperature-sensitive diode sensor 41. The first diodes 43, acting as sensor diodes, and the second diodes 44, acting as protective diodes, are formed within the temperature-sensitive diode region 9. The first diodes 43 (sensor diodes) are connected between the anode terminal electrode 37 and the cathode terminal electrode 38. The second diodes 44 (protective diodes) are connected in antiparallel to the first diodes 43 (sensor diodes) between the anode terminal electrode 37 and the cathode terminal electrode 38. The second diodes 44 form a protective element 42, which is designed to absorb electrostatic surges in order to protect the temperature-sensitive diode sensor 41.

[0159] Since the electrical characteristics of the second diodes 44 (protective diodes) do not affect the accuracy of the temperature sensing, the control patterns 95, 105 can be inserted into the diode pattern 94 (protective pattern 94P) of the second diodes 44.

[0160] This preferred embodiment further provides the semiconductor component 1. The semiconductor component 1 comprises the semiconductor layer 2 (semiconductor substrate 15). The semiconductor component 1 includes the power transistor cell 11 (semiconductor element or device), which is located in the active region 3 of the semiconductor layer 2 and generates heat during operation. The semiconductor component 1 includes the temperature-sensitive diode sensor 41, which is located in the temperature-sensitive diode region 9 of the semiconductor layer 2 and is configured to detect a temperature. The temperature-sensitive diode sensor 41 comprises the polysilicon layer 50, which is formed in the temperature-sensitive diode region 9. The diodes 43, 44, 47, and 48 are formed in the temperature-sensitive diode region 9.Diodes 43, 44, 47, 48 comprise anode regions 61, 62, into which p-type impurities are introduced into the polysilicon layer 50, and cathode regions 63, 64, into which n-type impurities are introduced into the polysilicon layer 50. In the temperature-sensitive diode region 9, control impurity patterns 97, 107 are present, which have a linewidth smaller than that formed in the polysilicon layer 50 in anode regions 61, 62 or cathode regions 63, 64.

[0161] The semiconductor component 1 configured in this way can be manufactured using the manufacturing processes mentioned above. The control impurity patterns 97, 107 can be used as quality control indices, indicating that the manufacturing process was carried out using a high-precision procedure in which both the cell area 8 and the temperature-sensitive diode area 9 are observed with an electron microscope, in relation to the photoresist masks 90, 100.

[0162] Common to the relationship between the control patterns 95, 105 and the element patterns 92, 102, the control impurity patterns 97, 107 have a line width that can be observed with an electron microscope having a magnification at which the line width of the element impurity patterns (contact areas 33, emitter areas 32, etc.) forming the power transistor cells 11 (semiconductor elements or devices) can be observed.

[0163] In this preferred embodiment, the control impurity patterns 97, 107 are also formed in the anode regions 61, 62 in a manner corresponding to the arrangement of the control patterns 95, 105 of the photoresist masks 90, 100. If the cathode regions 63, 64 have a relatively large area, one or both of the control patterns 95, 105 can be arranged within regions belonging to the cathode regions 63, 64. In this case, the control impurity patterns are accordingly formed within the cathode regions 63, 64.

[0164] The semiconductor component 1 according to this preferred embodiment comprises the anode terminal electrode 37 and the cathode terminal electrode 38, which are connected to the temperature-sensitive diode sensor 41. The diodes formed in the temperature-sensitive diode region 9 include the first diodes 43 (sensor diodes) connected between the anode terminal electrode 37 and the cathode terminal electrode 38 to form the temperature-sensitive diode sensor 41. The diodes formed in the temperature-sensitive diode region 9 also include the dummy diodes 47, 48, which are not connected between the anode terminal electrode 37 and the cathode terminal electrode 38. The control impurity patterns 97, 107 are formed in the regions of the dummy diodes 47, 48 (e.g., anode regions 61, 62).Accordingly, the temperature-sensitive diode sensors 41 can accurately detect the temperature, since the control impurity patterns 97, 107 do not significantly affect the electrical characteristics of the first diodes 43 (sensor diodes).

[0165] The semiconductor component 1 according to this preferred embodiment comprises the anode terminal electrode 37 and the cathode terminal electrode 38, which are connected to the temperature-sensitive diode sensor 41. The diodes formed in the temperature-sensitive diode region 9 include the first diodes 43 (sensor diodes) connected between the anode terminal electrode 37 and the cathode terminal electrode 38 to form the temperature-sensitive diode sensor 41. The diodes formed in the temperature-sensitive diode region 9 also include the second diodes 44 (protective diodes), which are connected antiparallel to the first diodes 43 (sensor diodes) between the anode terminal electrode 37 and the cathode terminal electrode 38. The second diodes 44 form the protective element 42, which is designed to absorb electrostatic overvoltage in order to protect the temperature-sensitive diode sensor 41.

[0166] Since the electrical characteristics of the second diodes 44 (protective diodes) do not affect the accuracy of the temperature sensing, the control impurity patterns 97, 107 can be formed in areas of the second diodes 44.

[0167] Fig. Figure 14 is a top view illustrating a configuration of a semiconductor component 120 according to a further preferred embodiment of the present invention. Since the configuration of the semiconductor component 120 is almost the same as that in the preferred embodiment mentioned above, with the exception of the arrangement of the temperature-sensitive diode area 9, components in Fig. 14, which correspond to those in the preferred embodiment mentioned above, are designated by the same reference numerals. Where applicable, reference is also made to the drawings referred to in the description of the preferred embodiment mentioned above.

[0168] In this preferred embodiment, the temperature-sensitive diode region 9 is provided within the active region 3 in such a way that it is surrounded by the cell region 8. The semiconductor device 120 configured in this way can also be manufactured using a manufacturing process as described above. This allows for the accuracy of the pattern dimensions and pattern arrangement of the photoresist masks 90, 100 (see Figure 1). Fig. 9 and Fig. 10), to confirm, not only in the cell area 8, but also in the temperature-sensitive diode area 9 in the middle of the manufacturing process, and thus to improve the yield. An arrangement of the temperature-sensitive diode area 9 within the active area 3 allows the temperature-sensitive diode sensor 41 to detect heat generation from the active area 3 more accurately.

[0169] As is the case in the above-mentioned preferred embodiments, the control impurity patterns 97, 107 (see Fig. 7) formed in the temperature-sensitive diode area 9. The control impurity patterns 97, 107 can be observed with an electron microscope if necessary. This allows confirmation that the semiconductor component 120 was manufactured using a high-precision process.

[0170] While the preferred embodiments of the present invention have been described so far, the present invention can be implemented in other forms.

[0171] For example, the preferred embodiments described above mainly describe an example in which the control patterns 95, 105 are arranged in the blind diode formation areas 55, 56 (blind diode areas). Alternatively or additionally, the control patterns can be arranged in the first diode formation areas 53 (sensor diode areas) and / or the second diode formation areas 54 (protective diode areas).

[0172] Furthermore, the preferred embodiments described above mainly represent an example in which the control patterns 95, 105 are arranged in regions belonging to the anode regions 61, 62. Alternatively or additionally, the control patterns can be arranged in regions belonging to the cathode regions 63, 64, as mentioned above. The control patterns 95, 105, which are preferably formed at positions away from the pn junction section 60, can be in contact with the position of the pn junction section 60 of the dummy diodes 47, 48 if the control patterns 95, 105 are formed in the dummy diode formation regions 55, 56. Furthermore, within the temperature-sensitive diode region 9, the control patterns can be arranged in regions that belong neither to the anode nor the cathode regions.

[0173] Furthermore, the preferred embodiments described above include an example in which the photoresist mask 90, used for p-type impurity ion implantation, has a control pattern 95, and the photoresist mask 100, used for n-type impurity ion implantation, has the control pattern 105. However, in some cases, the control pattern of the photoresist mask 90 or the photoresist mask 100 can be omitted. For example, in the preferred embodiment described above, the polysilicon 50 will be formed with added n-type impurities. p-type impurity ions and n-type impurity ions are implanted into the n-type polysilicon layer 50 to form the anode regions 61, 62 and the cathode regions 63, 64. The polysilicon 50 therefore remains n-type in the regions that are not implanted with p-type impurity ions.Accordingly, the resulting photoresist mask 90 for p-type impurity ion implantation is more important for the arrangement of the pn junction section 60. Therefore, the control pattern 105 of the photoresist mask 100, which is used for n-type impurity ion implantation, can be omitted.

[0174] Regarding cell area 8, the control pattern (cell area control pattern), which has a line width equal to that of contact area 33, emitter areas 32, etc., can be provided in the photoresist masks 90, 100 and observed with an electron microscope to assess the resulting photoresist mask 90, 100 within cell area 8.

[0175] Furthermore, the element pattern 102 and the control pattern 95, 105 etc. of the photoresist mask 90, 100 and in some cases, the element impurity patterns (contact areas 33, emitter areas 32 etc.) and the control impurity patterns 97, 107 can be examined with a transmission electron microscope, without restriction to a scanning electron microscope.

[0176] Furthermore, in the preferred embodiments mentioned above, the collector region 17 can be omitted and a MIS (metal insulator semiconductor)-type FET semiconductor device can be formed. In this case, "emitter" and "collector" are replaced by "source" and "drain" in the description of the preferred embodiments mentioned above. + A type contact layer for ohmic contact is preferably provided between the drain electrode 16 and the semiconductor layer 2.

[0177] Furthermore, n-type regions can be replaced by -type regions and vice versa in the above description and the accompanying drawings, since the conductivity type of each section of the semiconductor device 1 according to the above preferred embodiment is merely an example.

[0178] While preferred embodiments of the present invention have been described in detail above, these are merely specific examples used to illustrate the technical content of the present invention, and the present invention should not be interpreted as being limited to these specific examples, and the scope of the present invention is limited only by the attached claims.

[0179] This application claims priority over Japanese patent application No. 2019-115733, filed on June 21, 2019, the entire contents of which are incorporated herein by reference. Reference symbol list 1 Semiconductor component 2 Semiconductor layer 3 Active Area 4 Outdoor area 5 Emitter terminal electrode 6 Gate terminal electrode 7 Gate wire 8 cell area 9 temperature-sensitive diode area 10 Trench Gate structure 11 Power transistor cell 15 Semiconductor substrate 16 Collector electrode 20 Gate Trench 30 FET structure 31 Body area 32 emitter area 33 Contact area 37 Anode terminal electrode 38 Cathode terminal electrode 41 temperature-sensitive diode sensor 42 Protective element 43 First diode 44 Second diode 47 First blind diode 48 Second dummy diode 50 polysilicon layer 53 First diode training area 54 Second diode training area 55 First blind diode training area 56 Second blind diode training area 60: pn transition section 61 First anode area 62 Second anode area 63 First cathode area 64 Second cathode area 65 First anode opening 66 Second anode opening 67 First cathode opening 68 Second cathode opening 71 First diode wire 72 Second diode wire 73 First anode electrode 74 Second anode electrode 75 First cathode electrode 76 Second cathode electrode 77 First connecting electrode 78 Second connecting electrode 81 First series circuit 82 Second series connection 85 Polysilicon film 90 Photoresist Mask 91 element opening 92 element patterns 93 Diode opening 94 diode patterns 94S Sensor Pattern 94P Protective Pattern 94D Blind Pattern 95 control samples 95L Linear Section 97 control impurity samples 100 photoresist masks 101 Element opening 102 Element Patterns 103 Diode opening 104 diode patterns 104S Sensor Pattern 104P Protective Pattern 104D Blind Pattern 105 control samples 105L Linear Opening Section 107 control impurity samples 115 Predetermined pn transition position 120 semiconductor components

Claims

[1] A method for producing a semiconductor device in which a semiconductor element which generates heat during operation is formed in an active region of a semiconductor substrate and in which a temperature-sensitive diode sensor is formed in a temperature-sensitive diode region of the semiconductor substrate, which temperature-sensitive diode sensor is arranged to measure a temperature, the method comprising the steps of: Forming a polysilicon layer forming the temperature-sensitive diode sensor in the temperature-sensitive diode region; Forming a mask comprising an element pattern having an element opening through which a region constituting the semiconductor element is exposed in the active region, a diode pattern having a diode opening through which a portion of the temperature-sensitive diode region is exposed, and a control pattern provided in the diode pattern with a size smaller than that of the diode opening; and Introducing impurities through the mask into the semiconductor substrate and the polysilicon layer. [2] A method for manufacturing a semiconductor device according to claim 1, wherein the control pattern has a line width that can be seen with an electron microscope having a magnification at which a line width of the element pattern can be seen. [3] A method of manufacturing a semiconductor device according to claim 1 or 2, further comprising the step of observing the element pattern and the control pattern with an electron microscope having the same magnification. [4] A method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the control pattern comprises a control pattern arranged within the diode opening. [5] A method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the control pattern comprises a control pattern arranged outside the diode opening. [6] A method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein a diode having an anode region and a cathode region is formed in the temperature-sensitive diode region, and wherein the control pattern is arranged in a region belonging to the anode region. [7] A method for manufacturing a semiconductor device according to any one of claims 1 to 6, further comprising the step of forming an anode terminal electrode and a cathode terminal electrode to be connected to the temperature-sensitive diode sensor, wherein a sensor diode to be connected between the anode terminal electrode and the cathode terminal electrode, and a dummy diode not to be connected between the anode terminal electrode and the cathode terminal electrode are formed in the temperature-sensitive diode region, wherein the diode pattern comprises a sensor pattern belonging to the sensor diode and a dummy pattern belonging to the dummy diode, and wherein the control pattern is inserted into the blind pattern. [8] A method for manufacturing a semiconductor device according to any one of claims 1 to 7, further comprising the step of forming an anode terminal electrode and a cathode terminal electrode to be connected to the temperature-sensitive diode sensor, wherein a sensor diode to be connected between the anode terminal electrode and the cathode terminal electrode and a protective diode to be connected between the anode terminal electrode and the cathode terminal electrode anti-parallel to the sensor diode are formed in the temperature-sensitive diode region. [9] Semiconductor component with: a semiconductor substrate; a semiconductor element provided in an active region of the semiconductor substrate and which generates heat during operation; and a temperature-sensitive diode sensor provided in a temperature-sensitive diode region of the semiconductor substrate and configured to detect a temperature, wherein the temperature-sensitive diode sensor comprises a polysilicon layer formed in the temperature-sensitive diode region, wherein a diode comprising an anode region in which p-type impurities are introduced into the polysilicon layer and a cathode region in which n-type impurities are introduced into the polysilicon layer is formed in the temperature-sensitive diode region, and wherein in the temperature-sensitive diode region, a control impurity pattern having a line width smaller than that in the anode region or the cathode region is formed in the polysilicon layer. [10] The semiconductor device according to claim 9, wherein the control impurity pattern has a line width that can be seen with an electron microscope having a magnification at which a line width of an element impurity pattern constituting the semiconductor element can be seen. [11] A semiconductor device according to claim 9 or 10, wherein the control impurity pattern is formed in at least one of the anode region and the cathode region. [12] A semiconductor device according to any one of claims 9 to 11, further comprising an anode terminal electrode and a cathode terminal electrode connected to the temperature-sensitive diode sensor, wherein the diode comprises a sensor diode connected between the anode terminal electrode and the cathode terminal electrode to form the temperature-sensitive diode sensor, and a dummy diode not connected between the anode terminal electrode and the cathode terminal electrode, and wherein the control contamination pattern is formed in the area of ​​the dummy diode. [13] A semiconductor device according to any one of claims 9 to 12, further comprising an anode terminal electrode and a cathode terminal electrode connected to the temperature-sensitive diode sensor, the diode comprising a sensor diode connected between the anode terminal electrode and the cathode terminal electrode to form the temperature-sensitive diode sensor, and a protective diode connected anti-parallel to the sensor diode between the anode terminal electrode and the cathode terminal electrode.

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