COMPOUND STRUCTURES WITH RUTHENIUM LINING WITH COBAL INFUSION AND A COBAL COVER AND METHOD FOR FORMING SUCH COMPOUND STRUCTURES

Abstract

Methods for forming a connection structure, including: Forming a recess (108) within a dielectric layer (106); shape-adapted deposition of a barrier layer (110) within the recess; Forming a ruthenium lining with cobalt infusion over the barrier layer, the cobalt-containing ruthenium lining comprising: a first lining (120) directly above the barrier layer, wherein the first lining comprises ruthenium; a second lining (130) directly above the first lining, the second lining comprising cobalt; and a third lining (240) directly above the second lining, wherein the third lining contains ruthenium, wherein the ruthenium lining with cobalt infusion is formed by migration of cobalt atoms from the second lining into the first and the third lining; Deposition of a conductive material (242) over the ruthenium lining with cobalt infusion to fill the recess; and Forming a cover layer (256) over an upper surface of the conductive material, wherein the cover layer comprises cobalt.

Description

BACKGROUND

[0001] The present invention relates generally to the field of complementary metal oxide semiconductor units (CMOS units) and in particular copper compound structures comprising a ruthenium lining with cobalt infusion and a cobalt cover, and methods for forming such compound structures.

[0002] Typical components of an integrated circuit (IC) include transistors, capacitors, and similar components. In semiconductor chip manufacturing, these IC components are interconnected by interconnects that conduct current through the various circuit layers. These interconnects typically take the form of wires, grooves, or vias embedded in dielectric layers above the microelectronic units or metallization layers of the IC. Interconnects are typically formed by depositing a dielectric layer, etching a cavity into the dielectric layer, and filling the cavity with a metal. Typically, interconnects are made of copper and can be fabricated using single-damascus or double-damascus processes.In the single-Damascus process, connection structures are formed independently, while in the double-Damascus process they are produced simultaneously.

[0003] In general, interconnect structures are lined with a barrier layer located at the interface between the dielectric layer and the underlying metal plane. The presence of this barrier layer can reduce electromigration (EM) problems in the IC. Electromigration can be defined as the material transport induced by electron flow during operation under current, with the interface between the interconnect structure and the surrounding dielectric being the primary pathway for material transport in metal conductors. In 7 nm technologies and above, a ruthenium lining (Ru lining) is used to achieve better copper filling (Cu filling).However, cobalt (Co) from the cobalt cover used to encapsulate the copper filling can diffuse into the ruthenium lining, leading to electromagnetic degradation and thus posing a critical electromigration resistance (yield) problem for back-end-of-the-line (BEOL) technologies. Therefore, alternative designs and techniques for forming interconnect structures would be desirable.

[0004] Document US 2019 / 0355618A1 relates to a method for fabricating a semiconductor device. The method comprises the following steps: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first lining in the trench, the first lining comprising a Co-Ru alloy; forming a metal layer on the first lining; and planarizing the metal layer and the first lining to form a metal compound.

[0005] Document US 2008 / 0280432A1 relates to a method for reducing electromigration effects in a copper damascene device, the method comprising: forming a low k-value dielectric layer, wherein the low k-value dielectric layer has a surface with a recessed feature; forming a diffusion barrier layer over the surface of the low k-value dielectric layer; forming an adhesive layer on the diffusion barrier layer; filling the recessed feature with a conductor; annealing the conductor; and forming a cover layer on the conductor. SUMMARY

[0006] The invention relates to a semiconductor structure and a method for its fabrication, the features of which are specified in the corresponding claims. Embodiments of the invention are specified in the dependent claims.

[0007] The disadvantages of the prior art are overcome and additional advantages are provided by a method for forming a compound structure, which includes forming a cavity within a dielectric layer, shape-conforming deposition of a barrier layer within the cavity, and forming a ruthenium lining with cobalt infusion over the barrier layer. The ruthenium lining with cobalt infusion comprises a first lining over the barrier layer and a second lining over the first lining. The first lining contains ruthenium, while the second lining contains cobalt. Cobalt atoms from the second lining migrate into the first lining to form the ruthenium lining with cobalt infusion.A conductive material is deposited over the ruthenium-infused lining to fill the recess, followed by the formation of a cover layer over the upper surface of the conductive material, the cover layer containing cobalt. The formation of the ruthenium-infused lining reduces the cobalt concentration gradient between the cover layer and the first lining, thus preventing cobalt migration from the cover layer.

[0008] In another embodiment, an alternative method for forming a compound structure is provided, which includes forming a recess within a dielectric layer, shape-conforming deposition of a barrier layer within the recess, followed by shape-conforming deposition of a first lining over the barrier layer and a second lining over the first lining. The first lining comprises ruthenium, while the second lining comprises cobalt. Subsequently, a third lining is formed over the second lining, the third lining comprising ruthenium. Through the migration of cobalt atoms from the second lining into the first lining and the third lining, a cobalt-infused ruthenium lining is formed.A conductive material is formed over the ruthenium-infused lining to fill the recess, followed by the deposition of a cover layer over the upper surface of the conductive material, the cover layer containing cobalt. The formation of the ruthenium-infused lining reduces the cobalt concentration gradient between the cover layer and the first and third linings, thus preventing cobalt migration from the cover layer.

[0009] In a further embodiment, a semiconductor structure is provided which includes a compound structure within a dielectric layer, wherein the compound structure comprises a barrier layer arranged on a lower surface and on side walls of the compound structure, a first lining directly above the barrier layer, wherein the first lining comprises ruthenium, a second lining directly above the first lining, wherein the second lining comprises cobalt, a conductive material above the second lining which substantially fills the compound structure, and a cover layer directly above the conductive material, wherein the cover layer comprises cobalt. Migration of cobalt atoms from the second lining into the first lining reduces a concentration gradient between the cover layer and the first lining, thus preventing diffusion of cobalt atoms from the cover layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The following detailed description, which is given by way of example and is not intended to limit the invention solely to it, is best understood in conjunction with the accompanying drawings, in which: Fig. 1A is a cross-sectional view of a simplified semiconductor structure, which shows the formation of recesses in a dielectric layer and the deposition of a barrier layer within the recesses according to an embodiment of the present invention; Fig. 1B is a cross-sectional view of the simplified semiconductor structure, which shows the deposition of a first lining over the barrier layer according to an embodiment of the present invention; Fig. 1C is a cross-sectional view of the simplified semiconductor structure, which shows the deposition of a second lining over the first lining according to an embodiment of the present invention; Fig. Figure 1D shows a cross-sectional view of the simplified semiconductor structure, which shows the deposition of a first conductive material over the second lining according to an embodiment of the present invention; Fig. 1E is a cross-sectional view of the simplified semiconductor structure after a planarization process according to an embodiment of the present invention; Fig. 1F is a cross-sectional view of the simplified semiconductor structure, which shows first interconnection structures comprising a first cover layer over the first conductive material, according to an embodiment of the present invention; Fig. 2A is a cross-sectional view of the simplified semiconductor structure, which shows the formation of recesses in the dielectric layer and the deposition of the barrier layer within the recesses according to another embodiment of the present invention; Fig. 2B is a cross-sectional view of the simplified semiconductor structure, showing the deposition of the first lining over the barrier layer and the deposition of the second lining over the first lining according to another embodiment of the present invention; Fig. 2C is a cross-sectional view of the simplified semiconductor structure, which shows the deposition of a third lining over the second lining according to another embodiment of the present invention; Fig. 2D is a cross-sectional view of the simplified semiconductor structure, which shows the deposition of a second conductive material over the third lining according to another embodiment of the present invention; Fig. 2E is a cross-sectional view of the simplified semiconductor structure after a planarization process according to another embodiment of the present invention; Fig. 2F is a cross-sectional view of the simplified semiconductor structure, which shows second finished interconnect structures comprising a second cover layer over the second conductive material, according to another embodiment of the present invention; Fig. 3A is a cross-sectional view of the simplified semiconductor structure, which shows the formation of recesses in the dielectric layer and the deposition of the barrier layer within the recesses according to yet another embodiment of the present invention; Fig. 3B is a cross-sectional view of the simplified semiconductor structure, which shows the deposition of the first lining, the second lining and the third lining according to yet another embodiment of the present invention; Fig. Figure 3C shows a cross-sectional view of the simplified semiconductor structure, which shows the removal of horizontal sections of the first lining, the second lining and the third lining according to yet another embodiment of the present invention; Fig. 3D is a cross-sectional view of the simplified semiconductor structure, which shows the deposition of a second conductive material over the third lining according to another embodiment of the present invention; Fig. 3E is a cross-sectional view of the simplified semiconductor structure after a planarization process according to yet another embodiment of the present invention; Fig. Figure 3F shows a cross-sectional view of the simplified semiconductor structure, which shows second finished interconnect structures comprising the second cover layer over the second conductive material, according to yet another embodiment of the present invention.

[0011] The drawings are not necessarily to scale. They are merely schematic representations and are not intended to depict specific parameters of the invention. The drawings are intended only to show typical embodiments of the invention. In the drawings, identical numbers represent identical elements. DETAILED DESCRIPTION

[0012] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is understood that the disclosed embodiments are merely examples of the claimed structures and methods, which may be embodied in various forms. The present invention can, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments described herein. Details of well-known features and techniques may be omitted from the description to avoid making the described embodiments unnecessarily unclear.

[0013] For the purposes of this description, terms such as "upper," "lower," "right," "left," "vertical," "horizontal," "above," "below," and derivatives thereof shall refer to the disclosed structures and methods as oriented in the drawings. Terms such as "over," "over...," "on," "above on," "positioned on," or "above...positioned" mean that a first element, e.g., a first structure, is located on top of a second element, e.g., a second structure, whereby intermediate elements, e.g., an interface structure, may be present between the first and second elements. The term "direct contact" means that a first element, e.g., a first structure, and a second element, e.g., a second structure, are connected at the interface of the two elements without any intervening conductive layers, insulating layers, or semiconductor layers.

[0014] It is understood that, although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are used merely to distinguish one element from another. Thus, a first element described below could be referred to as a second element without deviating from the scope of the present concept.

[0015] To avoid any ambiguity in the presentation of embodiments of the present invention, some processing steps or operations known in the field may have been combined in the following detailed description for illustrative purposes and may not have been described in detail in some cases. In other cases, some processing steps or operations known in the field may not have been described at all. It is understood that the following description focuses instead on the characteristic features or elements of different embodiments of the present invention.

[0016] Copper (Cu) has been used for many years in the manufacture of integrated circuit (IC) chips. Copper is a better conductor than aluminum (Al) and allows for smaller metal components. However, copper can cause problems if it is not properly confined within the interconnect structures. To properly confine copper, cobalt (Co) has been used in current 7 nm (7-nanometer) interconnects, both as a cobalt liner and as a cobalt cover for copper encapsulation. Unfortunately, cobalt movement / diffusion has been associated with degraded electromigration lifetimes, especially when the cobalt cover is combined with the ruthenium liner (Ru liner) typically used in 7 nm technologies to improve copper filling.

[0017] Therefore, embodiments of the present invention provide a method and an associated structure for fabricating copper compound structures comprising a cobalt-containing ruthenium liner and a cobalt cover. The proposed embodiments prevent the diffusion of cobalt atoms from the cobalt cover into the ruthenium liner, thereby improving the electromigration properties. One way to prevent cobalt diffusion from the cobalt cover involves forming a tantalum nitride layer, followed by a ruthenium liner and a substantially thin cobalt liner capable of saturating the underlying ruthenium liner with cobalt atoms to form the cobalt-containing ruthenium liner, which can impede the driving force for cobalt diffusion from the cobalt cover.An embodiment by which the cobalt-containing ruthenium lining can be formed in copper compound structures is described below with reference to the accompanying drawings in . Fig. 1A to 1F are described in detail. Alternative embodiments by which the cobalt-containing ruthenium lining can be formed to prevent cobalt diffusion in copper compounds are described below with reference to the accompanying drawings. Fig. Sections 2A to 3F are described in detail.

[0018] Now, referring to Fig. Figures 1A to 1F show cross-sectional views of a simplified representation of a semiconductor structure 100 during a sequence of processing steps according to an embodiment of the present invention. Fig. The sequence of processing steps shown in 1A to 1F illustrates the formation of a connection structure 160 in the simplified semiconductor structure 100 (hereinafter referred to as "semiconductor structure").

[0019] Referring to Fig. In this step of the manufacturing process, the semiconductor structure 100 comprises a dielectric layer 106 in which recesses 108 have been formed by standard etching techniques. For illustrative purposes only, but not limited to, only two recesses 108 are shown within the dielectric layer 106. As is known to those skilled in the art, any number of recesses 108 can be formed depending on the circuit design and / or requirements.

[0020] The dielectric layer 106 is typically formed over (not shown) unit or metal planes of the semiconductor structure 100. Specifically, as is known to those skilled in the art, a dielectric material layer, e.g., the dielectric layer 106, is deposited over (not shown) active regions of the semiconductor structure 100 and then etched to form openings or recesses which are subsequently filled with a conductive material to form the interconnect structure(s).

[0021] The dielectric material forming the dielectric layer 106 can, for example, comprise a low-k dielectric material having a dielectric constant k in the range of approximately 2.4 to approximately 2.7. In some embodiments, the dielectric layer 106 can comprise silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, low-k silicon-based dielectrics, or porous dielectrics. The dielectric layer 106 can be formed by any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like.

[0022] As mentioned above, the dielectric layer 106 is etched to form the recesses 108. The recesses 108 can be formed by lithography and etching techniques, typically employed in single-damascus and double-damascus processes. The recesses 108 can be shaped to accommodate a variety of interconnect structures (e.g., trenches, conductors, or vias). Typically, the recesses 108 can extend through the dielectric layer 106 to expose (not shown) active regions of the semiconductor structure 100. The recesses 108 are then filled with a conductive metal, as detailed below.

[0023] As experts may know, the in Fig. The recesses 108 shown in Figure 1A have been etched into the dielectric layer 106 with a specific aspect ratio (H / D) of height (=H) to width (=D). In some embodiments, the range of aspect ratios varies from approximately 0.5 to approximately 20, with aspect ratios of 1 to 10 being preferred. However, in the actual unit, there may be high aspect ratios (H / D) greater than 20:1.

[0024] Further referring to Fig. In step 1A, a barrier layer 110 is deposited on the horizontal and vertical surfaces of the dielectric layer 106. In other words, the barrier layer 110 is deposited on a bottom surface, side walls, and top surfaces of the dielectric layer 106, as shown in the figure. The barrier layer 110 can comprise any barrier material suitable for preventing the diffusion of subsequently deposited metal layers (e.g., cobalt, ruthenium, or copper) into the dielectric layer 106. In particular, the barrier layer 110 can prevent the diffusion of atoms from the subsequently formed ruthenium and cobalt linings into the dielectric layer 106, also acting as an adhesion-promoting layer so that the ruthenium and cobalt linings are bonded to the dielectric layer 106.Experimental results have shown that direct deposition of ruthenium onto dielectric materials can lead to poor adhesion and cause reliability problems related to layer delamination.

[0025] According to one embodiment, the barrier layer 110 comprises tantalum nitride (TaN). In other embodiments, the barrier layer 110 can comprise alternative metal nitrides, such as titanium nitrate (TiN), tungsten nitride (WN), or the like. A standard deposition method can be used to form the barrier layer 110. For example, in some embodiments, the barrier layer 110 can be formed by CVD, PVD, or atomic layer deposition (ALD).

[0026] The barrier layer 110 can have a thickness that varies from approximately 0.5 nm to approximately 5 nm and lies in ranges in between, although a thickness of less than 0.5 nm and more than 5 nm may be acceptable.

[0027] The process continues by depositing a first, shape-adapted lining 120 directly over the barrier layer 110, as shown in Fig. Figure 1B is shown. In a preferred embodiment, the first liner 120 is substantially, if not entirely, composed of ruthenium and can be formed by standard deposition processes such as PVD, CVD, electroless plating, evaporation, or any other deposition process that deposits shape-conforming thin films. As described above, ruthenium-containing liners such as the first liner 120 are used in 7 nm technologies and beyond to improve copper filling (Cu filling). In particular, liners comprising ruthenium can adhere better to the copper nuclei, allowing them to be better shaped (i.e., defect-eliminating) and thinner.

[0028] The first lining 120 can have a thickness varying from approximately 0.5 nm to approximately 5 nm and in the ranges in between, although a thickness of less than 0.5 nm and more than 5 nm may be acceptable. In one embodiment, the first lining 120 can have a thickness of approximately 10 nm.

[0029] After the first lining 120 is formed, a second lining 130 is formed over the first lining 120, as shown in Fig. Figure 1C shows the second lining 130, which can comprise a very thin layer of a (metallic) material deposited in a shape-conforming manner onto the first lining 120. In a preferred embodiment, the second lining 130 is essentially, if not entirely, composed of cobalt (Co). To form the second lining 130, standard deposition processes such as PVD, CVD, electroless plating, evaporation, or any other deposition process that deposits shape-conforming thin films can be used.

[0030] By forming the second lining 130 in direct contact with the first lining 120, cobalt atoms migrate from the second lining 130 into the first lining 120 (i.e., the ruthenium lining), saturating the first lining 120 with cobalt, so that there is no driving force for cobalt diffusion from a subsequently formed cobalt cover (e.g., the first cover layer 156 in Fig. 1F). Therefore, depletion of the cobalt cover formed subsequently is prevented, which in turn improves the electromigration properties of the (first) compound structure(s) 160 ( Fig. 1F) can improve.

[0031] It should be noted that cobalt diffusion into the ruthenium liner (e.g., the first liner 120) typically occurs during heat treatment(s) performed during processing steps such as annealing or high-temperature thin-film deposition on the semiconductor structure 100. Since the driving force for cobalt diffusion is the cobalt concentration gradient between the cobalt cover formed below (e.g., the first cover layer 156 in Fig. 1F) and the first lining 120 (i.e. the ruthenium lining), the incorporation of cobalt atoms from the second lining 130 into the first lining 120 reduces the cobalt concentration gradient between the cobalt cover and the first lining 120, thereby effectively suppressing or attenuating cobalt diffusion into the semiconductor structure 100.

[0032] The thickness of the second lining 130 can be less than the thickness of the first lining 120. In one embodiment, the second lining 130 can have a thickness of less than approximately 5 nm. In other embodiments, the thickness of the second lining 130 can vary from approximately 0.1 nm to approximately 5 nm. In yet another embodiment, the second barrier lining can be thicker than the first lining 120.

[0033] Now, referring to Fig. In 1D, a first conductive material 142 can be shaped and deposited directly onto an upper surface of the second lining 130. According to one embodiment, the first conductive material 142 comprises copper (Cu). In some embodiments, the first conductive material 142 can further comprise dopants such as manganese, magnesium, copper, aluminum, or other known dopants. The first conductive material 142 can be formed by electroplating, electroless plating, PVD, CVD, or any combination thereof.

[0034] The thickness of the first conductive material 142 may be sufficient to completely fill the remaining space within the recesses 108. However, in some cases, the thickness of the first conductive material 142 may exceed the depth of the recesses 108, as shown in Fig. 1D representation. In these cases, a planarization process can be performed on the semiconductor structure 100 to remove areas of the first conductive material 142 that exceed the depth of the recesses 108, as shown in Fig. 1E is shown.

[0035] As in Fig. As shown in Figure 1E, excess sections of the first conductive material 142 can be removed from the semiconductor structure 100 by any planarization process known in the field, including, for example, chemical-mechanical polishing (CMP). Furthermore, during the planarization process, (horizontal) sections or areas of the barrier layer 110, the first lining 120, and the second lining 130 parallel to the dielectric layer 106 can also be removed.

[0036] The process continues with the formation of the first cover layer 156, which is in Fig. Figure 1F shows the first cover layer 156, which is essentially, if not entirely, composed of cobalt (Co). The first cover layer 156 can be deposited by any suitable deposition method and can have a thickness ranging from approximately 0.5 nm to approximately 5 nm. As is known to those skilled in the art, the first cover layer 156 is typically used in back-end-of-the-line (BEOL) technologies to encapsulate the copper (Cu) in the first conductive material 142, thereby reducing Cu migration in the interconnect structure 160 and overall improving the reliability of the semiconductor structure 100.

[0037] Further referring to Fig. Figure 1F shows a final step in the formation of the first interconnect structures 160. According to one embodiment, each of the resulting first interconnect structures 160 comprises the first barrier lining 120 directly over the barrier layer 110 and the (thin) second lining 130 directly over the first lining 120, wherein the first conductive material 142 over the second lining 130 substantially fills the first interconnect structure 160, and the first cover layer 156 over an upper surface of the first conductive material 142. This configuration can prevent cobalt diffusion from the first cover layer 156 into the first lining 120. By preventing the diffusion of cobalt atoms from the first cover layer 156, depletion of the first cover layer 156 can be avoided, thus improving the electromigration properties.Specifically, the cobalt from the second lining 130 saturates the ruthenium-based first lining 120, forming a cobalt-infused ruthenium lining which is able to halt the driving force for cobalt diffusion from the first cover layer 156 due to the reduced (cobalt) concentration gradient.

[0038] Now, referring to Fig. Figures 2A to 2F show cross-sectional views of the semiconductor structure 100 during an alternative processing sequence for forming a connection structure according to another embodiment of the present invention. The sequence of processing steps shown in Fig. Figures 2A to 2F illustrate an alternative method for forming second interconnect structures 260 in the semiconductor structure 100. The second interconnect structures 260 are formed similarly to the first interconnect structures 160, which are shown above in relation to Fig. 1A to 1F are described. However, in this embodiment, after forming the second barrier lining 130 ( Fig. 2B) a third barrier lining 240 formed directly above the second barrier lining 130, as in Fig. 2C is shown.

[0039] As in Fig. As can be seen in Figure 2C, in this embodiment the second lining 130 is positioned between the first lining 120 and the third lining 240. According to one embodiment, the third lining 240 is made of essentially the same material as the first lining 120 (i.e., ruthenium) and can be formed by analogous deposition methods. The third lining 240 can have a thickness that varies from approximately 0.5 nm to approximately 5 nm. As explained above, ruthenium-containing linings are typically used in modern BEOL fabrication to enhance the copper filling. However, the combination of ruthenium linings with cobalt covers (e.g., the first cover layer 156 of the Fig. 1F and the second cover layer 256 of the Fig. 2F), which are used for copper encapsulation, have been associated with deteriorated electromigration lifetimes.

[0040] Therefore, by arranging the second lining 130 between the first lining 120 and the third lining 240, saturation of the first lining 120 and the third lining 240 with cobalt atoms from the second lining 130 can occur, so that cobalt migration from the subsequently formed cobalt cover layer (e.g., the cover layer 256 in Fig. 2F). Furthermore, in this embodiment, the ruthenium / copper interface (Ru / Cu interface) is retained, which improves the copper filling properties for either copper plating or PVD copper reflow. Specifically, the Ru / Cu interface remains present when the third lining 240 is deposited over the second lining 130 after the deposition of the second conductive material 242.

[0041] In some embodiments, after deposition of the third lining 240, an etching process can be carried out on the semiconductor structure 100 to selectively remove horizontal sections of the first, second, and third linings 120, 130, and 240 from the dielectric layer 106, as shown in Fig. 3C is shown. In other words, sections of the first, second, and third linings 120, 130, and 240 parallel to the dielectric layer 106 are selectively removed by any suitable etching method. For example, argon plasma (Ar plasma) etching can be performed to remove the horizontal sections of the first, second, and third linings 120, 130, and 240 from the semiconductor structure 100.

[0042] By removing these sections of the first, second and third linings 120, 130 and 240, upper (horizontal) surfaces of the barrier layer 110 are exposed, as shown in Fig. 3C is shown. In other words, after the etching step of the Fig. 3C, the first, second and third linings 120, 130 and 240 remain only on opposite side walls of the second connecting structures 260, as in Fig. 3F is shown. By performing this etching step ( Fig. 3C) the resulting second connection structures 260 ( Fig. 3F) in addition to reduced cobalt diffusion from the second cover layer 256 due to the absence of the first, second and third linings 120, 130 and 240 on the lower section of the second interconnect structures 260, exhibit reduced via resistance.

[0043] Now, referring to Fig. 2D, the process involves the deposition of a second conductive material 242 similar to the first conductive material 142 in Fig. 1D continued. The second conductive material 242 can be prepared from analogous materials and deposited in similar ways to the first conductive material 142 ( Fig. 1D). It should be noted that with or without the in Fig. In the etching step shown in 3C, the process continues with the deposition of the second conductive material 242.

[0044] As in Fig. As shown in Figure 2E, excess sections of the second conductive material 242 can be removed from the semiconductor structure 100 by any planarization process, including, for example, CMP. Furthermore, during the planarization process, horizontal sections or areas of the barrier layer 110, the first lining 120, the second lining 130, and the third lining 240 parallel to the dielectric layer 106 can also be removed from the semiconductor structure 100.

[0045] The process continues with the formation of the second covering layer 256, which is in Fig. 2F is shown. The second cover layer 256 is built up from analogous materials and deposited in similar ways to the first cover layer 156 ( Fig. 1F).

[0046] Further referring to Fig.Figure 2F shows a final step in the formation of the second interconnect structures 260. According to one embodiment, each of the resulting second interconnect structures 260 comprises the first lining 120 directly above the barrier layer 110 and the (thin) second lining 130 arranged between the first lining 120 and the third lining 240, the second conductive material 242 above the third lining 240, which substantially fills the interconnect structures 260, and the second cover layer 256 over an upper surface of the second conductive material 242. As explained above, this configuration can prevent cobalt diffusion from the second cover layer 256 into the ruthenium-containing linings (i.e., the first lining 120 and the third lining 240).By preventing the diffusion of cobalt from the second cover layer 256, depletion of the second cover layer 256 can be avoided, thus improving the electromigration properties. In particular, cobalt atoms from the second lining 130 saturate the first and third linings 120, 240, which are made of ruthenium, thereby halting the driving force for cobalt diffusion from the second cover layer 256.

[0047] Therefore, embodiments of the present invention provide copper compound structures with improved electromigration properties. In one embodiment, the improved electromigration properties are achieved by forming a (thin) cobalt lining in direct contact with a ruthenium lining, thus creating a ruthenium lining with cobalt infusion. This infusion is caused by the migration of cobalt atoms from the cobalt lining into the ruthenium lining, which in turn can reduce the driving force for cobalt diffusion from the cobalt lining. In another embodiment, the thin cobalt lining is formed within or between ruthenium linings. In these embodiments, the Ru / Cu interface can be retained, which further improves the copper filling.In yet another embodiment, the cobalt / ruthenium linings can be removed from a lower surface of the interconnect structures, thereby reducing the through-hole resistance in addition to reducing cobalt diffusion from the cobalt covering, thus further improving the performance and reliability of the unit.

Claims

[1] Method for forming a compound structure, comprising: Forming a recess (108) within a dielectric layer (106); shape-adapted deposition of a barrier layer (110) within the recess; Forming a ruthenium lining with cobalt infusion over the barrier layer, the cobalt-containing ruthenium lining comprising: a first lining (120) directly above the barrier layer, wherein the first lining comprises ruthenium; a second lining (130) directly above the first lining, the second lining comprising cobalt; and a third lining (240) directly above the second lining, wherein the third lining contains ruthenium, wherein the ruthenium lining with cobalt infusion is formed by migration of cobalt atoms from the second lining into the first and the third lining; Deposition of a conductive material (242) over the ruthenium lining with cobalt infusion to fill the recess; and Forming a cover layer (256) over an upper surface of the conductive material, wherein the cover layer comprises cobalt. [2] Method according to claim 1, wherein forming the ruthenium lining with cobalt infusion over the barrier layer comprises: Shape-adapted deposition of the first lining above the barrier layer; Form-fitting deposition of the second lining over the first lining; and Shape-adapted deposition of the third lining over the second lining. [3] Method according to claim 1 or claim 2, wherein the formation of the ruthenium lining with cobalt infusion reduces the concentration gradient between the cover layer and the ruthenium lining with cobalt infusion, thereby preventing diffusion of cobalt atoms from the cover layer. [4] Method according to claim 1 or claim 2, wherein the thickness of the second lining is less than the thickness of the first lining. [5] Method according to claim 1 or claim 2, wherein the thickness of the second lining is greater than the thickness of the first lining. [6] Method according to claim 2, wherein the thickness of the second lining is less than the thickness of the third lining. [7] Method according to claim 1 or claim 2, wherein the conductive material comprises copper. [8] Method according to claim 1 or claim 2, wherein the barrier layer comprises tantalum nitride. [9] Method according to claim 1 or claim 2, further comprising performing a planarization process to remove excess conductive material from the connection structure. [10] Method according to claim 2, further comprising selectively removing sections of the first lining, sections of the second lining and sections of the third lining parallel to the dielectric layer from a lower zone of the interconnect structure, wherein remaining sections of the first lining, the second lining and the third lining remain on side walls of the interconnect structure. [11] Method according to claim 10, wherein the through-hole resistance is reduced by selectively removing the sections of the first lining, the sections of the second lining and the sections of the third lining parallel to the dielectric layer from the lower zone of the interconnect structure. [12] Semiconductor structure (100), comprising: a connection structure within a dielectric layer (106), wherein the connection structure has: a barrier layer (110) which is arranged on a lower surface and on side walls of the connecting structure; a first lining (120) directly above the barrier layer, wherein the first lining comprises ruthenium; a second lining (130) directly above the first lining, the second lining comprising cobalt; a third lining (240) directly above the second lining, the third lining having ruthenium; a conductive material (242) over the second lining, which substantially fills the connecting structure; and a covering layer (256) directly over the conductive material, wherein the covering layer comprises cobalt, wherein a ruthenium lining with cobalt infusion is formed by migration of cobalt atoms from the second lining into the first and third linings. [13] Semiconductor structure according to claim 12, wherein the ruthenium lining with cobalt infusion reduces a concentration gradient between the cover layer and the ruthenium lining with cobalt infusion and prevents diffusion of cobalt atoms from the cover layer. [14] Semiconductor structure according to claim 13, wherein sections of the first lining, sections of the second lining and sections of the third lining remain on side walls of the interconnect structure and a lower section of the interconnect structure is covered only by the barrier layer. [15] Semiconductor structure according to claim 14, wherein the thickness of the second lining is less than the thickness of the first lining and the third lining. [16] Semiconductor structure according to claim 12, wherein the conductive material comprises copper and the barrier layer comprises tantalum nitride.

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