Manufacturing process for semiconductor silicon wafers

Abstract

Method for producing a semiconductor silicon wafer, which is composed of a silicon wafer substrate and a monocrystalline silicon epitaxial layer on it, comprising: a step (S4) of forming a silicon oxide layer with a thickness of at least 300 nm and at most 700 nm on the back side of the silicon wafer substrate, wherein the silicon wafer substrate is produced from a silicon ingot grown by the Czochralski process, is doped with phosphorus, has a resistivity adjusted to at most 1.05 mΩ·cm and contains defects which are essentially Si-P crystal defects formed by the aggregation of phosphorus in the crystal; a step (S5) of high-gloss polishing of a silicon wafer substrate; a step (S8) of the heat treatment to hold the silicon wafer substrate mounted on a substrate holder at a constant temperature of at least 700 °C and at most 850 °C for at least 30 minutes and at most 120 minutes at a process gas flow velocity of at least 0.1 m / s and at most 1.0 m / s at a distance of within 5 mm from the silicon wafer substrate and then, after increasing the temperature, at a constant temperature of at least 1100 °C and at most 1250 °C for at least 30 minutes and at most 120 minutes, maintaining the process gas flow velocity, wherein the substrate holder, which is made of silicon or silicon carbide, has a silicon oxide layer (4a1) on the surface with a thickness of at least 200 nm and at most 500 nm and satisfies a relation equation Y = C - X, where X denotes the thickness of the silicon oxide layer (4a1) of the substrate holder and Y denotes the thickness of the silicon oxide layer (4a1) formed on the back of the silicon wafer substrate, and C denotes a constant with a value of 800 to 1000; a step (S11) of removing the silicon oxide layer (4a1) on the back side of the silicon wafer substrate by circumferential machining to a distance of 0.1 mm to 1.0 mm from the circumferential periphery of the silicon wafer substrate after heat treatment; and a step (S13) of depositing a monocrystalline silicon epitaxy layer with a thickness of at least 1.3 µm and at most 10.0 µm.

Description

Technical field

[0001] The present invention relates to a method for producing semiconductor silicon wafers, in particular a method for producing a semiconductor silicon wafer which is composed of a silicon wafer substrate and a monocrystalline silicon epitaxy layer which is to be formed thereon, wherein the silicon wafer substrate is doped with phosphorus P and has a specific resistance of at most 1.05 mΩ·cm. Technical background

[0002] The specific resistance of the most advanced epitaxial wafer for power metal-oxide-semiconductor field-effect transistors (MOS-FETs) is at most 1.00 mΩ·cm. To further reduce the specific resistance of the substrate, the dopant concentration must be increased. Therefore, the n-type dopant has shifted from arsenic and antimony to phosphorus (P), which has relatively low volatility and whose concentration is approximately 1 × 10⁻⁶. 20 atoms / cm² 3 amounts.

[0003] As described in JP 5 845 143 B2 and JP 6 477 210 B2, the growth of an epitaxial layer with an increased dopant concentration leads to the formation of stacking defects (hereinafter also referred to as SF) in the epitaxial layer. SF can occur particularly with substrates having a resistivity of at most 1.1 mΩ·cm.

[0004] Patent documents JP 5 845 143 B2 and JP 6 477 210 B2 describe the suspected cause of crystal defects originating from SF6, which are attributed to phosphorus (P) and oxygen (O) clusters. Furthermore, documents JP 5 845 143 B2 and JP 6 477 210 B2 also report on technologies for preventing crystal defects during heat treatment and epitaxial growth.

[0005] In particular, clusters of phosphorus and oxygen (microprecipitates) are formed in a heavily phosphorus-doped silicon wafer. To then remove the natural oxide layer on the surface of the silicon wafer, the clusters are selectively etched by heat treatment in a hydrogen gas atmosphere (hereinafter referred to as hydrogen flame treatment). This process, due to the etching action of the hydrogen and the difference in etching rate between the outermost surface of the silicon wafer and the clusters, results in the formation of fine pits. Documents JP 5 845 143 B2 and JP 6 477 210 B2 report that it is suspected that during the growth of an epitaxial layer on a silicon wafer in which the micropits are formed, SF6 (sulfur-free precipitates) originating from the micropits are generated in the epitaxial layer.

[0006] JP 5 845 143 B2 discloses a method for producing an epitaxial silicon wafer, which has: a step in the formation of an oxide layer on the back of a silicon wafer cut from a single crystal block produced using the CZ process, a step to remove the oxide layer that is present on the outer circumference of the silicon wafer, a step of argon annealing in which the silicon wafer, after removal of the backside oxide, is heat-treated at a temperature of 1200 °C and at most 1220 °C in at least an argon atmosphere, a step of the hydrogen firing process in which the wafer is heat-treated in a hydrogen atmosphere for at least 30 seconds and at most 300 seconds after the argon annealing step, at a temperature of at least 1050 °C and at most 1200 °C, and a step in the growth of an epitaxial layer on the surface of the silicon wafer after the hydrogen firing process.

[0007] Document JP 5 845 143 B2 also describes how SF (SF) in the epitaxial layer can be prevented by the above-mentioned procedural steps.

[0008] JP 6 477 210 B2 also describes, similar to JP 5 845 143 B2, a method for producing an epitaxial silicon wafer that prevents the occurrence of SF in the epitaxial layer.

[0009] The heat treatment described in JP 5 845 143 B2 and JP 6 477 210 B2 is generally carried out with a view to productivity by mounting several substrates on the substrate holder and processing them all at once in a batch process. Summary of the invention: Technical problem

[0010] Studies by the present inventors demonstrate that the countermeasures described in JP 5 845 143 B2 and JP 6 477 210 B2 are not sufficient to reduce SF.

[0011] In their experiments, monocrystalline silicon wafers doped with phosphorus and with a resistivity of 0.8 mΩ·cm and an oxygen concentration of 0.8×10 18 / cm 3 exhibiting which were grown using the Czochralski method, heat-treated for one hour in an argon atmosphere at 1200 °C.

[0012] Subsequently, after hydrogen firing at 1180 °C for 60 seconds in a hydrogen gas atmosphere, an epitaxial layer 3 µm thick was grown on the wafer surface. The number of LPDs with a size of at least 90 nm was then evaluated using SP-1, manufactured by KLA-Tencor Corporation, in DCN mode. The density of the LPDs originating from SF6 was found to be at least 10⁻⁶ / cm³. 2 is, i.e., not less than 3140 per wafer.

[0013] As shown above, it is difficult to prevent the formation of SF6 even if the concentration of oxygen in the solid solution in the surface layer is sufficiently reduced by heat treatment under an argon gas atmosphere.

[0014] The inventors of this invention have intensively studied the prevention of SF in an epitaxial layer. As a result, they discovered that the cause of SF in the epitaxial layer is P aggregation defects, i.e., Si-P defects formed from phosphorus and silicon.

[0015] Furthermore, they found that P aggregation defects (Si-P defects) contain an internal additional Si layer (SF) which becomes a crystal strain on the substrate surface, present prior to the deposition of the epitaxial layer and forming SF that spreads as the epitaxial layer (epi-layer) grows.

[0016] The Si-P defects, as shown in the publications "SENDA, Takeshi [et al.]: "Atomic structures of grown-in Si-P precipitates in red-phosphorus heavily doped CZ-Si crystals" in "29th International Conference on Defects in Semiconductors" and "SENDA, Takeshi [et al.]: "Atomic structures of grown-in Si-P defects in red-phosphorus heavily doped CZ-Si crystals" in "The 78th JSAP Autumn Meeting", are platelet-shaped defects containing silicon and a few atomic percent of phosphorus. The phosphorus atoms are not located at the atomic site but interstitially, and excess silicon atoms (extrinsic SF) are also present.

[0017] The phosphorus concentration, estimated from the specific resistivity around the defects, is approximately 0.2 atomic percent; the phosphorus aggregates locally, and the epitaxial layer contains crystal stresses.

[0018] The inventors also found that it is difficult to prevent SF caused by P aggregation defects (Si-P defects) using the techniques described in documents JP 5 845 143 B2 and JP 6 477 210 B2, and that it is necessary to optimize all processes such as heat treatment and epitaxial layer growth, and have thus completed the present invention.

[0019] Furthermore, the inventors have intensively addressed the technical problem that the diffusion of phosphorus (P) as a dopant from the phosphorus (P) doped substrate during processes such as heat treatment and epitaxial layer growth to suppress SF, which originated from P aggregation defects (Si-P defects), leads to variations in the specific resistance of the epitaxial layer (epi-layer) and the active layer formed therein.

[0020] A silicon oxide layer is typically formed on the back side of the silicon wafer in the case of power metal oxide field-effect transistors (power MOSFETs). This silicon oxide layer serves to prevent self-doping during epitaxial layer deposition.

[0021] Meanwhile, the silicon oxide layer is etched by the furnace gas during heat treatment. There is a risk of extreme thinning of the silicon oxide layer thickness due to direct reduction by the substrate holder material at the substrate's holding position, or a risk of exposing the substrate surface.

[0022] As a result, there is a risk that a variation in the specific resistance of the epitaxial layer (epi-layer) or the active layer of the devices to be manufactured therein will be caused by the diffusion of phosphorus (P) as a dopant from the heavily phosphorus-doped substrate.

[0023] The intensive study leads the inventors to make an invention with the acquired knowledge that the diffusion of phosphorus (doping agent) from the P-doped substrate and the variation of the specific resistance in the epitaxial layer (epi-layer) or the active layer in the devices to be built in the epitaxial layer are suppressed when a certain ratio between the thickness of the silicon oxide layer formed on the back of the wafer and that of the silicon oxide layer formed on the substrate holder is present in processes such as heat treatment and epitaxial layer growth in order to suppress SF originating from P aggregation defects (Si-P defects).

[0024] The present invention was made taking these circumstances into account and aims to provide a manufacturing process for silicon wafers that is able to suppress the generation of P aggregation defects (Si-P defects), the occurrence of SF in the epitaxial layers and the variation of the specific resistance.

[0025] Furthermore, JP 2016-213232A discloses a method for producing an epitaxial silicon wafer, comprising: a step for forming an oxide layer on the back side of a silicon wafer; a step for removing the oxide layer on the back side to remove the oxide layer present on an outer edge region of the silicon wafer; an argon annealing step to perform heat treatment under an argon gas atmosphere; and a step for forming an epitaxial layer to create an epitaxial layer on a surface of the silicon wafer. JP 2019-142733A discloses a method for predicting the formation of lamination defects in an epitaxial silicon wafer. JP 2017-88460A discloses a method for producing an epitaxial wafer comprising a build-up step and a growth step.DE 11 2014 002 133 T5 discloses a manufacturing process for a single crystal using a single-crystal pulling device. JP 2010 - 205 866 A discloses a process for manufacturing a silicon epitaxy wafer. Problem solving

[0026] The method for producing semiconductor silicon wafers according to the present invention, which was made to solve the above problem, comprises: a step of forming a silicon oxide layer with a thickness of at least 300 nm and less than 700 nm on a back side of a silicon wafer substrate, wherein the silicon wafer substrate is produced from a Si single crystal block grown by the Czochralski process, wherein the silicon wafer substrate has a dopant of phosphorus (P) adjusted to a specific resistance of at most 1.05 mΩ·cm and contains defects formed by the aggregation of P in the crystal, which consist essentially of a Si-P crystal defect; a step in the high-gloss polishing of the silicon wafer substrate; After the polishing step, a heat treatment step is performed to maintain the silicon wafer substrate mounted on a substrate holder at a constant temperature of at least 700 °C and at most 850 °C for at least 30 minutes and at most 120 minutes at a process gas flow velocity of at least 0.1 m / s and at most 1.0 m / s at a distance of within 5 mm from the silicon wafer substrate, and then, after increasing the temperature, at a constant temperature of at least 1100 °C and at most 1250 °C for at least 30 minutes and at most 120 minutes, maintaining the process gas flow velocity, and the substrate holder, which is made of silicon (Si) or silicon carbide (SiC), has a silicon oxide layer on its surface with a thickness of at least 200 nm and at most 500 nm and satisfies a relation equation Y = C - X.where X denotes the thickness of the silicon oxide layer of the substrate holder, Y denotes the thickness of the silicon oxide layer formed on the back of the silicon wafer substrate, and C denotes a constant with a value of 800 to 1000.

[0027] Consequently, the silicon wafer manufacturing process according to the invention makes it possible to prevent the formation of SF6 in the epitaxial layer, since the formation of P-aggregation defects (Si-P defects) is prevented during the heat treatment step. In particular, the silicon wafer substrates to be used in the present invention are those that are doped with phosphorus and adjusted to have a resistivity of at most 1.05 mΩ·cm and contain defects formed by the aggregation of phosphorus in the crystal, which are essentially Si-P crystal defects.

[0028] It is desirable that the maximum side length of the Si-P crystal defects be less than 100 nm and their density less than 10 12 / cm 3 If the maximum side length is at least 100 nm, Si-P defects appear as SF (Light Point Defect; LPD) after the epitaxial layer formation process. Furthermore, it is undesirable because if the density of Si-P defects is not less than 1 × 10 12 / cm 3 When the value is high, the number of SFs increases significantly.

[0029] Furthermore, the diffusion of phosphorus as a dopant from the silicon wafer substrate is prevented, and the variation of the specific resistance in the epitaxial layer (epi-layer) and in the active layer of the components formed therein is prevented because a silicon oxide layer with a thickness of at least 300 nm and at most 700 nm is formed on the back of the silicon wafer substrate, and the silicon wafer substrate is heat-treated and mounted on the substrate holder on which a silicon oxide layer of a certain thickness is formed.

[0030] While the flow rate of the process gas within a distance of 5 mm from the silicon wafer substrate is not less than 0.1 m / s and not more than 1 m / s, the silicon wafer substrate is held at a constant temperature of not less than 700 °C and not more than 850 °C for not less than 30 minutes and not more than 120 minutes.

[0031] During thermal processing at a temperature of at least 700 °C, impurities, moisture, and oxygen are desorbed from the silicon oxide layer formed on the back of the wafer. In contrast, the surface of the silicon wafer substrate reacts when thermally treated at a temperature of at least 850 °C. Therefore, the surface roughness of the wafer deteriorates during thermal treatment at a temperature of at least 850 °C due to the impurities desorbed from the silicon oxide layer.

[0032] In the present invention, the deterioration of surface roughness caused by impurities desorbed from the silicon oxide layer is prevented by maintaining the wafer at a constant temperature of not less than 700 °C and not more than 850 °C. Since the growth temperature of phosphorus aggregation defects (Si-P defects) is below 700 °C and the temperature required to eliminate these defects is not below 700 °C, maintaining the wafer at a constant temperature of not less than 700 °C and not more than 850 °C enables the reduction of phosphorus aggregation defects (Si-P defects). The holding time of the silicon wafer substrate in this temperature range is at least 30 minutes and at most 120 minutes.

[0033] A holding time shorter than 30 minutes is not desirable because the compaction of the silicon oxide layer is insufficient and P aggregation defects (Si-P defects) cannot be eliminated, and a holding time longer than 120 minutes is not desirable because productivity decreases.

[0034] The flow velocity of the process gas at a distance of less than 5 mm from the silicon wafer substrate is set to not less than 0.1 m / s and not more than 1.0 m / s, taking into account the etching of the oxide layer on the back of the silicon wafer substrate.

[0035] It is undesirable because, if the process gas flow velocity is less than 0.1 m / s, the gas flow in the furnace is not rectified and becomes a source of contamination; and it is undesirable because, if the flow velocity is greater than 1.0 m / s, etching of the oxide layer on the back side of the silicon wafer substrate is promoted. The phrase "within 5 mm of the silicon wafer substrate" means that the distance from the back side of the silicon wafer substrate is within 5 mm, and the reason for specifying the distance as within 5 mm is that the distance determines the extent of etching of the oxide layer on the back side of the silicon wafer substrate.

[0036] After the silicon wafer substrate is held at a constant temperature of not less than 700 °C and not more than 850 °C for not less than 30 minutes and not more than 120 minutes, the temperature is increased while maintaining the flow rate of the process gas, and the silicon wafer substrate is held at a constant temperature of not less than 1100 °C and not more than 1250 °C for not less than 30 minutes and not more than 120 minutes.

[0037] Maintaining the silicon wafer substrate at a constant temperature of not less than 1100 °C and not more than 1250 °C for not less than 30 minutes and not more than 120 minutes serves to relax the stresses caused by Si-P defects, and the relaxation of the stresses caused by Si-P defects enables the prevention of P aggregation defects (Si-P defects).

[0038] Subsequently, the temperature of the silicon wafer substrate is lowered, and the experience time of the wafers at a temperature of at most 700 °C and at least 450 °C is preferably reduced to less than 10 minutes. By shortening the transit time through the temperature range of 700 °C to 450 °C, phosphorus aggregation defects (Si-P defects) can be prevented.

[0039] The process gas used in heat treatment is a gas mixture of hydrogen (H2) and argon (Ar).

[0040] Since the heat treatment of silicon wafers, as described above, is carried out with a gas mixture of hydrogen (H₂) and argon (Ar), impurities such as moisture in the oxide layer are reduced at a hydrogen partial pressure of 80 to 50% and a temperature of less than 850 °C. As a result, densification is promoted. If the hydrogen partial pressure is 0.01% to 20% and the temperature is at least 850 °C, the reduction of the silicon dioxide layer (SiO₂) by hydrogen (H₂) is preferably suppressed, and the decrease in thickness is preferably prevented.

[0041] After the heat treatment step, the oxide layer on the back of the silicon wafer substrate is removed by machining at a distance of 0.1 mm to 1.0 mm from the circumference. The phrase "distance of 0.1 mm to 1.0 mm from the circumference" means that the distance from the circumference of the silicon wafer substrate inwards is between 0.1 mm and 1.0 mm.

[0042] The reason the oxide layer on the back of the silicon wafer substrate is removed by grinding to a specific distance of 0.1 mm to 1.0 mm from the circumference is that the removed section is the point from which phosphorus diffuses out during prolonged heat treatment. Therefore, diffusion of phosphorus from this point during the epitaxial layer formation process is prevented, thus counteracting self-doping. It should be noted that the removed area is very small, and the amount of phosphorus diffusing into the wafer after prolonged heat treatment is negligible.

[0043] Furthermore, it is undesirable that the above-mentioned effect is not achievable if the distance length of the silicon oxide layer is less than 0.1 mm, and if, on the other hand, the distance of the silicon oxide layer is more than 1.0 mm, the mechanical damage caused by the substrate holder during the prolonged heat treatment and the epitaxial layer formation process increases due to the enlargement of the area without the oxide layer.

[0044] Following heat treatment, a monocrystalline silicon epitaxial layer with a thickness of at least 1.3 µm and at most 10 µm is deposited. If the thickness of the monocrystalline silicon epitaxial layer is less than 1.3 µm, controlling the electrical properties during operation of the device becomes difficult. A layer thickness exceeding 10 µm is undesirable for cost reasons.

[0045] As described above, according to the present invention, SF in the epitaxial layer can ultimately be prevented by preventing phosphorus aggregation defects (Si-P defects) during the heat treatment step. As described above, according to the present invention, the diffusion of phosphorus as a dopant from the silicon wafer substrate is further prevented, and the resistance variation in the epitaxial layer (epi-layer) and in the active layer of the devices to be formed therein can be suppressed.

[0046] The substrate holder has a holding surface for holding the silicon wafer substrate, and it is preferred to set the angle between the perpendicular line to the holding surface and the perpendicular line to the silicon wafer substrate surface to be held to at least 0.5 degrees and at most 5.0 degrees.

[0047] If the angle between the perpendicular line to the holding surface and the perpendicular line to the silicon wafer substrate surface is less than 0.5 degrees, the thicknesses of the oxide layers on both the back of the wafer and on the substrate holder decrease significantly due to the increase in the contact area between them, which is undesirable.

[0048] On the other hand, if the angle between the perpendicular line to the holding surface and the perpendicular line to the surface of the held silicon wafer substrate is more than 0.5 degrees, the holding position will be towards the beveled part of the wafer and the beveled part will be easily damaged, which is undesirable.

[0049] It is preferred that the substrate holder holds multiple silicon wafer substrates and that the distance between the silicon wafer substrates is at least 10 mm and at most 15 mm. A distance of less than 10 mm between the silicon wafer substrates is not preferred, as the surfaces of opposing wafers are continuously oxidized and etched in the vapor phase by the decomposing oxide layer, leading to an increase in surface roughness. A distance of more than 15 mm between the silicon wafer substrates is undesirable because productivity decreases due to the smaller number of wafers processed.

[0050] The silicon oxide layer on the surface of the substrate holder is preferably formed using two source gases, oxygen and nitrogen, at a temperature of at least 1000 °C. The reason for using oxygen and nitrogen as the source gases is that the layer to be formed is an oxynitride, and this prevents the decomposition of the silicon oxide layer by a chemical reaction.

[0051] It is desirable that the process gas for heat treatment in a temperature range of at least 700 °C to less than 850 °C is a dilute argon gas with hydrogen, whose partial pressure is in a range of 50% to 80%, and that the process gas at a higher temperature of at least 850 °C is a dilute argon gas with hydrogen, whose partial pressure is in a range of 0.01% to 20%.

[0052] The reason the process gas for heat treatment in a temperature range of at least 700 °C to less than 850 °C is a dilute argon gas with hydrogen, whose partial pressure is in the range of 50% to 80%, is to promote the densification of the silicon oxide layer. This is because impurities such as moisture in the oxide layer are reduced at temperatures below 850 °C in a dilute argon gas with hydrogen, whose partial pressure is in the range of 50% to 80%. The reason the process gas is a dilute argon gas with hydrogen, whose partial pressure is in the range of 0.01% to 20%, at temperatures below 700 °C and at least 850 °C is to prevent the reduction of the oxide layer (SiO₂) by hydrogen (H₂).

[0053] On silicon wafer substrates, a surface cleaning step is carried out prior to the formation of an epitaxial layer, in which the surface silicon is preferably removed to a depth of at least 50 nm and at most 150 nm by etching with a mixed gas of hydrogen (H2), hydrogen chloride (HCl) and Si-H-Cl gas.

[0054] Consequently, by performing the cleaning step, the SF can be further reduced after the growth of the epitaxial layer.

[0055] In this case, the elimination of defects by hydrogen chloride HCl is effective, and the elimination of defects by a mixed gas of hydrogen H2 and hydrogen chloride HCl is also desirable.

[0056] However, the remaining depth of the defects is at most 100 nm, and etching the silicon surface to a depth of at least 50 nm to at most 150 nm is appropriate when productivity is taken into account.

[0057] Silicon is preferably deposited at a temperature of at least 1100 °C and at most 1150 °C at a deposition rate of at least 3.5 µm / min and at most 6.0 µm / min.

[0058] It was found that LPD is prevented by setting the temperature to at least 1100 °C and at most 1150 °C and the deposition rate to at least 3.5 µm / min and at most 6.0 µm / min.

[0059] The reason why the single-crystal silicon epitaxial layer is deposited with a thickness of at least 1.3 µm and at most 10 µm is as follows: It is undesirable because the single-crystal silicon epitaxial layer deposited with a thickness of less than 1.3 µm cannot withstand the electrical voltage applied during the device process, and the layer with a thickness of more than 10.0 µm increases the cost of the epitaxial wafers. Advantageous effect of the invention

[0060] According to the present invention, a manufacturing process for semiconductor silicon wafers is provided by which P aggregation defects (P-Si defects) are prevented, SF in the epitaxial layer is prevented and resistance variations are prevented. Brief description of the drawings Fig. 1 is a flowchart of an embodiment of a manufacturing process for silicon wafers according to the present invention; Fig. 2 is the continuation of the flowchart of Fig. 1 of the embodiment of the manufacturing process for silicon wafers according to the present invention; Fig. 3 is the continuation of the flowchart of the Fig. 2 of the embodiment of the manufacturing process for silicon wafers according to the present invention; Fig. Figure 4 is a schematic drawing that illustrates the chemical reaction between the silicon oxide layer formed on the back of the silicon wafer substrate and the silicon oxide layer formed on the substrate holder; Fig. Figure 5 shows the ratio between the thickness of the silicon oxide layer formed on the back of the silicon wafer substrate and the thickness of the silicon oxide layer formed on the substrate holder; Fig. Figure 6 is a drawing that depicts the vertical type substrate holder; Fig. 7 is a partially enlarged view of the in Fig. 6 substrate holders shown; Fig. Figure 8 shows the dependence of the number of LPDs on the growth temperature of the silicon layer and the growth rate; Fig. 9 is an overview of a lifting device with a water cooler; Fig. Figure 10 is a diagram showing the results of Experiment 1; Fig. Figure 11 is a diagram showing the results of Experiment 2; Fig. Figure 12 is a diagram showing the results of Experiment 3; Fig. Figure 13 is a diagram showing the results of experiment 5; Fig. Figure 14 is a diagram showing the results of experiment 6; Fig. Figure 15 is a diagram showing the results of experiment 7; and Fig. Figure 16 is a diagram showing the results of experiment 8. Description of the embodiments

[0061] Embodiments of the inventive method for producing silicon wafers are described with reference to the Fig. Sections 1 to 3 are described in detail. The embodiments shown below are examples and the invention is not limited to these embodiments.

[0062] As in Fig. As shown in Figure 1, a silicon single crystal is grown using the Czochralski (CZ) method to produce a silicon single-crystal block (step S1). In this step, a phosphorus (P)-doped silicon single crystal is grown at a rate of at least 0.5 mm / min and at most 1.0 mm / min under an applied magnetic field of at least 2000 G and at most 4000 G.

[0063] The reason why the draw-up speed is set in the range of 0.5 mm / min to 1.0 mm / min is that the ratio G / V must be large to suppress the occurrence of the phenomenon of constitutional undercooling, in which crystals grow in a cell-like form in a region of low resistance, where G is the temperature slope of the melt and V is the draw-up speed.

[0064] This means that the phenomenon of constitutional undercooling can be suppressed by reducing the pull-up rate V. However, reducing the pull-up rate does not prevent the formation of p-aggregation defects (Si-P defects), as the throughput time increases at temperatures of up to 700 °C, i.e., within a temperature range of 600 °C to 700 °C.

[0065] For this reason, by installing a water cooler in the drawing furnace for forced cooling of the crystals, setting the drawing speed to at least 0.5 and at most 1.0 mm / min, and applying a magnetic field of at least 2000 and 4000 gauss, the temperature gradient G is increased, the constitutional undercooling phenomenon is suppressed, and phosphate aggregation defects (Si-P defects) are suppressed. This manufacturing condition is essential for shortening the throughput time, because during crystal growth, the temperature range between 600 °C and 700 °C is the range that promotes the growth of Si-P defects.

[0066] This is particularly undesirable because P aggregation defects (Si-P defects) cannot be prevented at a drawing rate of less than 0.5 mm / min, and the phenomenon of constitutional undercooling cannot be suppressed at a drawing rate of more than 1.0 mm / min.

[0067] The grown crystal is forced-cooled by the water cooler located in the tuyere furnace. As in Fig. As shown in Figure 9, for example, the grown silicon single crystal 15 is forcibly cooled by means of the water cooler, which is arranged in a space between the upper area of ​​the drawing furnace 2 and the radiation shield 4 in the drawing device 11, thereby shortening the throughput time in a temperature range of at least 600 °C to at most 700 °C. Fig. 9 designates the reference digit 16 the quartz glass crucible, the digit 17 the heating element, the digit 18 the magnetic field application unit, and the digit 19 the wire for growing a silicon single crystal 15.

[0068] Consequently, the grown silicon single crystal is forcibly cooled to a temperature of less than 600 °C. As in Fig. As shown in Figure 4, P aggregation defects (Si-P defects) are prevented by shortening the experience time of the wafers in a temperature range of at least 600 °C to a maximum of 700 °C.

[0069] Silicon wafer substrates are produced by cutting a silicon single-crystal block at an angle of 0.1° to 0.4° against the principal face orientation (step S2).

[0070] The cutting angle of the silicon wafer substrates influences the growth and removal of SF at the time of epitaxial layer deposition. The principal surface orientation is Si(100) and the cutting angle is between 0.1 and 0.4 degrees.

[0071] A silicon step terrace, which would provide a path for the movement of silicon atoms during epitaxial layer formation to eliminate stacking fault defects, is formed by setting the cut angle in a range of 0.1 degrees to 0.4 degrees relative to the principal surface orientation. The formation of the silicon step terrace allows the silicon atoms to move along the terrace. This movement enables the elimination of stress on the silicon atoms and the removal of stacking fault defects.

[0072] The silicon wafer substrates produced in this way exhibit a specific resistance of at most 1.05 mΩ·cm and an oxygen concentration in solid solution of at most 0.9×10 18 atoms / cm² 3 and contain Si-P defects, which are essentially caused by aggregation of phosphorus in the crystal (step S3).

[0073] Silicon wafer substrates used in technical applications have a specific resistance of at most 1.05 mΩ·cm and an oxygen concentration in solid solution of at most 0.9 × 10 18 atoms / cm² 3 Si-P crystal defects are prevented by the silicon wafer substrate process described above (steps S1 and S2), but Si-P crystal defects still remain; the silicon wafer substrates contain Si-P crystal defects. The values ​​mentioned above for resistivity and oxygen concentration in solid solution can be achieved by adjusting the dopant concentration, the pull-up speed, and the magnetic field strength.

[0074] The dopant concentration, the pull-up speed, and the strength of the magnetic field can be varied to achieve the specified specific resistance and oxygen concentration in the solid solution.

[0075] The Si-P defects of the silicon wafer substrates produced in this way preferably have a side length of less than 100 nm and a defect concentration of less than 1×10 12 / cm 3 on.

[0076] If the maximum side length of the Si-P defects is at least 100 nm, the Si-P defects manifest as SF (LPD) after the formation of the epitaxial layer. If the density of the Si-P defects is at least 1 × 10 12 / cm 3 SF (LPD) remains the same.

[0077] Therefore, it is desirable that the maximum side length of the Si-P defects is less than 100 nm and the density of the Si-P defects is less than 1×10 12 / cm 3 is and the crystal growth thus set is carried out in a desirable manner.

[0078] Next, a silicon oxide layer is formed on the back side of the silicon wafer substrate (step S4). In power MOSFET devices, a silicon oxide layer is generally formed on the back side of the wafer, and the silicon oxide layer is formed, for example, by low-temperature CVD at a temperature of less than 500 °C.

[0079] The oxide layer on the back side serves to prevent self-doping during the growth of the epitaxial layer. This oxide layer typically forms to a thickness of 300 nm to 700 nm in a reduced-pressure atmosphere at a temperature of 400 °C to 500 °C.

[0080] Furthermore, the thickness of the silicon oxide layer of the substrate holder described later, denoted by X, and the thickness of the silicon oxide layer formed on the back of the silicon wafer substrate, denoted by Y, satisfy the relation expression Y=CX, where C is a constant with a value of 800 to 1000.

[0081] Since the thickness of the silicon oxide layer of the substrate holder described below, denoted by X, and the thickness of the silicon oxide layer formed on the back of the silicon wafer substrate, denoted by Y, fall within a certain range as indicated above, the diffusion of phosphorus P as a dopant from the silicon wafer substrate can be prevented, and the variation in the resistivity of the epitaxial layer (epi-layer) and the active layer of the devices formed therein can be suppressed when the silicon wafer substrate mounted on the substrate holder is subjected to heat treatment.

[0082] If it is described in particular how in Fig. Figure 4 shows how silicon dioxide SiO2 desorbs from the silicon oxide layer (low temperature oxide; LTO) formed on the back side of the silicon wafer substrate: Si + SiO2 → 2SiO (Gas).

[0083] The desorbed SiO (gas) oxidizes the silicon oxide layer (thermal oxide layer) on the substrate holder, the silicon boat or silicon carbide, on whose surface a silicon oxide layer forms, and silicon is released: 2SiO (gas) + SiO2 → 2SiO2 + Si.

[0084] SiO (gas) also desorbs from the silicon oxide layer (thermal oxide layer) of the substrate holder, the Si boat, but is negligible, as the amount is 1 / 100 of the amount of silicon oxide (LTO) that forms on the back of the silicon wafer substrate.

[0085] Consequently, if the silicon oxide layer (thermal oxide layer) on the substrate holder becomes oxidized, it is difficult to keep the silicon wafer substrate in the same condition and to mount it.

[0086] Therefore, it is necessary to specify the thickness of the oxide layer of both the silicon oxide layer formed on the back of the silicon wafer substrate and the silicon oxide layer (thermal oxide layer) of the substrate holder.

[0087] To prevent the diffusion of silicon into the layer and the subsequent diffusion of dopants outwards, the thickness of the silicon oxide layer (LTO) formed on the back of the silicon wafer substrate should be at least 300 nm and at most 700 nm, and the thickness of the silicon oxide layer (thermal oxide layer) on the substrate holder, the Si boat, should be at least 200 nm and at most 500 nm.

[0088] If the thickness of the silicon oxide layer formed on the back side of the silicon wafer substrate is less than 300 nm, self-doping from the silicon wafer substrate is significant because phosphorus migrates through the oxide layer, which is undesirable. If the thickness exceeds 700 nm, this is not desirable because it reduces productivity and increases costs.

[0089] Furthermore, it is not preferred that the thickness of the silicon oxide layer (thermal oxide layer) on the substrate holder be less than 200 nm, as the decrease in the oxide layer on the back of the silicon wafer substrate becomes significant, and it is not preferred that the thickness exceed 500 nm, as productivity decreases and costs increase.

[0090] The thickness variation of the silicon oxide layer (thermal oxide layer) of the substrate holder decreases when the increase in thickness of the silicon oxide layer (thermal oxide layer) of the substrate holder due to the addition of SiO₂ (gas) from the silicon oxide layer formed on the back of the silicon wafer substrate equals the decrease in thickness of the silicon oxide layer (thermal oxide layer) of the substrate holder due to oxidation. Excessive thickening can lead to an increase in costs.

[0091] As in Fig. As shown in Figure 4, SiO₂ desorbs from the silicon oxide layer (LTO) formed on the back side of the silicon wafer substrate. The desorbed SiO₂ diffuses into the thermal oxide layer, oxidizes, and releases Si atoms. When the thermal oxide layer on the substrate holder is oxidized, it is difficult to keep the silicon wafer substrate in a constant state. Therefore, the thickness of the LTO and the thermal oxide layer on the substrate holder must be taken into account. Since the diffusion rates in the LTO and the thermal oxide layer on the substrate holder depend on their thickness, equilibrium in the thickness variation of both layers can be maintained by keeping one thicker and the other thinner. Fig. Figure 5 illustrates this situation, and the shaded area is the corresponding area.

[0092] After the formation of the silicon oxide layer on the back of the silicon wafer substrate, the front side of the silicon wafer substrate is subjected to a high-gloss polishing process (step S5).

[0093] High-gloss polishing is generally achieved through the mechanical action of a polishing cloth and the chemical action of a slurry. High-gloss polishing does not directly reduce silicon-phosphate (Si-P) defects. However, by reducing surface roughness, it prepares the surface for Si-P defects to be eliminated in subsequent heat treatment.

[0094] The oxide layer on the front of the highly polished surface is removed with an acidic solution or in an acidic atmosphere, as in Fig. 2 (step S6) shown.

[0095] To eliminate Si-P defects, it is necessary to remove the natural oxide layer on the front face of the silicon wafer substrate and to clean the silicon surface. As an example of removing the oxide layer with a chemical solution, the process preferably uses hydrofluoric acid diluted with pure water at a concentration of 0.1% to 5% for 30 to 120 s.

[0096] Then the silicon wafer substrate with a silicon oxide layer on the surface is mounted onto the substrate holder made of silicon or silicon carbide (step S7).

[0097] A vertical wafer boat can, for example, be used as a substrate holder, as in Fig. Figure 6 shows that the wafer boat is composed of a base plate 2, a top plate 3, and four columns 4, and is made of silicon (Si) or silicon carbide (SiC). A silicon oxide layer 4a1 is formed on its surface.

[0098] The lower plate 2 is attached to the lower part of the column 4, and the upper plate 3 is attached to the upper part of the columns parallel to the lower plate 21. Several storage sections 4a are formed along the vertical direction of the columns 4, and silicon wafer substrates are attached to the storage section 4a.

[0099] As in Fig. As shown in Figure 7, the vertical wafer boat 1 holds several wafers W. The distance between the wafers being held is between 10 mm and 15 mm. If the distance t between the wafers W is less than 10 mm, the effects of gas desorbed from the oxide layer on the wafer surface are not prevented. If the distance t between the wafers W is more than 15 mm, productivity decreases, which is undesirable.

[0100] As in Fig. As shown in Figure 7, the angle between the perpendicular line L1 to the holding surface of the storage section 4a for holding wafers and the perpendicular line L2 to the surface of the silicon wafer substrate is set to at least 0.5 degrees and at most 5.0 degrees.

[0101] The reason why the angle between the perpendicular line L1 to the holding surface of the tray section 4a for holding wafers and the perpendicular line L2 to the surface of the silicon wafer substrate is set to at least 0.5 degrees and at most 5.0 degrees is that this range makes it possible to reduce and minimize the contact area between the oxide layer formed on the back of the silicon wafer substrate and the substrate holder, the tray section 4a of the vertical boat 1.

[0102] The maximum value is set at 5 degrees, taking into account the typical taper angle of the beveled part of the semiconductor silicon wafer substrates.

[0103] The substrate holder is, for example, a vertical wafer boat 1, as shown in Fig. Figure 7 shows that a silicon oxide layer 4a1 with a thickness X of at least 200 nm and at most 500 nm is formed on the surface of the substrate holder.

[0104] The silicon oxide layer is formed in advance on the substrate holder, such that the thickness X (the silicon oxide layer on the substrate holder) and the thickness Y (the silicon oxide layer on the back of the silicon wafer substrate) satisfy the relation expression Y=CX, where C is a constant in the range of 800 to 1000.

[0105] The silicon oxide layer on the surface of the substrate holder is formed using two source gases (oxygen and nitrogen) at a temperature of at least 1000 °C. A temperature of at least 1000 °C is necessary because the density of the silicon oxide layer is nearly constant at this temperature or higher. To maintain the material's strength, the upper limit is preferably 1200 °C.

[0106] The use of nitrogen as a gas source results in the silicon oxide layer containing silicon nitride (Si3N4), thus increasing the layer's resistance. This is because the reaction inhibits the degradation of the silicon oxide layer by transforming the formed layer into oxynitride.

[0107] Next, the silicon wafer substrate is prepared, as shown in Fig. 2 shown, subjected to a heat treatment to maintain it at a constant temperature of at least 700 °C and at most 850 °C for a minimum of 30 minutes and a maximum of 120 minutes (step S8).

[0108] The silicon oxide layer densifies at a temperature of at least 700 °C, during which impurities, moisture, and oxygen are desorbed from the silicon oxide layer. The surface of the silicon wafer substrate reacts at a temperature of at least 850 °C, and with the presence of desorbed substances as described above, the surface roughness of the wafer increases. The decomposition of aggregated phosphorus in Si-P defects and diffusion are promoted at a temperature of at least 700 °C and at most 850 °C; however, neither an increase in Si-P defects nor a density increase occurs due to the low-temperature zone.

[0109] Accordingly, impurities, moisture and oxygen can be diffused out of the silicon oxide layer by adjusting the temperature of the desorption reaction to the aforementioned temperature range, i.e., to a constant temperature of at least 700 °C and less than 850 °C, and an increase in the surface roughness of the wafers can also be prevented.

[0110] Furthermore, the holding time within the aforementioned temperature range is at least 30 minutes and at most 120 minutes. It is not preferred because diffusion is not promoted if the holding time is less than 30 minutes, and productivity decreases if it exceeds 120 minutes.

[0111] Furthermore, the furnace atmosphere for heat treatment is a mixed gas (process gas) of hydrogen and argon. The reason for using an argon gas diluted with hydrogen at a partial pressure of 50% to 80% is to accelerate the extinction of Si-P defects with hydrogen and to prevent the physical etching of the silicon oxide layer by hydrogen (H₂).

[0112] The flow velocity of the process gas, which consists of hydrogen H2 and argon Ar, is not less than 0.1 m / s and not more than 1 m / s at a distance of 5 mm from the silicon wafer substrate.

[0113] The reason the process gas flow rate is limited to a maximum of 1 m / s within a 5 mm distance of the silicon wafer substrate is to prevent the desorption of gases from the oxide layer on the back of the silicon wafer substrate. Furthermore, repetitive reactions are suppressed because the density of SiO₂ gas and other gases increases.

[0114] It is not preferred that the gas flow in the furnace is not unidirectional and that this becomes a cause of impurities when the process gas flow velocity is less than 0.1 m / s, and it is not preferred that the etching of the oxide layer on the back side of the silicon wafer substrate is promoted when the flow velocity is greater than 1.0 m / s. The expression "within 5 mm of the silicon wafer substrate" means that the distance from the back side of the silicon wafer substrate is within 5 mm, and the reason for specifying the distance as within 5 mm is to take into account the area of ​​influence of the flow velocity, which determines the degree of oxide layer etching.

[0115] After the temperature has been increased, the silicon wafer substrate is subsequently held at a constant temperature of at least 1100 °C and at most 1250 °C for at least 30 minutes and at most 120 minutes (step S9). The furnace atmosphere for the heat treatment is a gas mixture of hydrogen (H2) and argon (Ar), similar to that in step S8, and the flow rate is maintained.

[0116] Therefore, by maintaining the silicon wafer substrate at a constant temperature of not less than 1100 °C and not more than 1250 °C for not less than 30 minutes and not more than 120 minutes, the relaxation of stresses due to Si-P defects is achieved, and the relaxation of stresses due to Si-P defects makes it possible to prevent P aggregation defects (Si-P defects).

[0117] It is not preferred because Si-P defects cannot be relaxed if held at a temperature below 1100 °C or in the temperature range mentioned above for less than 30 minutes, and because the silicon wafer substrates deform if held at a temperature above 1250 °C or for at least 120 minutes.

[0118] Furthermore, the temperature of the silicon wafer substrate is then reduced so that the wafer experience time at a temperature of at most 700 °C and at least 450 °C is less than 10 minutes (step S10). Similar to step S8, the furnace atmosphere for the heat treatment is a mixed gas of hydrogen (H2) and argon (Ar), and the flow rate is maintained. This reduction in the wafer experience time at a temperature of at most 700 °C and at least 450 °C prevents phosphorus aggregation defects (Si-P defects).

[0119] The furnace atmosphere, a mixture of H2 and Ar (process gas), is preferably dilute argon gas with a hydrogen partial pressure of 80% to 50% at a temperature of at least 700°C and less than 850°C in the above heat treatment process, and dilute argon gas with an H2 partial pressure of 0.01% to 20% at temperatures below 700°C and at least 850°C.

[0120] The reason why the furnace atmosphere is a dilute argon gas with a hydrogen partial pressure of 80% to 50% at a temperature of at least 700°C and less than 850°C is that the densification of the oxide layer is promoted because impurities such as moisture in the oxide layer are reduced in the atmosphere of dilute argon gas with a hydrogen partial pressure of 80% to 50% at a temperature of less than 850°C.

[0121] The reason why the furnace atmosphere is a dilute argon gas with a hydrogen partial pressure of 0.01% to 20% at temperatures below 700°C and at least 850°C is to suppress the reduction of the oxide layer (SiO2) by hydrogen (H2).

[0122] As in Fig. As shown in Figure 3, after the heat treatment described above, the silicon oxide layer on the back side of the silicon wafer substrate is removed by peripheral machining at a distance of 0.1 mm to 1.0 mm from the silicon wafer substrate periphery (step S11). This aims to prevent the silicon oxide layer on the back side of the silicon wafer substrate from detaching during subsequent machining by removing the edge region of the oxide layer that was partially etched by the heat treatment. The distance is set to 0.1 mm to 1.0 mm from the periphery of the wafer, which corresponds to the degree that does not impair autodoping.

[0123] As described above, the reason the silicon oxide layer on the back of the silicon wafer substrate is removed by machining to a certain distance of 0.1 mm to 1.0 mm from the perimeter of the silicon wafer substrate is that this area is the position from which phosphorus diffuses out during the subsequent long-term heat treatment. As a result, the diffusion of phosphorus from the aforementioned position during the epitaxial layer growth process is suppressed, thus counteracting self-doping. It should be noted that the removed area is small and the amount of diffusion into the wafer after long-term heat treatment is negligible.

[0124] Furthermore, removing less than 0.1 mm of the silicon oxide layer from the circumference has none of the effects described above, while it is undesirable, since removing more than 1.0 mm of the silicon oxide layer from the circumference leads to an increase in mechanical damage from the substrate holder during long-term heat treatment or the epitaxial layer growth process due to the increase in the area without an oxide layer.

[0125] Next, as in Fig. Figure 3 shows the silicon wafer substrate undergoing surface cleaning before the growth of the epitaxial layer (step S12).

[0126] In surface cleaning, the silicon surface is etched with a gas mixture of hydrogen (H2) and hydrogen chloride (HCl) to remove at least 50 nm and at most 150 nm.

[0127] Surface cleaning of the silicon wafer substrate in this manner can further reduce SF6 after the growth of the epitaxial layer. In this case, defect removal with hydrogen chloride (HCl) is effective, and defect removal with a gas mixture of hydrogen (H2) and hydrogen chloride (HCl) is also desirable.

[0128] However, the remaining depth of the defects is at most about 100 nm, and etching the silicon surface to a depth of at least 50 nm to at most 150 nm is appropriate in terms of productivity.

[0129] Then a silicon epitaxy layer is deposited at a temperature of at least 1100 °C and at most 1150 °C with a deposition rate of at least 3.5 µm / min and at most 6.0 µm / min (step S13).

[0130] Intensive studies have shown that there is a suitable combination of growth rate and temperature of the monocrystalline silicon epitaxy layer for the reduction of SF.

[0131] As in Fig. Figure 8 shows that the deposition of the silicon layer at a temperature of at least 1100 °C and at most 1150 °C at a deposition rate of at least 3.5 µm / min and at most 6.0 µm / min can suppress the formation of LPD.

[0132] This is not desirable because controlling the electrical properties in device operation is difficult in the monocrystalline silicon epitaxial layer deposited with a thickness of less than 1.3 µm, and the layer with a thickness of more than 10.0 µm increases the cost of the epitaxial wafers.

[0133] A silicon layer is created by the movement of silicon atoms on the steps of the silicon surface. This process prevents the formation of SF6 because the movement of the silicon atoms relaxes the disturbances in the arrangement of the silicon atoms caused by Si-P defects.

[0134] In order to achieve both the deposition of the Si layer and this relaxation, the temperature for the deposition of the Si layer must be at least 1100 °C and at most 1150 °C, and the deposition rate must be at least 3.5 µm / min and at most 6.0 µm / min. Designs

[0135] The present invention is described in more detail based on examples and comparative examples, however the present invention is not limited to these examples. Experiment 1

[0136] The changes in the size and density of the Si-P defects occurring in the silicon wafer substrate, which are due to changes in the pull-up speed of the silicon single crystal, changes in the magnetic field strength, and the presence of forced cooling by a water cooler, were verified.

[0137] A silicon single crystal doped with phosphorus (P) with a resistance set to 0.05 mΩ·cm was grown to such a height that the oxygen concentration in the solid solution was at most 0.9×10 18 atoms / cm² 3 fraud.

[0138] The drawing speed was varied between 0.3 mm / min and 1.4 mm / min. The applied magnetic field was 3000 G. Both the maximum side length and the density of the Si-P defects were investigated with and without a water cooler in the drawing furnace. The results are presented in Fig. 10 shown.

[0139] The size of the Si-P defects was measured using a transmission electron microscope. The density of the Si-P defects was calculated from the observed area obtained through defect observation with the transmission electron microscope.

[0140] The results show that the maximum side length of the Si-P defects is less than 100 nm, with or without the installation of the water cooler.

[0141] In the case where no water cooler is installed, the density tends to decrease with increasing pull-up speed, i.e., the density is at most 1×10 12 / cm 3 at a lifting speed of at least approximately 0.7 mm / min.

[0142] In contrast, the density when installing the water cooler at a lifting speed of at least 0.5 mm / min is at most 1 × 10 12 / cm 3 .

[0143] Even if the drawing speed is increased by more than 1 mm / min, the density tends to decrease with increasing drawing speed. Since the effect of increasing the drawing speed is small and this also reduces productivity, a drawing speed of no more than 1 mm / min is preferable. Experiment 2

[0144] Experiment 2 verified that the accumulated slip length is less than 10 mm when the silicon oxide layer thicknesses X and Y fall within a range described by the relation expression: Y=CX, where C is a constant between 800 and 1000, as in step 7 in Fig. 2 shown.

[0145] The dopant is red phosphorus, the draw-up speed was 0.7 mm / min, and the magnetic field strength was 3000 G. Subsequently, silicon wafer substrates with a resistivity of 0.80 mΩ-cm and an oxygen concentration of 0.8 × 10⁻⁶ were used. 18atoms / cm² 3 and manufactured with a cutting angle of 0.3 degrees.

[0146] Furthermore, an oxide layer with a thickness of 500 nm was formed on the back side at a temperature of 430 °C, and the front side of the silicon wafer substrate was highly polished under mechanical and chemical conditions using a polishing cloth and a slurry containing colloidal silicon dioxide.

[0147] The thickness of the oxide layer (LTO) on the back of the silicon wafer substrate was changed by varying the heat treatment time, and the thickness of the thermal oxide layer that forms on the silicon boat for processing the silicon wafer substrate was changed.

[0148] After the silicon wafer substrates had been heat-treated for 60 minutes at a temperature of 1200 °C, the accumulated slip length of each silicon wafer substrate was measured using X-ray topography, and these changes were combined.

[0149] The graphical representation in Fig. Figure 11 shows the measurement results. Fig. 11 the open circle (◯) means that the accumulated slip length is less than 10 mm, the triangle (Δ) means that the accumulated slip length is between 10 mm and 50 mm, and the cross (×) means that the accumulated slip length exceeds 50 mm.

[0150] If the thickness of the thermal oxide layer formed on the silicon boat is between 200 nm and 500 nm, and the thickness X of the thermal oxide layer and the thickness Y of the silicon oxide layer (LTO) on the back of the silicon wafer substrate are in the range represented by the relation expression Y=CX, where C is a constant between 800 and 1000, then the accumulated slip length will be less than 10 mm; favorable results can be achieved. Experiment 3

[0151] In Experiment 3, a verification experiment was performed to reduce the increase in wafer surface roughness by holding the silicon wafer substrate at a constant temperature of at least 700 °C and less than 850 °C for at least 30 minutes and at most 120 minutes, as well as to prevent the formation of wafer surface pits (LPD) due to the aforementioned heat treatment and to accelerate the extinction of Si-P defects, which is referred to as step S8 in Fig. 2 is shown.

[0152] A silicon oxide layer is formed on the back of the silicon wafer substrate, which has a specific resistance of at most 1.05 mΩ·cm and an oxygen concentration of 0.9×10 18 atoms / cm² 3 and Si-P defects with a maximum side length of less than 100 nm and a density of less than 1×10 12 / cm 3exhibits the following properties. The oxide layer was deposited at a temperature in the range of 400 °C to 450 °C up to a thickness of 500 nm.

[0153] The front surface of the silicon wafer substrate was then highly polished; the thickness removed by polishing was 15 µm. The surface-polished silicon wafer substrate was heat-treated in a vertical diffusion furnace at 1200 °C for 60 minutes. The furnace atmosphere during heat treatment was a mixture of hydrogen and argon, a dilute argon gas with a hydrogen partial pressure of 1%.

[0154] At the time of the temperature increase prior to heat treatment at 1200 °C and for 60 minutes, the silicon wafer substrate was heat treated at 650 °C, 700 °C, 800 °C, 850 °C and 900 °C and held at each temperature for 15 minutes, 30 minutes, 120 minutes and 180 minutes.

[0155] The furnace atmosphere during heat treatment was a mixed gas of hydrogen and argon, a dilute argon gas with a hydrogen partial pressure of 60%, and the flow rate of the process gas was 0.7 m / s at a distance of 5 mm from the silicon wafer substrate.

[0156] A monocrystalline silicon epitaxial layer with a thickness of 4 µm was deposited at a growth rate of 4.0 µm / min at 1150 °C. The amount of silicon surface layer removed prior to epitaxial growth was 100 nm at a partial pressure of hydrogen chloride of 0.5%.

[0157] The verification procedure consists of measuring the number of LPDs using the SurfScan SP1 from KLA-Tencor Corporation. Fig. Figure 12 shows the measurement results. As in Fig. As can be seen in Figure 12, the number of LPDs reaches an almost constant value after a dwell time of 30 minutes. It is confirmed that, considering productivity, the dwell time is preferably between 30 and 120 minutes.

[0158] The deterioration of the LPD number at 650 °C or 900 °C is due to the desorbing of impurities, moisture, and oxygen from the oxide layer on the back of the wafer at these temperatures, thereby increasing roughness and creating depressions that remain as LPDs after epitaxial growth. The heat treatment temperature of the silicon wafer substrate is preferably between 700 °C and 850 °C. Experiment 4

[0159] At the time of the temperature increase prior to heat treatment to 1200 °C for 60 minutes, the silicon wafer substrate was held at 800 °C for 120 minutes and the flow rate of the process gas was set to 0.05 m / s, 0.1 m / s, 0.5 m / s, 1.0 m / s and 1.5 m / s.

[0160] Visual inspection of the wafers revealed that at a flow rate of 0.05 m / s, clearly visible opacities were present on the front of the wafers, and at a flow rate of 1.5 m / s, etching-induced pinholes were visible on the back of the wafers, while at flow rates of 0.1 m / s, 0.5 m / s and 1.0 m / s, none of this was visible. Experiment 5

[0161] In Experiment 5, verification experiments were carried out to confirm that the stress through Si-P defects can be relaxed by holding the silicon wafer substrate at a constant temperature of at least 1100 °C and at most 120 °C for a minimum of 30 minutes and a maximum of 120 minutes (see step 9 in Fig. 2).

[0162] First, a silicon oxide layer was deposited on the back of a silicon wafer substrate with a specific resistance of at most 1.05 mΩ·cm and an oxygen concentration in solid solution of at most 0.9 x 10 18 atoms / cm² 3 , Si-P defects with a maximum side length of less than 100 nm and a density of less than 1×10 12 / cm 3The oxide layer was formed and grown to a thickness of 500 nm at a temperature between 400 °C and 450 °C. Subsequently, the front surface of the silicon wafer substrate was highly polished, and the amount removed by the high-gloss polishing was 15 µm.

[0163] The highly polished silicon wafer substrate was then heat-treated in a vertical diffusion furnace at temperatures of 1050 °C, 1100 °C, 1200 °C, 1250 °C, and 1270 °C for 15 minutes, 30 minutes, 120 minutes, and 180 minutes at each temperature, respectively. Prior to the 60-minute heat treatment at 1200 °C, the silicon wafer substrate was also heat-treated at 800 °C for 120 minutes. The atmosphere in the furnace during this process was a mixed gas of hydrogen and argon with a hydrogen partial pressure of 1%.

[0164] The silicon surface layer of the silicon wafer substrate was removed by 100 nm using hydrogen chloride (HCl) before a monocrystalline silicon epitaxy layer was formed. The partial pressure of the hydrogen chloride was 0.5% and the temperature was 1180 °C.

[0165] Then a monocrystalline silicon epitaxy layer with a thickness of 4.0 µm was deposited at a growth rate of 4.0 µm / min at 1150 °C.

[0166] The verification procedure consists of measuring the number of LPDs using the SurfScan SP1 from KLA-Tencor Corporation. Fig. Figure 13 shows the measurement results. As in Fig. As shown in Figure 13, the number of LPDs reaches an approximately constant value at a dwell time of 30 minutes. It is confirmed that, considering productivity, the dwell time is preferably between 30 and 120 minutes. As shown in Figure 13, the number of LPDs reaches an approximately constant value at a dwell time of 30 minutes. Fig. As shown in Figure 13, the number of LPDs decreases with increasing temperature. Considering slippage and productivity issues, the temperature is preferably between 1100 °C and 1250 °C. Experiment 6

[0167] In Experiment 6, verification experiments were conducted to confirm that reducing the temperature from less than 700 °C to 450 °C to shorten the run-through time to less than 10 minutes, and reducing the experience time at temperatures from at least 450 °C to less than 700 °C, can prevent P-aggregated defects (Si-P defects), as described in step 10 in Fig. 2 is shown.

[0168] First, a silicon oxide layer was deposited on the back of a silicon wafer substrate with a specific resistance of at most 1.05 mΩ·cm and a solid solution oxygen concentration of at most 0.9×10 18 atoms / cm² 3, Si-P defects with a maximum side length of less than 100 nm and a density of less than 1×10 12 / cm 3 The oxide layer was formed. It grew to a thickness of 500 nm at a temperature between 400 °C and 450 °C.

[0169] Subsequently, the front side of the silicon wafer substrate was highly polished, and the amount removed by the high-gloss polishing was 15 µm.

[0170] The surface-polished silicon wafer substrate was heat-treated for 60 minutes at 1200 °C. The furnace atmosphere during heat treatment was a mixed gas of hydrogen and argon, a dilute argon gas with a hydrogen partial pressure of 1%.

[0171] At the point of temperature increase prior to heat treatment, the silicon wafer substrate was heated to 1200 °C for 60 minutes and then heat-treated at 800 °C for 120 minutes. The furnace atmosphere during heat treatment was a mixed gas of hydrogen and argon, a dilute argon gas with a hydrogen partial pressure of 60%.

[0172] The withdrawal temperature after the heat treatment described above was set to 700 °C, and the withdrawal rate from the furnace was varied from that point onward. The temperature of the silicon wafers exposed to the atmosphere was measured thermographically, and the experience time was calculated by adding the withdrawal time to the holding time at 700 °C.

[0173] The experience time of the wafers was varied at temperatures below 700 °C to at least 450 °C: 3 minutes, 5 minutes, 8 minutes, 10 minutes, 12 minutes, 15 minutes, and 20 minutes.

[0174] Furthermore, the surface layer of the silicon wafer substrates was removed by 100 nm using hydrogen chloride prior to the deposition of a monocrystalline silicon epitaxial layer. At this time, the partial pressure of hydrogen chloride was 0.5% and the temperature was set to 1180 °C.

[0175] Then, a single-crystal silicon epitaxy layer with a thickness of 4 µm was formed on the silicon wafer substrate at a deposition rate of 4 µm / min at 1150 °C.

[0176] Fig. 14 shows the results. As in Fig. Figure 14 shows that by reducing the temperature to a wafer experience time of less than 10 minutes at a temperature between less than 700 °C and at least 450 °C, the number of LPDs was at most 100 and the P aggregation defects (Si-P defects) could be prevented. Experiment 7

[0177] In Experiment 7, the effect of removing the Si oxide layer on the back of the silicon wafer substrate by external peripheral machining at a distance of 0.1 to 1.0 mm from the outer circumference of the silicon wafer substrate was verified.

[0178] First, a silicon oxide layer was deposited on the back of a silicon wafer substrate with a specific resistance of at most 1.05 mΩ·cm and an oxygen concentration in solid solution of at most 0.9×10 18 atoms / cm² 3 , Si-P defects with a maximum side length of less than 100 nm and a density of less than 1×10 12 / cm 3 The oxide layer was formed. It grew to a thickness of 500 nm at a temperature between 400 °C and 450 °C.

[0179] Subsequently, the front side of the silicon wafer substrate was highly polished, and the amount removed by the high-gloss polishing was 15 µm.

[0180] The surface-polished silicon wafer substrate was heat-treated for 60 minutes at 1200 °C. The furnace atmosphere during heat treatment was a mixed gas of hydrogen and argon, a dilute argon gas with a hydrogen partial pressure of 1%.

[0181] At the point of temperature increase prior to heat treatment at 1200 °C for 60 minutes, the silicon wafer substrate was heat-treated at 800 °C for 120 minutes. The atmosphere in the furnace for this treatment was a mixed gas of hydrogen and argon, a dilute argon gas with a hydrogen partial pressure of 60%.

[0182] After the aforementioned heat treatment, the removal temperature from the furnace was 700 °C, and the removal rate was varied. The temperature of the silicon wafers exposed to the atmosphere was measured thermographically, and the experience time was calculated by adding the removal time to the holding time at 700 °C.

[0183] This should ensure that the wafers have an exposure time of at least 8 minutes at temperatures below 700 °C and at least 450 °C.

[0184] The removal of the silicon oxide layer on the back of the silicon wafer substrate was varied at distances of 0.1 mm, 0.2 mm, 0.5 mm, 1.0 mm and 1.5 mm from the perimeter of the silicon wafer substrate.

[0185] The surface layer of this silicon wafer substrate was removed by 100 nm using hydrogen chloride prior to the deposition of a monocrystalline silicon epitaxial layer, with a partial pressure of hydrogen chloride of 0.5% and a temperature of 1180 °C.

[0186] Subsequently, a monocrystalline silicon epitaxy layer with a thickness of 4.0 µm was deposited at a growth rate of 4.0 µm / min at 1150 °C.

[0187] As in Fig. As can be seen in Figure 15, the diffusion of phosphorus from the covered part is insufficient at the time of long-term heat treatment if the processed width at the circumference is less than 0.1 mm.

[0188] Since the oxide layer of the covered area is etched during epitaxial growth, the diffusion of phosphorus from the etched area leads to a deterioration of the resistivity variation. If the machined width at the circumference is at least 1 mm, the area of ​​the uncovered region is large, and the diffusion of phosphorus is insufficient during the prolonged heat treatment. Consequently, the diffusion of phosphorus from the uncovered region further degrades the resistivity variation during epitaxial growth. Therefore, the preferred machined width is in the range of 0.1 mm to 1.0 mm. Experiment 8

[0189] In Experiment 8, the silicon removal rate of the silicon wafer substrate surface and the SF (LPD) due to Si-P defects were verified, as described in step S12 in Fig. Figure 3 shows the verification procedure. The verification method involves measuring the number of LPDs using the SurfScan SP1 from KLA-Tencor Corporation.

[0190] First, a silicon oxide layer was deposited on the back of a silicon wafer substrate with a specific resistance of at most 1.05 mΩ·cm and an oxygen concentration in solid solution of at most 0.9 x 10 18 atoms / cm² 3 , Si-P defects with a maximum side length of less than 100 nm and a density of less than 1 x 10 12 / cm 3 The oxide layer was formed. It was grown to a thickness of 500 nm at a temperature of 400 °C to 450 °C.

[0191] The surface of the front side of the silicon wafer substrate was then highly polished, removing 15 µm of material. The surface-polished silicon wafer substrate was then subjected to heat treatment at 800 °C for 120 minutes and 1200 °C for 60 minutes in a vertical diffusion furnace.

[0192] The wafers were heated for 8 minutes at temperatures below 700 °C to at least 450 °C. The furnace atmosphere during heat treatment was a mixed gas of hydrogen and argon, a diluted argon gas with a hydrogen partial pressure of 60%.

[0193] A single-crystal silicon epitaxial layer with a thickness of 4 µm was then deposited at a growth rate of 4.0 µm / min at 1150 °C. The removal of the silicon surface layer prior to epitaxial growth using hydrogen chloride was varied to a maximum of 500 nm at a hydrogen chloride partial pressure of 0.5%. Subsequently, the number of LPDs (65 nm) on the silicon wafer substrate was measured.

[0194] Fig. Figure 16 shows the results. Fig. 16 denotes “ea” on the vertical axis as the number of LPDs. The term LPD (65 nm) refers to the measurement of LPDs on the main surface that exhibit a scattering intensity equivalent to that of a particle with a standard particle size of at least 65 nm.

[0195] As in Fig. As shown in Figure 16, the number of LPDs (65 nm) is 10,000 when silicon removal from the surface of the silicon wafer substrate is not performed, while the number of LPDs (65 nm) is 100 to 200 when the silicon removal from the surface of the silicon wafer substrate is 50 nm to 200 nm. The preferred amount of silicon removed is at least 50 nm and at most 150 nm, taking productivity into account. Experiment 9

[0196] Verification experiments were carried out to confirm whether P-aggregate defects (P-Si defects) are prevented by the deposition of an epitaxial layer with a thickness of at least 1.3 µm and at most 10.0 µm at a deposition rate of at least 3.5 µm / min and at most 6.0 µm / min at a deposition temperature of at least 1100 °C and at most 1150 °C.

[0197] First, a silicon oxide layer was deposited on the back of a silicon wafer substrate with a specific resistance of at most 1.05 mΩ·cm and a solid solution oxygen concentration of at most 0.9×10 18 atoms / cm² 3 , Si-P defects with a maximum side length of less than 100 nm and a density of less than 1×10 12 / cm 3 The oxide layer was formed with a thickness of 500 nm at a temperature of 400 °C to 450 °C.

[0198] The surface of the front side of the silicon wafer substrate was then highly polished, removing 15 µm of material. The polished silicon wafer substrate was heat-treated in a vertical diffusion furnace at 1200 °C for 60 minutes. The furnace atmosphere during heat treatment was a mixture of hydrogen and argon, a dilute argon gas with a hydrogen partial pressure of 1%.

[0199] At the point of temperature increase prior to heat treatment, the silicon wafer substrate was heated to 1200 °C for 60 minutes and then heat-treated at 800 °C for 120 minutes. The furnace atmosphere during heat treatment was a mixed gas of hydrogen and argon, a dilute argon gas with a hydrogen partial pressure of 60%.

[0200] The experience time of the wafers at less than 700 °C to at least 450 °C should be 8 minutes.

[0201] The silicon surface layer of the silicon wafer substrate was then removed by 100 nm using hydrogen chloride (HCl) before a monocrystalline silicon epitaxial layer was formed. The partial pressure of the hydrogen chloride was 0.5% and the temperature was 1180 °C.

[0202] Then a single-crystal silicon epitaxy layer with a thickness of 4.0 µm was deposited, with the growth rate varying from 2.4 µm / min, 3.8 µm / min, 4.0 µm / min, 5.0 µm / min and 6.4 µm / min at temperatures of 1100 °C, 1125 °C and 1150 °C.

[0203] The number of LPDs was then measured using the SurfScan SP1 from KLA-Tencor Corporation. Fig. Figure 8 shows the results.

[0204] As in Fig. As shown in Figure 8, LPDs can be prevented by setting the deposition temperature to at least 1100 °C and at most 1150 °C and the deposition rate to at least 3.5 µm / min and at most 6.0 µm / min. The deposition temperature of the silicon layer is preferably at least 1100 °C and at most 1150 °C, since problems such as slippage in the silicon wafer substrate occur at a deposition temperature of 1200 °C.

Claims

[1] Method for producing a semiconductor silicon wafer comprising a silicon wafer substrate and a monocrystalline silicon epitaxial layer thereon, comprising: a step (S4) of forming a silicon oxide layer with a thickness of at least 300 nm and at most 700 nm on the back side of the silicon wafer substrate, wherein the silicon wafer substrate is produced from a silicon ingot grown by the Czochralski process, is doped with phosphorus, has a resistivity adjusted to at most 1.05 mΩ·cm and contains defects which are essentially Si-P crystal defects formed by the aggregation of phosphorus in the crystal; a step (S5) of high-gloss polishing of a silicon wafer substrate; a step (S8) of the heat treatment to hold the silicon wafer substrate mounted on a substrate holder at a constant temperature of at least 700 °C and at most 850 °C for at least 30 minutes and at most 120 minutes at a process gas flow velocity of at least 0.1 m / s and at most 1.0 m / s at a distance of within 5 mm from the silicon wafer substrate and then, after increasing the temperature, at a constant temperature of at least 1100 °C and at most 1250 °C for at least 30 minutes and at most 120 minutes, maintaining the process gas flow velocity, wherein the substrate holder, which is made of silicon or silicon carbide, has a silicon oxide layer (4a1) on the surface with a thickness of at least 200 nm and at most 500 nm and satisfies a relation equation Y = C - X, where X denotes the thickness of the silicon oxide layer (4a1) of the substrate holder and Y denotes the thickness of the silicon oxide layer (4a1) formed on the back of the silicon wafer substrate, and C denotes a constant with a value of 800 to 1000; a step (S11) of removing the silicon oxide layer (4a1) on the back side of the silicon wafer substrate by circumferential machining to a distance of 0.1 mm to 1.0 mm from the circumferential periphery of the silicon wafer substrate after heat treatment; and a step (S13) of depositing a monocrystalline silicon epitaxy layer with a thickness of at least 1.3 µm and at most 10.0 µm. [2] Method for producing a semiconductor silicon wafer according to claim 1, wherein the substrate holder has a holding surface for holding the silicon wafer substrate and the angle between the normal of the holding surface and the normal of the surface of the silicon wafer substrate is set to at least 0.5 degrees and at most 5.0 degrees. [3] Method for producing a semiconductor silicon wafer according to claim 1 or claim 2, wherein the substrate holder holds several silicon wafer substrates and the distance between the held silicon wafer substrates is set to at least 10 mm and at most 15 mm. [4] Method for producing a semiconductor silicon wafer according to claim 1, wherein the silicon oxide layer (4a1) is deposited on the surface of the silicon wafer substrate holder using two types of source gases from oxygen and nitrogen at a temperature of at least 1000 °C. [5] Method for producing a semiconductor silicon wafer according to claim 1, wherein the process gas in the heat treatment step is a dilute argon gas with a hydrogen partial pressure of 50% to 80% at a temperature of at least 700°C and less than 850°C and a dilute gas with a hydrogen partial pressure of 0.01% to 20% at a temperature of less than 700°C and at most 850°C. [6] Method for producing a semiconductor silicon wafer according to claim 1, further comprising a step (S12) of surface cleaning of the silicon wafer substrate prior to the deposition of an epitaxial layer, wherein in the surface cleaning step the surface silicon of the silicon wafer substrate is etched to a depth of at least 50 nm to at most 150 nm with a gas mixture of hydrogen and hydrogen chloride. [7] Method for producing a semiconductor silicon wafer according to claim 1, wherein in the step of forming a monocrystalline silicon epitaxial layer the epitaxial layer is deposited at a deposition temperature of at least 1100 °C and at most 1150 °C at a deposition rate of at least 3.5 µm / min and at most 6.0 µm / min.

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