HYBRID SERIAL RECEIVER CIRCUIT

Abstract

Facility, including: a front-end circuit (101) configured to generate an equalized signal (108, 109) using at least one signal encoding a serial data stream including a plurality of data symbols (107, 110, 111); an ADC-based receiver circuit (102) including at least one analog-to-digital converter circuit, the ADC-based receiver circuit (102) configured to generate a first plurality of recovered data symbols (107, 110, 111) using the equalized signal (108, 109) and a plurality of first clock signals based on a baud rate of the serial data stream; a first analog receiver circuit (100, 102, 103, 705) configured, based on the baud rate of the serial data stream, to generate a second plurality of recovered data symbols (107, 110, 111) using the equalized signal (108, 109) and a plurality of second clock signals; and a clock circuit (104) configured to: generating the plurality of first clock signals using first control information determined during generation of the first plurality of recovered data symbols (107, 110, 111); and Generating the plurality of second clock signals using second control information determined during generation of the second plurality of recovered data symbols (107, 110, 111).

Description

BACKGROUNDTechnical field

[0001] This disclosure relates to the field of interface design for high-speed communications, and more particularly to the use of a hybrid analog / analog-to-digital converter (ADC) based receiver circuit. Description of the state of the art

[0002] Computing systems typically include a number of interconnected integrated circuits. In some cases, the integrated circuits can communicate using communication channels or links to transmit and receive data bits. The communication channels can support parallel communication, in which multiple data bits are transmitted in parallel, or serial communication, in which the data bits are transmitted bit by bit in serial form.

[0003] Data transmitted between integrated circuits can be encoded to aid transmission. For example, in serial communication, data can be encoded to provide sufficient transitions between logic states to operate clock and data recovery circuits. Alternatively, in parallel communication, data can be encoded to reduce switching noise or improve signal integrity.

[0004] During data transmission, the physical characteristics of the communication channel can attenuate a transmitted signal associated with a particular data bit. For example, the impedance of the wiring included in the communication channel or connection can attenuate certain frequency ranges of the transmitted signal. Additionally, impedance mismatches between the wiring included in the communication channel and the devices coupled to the communication channel can induce reflections of the transmitted signal, which can affect subsequently transmitted signals corresponding to other data bits.

[0005] The prior art document US 9,537,617 B2 describes an integrated circuit with a plurality of receivers, each having a clock and data recovery circuit.

[0006] The prior art document US 11,088,818 B1 describes a receiver with a first clock and data recovery circuit, CDR, a control circuit and a second CDR circuit. SUMMARY OF THE EMBODIMENTS

[0007] Various embodiments for processing a serial data stream are disclosed. Generally, a hybrid receiver circuit includes a front-end circuit, an ADC-based receiver circuit, an analog receiver circuit, and a clock circuit. The front-end circuit may be configured to generate an equalized signal using at least one signal encoding a serial data stream including a plurality of data symbols. The ADC-based receiver circuit may include at least one analog-to-digital converter circuit and may be configured to generate a first plurality of recovered data symbols using the first equalized signal and a plurality of first clock signals based on a baud rate of the serial data stream.The analog receiver circuit may be configured to generate a second plurality of recovered data symbols using the second equalized signal and a plurality of second clock signals based on the baud rate of the serial data stream. The clock circuit may be configured to generate the plurality of first clock signals using first control information determined during the generation of the first plurality of recovered data symbols and to generate the plurality of second clock signals using second control information determined during the generation of the second plurality of recovered data symbols. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of one embodiment of a hybrid receiver circuit for a computer system. Fig. 2 is a block diagram of one embodiment of an analog front-end circuit. Fig. 3 is a block diagram of an embodiment of an ADC-based receiver circuit for a hybrid receiver circuit. Fig. 4 is a block diagram of one embodiment of an analog receiver circuit for a hybrid receiver circuit. Fig. 5 is a block diagram of one embodiment of a sampling circuit for an ADC-based receiver circuit. Fig. 6 is a block diagram of one embodiment of a clock circuit for a hybrid receiver circuit. Fig. Figure 7 is a block diagram of a computer system including a transmitter circuit and a receiver circuit. Fig. 8 is a flowchart of one embodiment of a method for operating a hybrid receiver circuit. Fig. 9 is a block diagram of one embodiment of a system-on-a-chip including a receiver circuit. Fig. 10 is a block diagram of various embodiments of a computer system that may include receiver circuitry. Fig. 11 illustrates an example of a non-transitory computer-readable storage medium that stores circuit design information. DETAILED DESCRIPTION OF EMBODIMENTS

[0008] A computing system may include one or more integrated circuits, such as a central processing unit (CPU) and memory. Each of the computing system's integrated circuits can communicate via either a serial or parallel interface. With a parallel interface, multiple data bits are communicated simultaneously, whereas with a serial interface, the data is communicated as a series of sequential individual data bits. When using a serial interface to communicate data between two devices included in a computing system, the data may be transferred using different protocols. For example, the data may be transferred using return-to-zero (RZ), non-return-to-zero (NRZ), pulse amplitude modulation (PAM), or any suitable combination thereof.

[0009] Serial data streams are often transmitted without an accompanying clock signal. In such cases, a clock signal is recovered from the serial data stream (in a process called "clock recovery") and used to sample the serial data stream to determine the values ​​of the included data symbols (in a process called "data recovery"). Various techniques can be used to recover both the data and the clock signal. For example, a receiver circuit can generate a clock signal whose frequency is approximately the same as that of a clock signal used to generate the data stream. A phase-locked loop circuit can then be used to align the clock signal with transitions in the serial data stream. Alternatively, the serial data stream can be oversampled, i.e.sampled at a higher frequency than the clock signal used to generate the serial data stream.

[0010] Receiver circuits for serial data streams can be analog-based or they can use analog-to-digital converter (ADC) circuits. ADC-based receiver circuits convert an equalized version of the input data signals into bits in the digital domain, allowing additional processing (e.g., feedforward equalization) to be performed as digital signal processing operations.

[0011] In the new interconnect standards, receiver circuits must support a wide range of baud rates. As used and defined herein, baud rate (or "symbol rate") is the rate at which information is transmitted over a communications channel. In PCIE, for example, data rates can vary from 2.5 Gbaudps to 32 Gbaudps. At the lower end of such a range, an analog receive circuit can be a power-efficient solution for sampling a signal transmitted over the communications channel. However, as the signal's baud rate increases, the analog receiver circuit cannot provide the power needed to consistently recover the data. At high baud rates, ADC-based receiver circuits can provide the power required to receive the signal, but are inefficient at lower baud rates.There is no single receiver circuit topology that covers the required data rate range without sacrificing capability or performance.

[0012] The embodiments illustrated in the drawings and described below may provide techniques for using a hybrid receiver circuit that includes both an analog-based receiver circuit and an ADC-based receiver circuit to sample a signal encoding a serial data stream. Under certain conditions (e.g., low baud rates, low-loss communication channels, etc.), the analog-based receiver circuit may be enabled to receive the signal in a power-efficient manner. In response to a change in conditions (e.g., an increase in the baud rate of the received data stream), the analog-based receiver circuit may be disabled and the ADC-based receiver circuit enabled to provide the required performance under the new conditions.

[0013] A block diagram depicting an embodiment of a hybrid receiver circuit is shown in Fig. 1. As illustrated, the hybrid receiver circuit 100 includes the front-end circuit 101, the ADC-based receiver circuit 102, the analog receiver circuit 103, the clock circuit 104, and the multiplexing circuit 105.

[0014] Front-end circuitry 101 is configured to generate an equalized signal 108 using signal 106. In various embodiments, signal 106 encodes a serial data stream including data symbols 107. Although front-end circuitry 101 is depicted generating a single equalized signal used by both ADC-based receiver circuitry 102 and analog receiver circuitry 103, in other embodiments, front-end circuitry 101 may be configured to generate different equalized signals for each of ADC-based receiver circuitry 102 and analog receiver circuitry 103.

[0015] In some embodiments, signal 106 may encode data symbols 107 according to one of various symbol encodings. For example, signal 106 may be transmitted according to RZ, NRZ, PAM3, or any other suitable symbol encoding. It is noted that although a single signal is depicted as encoding data symbols 107, in other embodiments, multiple signals may be used to encode data symbols 107. For example, in some cases, two signals may be used to encode data symbols 107 when differential signaling standards are used.

[0016] The ADC-based receiver circuit 102 includes an analog-to-digital converter circuit 116 and is configured to generate recovered data symbols 110 using clock signals 114 and equalized signals 108 based on the baud rate of the serial data stream including data symbols 107. As described below, the ADC-based receiver circuit 102 may include multiple analog-to-digital converter circuits that sample the equalized signal 108 at different resolutions. In various embodiments, different ones of the multiple analog-to-digital converter circuits may be used based on the baud rate of the serial data stream including data symbols 107.

[0017] The analog receiver circuit 103 is configured, based on the baud rate of the serial data stream including data symbols 107, to generate recovered data symbols 111 using clock signals 115 and equalized signal 108. As described below, the analog receiver circuit 103 may be implemented using primarily analog circuits that perform various functions (e.g., decision feedback equalization) in the analog domain. It is noted that the power consumption of the analog-based receiver circuit 103 may be less than the power consumption of the ADC-based receiver circuit 102 at baud rates below a threshold. Although in the embodiment of Fig. 1 only a single analog receiver circuit is depicted, in other embodiments additional analog receiver circuits may be used, each configured to be activated under corresponding sets of conditions (e.g., baud rate of the input data stream, channel conditions, and the like).

[0018] Clock circuit 104 is configured to generate clock signals 114 using control information 112 and to generate clock signals 115 using control information 113. In some embodiments, clock circuit 104 may be configured to generate either clock signals 114 or clock signals 115 based on mode signal 120. For example, clock circuit 104 may be configured to generate clock signals 114 in response to a determination that mode signal 120 is a certain value. Alternatively, clock circuit 104 may be configured to generate clock signals 115 in response to a determination that mode signal 120 is a different value. Although clock signals 114 and 115 are depicted as a single wire line, in various embodiments, clock signals 114 and 115 may include multiple clock signals with respective phases.It is noted that a value of the mode signal 104 may correspond to a particular set of conditions (e.g., baud rate of the input data stream, channel conditions, and the like). A change in one or more of the conditions may result in a different value for the mode signal 104.

[0019] Clock circuit 104 may be configured to generate clock signals 114 in response to determining that the baud rate of the serial data stream is equal to certain baud rate values, or to generate clock signals 115 otherwise. In various embodiments, the baud rate determination may be performed during an initialization process associated with a communication channel to which hybrid receiver circuit 100 is coupled.

[0020] In various embodiments, the ADC-based receiver circuit 102 is configured to determine control information 112 during the generation of recovered data symbols 110. Similarly, the analog receiver circuit 103 is further configured to determine control information 113 during the generation of recovered data symbols 111. Control information 112 may include information indicating a phase error detected during the generation of recovered data symbols 110, and the control information 113 may include information indicating a phase error detected during the generation of recovered data symbols 111.

[0021] In various embodiments, multiplexing circuitry 105 is configured to generate output data symbols 121 by selecting either recovered data symbols 110 or recovered data symbols 111 using mode signal 120. Multiplexing circuitry 105 may be implemented using multiple logic gates, multiple pass-gate circuits coupled together in a wired-OR fashion, or any other suitable circuitry configured to select between the two sets of recovered data symbols. It is noted that multiplexing circuitry 105 may be optional, as in some embodiments, a load circuit may directly receive recovered data symbols 110 and recovered data symbols 111.

[0022] Transitional to Fig. Figure 2 depicts a block diagram of one embodiment of a front-end circuit 101. As illustrated, the front-end circuit 101 includes the filter circuit 201 and the automatic gain control circuit 202A. Although the front-end circuit 101 is depicted as generating a single equalized signal, in other embodiments, the front-end circuit 101 may be configured to generate any number of equalized signals using the signal 106.

[0023] The filter circuit 201 is configured to generate the filtered signal 203 using the signal 106. In various embodiments, the filter circuit 201 may be further configured to attenuate high-frequency noise in the signal 106 to generate the filtered signal 203. In some cases, the filter circuit 201 may also be configured to attenuate low-frequency components at or near DC levels in the signal 106.

[0024] The automatic gain control circuit 202 is configured to generate an equalized signal 108 using the filtered signal 203. In various embodiments, the automatic gain control circuit 202 may be implemented as a closed-loop control circuit that uses feedback derived from the equalized signal 108 to maintain the amplitude of the data symbols at an optimal level for sampling. In various embodiments, the automatic gain control circuit 202 may include any suitable combination of attenuator and amplifier circuits that can be dynamically enabled or disabled to maintain the amplitude of the data symbols.

[0025] Although in the embodiment of Fig. While a single automatic gain circuit is depicted in Figure 2, additional automatic gain control circuits may be used in other embodiments where multiple equalized signals are required. In such cases, the additional automatic gain circuits may apply different amounts of gain and / or attenuation to their respective equalized signals.

[0026] Transitional to Fig. Figure 3 depicts a block diagram of one embodiment of an ADC-based receiver circuit 102. As illustrated, the ADC-based receiver circuit 102 includes the sampling circuit 301 and the recovery circuit 302.

[0027] Sampling circuit 301 is configured to generate sample values ​​303 using an equalized signal 108 and clock signals 114. As described below, in various embodiments, sampling circuit 301 may include multiple analog-to-digital converter circuits. In such cases, sampling circuit 301 may be further configured to select a first analog-to-digital converter circuit from the multiple analog-to-digital converter circuits based on the baud rate of the serial data stream including data symbols 107. The first analog-to-digital converter circuit may be configured to sample equalized signal 108 using clock signals 114 to generate sample values ​​303.

[0028] The sampling circuit 301 may be further configured to select a second analog-to-digital converter circuit from the plurality of analog-to-digital converter circuits based on the baud rate of the serial data stream including data symbols 107. The second analog-to-digital converter circuit is configured to sample the equalized signal 108 using clock signals 114 to generate the sampled signal 303. It is noted that the sampled signal 303 may include a stream of multiple samples. In various embodiments, a resolution of the second analog-to-digital converter circuit is greater than a resolution of the first analog-to-digital converter circuit. As used and described herein, the resolution of an analog-to-digital converter circuit refers to the smallest incremental voltage that causes a change in the digital output of an analog-to-digital converter circuit.In some cases, a sampling circuit, such as sampling circuit 301, may include multiple groups of analog-to-digital circuits (referred to as "sub-analog-to-digital converter circuits" or "sub-ADCs") coupled in parallel and activated sequentially to increase resolution.

[0029] The restoration circuit 302 is configured to generate restored data symbols 110 and control information 112 using samples 303. To generate restored data symbols 110 and control information 112, the restoration circuit 302 may be configured to perform equalization operations such as feedforward equalization (FFE) and decision feedback equalization (DFE). In other embodiments, the restoration circuit 302 may be further configured to correct a mismatch in the samples 303, as well as to multiply the sample 303 by a gain factor. In various embodiments, the restoration circuit 302 may be implemented as a digital signal processor (DSP) or other suitable processing circuitry.

[0030] Transitional to Fig. Figure 4 depicts a block diagram of one embodiment of an analog receiver circuit 103. As illustrated, the analog receiver circuit 103 includes a slicer circuit 401 and a restoration circuit 402.

[0031] The slicer circuit 401 is configured to generate samples using an equalized signal 109 and the clock signals 115. In various embodiments, the slicer circuit 401 is configured to compare an equalized signal 109 to a plurality of thresholds. Such thresholds may correspond to the voltage levels associated with the precursor or postcursor effects. In various embodiments, the slicer circuit 401 may be further configured to generate one or more error signals that may be included in the control information 113. In some embodiments, the slicer circuit 401 may be further configured to perform equalization, such as decision feedback equalization (DFE).

[0032] The restoration circuit 402 is configured to generate restored data symbols 111 and control information 113 using the sampled signal 403. Note that the sampled signal 403 may include a stream of samples generated by the slicer circuit 401. To generate control information 113, the restoration circuit 402 may be configured to perform phase detection. For example, in various embodiments, the restoration circuit 402 may be configured to perform Mueller-Muller phase detection or Alexander phase detection. In various embodiments, the restoration circuit 402 may be configured to perform such phase detection in the analog domain.

[0033] With reference to Fig. 5, one embodiment of sampling circuit 301 is depicted. As illustrated, sampling circuit 301 includes sampling buffers 501A-501D, sub-analog-to-digital converter circuits (referred to as "sub-ADCs 502A-502D"), switches 503A-503D, and a clock generation circuit 504. It is noted that, although in the embodiment of Fig. 5 depicts four sample buffers, four switches, and four sub-ADCs, in other embodiments a different number of sample buffers, switches, and sub-ADCs may be used.

[0034] Switches 503A-503D are configured to couple the equalized signal 108 to the corresponding sample buffers 501A-501D using buffer clocks 505. In various embodiments, each of the buffer clocks 505 may be phase-shifted from each other such that only one of the switches 503A-503D is closed at a given time. The respective frequencies of the buffer clocks 505 may, in various embodiments, be based on a frequency of the recovered clock signal 512 as well as the number of sample buffers and sub-ADCs included in the sampling circuit 301.

[0035] The switches 503A-503D may be implemented in various embodiments using one or more p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAAFETs), or any other suitable switching device.

[0036] Each of the sample buffers 501A-501D is configured to buffer the equalized signal 108 and control the analog-to-digital converter circuits included in the corresponding one of the sub-ADCs 502A-502D. In various embodiments, the sample buffers 501A-501D may be implemented as unity gain amplifier circuits or other suitable circuits configured to buffer an analog signal and provide additional control to enable the control of multiple analog-to-digital converter circuits.

[0037] Each of the sub-ADCs 502A-502D includes a plurality of analog-to-digital converter circuits coupled to a corresponding one of the sample buffers 501A-501D and configured to generate sampled signals 507A-507D based on a voltage level of the outputs of the corresponding one of the sample buffers 501A-501D. In various embodiments, the sampled signals 507A-507D each include a corresponding stream of samples generated by corresponding sub-ADCs 502A-502D. The analog-to-digital circuits included in each of the sub-ADCs 502A-502D are sequentially activated by the ADC clocks 506A and 506B. In various embodiments, the number of analog-to-digital converter circuits included in a sub-ADC determines an interleaving factor of the sub-ADC.

[0038] As described above, sub-ADCs 502A-502D can be activated sequentially. Once a particular one of sub-ADCs 502A-502D has been activated, the included analog-to-digital converter circuits can then be activated sequentially. In such cases, the samples generated by sub-ADCs 502A-502D can be interleaved. A recovery circuit, such as recovery circuit 302, can be configured to correctly align the samples and shift the data to a different, and possibly slower, clock domain.

[0039] When a given analog-to-digital converter circuit is activated, it samples the output of the corresponding sample buffer. Once the output has been sampled, a period of time may elapse (referred to as a "resolution period" or "resolution period") during which the analog-to-digital converter circuit generates multiple bits whose combined value corresponds to the voltage level of the sampled output. The duration of the resolution period and the number of bits generated vary with the type of analog-to-digital circuit used. In various embodiments, the total sampling and resolution periods for the analog-to-digital converter circuits included in a given sub-ADC may be less than or equal to an active time of a corresponding one of the buffer clocks 505.

[0040] The individual analog-to-digital converter circuits included in sub-ADCs 502A-502D may be implemented as flash ADCs, successive approximation ADCs, or other suitable analog-to-digital converter circuits. Although only four ADCs are depicted as being included in sub-ADCs 502A-502D, any suitable number of analog-to-digital converter circuits may be used in other embodiments. In such cases, clock generator circuit 504 would be configured to generate the required number of ADC clock signals.

[0041] Clock generator circuit 504 is configured to generate buffer clocks 505 and ADC clocks 506A and 506B. In various embodiments, clock generator circuit 504 may be implemented using phase-locked loop circuits, delay-locked loop circuits, delay circuits, or any other type of circuit suitable for generating multiple clock signals with different phases.

[0042] Transitional to Fig. 6 depicts a block diagram of one embodiment of a clock circuit 104. As illustrated, clock circuit 104 includes multiplexing circuit 601, multiplexing circuit 602, oscillator circuit 603, oscillator circuit 604, logic circuit 605, logic circuit 606, buffer circuit 607, multiplexing circuit 608, clock generator circuit 609, and buffer circuit 610.

[0043] The multiplexing circuit 601 is configured to select either the control information 112 or the control information 113 to generate a tuning signal at node 612. In various embodiments, the multiplexing circuit 601 may be configured to use the mode signal 120 to select either the control information 112 or the control information 113. Similarly, the multiplexing circuit 602 is configured to select either the control information 112 or the control information 113 to generate a tuning signal at node 613.

[0044] In various embodiments, multiplexing circuits 601 and 602 may be implemented using multiple logic gates. In other embodiments, multiplexing circuits 601 and 602 may be implemented using multiple pass gate circuits coupled together in a wired OR fashion.

[0045] Oscillator circuit 603 is configured to generate one or more clock phases at node(s) 614 using the tuning signal at node 612. In various embodiments, oscillator circuit 603 may be an inductor-capacitor oscillator circuit (referred to as an "LC oscillator circuit"). Similarly, oscillator circuit 604 is configured to generate one or more clock phases at node(s) 615 using the tuning signal at node 613. In various embodiments, oscillator circuit 604 may be implemented as a ring oscillator circuit.

[0046] Logic circuitry 605 is configured to generate one or more clock phases at node(s) 616 and node(s) 621 using the clock phases at node(s) 614 and test clock 620. In various embodiments, logic circuitry 605 may be configured to use test clock 620 instead of the clock phases at node(s) 614 during a test mode. To generate the clock phases at node(s) 621 and node(s) 616, logic circuitry 605 may be further configured to adjust the skew of the clock phases as well as to buffer the clock phases.

[0047] Logic circuitry 606 is configured to generate clock phases at node(s) 618 using the clock phases at node(s) 615 and test clock 620. To generate the clock phases at node(s) 618, logic circuitry 606 may be further configured to perform frequency division using at least one clock phase of the clock phases at node(s) 615. In other embodiments, logic circuitry 606 may be configured to delay one or more of the clock phases at node(s) 615 to generate the clock phases at node(s) 618.

[0048] Multiplexing circuit 608 is configured to select clock phases from either node 621, node 616, or node 618 to generate block phases at node(s) 619. In various embodiments, multiplexing circuit 608 may be configured to make the selection using mode signal 120 or based on the baud rate of the serial data stream including data symbols 107. In various embodiments, multiplexing circuit 608 may be implemented using multiple logic gates, multiple pass-gate circuits coupled together in a wired-OR fashion, or any other suitable circuit.

[0049] Clock generator circuit 609 is configured to generate clock signals 114 using the clock phases at node(s) 619. In various embodiments, a number of clock signals included in clock signals 114 may be greater than a number of clock phases at node(s) 619. In such cases, clock generator circuit 609 may be further configured to delay various ones of the clock phases at node(s) 619 to generate clock signals 114, such that individual clock signals 114 have respective phase shifts.

[0050] The multiplexing circuit 610 is configured to select clock phases from either the node(s) 616 or the node(s) 618 to generate clock signals 115. In various embodiments, the multiplexing circuit 610 may be configured to make the selection using the mode signal 120 or based on the baud rate of the serial data stream including the data symbols 107. In various embodiments, the multiplexing circuit 610 may be implemented using multiple logic gates, multiple pass-gate circuits coupled together in a wired-OR fashion, or any other suitable circuit.

[0051] As described above, a receiver circuit such as the hybrid receiver circuit 100 may be used in a computer system. A block diagram of one embodiment of such a computer system is shown in Fig. 7. As illustrated, computer system 700 includes devices 701 and 702 coupled by communication bus 707.

[0052] Device 701 includes circuit block 703 and transmitter circuit 704. In various embodiments, device 701 may be a processor circuit, a processor core, a memory circuit, or other suitable circuit block that may be included on an integrated circuit in a computer system. It is noted that although device 701 depicts only a single circuit block and a single transmitter circuit, additional circuit blocks and additional transmitter circuits may be used in other embodiments.

[0053] Transmitter circuit 704 is configured to serially transmit signals corresponding to the data received from circuit block 703 over communication bus 707. Such signals may differentially encode one or more bits, such that a difference between the respective voltage levels of wires 708A and 708B at a particular time corresponds to a particular bit value. In some cases, generating the signals may include encoding the bits prior to transmission. It should be noted that although communication bus 707 is depicted as including two wires, any suitable number of wires may be used in other embodiments.

[0054] The device 702 includes the receiver circuit 705 and the circuit block 706. Like the device 701, the device 702 may be a processor circuit, a processor core, a memory circuit, or other suitable circuit block configured to receive data from the transmitter circuit 704. In various embodiments, the receiver circuit 705 may correspond to the hybrid receiver circuit 100, as shown in Fig. 1 shown.

[0055] Devices 701 and 702 may, in some embodiments, be fabricated on a common integrated circuit. In other embodiments, devices 701 and 702 may be located on different integrated circuits mounted on a common substrate or circuit board. In such cases, communication bus 707 may include metal or other conductive traces on the substrate or circuit board. Although only two devices are depicted in computer system 700 in other embodiments, any suitable number of devices may be used.

[0056] Transitional to Fig. 8 illustrates a flowchart depicting one embodiment of a method for operating a hybrid receiver circuit. The method, which may be applied to various hybrid receiver circuits, such as hybrid receiver circuit 100, begins at block 801.

[0057] The method includes generating an equalized signal using at least one signal encoding a serial data stream including a plurality of data symbols (block 802). In some embodiments, generating the equalized signal includes filtering the plurality of signals to generate a filtered signal. In such cases, the method may include buffering the filtered signal with a gain factor to generate the equalized signal. In various embodiments, the method may further include generating a plurality of equalized signals using the at least one signal.

[0058] The method further includes activating a particular receiver circuit from a plurality of receiver circuits based on an operating condition, wherein the particular receiver circuit includes at least one analog-to-digital converter circuit (block 803). In various embodiments, the plurality of receiver circuits includes a plurality of ADC-based receiver circuits and a plurality of analog receiver circuits that are activated in response to detecting respective operating conditions. As used and defined herein, an operating condition refers to a set of physical and electrical parameters that affect the transmission of a signal encoding a serial data stream, as well as the properties of the signal itself. For example, a particular operating condition may include the baud rate of the serial data stream, as well as the electrical properties (e.g.,the impedance) of a channel over which the serial data stream is transmitted. In various embodiments, activating the particular receiver circuit based on the baud rate of the serial data stream includes performing a comparison of the baud rate of the serial data stream to a threshold and activating the particular receiver circuit in response to determining that the baud rate of the serial data stream is greater than the threshold.

[0059] In some embodiments, the method further includes activating another receiver circuit of a plurality of receiver circuits, including an analog receiver circuit, in response to detecting a different operating condition. In such cases, the method may further include generating, by the other receiver circuit, a second plurality of recovered data symbols using the second equalized signal and a different set of clock signals, and generating, by the clock circuit, the different set of clock signals using different control information determined during the generation of the second plurality of recovered data symbols.

[0060] In other embodiments, activating in response to detecting the different operating states includes receiving, by the other receiver circuit, baud rate information for the serial data stream. In various embodiments, the other receiver circuit may receive the baud rate information during an initialization or startup process associated with a communication channel. In such cases, the method may also include deactivating the particular receiver circuit in response to detecting the different operating states.

[0061] The method further includes generating, by the respective receiver circuit, a first plurality of recovered data symbols using the first equalized signal and a particular set of clock signals (block 804). In some embodiments, the particular receiver circuit includes a plurality of analog-to-digital converter circuits. In such cases, generating, by the particular receiver circuit, the first plurality of recovered data symbols includes selecting, based on the baud rate of the serial data stream, a first analog-to-digital converter circuit from the plurality of analog-to-digital converter circuits, and sampling, by the first analog-to-digital converter circuit, the first equalized signal using the particular set of clock signals to generate a plurality of sample values.The method may also include generating the first plurality of recovered data symbols using the plurality of samples.

[0062] In other embodiments, the method may further include selecting, based on the baud rate of the serial data stream, a second analog-to-digital converter circuit of the plurality of analog-to-digital converter circuits. In various embodiments, a resolution of the second analog-to-digital converter circuit is greater than a resolution of the first analog-to-digital converter circuit. In such cases, the method also includes sampling, by the second analog-to-digital converter circuit, the first equalized signal using the determined set of clock signals to generate a plurality of interleaved samples, and generating the first plurality of recovered data symbols using the plurality of interleaved samples.

[0063] The method further includes generating, by a clock circuit, the particular set of clock signals using particular control information determined during generation of the first plurality of recovered data symbols (block 805). In some embodiments, the clock circuit may include a plurality of oscillator circuits. In such cases, generating the particular set of clock signals includes adjusting a frequency of at least one oscillator circuit of the plurality of oscillator circuits using the particular control information. The method ends in block 806.

[0064] A block diagram of a System-on-a-Chip (SoC) is shown in Fig. 9. In the illustrated embodiment, the SoC 900 includes a processor circuit 901, a memory circuit 902, analog / mixed-signal circuits 903, and input / output circuits 904, each of which is coupled to the communication bus 905. In various embodiments, the SoC 900 may be configured for use in a desktop computer, a server, or a mobile computing application, such as a tablet or laptop computer or a wearable computing device.

[0065] In various embodiments, processor circuitry 901 may be exemplary of a general-purpose processor that performs computational operations. For example, processor circuitry 901 may be a central processing unit (CPU), such as a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA).

[0066] The memory circuit 902 may, in various embodiments, include any suitable memory type, such as dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or non-volatile memory. It is noted that, although Fig. 9 illustrates a single memory circuit, in other embodiments any suitable number of memory circuits may be used.

[0067] The analog / mixed-signal circuitry 903 may include a crystal oscillator circuit, a phase-locked loop (PLL) circuit, an analog-to-digital converter (ADC) circuit, and a digital-to-analog converter (DAC) circuit (all not shown). In other embodiments, the analog / mixed-signal circuitry 903 may be configured to perform power management tasks, including on-chip power supplies and voltage regulators.

[0068] Input / output circuitry 904 may be configured to coordinate data transfer between the SoC 900 and one or more peripheral devices. Such peripheral devices may include, without limitation, data storage devices (e.g., magnetic or optical media-based data storage devices, including hard disk drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral device. In some embodiments, the input / output circuitry 904 may be configured to implement a version of the Universal Serial Bus (USB) protocol or the IEEE 1394 (Firewire®) protocol and include the hybrid receiver circuit 100, as in the embodiment of Fig. 1. In such cases, the input / output circuitry 904 may also include the mode control circuitry 906 configured to generate the mode signal 120. In some cases, the mode control circuitry 906 may be configured to adjust a value of the mode signal 120 based on a rate at which data is received by the hybrid receiver circuitry 100. In other cases, the mode control circuitry 906 may be configured to adjust the value of the mode signal 120 during an initialization or boot operation of the SoC 900.

[0069] Input / output circuitry 904 may also be configured to coordinate data transmission between SoC 900 and one or more devices (e.g., other computing systems or integrated circuits) coupled to SoC 900 over a network. In one embodiment, input / output circuitry 904 may be configured to perform the data processing necessary to implement, for example, an Ethernet network standard (IEEE 802.3 network standard), such as Gigabit Ethernet or 10 Gigabit Ethernet, although it is contemplated that any suitable network standard may be implemented. In some embodiments, input / output circuitry 904 may be configured to implement multiple separate network interface ports.

[0070] Now referring to Fig. 10 illustrates various types of systems that may include any of the circuits, devices, or systems described above. The system or device 1000, which may include or otherwise utilize one or more of the techniques described herein, may be used in a wide variety of areas. For example, the system or device 1000 may be used as part of the hardware of systems such as a desktop computer 1010, a laptop computer 1020, a tablet computer 1030, a cellular or mobile phone 1040, or a television 1050 (or a set-top box coupled to a television).

[0071] Similarly, the disclosed elements may be utilized in a wearable device 1060, such as a smartwatch or a health monitoring device. Smartwatches, in many embodiments, may perform a variety of different functions, such as accessing email, cellular services, calendars, health monitoring, etc. A wearable device may also be designed to exclusively perform health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communication with emergency medical services, etc.Other types of devices are also conceivable, including devices worn around the neck, devices that can be implanted in the human body, glasses or helmets that provide computer-generated reality experiences such as those based on augmented and / or virtual reality, etc.

[0072] The system or device 1000 may also be used in various other contexts. For example, the system or device 1000 may be used in conjunction with a server computer system, such as a dedicated server or on shared hardware implementing a cloud-based service 1070. Furthermore, the system or device 1000 may be implemented in a wide range of specialized, everyday devices, including common household devices 1080 such as refrigerators, thermostats, security cameras, etc. The networking of such devices is often referred to as the "Internet of Things" (IoT). The elements may also be implemented in various means of transportation. For example, the system or device 1000 could be used in the control systems, guidance systems, entertainment systems, etc. of various types of vehicles 1090.

[0073] The Fig. The applications illustrated in Figure 10 are merely exemplary and are not intended to limit the possible future applications of the disclosed systems or devices. Other example applications include, without limitation, portable gaming devices, music players, data storage devices, unmanned aerial vehicles, etc.

[0074] Fig. 11 is a block diagram illustrating an example of a non-transitory computer-readable storage medium storing circuit design information, according to some embodiments. In the illustrated embodiment, semiconductor production system 1120 is configured to process design information 1115 stored on non-transitory computer-readable storage medium 1110 and produce integrated circuit 1130 based on design information 1115.

[0075] The non-transitory computer-readable storage medium 1110 may include any of various suitable types of storage devices or storage devices. The non-transitory computer-readable storage medium 1110 may be an installation medium, e.g., a CD-ROM, floppy disks, or a tape device; a computer system memory or random access memory, such as DRAM, DDR-RAM, SRAM, EDO-RAM, Rambus-RAM, etc.; a non-volatile memory, such as flash memory; magnetic media, e.g., a hard disk or optical storage; registers or other similar types of storage elements, etc. The non-transitory computer-readable storage medium 1110 may also include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 1110 may include two or more storage media that may be located in different locations, e.g.,in different computer systems connected via a network.

[0076] Design information 1115 may be specified using any of various suitable computer languages, including hardware description languages ​​such as, without limitation, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information 1115 may be usable by semiconductor manufacturing system 1120 to manufacture at least a portion of integrated circuit 1130. The format of design information 1115 may be recognized by at least one semiconductor manufacturing system, such as semiconductor manufacturing system 1120. In some embodiments, design information 1115 may include a netlist specifying elements of a cell library and their connectivity. One or more cell libraries used during logic synthesis of circuits included in integrated circuit 1130 may also be included in design information 1115.Such cell libraries may include information indicating device or transistor level netlists, mask design data, characterization data, and the like of cells included in the cell library.

[0077] Integrated circuit 1130, in various embodiments, may include one or more user-defined macrocells, such as memory, analog or mixed-signal circuits, and the like. In such cases, design information 1115 may include information related to included macrocells. Such information may include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device- or transistor-level netlists. As used herein, mask design data may be formatted according to the Graphics Data System (GDSII) or any other suitable format.

[0078] Semiconductor manufacturing system 1120 may include any of various suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor materials (e.g., on a wafer, which may include masking), removing materials, changing the shape of deposited materials, modifying materials (e.g., by doping materials or modifying dielectric constants using ultraviolet processing), etc. Semiconductor manufacturing system 1120 may also be configured to perform various tests of manufactured circuits for proper operation.

[0079] In various embodiments, integrated circuit 1130 is configured to operate according to a circuit design specified by design information 1115, which may include performing any of the functionality described herein. For example, integrated circuit 1130 may include any of the various elements shown or described herein. Further, integrated circuit 1130 may be configured to perform various functions described herein in conjunction with other components. Further, the functionality described herein may be performed by multiple connected integrated circuits.

[0080] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, this phrase indicates that the design information describes a circuit that, after manufacturing, is configured to perform the specified actions or include the specified components.

[0081] The present disclosure includes references to "embodiments" that are non-limiting implementations of the disclosed concepts. References to "embodiment," "one embodiment," "a particular embodiment," "some embodiments," "various embodiments," and the like do not necessarily refer to the same embodiment. A wide variety of possible embodiments are contemplated, including specific embodiments described in detail, as well as modifications or alternatives that fall within the spirit or scope of the disclosure. Not all embodiments necessarily exhibit any or all of the potential advantages described herein.

[0082] Unless otherwise indicated, the specific embodiments are not intended to limit the scope of any claims based on this disclosure to the disclosed forms, even if only a single example is described with respect to a particular feature. Thus, the disclosed embodiments are intended to be illustrative and not restrictive unless otherwise indicated. This application is intended to cover alternatives, modifications, and equivalents that would be obvious to those skilled in the art having the benefit of this disclosure.

[0083] Particular features, structures, or properties may be combined in any suitable manner consistent with this disclosure. The disclosure is thus intended to include any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalizations thereof. Accordingly, during the prosecution of this application (or an application claiming priority hereto), new claims may be drafted to any such combination of features. In particular, with reference to the appended claims, features of dependent claims may be combined with those of the independent claims, and features of the respective independent claims may be combined in any suitable manner and not only in the specific combinations recited in the appended claims.

[0084] For example, while the accompanying dependent claims are drafted such that each depends on a single other claim, additional dependencies are also contemplated. Where appropriate, it is also contemplated that claims drafted in one given type (e.g., device) may point to corresponding claims of another given type (e.g., method).

[0085] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and legal interpretation. Notice is hereby given that the following paragraphs, as well as definitions provided throughout this disclosure, should be used in determining how claims based on this disclosure are to be interpreted.

[0086] References to the singular forms, such as "a," "an," and "the," are intended to mean "one or more" unless the context clearly dictates otherwise. Thus, a reference to "an element" in a claim does not preclude additional instances of the element.

[0087] The word “may” is used herein in a permissive sense (i.e., having the potential, being able to) and not in a mandatory sense (i.e., must).

[0088] The terms “comprehensive” and “including” and forms thereof are open-ended and mean “including, but not limited to.”

[0089] When the term "or" is used in this disclosure with reference to a list of options, it is generally understood to be used in the inclusive sense unless the context indicates otherwise. Thus, a statement of "x or y" is equivalent to "x or y or both" and covers x but not y, y but not x, and both x and y. On the other hand, a phrase such as "either x or y, but not both" makes it clear that "or" is used in the exclusive sense.

[0090] A statement of "w, x, y, or z, or any combination thereof" or "at least one of ... w, x, y, and z" is intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, for the set [w, x, y, z], these phrases cover any single element of the set (e.g., w, but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "at least one of ... w, x, y, and z" thus refers to at least one element of the set [w, x, y, z], covering all possible combinations in this list of options. This phrase should not be interpreted to require that at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z be present.

[0091] Various "labels" may precede nouns in this disclosure. Unless the context indicates otherwise, different labels used for a feature (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. The labels "first," "second," and "third," when applied to a particular feature, do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless otherwise noted.

[0092] Within this disclosure, various entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. This phrase—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., something physical). In particular, this phrase is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure may be referred to as being "configured to" perform a task even if the structure is not currently operating.Thus, an entity described or specified as being “configured to” perform a task refers to something physical, such as a device, a circuit, a memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to anything intangible.

[0093] The term "configured to" is not intended to imply "configurable to." For example, an unprogrammed FPGA would not be considered "configured to" perform a specific function. However, this unprogrammed FPGA can be "configurable to" perform that function.

[0094] Stating in the appended claims that a structure is "configured to" perform one or more tasks is expressly not intended to invoke 35 USC § 112(f) for that claim element. If the applicant wishes to invoke the application of Section 112(f) during the grant process, it will specify claim elements using the construct "means for" [performing a function].

[0095] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not preclude the possibility that additional factors may influence the determination. That is, a determination may be based solely on stated factors or may be based on the stated factors as well as other, unstated factors. Consider the phrase "determine A based on B." This phrase specifies that B is a factor used to determine A or that influences the determination of A. This phrase does not preclude that the determination of A may also be based on another factor, such as C. This phrase is also intended to cover an embodiment in which A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0096] The phrase "in response to" describes one or more factors that trigger an effect. This phrase does not preclude the possibility that additional factors may influence or otherwise trigger the effect. That is, an effect may occur solely in response to those factors, or it may occur in response to the specified factors as well as other, unspecified factors. Consider the phrase "performing A in response to B." This phrase specifies that B is a factor that triggers performance of A. This phrase does not preclude that performance of A may also occur in response to another factor, such as C. This phrase is also intended to cover an embodiment in which A is performed solely based on B.

Claims

[1] Facility comprising: a front-end circuit (101) configured to generate an equalized signal (108, 109) using at least one signal encoding a serial data stream including a plurality of data symbols (107, 110, 111); an ADC-based receiver circuit (102) including at least one analog-to-digital converter circuit, the ADC-based receiver circuit (102) configured to generate a first plurality of recovered data symbols (107, 110, 111) using the equalized signal (108, 109) and a plurality of first clock signals based on a baud rate of the serial data stream; a first analog receiver circuit (100, 102, 103, 705) configured, based on the baud rate of the serial data stream, to generate a second plurality of recovered data symbols (107, 110, 111) using the equalized signal (108, 109) and a plurality of second clock signals; and a clock circuit (104) configured to: generating the plurality of first clock signals using first control information determined during generation of the first plurality of recovered data symbols (107, 110, 111); and Generating the plurality of second clock signals using second control information determined during generation of the second plurality of recovered data symbols (107, 110, 111). [2] The device of claim 1, further comprising a multiplexing circuit (105, 601, 602, 608, 610) configured to select either the first plurality of recovered data symbols (107, 110, 111) or the second plurality of recovered data symbols (107, 110, 111) based on the baud rate of the serial data stream to generate a plurality of output data symbols. [3] The device of any preceding claim, wherein the clock circuit (104) is further configured to: Receiving baud rate information for the serial data stream; and In response to a determination that the baud rate information matches a particular value, generating the plurality of first clock signals using first control information determined during generation of the first plurality of recovered data symbols (107, 110, 111); otherwise, generating the plurality of second clock signals using second control information determined during generation of the second plurality of recovered data symbols (107, 110, 111). [4] The device of any preceding claim, wherein the ADC-based receiver circuit (102) includes a plurality of analog-to-digital converter circuits, and wherein, to generate the first plurality of recovered data symbols (107, 110, 111), the ADC-based receiver circuit (102) is further configured to select a first analog-to-digital converter circuit of the plurality of analog-to-digital converter circuits based on the baud rate of the serial data stream; wherein the first analog-to-digital converter circuit is configured to sample the equalized signal (108, 109) using the plurality of first clock signals to generate a first plurality of samples (303); and wherein the ADC-based receiver circuit (102) is further configured to generate a first portion of the first plurality of recovered data symbols (107, 110, 111) using the first plurality of samples (303). [5] The device of claim 4, wherein the ADC-based receiver circuit (102) is further configured to select a second analog-to-digital converter circuit from the plurality of analog-to-digital converter circuits based on the baud rate of the serial data stream, wherein a second resolution of the second analog-to-digital converter circuit is greater than a first resolution of the first analog-to-digital converter circuit; wherein the second analog-to-digital converter circuit is configured to sample the equalized signal (108, 109) using the plurality of first clock signals to generate a second plurality of samples (303); and wherein the ADC-based receiver circuit (102) is further configured to generate a second portion of the first plurality of recovered data symbols (107, 110, 111) using the second plurality of samples (303). [6] The device of claim 1, further comprising a second analog receiver circuit (100, 102, 103, 705) configured to generate a third plurality of recovered data symbols (107, 110, 111) based on the baud rate of the serial data stream using the equalized signal (108, 109) and a plurality of third clock signals. [7] Method comprising: generating an equalized signal (108, 109) using at least one signal encoding a serial data stream including a plurality of data symbols (107, 110, 111); activating, based on an operating state, a particular receiver circuit from a plurality of receiver circuits (100, 102, 103, 705), wherein the particular receiver circuit includes at least one analog-to-digital converter circuit; generating, by the particular receiver circuit, a first plurality of recovered data symbols (107, 110, 111) using the equalized signal (108, 109) and a particular set of clock signals; and Generating, by a clock circuit (104), the determined set of clock signals using determined control information determined during the generation of the first plurality of recovered data symbols (107, 110, 111). [8] The method of claim 7, wherein activating, based on the operating state, the particular receiver circuit includes activating the particular receiver circuit in response to determining that the operating state matches a particular value. [9] The method of claim 8, further comprising: activating, in response to determining that the operating state has changed, another receiver circuit from a subset of the plurality of receiver circuits (100, 102, 103, 705) including corresponding analog receiver circuits (100, 102, 103, 705); generating, by the other receiver circuit, a second plurality of recovered data symbols (107, 110, 111) using the second equalized signal (108, 109) and another set of clock signals; and Generating, by the clock circuit (104), the other set of clock signals using different control information determined during the generation of the second plurality of recovered data symbols (107, 110, 111). [10] The method of claim 9, wherein the operating state includes a baud rate of the serial data stream, and wherein activating, based on the operating state, the different receiver circuit includes: Receiving information indicating the baud rate of the serial data stream; in response to determining that the baud rate of the serial data stream matches a given baud rate value: Activating the other receiver circuit; and Deactivating the specific receiver circuit. [11] The method of claim 7, wherein the particular receiver circuit includes a plurality of analog-to-digital converter circuits, and wherein generating the first plurality of recovered data symbols (107, 110, 111) by the particular receiver circuit includes: Selecting, based on a baud rate of the serial data stream, a first analog-to-digital converter circuit of the plurality of analog-to-digital converter circuits; Sampling, by the first analog-to-digital converter circuit, the equalized signal (108, 109) using the determined set of clock signals to generate a first plurality of samples (303); and Generating a first portion of the first plurality of recovered data symbols (107, 110, 111) using the first plurality of samples (303). [12] The method of claim 11, further comprising: Selecting, based on the baud rate of the serial data stream, a second analog-to-digital converter circuit from the plurality of analog-to-digital converter circuits, wherein a second resolution of the second analog-to-digital converter circuit is greater than a first resolution of the first analog-to-digital converter circuit; Sampling, by the second analog-to-digital converter circuit, the equalized signal (108, 109) using the determined set of clock signals to generate a second plurality of samples (303); and Generating a second portion of the first plurality of recovered data symbols (107, 110, 111) using the second plurality of samples (303). [13] The method of claim 7, wherein the clock circuit (104) includes a plurality of oscillator circuits (603, 604), and wherein generating the determined set of clock signals includes adjusting a frequency of at least one oscillator circuit (603, 604) of the plurality of oscillator circuits (603, 604) using the determined control information. [14] Facility comprising: a first device including a first functional circuit block, the first device being configured to: Receiving, from the first functional circuit block, a serial data stream including a plurality of data symbols (107, 110, 111); Generating a plurality of signals (106, 108, 120, 203, 507A-D) that encode the serial data stream; and Transmitting the plurality of signals (106, 108, 120, 203, 507A-D) over a communication channel; and a second device including a plurality of receiver circuits (100, 102, 103, 705), the second device being configured to: Receiving the plurality of signals (106, 108, 120, 203, 507A-D) via the communication channel; generating an equalized signal (108, 109) using the plurality of signals (106, 108, 120, 203, 507A-D); activating, based on a baud rate of the serial data stream, a particular receiver circuit of the plurality of receiver circuits (100, 102, 103, 705), wherein the particular receiver circuit includes at least one analog-to-digital converter circuit; generating, by the particular receiver circuit, a first plurality of recovered data symbols (107, 110, 111) using the equalized signal (108, 109) and a particular set of clock signals; and Generating the particular set of clock signals using particular control information determined during generation of the first plurality of recovered data symbols (107, 110, 111). [15] The apparatus of claim 14, wherein to activate the particular receiver circuit, the second device is further configured to activate the particular receiver circuit in response to a determination that the baud rate of the serial data stream matches a given baud rate value. [16] The device of claim 15, wherein the second device is further configured to: activating, based on the baud rate of the serial data stream, another receiver circuit from a subset of the plurality of receiver circuits (100, 102, 103, 705) including corresponding analog receiver circuits (100, 102, 103, 705); generating, by the other receiver circuit, a second plurality of recovered data symbols (107, 110, 111) using the equalized signal (108, 109) and another set of clock signals; and Generating the other set of clock signals using different control information determined during generation of the second plurality of recovered data symbols (107, 110, 111). [17] The apparatus of claim 16, wherein to activate the other receiver circuit, the second device, in response to a determination that the baud rate of the serial data stream matches another baud rate value, is further configured to: Activating the other receiver circuit; and Deactivating the specific receiver circuit. [18] The apparatus of claim 17, wherein the particular receiver circuit includes a plurality of analog-to-digital converter circuits, and wherein, to generate the first plurality of recovered data symbols (107, 110, 111), the particular receiver circuit is further configured to: Selecting, based on the baud rate of the serial data stream, a first analog-to-digital converter circuit of the plurality of analog-to-digital converter circuits; and wherein the first analog-to-digital converter circuit is configured to sample the equalized signal (108, 109) using the determined set of clock signals to generate a first plurality of samples (303); and wherein the particular receiver circuit is further configured to generate a first portion of the first plurality of recovered data symbols (107, 110, 111) using the first plurality of samples (303). [19] The apparatus of claim 18, wherein the particular receiver circuit is further configured to select a second analog-to-digital converter circuit from the plurality of analog-to-digital converter circuits based on the baud rate of the serial data stream, wherein a second resolution of the second analog-to-digital converter circuit is greater than a first resolution of the first analog-to-digital converter circuit; and wherein the second analog-to-digital converter circuit is configured to sample the equalized signal (108, 109) using the determined set of clock signals to generate a second plurality of samples (303); and wherein the particular receiver circuit is further configured to generate a second portion of the first plurality of recovered data symbols (107, 110, 111) using the plurality of samples (303). [20] The apparatus of claim 14, wherein the second device includes a plurality of oscillator circuits (603, 604), and wherein, to generate the determined set of clock signals, the second device is further configured to adjust a frequency of at least one oscillator circuit (603, 604) of the plurality of oscillator circuits (603, 604) using the determined control information.

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