METHOD FOR PRODUCING A SEMICONDUCTOR BODY, SEMICONDUCTOR BODY AND POWER SEMICONDUCTOR DEVICE

Abstract

According to one embodiment, the method for producing a semiconductor body (10) comprises the step of providing a first semiconductor layer (1) made of SiC, a further step of introducing carbon into the first semiconductor layer so that at least a part of the first semiconductor layer becomes at least one C-rich region (11), and a step of growing a second semiconductor layer (2) made of SiC on the first semiconductor layer, which has the at least one C-rich region.

Description

The present disclosure relates to a method of manufacturing a semiconductor body, a semiconductor body, and a power semiconductor device.There is a need for an improved method of manufacturing a semiconductor body, e.g., a method that enables the manufacture of a semiconductor body with high charge carrier mobility. A further object is to provide an improved semiconductor body, e.g. with high charge carrier mobility. Another object is to provide a power semiconductor device having such a semiconductor body.Embodiments of the disclosure relate to an improved method for manufacturing a semiconductor body, an improved semiconductor body and an improved power semiconductor device.According to an embodiment, the method for manufacturing a semiconductor body comprises the step of providing a first semiconductor layer of silicon carbide, SiC for short, a further step of introducing carbon, C for short, into the first semiconductor layer such that at least a part of the first semiconductor layer becomes at least one carbon-rich region, C-rich region for short, and a step of growing a second semiconductor layer of SiC on the first semiconductor layer comprising the at least one C-rich region.The present invention is based, inter alia, on the finding that carbon vacancies are the most important point defects of SiC, for example n-type 4H-SiC. Carbon vacancies result in two electrically active band gap levels, denoted Z 1 / 2 and EH 6 / 7 and located at 0.65 eV and 1.6 eV, respectively, below the conduction band margin. In particular, Z 1 / 2 is known to be a recombination center that affects the lifetime in bipolar devices.The inventors of the present invention had the idea of forming at least one C-rich region within a semiconductor layer sequence. This C-rich region will eventually release carbon from interstitial sites which will then anneal the carbon vacancies. By forming the at least one C-rich region during the formation of the semiconductor layer sequence, i.e. after the application of the first semiconductor layer and before the growth of the second semiconductor layer, the C-rich region can be formed within the semiconductor layer sequence and thus provide all regions of the semiconductor layer sequence more efficiently with carbon from carbon interstitials.Furthermore, the formation of the at least one C-rich region during the formation of the semiconductor layer sequence, as proposed here, is advantageous compared to the formation of the C-rich region after the complete growth of the semiconductor layer sequence. This is because in the second case, the formation of the C-rich region within the semiconductor layer sequence would have to be performed by deep C-ion implantation, which would require high implantation energies. This makes the process costly and also leads to an amorphization of the crystal and thus to more electrically active levels. The method proposed here is less costly and gentler, i.e. it generates much less active levels compared to deep ion implantation.The first semiconductor layer may be formed as a continuous layer, e.g. without interruptions. Providing the first semiconductor layer may include the step of growing, e.g. epitaxially growing, the first semiconductor layer on a substrate. The first semiconductor layer may be grown by chemical vapor deposition, CVD for short. The substrate is formed of, for example, SiC. The substrate may be doped, e.g., n-doped. The doping concentration in the substrate may be at least 10 18 cm -3.The thickness of the first semiconductor layer is, for example, at least 1 μm or at least 2 μm or at least 5 μm. Additionally or alternatively, the thickness of the first semiconductor layer may be at most 30 μm or at most 20 μm. The thickness of the substrate may be greater than the thickness of the first semiconductor layer. For example, the thickness of the substrate is at least 100 μm or at least 300 μm and / or at most 600 μm or at most 400 μm.The thickness of a layer, a region or a substrate is to be understood here as meaning the extent thereof in the vertical direction, i.e. in a direction at right angles to the main plane of extent of the first semiconductor layer. The SiC of the various semiconductor layers and / or the substrate mentioned here is, for example, 4H-SiC, in particular n-doped 4H-SiC.The first semiconductor layer may be doped, e.g. n-doped. For example, the average and / or maximum doping concentration in the first semiconductor layer is smaller than the average and / or minimum doping concentration in the substrate, e.g. by at least one or at least two or at least three orders of magnitude. For example, the average doping concentration in the first semiconductor layer is between 10 14 cm -3 and 10 17 cm -3. The first semiconductor layer may already be n-doped when provided. For example, the first semiconductor layer is doped during its growth.The step of introducing carbon into the first semiconductor layer is performed such that at least a part of the first semiconductor layer becomes at least a C-rich region. A C-rich region is understood here to mean a region in which the carbon concentration is higher than in an ideal SiC crystal. In a C-rich region, the additional carbon atoms (C atoms) or carbon ions (C ions) are located, for example, at interstitial sites.A C-rich region is defined here, for example, as a region in which the minimum and / or average concentration of C atoms or C ions at the interstitial sites is at least 100 times or at least 1000 times or at least 10000 times greater than the maximum and / or average concentration in the remainder of the first semiconductor layer or than in the first semiconductor layer before the carbon introduction step. The carbon at the interstitial sites is typically charged, so that they are mainly C ions at the interstitial sites.By minimum concentration in or from a region, layer or the like is meant herein the lowest concentration that can be found in that region, layer, etc. Accordingly, a maximum concentration in a region, a layer, etc. is the highest concentration that can be found in that region, layer, etc. An average concentration in or from a region, layer, etc. is the concentration averaged over the entire volume of the region, layer, etc.For example, only a part, but not all, of the first semiconductor layer becomes a C-rich region. For example, only the portion on an exposed surface through which the carbon enters the first semiconductor layer becomes C-rich. For example, at most 10%, or at most 5%, or at most 1%, of the volume of the first semiconductor layer becomes the at least one C-rich region."At least one C-rich region" means that only a continuous region of the first semiconductor layer becomes a C-rich region, or alternatively, that a plurality of spatially separated regions of the first semiconductor layer each become a C-rich region. All features disclosed herein for a C-rich region are also disclosed for all other C-rich regions.The introduction of the carbon into the first semiconductor layer may be performed by C ion implantation or by annealing in a C-rich region, e.g. CO 2, CH 4 etc., or e.g. by PIII. Once the carbon is introduced, it may be diffused by thermal annealing.The second semiconductor layer is also formed of SiC and is grown on the first semiconductor layer after the at least one C-rich region is formed. That is, the second semiconductor layer is grown on the first semiconductor layer already having the at least one C-rich region. The second semiconductor layer is in particular grown in such a way that it partially or completely covers the at least one C-rich region. The main extension plane of the second semiconductor layer may be parallel to that of the first semiconductor layer.The second semiconductor layer may be epitaxially grown on the first semiconductor layer. For example, the second semiconductor layer is grown directly on the first semiconductor layer, i.e. it adjoins the first semiconductor layer, in particular the at least one C-rich region. The growth technique may be the same as that used for the first semiconductor layer.After its growth, the second semiconductor layer may have a thickness of at least 2 μm or at least 5 μm. Additionally or alternatively, the thickness of the second semiconductor layer may be at most 30 μm or at most 20 μm. The second semiconductor layer may be grown as a continuous layer, e.g. without interruptions. It may extend over the entire lateral extension of the first semiconductor layer. Here, lateral directions are considered to be directions parallel to the main extension plane of the first semiconductor layer.During the growth, the second semiconductor layer may be doped, e.g. n-doped. The doping concentrations are e.g. the same as indicated in connection with the first semiconductor layer.According to another embodiment, the C-rich region is formed at an exposed side of the first semiconductor layer. That is, the C-rich region is formed so as to be adjacent to the top surface of the first semiconductor layer through which the carbon is introduced and on which the second semiconductor layer is subsequently grown.According to another embodiment, the C-rich region is formed so as to be interposed between the second semiconductor layer and a remaining portion of the first semiconductor layer that has not yet become C-rich after the growth of the second semiconductor layer. In other words, the C-rich region is formed so as not to extend over the entire thickness of the first semiconductor layer. For example, the depth (thickness) of the C-rich region is at most 10%, or at most 5%, or at most 1% of the thickness of the first semiconductor layer.According to a further embodiment, the carbon is introduced into the first semiconductor layer by means of plasma ion immersion implantation, PIII for short. PIII is a particularly gentle implant process that produces very shallow implant regions, i.e., shallow depth (thickness) implant regions. The use of PIII can be detected by SIMS in the finished semiconductor body due to the particular implantation form generated by PIII and by the presence of additional species originating from the precursor(s) used.According to a further embodiment, the method comprises a further step of implanting dopants of the first type into the semiconductor layer sequence, wherein the semiconductor layer sequence comprises the first and the second semiconductor layer. That is, the dopants of the first type are implanted after the second semiconductor layer is grown. The semiconductor layer sequence into which the dopants of the first type are implanted can also have one or more additional semiconductor layers in addition to the first and the second semiconductor layer. For example, at least one further semiconductor layer is grown before the growth of the first semiconductor layer and / or after the growth of the second semiconductor layer.For example, the implantation of the dopants of the first type is carried out after the growth of the semiconductor layer sequence is completed, i.e. after all growth steps for producing the semiconductor body have been carried out. The implantation of the dopants of the first type into the semiconductor layer sequence is performed, for example, via a side of the semiconductor layer sequence that is closer to the second semiconductor layer than to the first semiconductor layer. For example, the dopants of the first type are implanted at such a depth that they do not reach the C-rich region(s) and / or the first semiconductor layer. For example, the dopants of the first type are implanted into the second semiconductor layer. The dopants of the first type may be p-type dopants, e.g., boron. For example, p-wells are formed during the implantation of the dopants of the first type.According to a further embodiment, the dopants of the first type are activated at a temperature of at least 1000° C. or at least 1500° C. Additionally or alternatively, the temperature for the activation of the dopants of the first type may be at most 1800° C. or at most 1700° C.By heating the semiconductor layer sequence to such temperatures, the carbon is also liberated at the interstitial sites of the C-rich region. The released carbon then connects again to the carbon vacancies that have formed during the implantation of the dopants of the first type and / or to the carbon vacancies already present.Additionally or alternatively, the semiconductor layer sequence can be heated to the aforementioned temperatures independently of the implantation of the dopants of the first type. For example, the semiconductor layer sequence may be heated to these temperatures before the implantation of the dopants of the first type or even without performing the implantation of the dopants. This heating has the same effect that carbon is released from the interstitial sites and eventually joins the carbon vacancies.According to a further embodiment, the implantation is carried out with an energy of the C ions in the range between 0.5 keV inclusive and 100 keV inclusive, for example between 1 keV inclusive and 50 keV inclusive. With such implant energies, damage caused by the implant can be kept low.According to a further embodiment, the minimum and / or average concentration of C atoms or C ions at interstitial sites is at least 10 14 cm -3 or at least 10 16 cm -3 or at least 10 17 cm -3 or at least 10 18 cm -3 in the C-rich region. Additionally or alternatively, the maximum concentration of C atoms or C ions at interstitial sites is at most 10 21 cm -3 in the C-rich region. In particular, a C-rich region may be defined as a region in which this minimum concentration is present throughout this region or as a region having this average concentration.According to a further embodiment, at least one buffer region of the second semiconductor layer adjoins the C-rich region and is doped with dopants of the second type. The dopants of the second type are, for example, dopants of the n-type. In particular, the dopants of the second type differ from the dopants of the first type, i.e. they are of the opposite conductivity type.According to a further embodiment, the minimum and / or average concentration of the dopants of the second type in the at least one buffer region of the second semiconductor layer is greater than a maximum and / or average concentration of dopants of the second type in the first semiconductor layer. For example, the minimum and / or average concentration of the dopants of the second type in the buffer region is at least 10 times or at least 100 times or at least 1000 times greater than the maximum and / or average concentration of the dopants of the second type in the first semiconductor layer. The minimum and / or average concentration of second type dopants in the buffer region is, for example, at least 10 16 cm -3 or at least 10 17 cm -3. Additionally or alternatively, the maximum and / or average concentration of second type dopants in the buffer region may be at most 10 19 cm -3 or at most 10 18 cm -3. Also in this case, the buffer region may be defined by the region where the minimum doping concentration conditions are satisfied everywhere or where the average concentration condition is satisfied.The buffer region may be a buffer layer which extends continuously, for example without interruptions, over the entire lateral extension of the second semiconductor layer.The C-rich regions may result in stresses in the crystal lattice. The buffer region may equalize these voltages and, e.g., improve growth conditions for the rest of the second semiconductor layer.According to a further embodiment, a plurality of C-rich regions are formed in the first semiconductor layer, which regions are laterally spaced apart from one another. The plurality of C-rich regions are formed in the step of introducing carbon into the first semiconductor layer, e.g., by C-ion implantation. The C-rich regions of the first semiconductor layer may all be arranged at the same height with respect to the main extension plane of the first semiconductor layer. That is, a plane parallel to the main extension plane of the first semiconductor layer intersects each of the C-rich regions in the first semiconductor layer.For example, each of the C-rich regions has a lateral extent of at most 2 μm or at most 1 μm and / or at least 0.5 μm. The distance between each two adjacent C-rich regions, measured in the lateral direction, is e.g. at most 5 μm or at most 2 μm and / or at least 0.5 μm. The C-rich regions may be arranged at lattice points of a regular lattice. For example, each C-rich region is a rectangular region or a circular region when viewed in plan on the side of the first semiconductor layer on which the second semiconductor layer is grown. Alternatively, the C-rich regions of the first semiconductor layer may be formed as stripes, e.g. extending parallel to each other.Forming a plurality of C-rich regions may be performed using a mask, e.g., during the C-ion implantation process.According to a further embodiment, the method comprises a step of introducing carbon into the second semiconductor layer such that at least a part of the second semiconductor layer becomes at least one C-rich region. All features disclosed in connection with the at least one C-rich region of the first semiconductor layer are also disclosed for the at least one C-rich region of the second semiconductor layer. For example, the C-rich region or regions in the second semiconductor layer may be formed by the same method as the C-rich region or regions in the first semiconductor layer, e.g. by PIII.According to a further embodiment, the method comprises a step of growing a third semiconductor layer of SiC on the second semiconductor layer. The third semiconductor layer is epitaxially grown, for example. All features disclosed in connection with the second semiconductor layer are also disclosed for the third semiconductor layer, in particular with regard to doping and thickness.According to a further embodiment, a plurality of C-rich regions are formed in the second semiconductor layer, which regions are laterally spaced apart from one another. The features disclosed in connection with the plurality of C-rich regions in the first semiconductor layer are also disclosed for the plurality of C-rich regions in the second semiconductor layer.According to a further embodiment, the C-rich regions in the first semiconductor layer and the C-rich regions in the second semiconductor layer are arranged offset. This means in particular that the C-rich regions of the first semiconductor layer at most partially overlap the C-rich regions of the second semiconductor layer in at least one lateral direction. For example, the C-rich regions of the first semiconductor layer do not overlap with the C-rich regions of the second semiconductor layer in at least one lateral direction. The C-rich regions of the first semiconductor layer are arranged at a different height with respect to the main extension plane of the first semiconductor layer than the C-rich regions of the first semiconductor layer and do not overlap, for example, in the vertical direction.Then, the semiconductor body is specified. The semiconductor body can be produced in particular by the method according to one of the embodiments described here. Thus, all features disclosed in connection with the method are also disclosed for the semiconductor body and vice versa.According to an embodiment, the semiconductor body comprises a first semiconductor layer of SiC, a second semiconductor layer of SiC on the first semiconductor layer and at least one C-rich region in the first semiconductor layer. The C-rich region adjoins the second semiconductor layer. In the C-rich region, the minimum and / or average concentration of C atoms or C ions at interstitial sites is at least 10 17 cm -3. The thickness of the C-rich region is at most 100 nm or at most 50 nm or at most 30 nm and / or at least 10 nm or at least 15 nm. The thickness is measured at right angles to the main plane of extension of the first semiconductor layer.According to a further embodiment, the C-rich region has its maximum concentration of C atoms or C ions at interstitial sites at the interface to the second semiconductor layer. For example, the concentration profile in the vertical direction, perpendicular to the main extension plane of the first semiconductor layer, is asymmetric with respect to the interface between the first and the second semiconductor layer. For example, the distance measured in the vertical direction from the interface at which the concentration falls below 0.01 times the maximum concentration is greater in the first semiconductor layer by at least two orders of magnitude or by at least three orders of magnitude than in the second semiconductor layer. For example, the distance in the first semiconductor layer is at least 5 nm or at least 10 nm and / or at most 30 nm or at most 25 nm. The maximum concentration of C atoms / C ions at interstitial sites in the C-rich region may be at least 10 19 cm -3 and / or at most 10 21 cm -3.The thickness of the part of the C-rich region in which the minimum and / or average concentration of C atoms / C ions at interstitial sites is at least 10 18 cm -3 may be at most 30 nm or at most 25 nm and / or at least 5 nm or at least 10 nm. The thickness of the part of the C-rich region in which the minimum and / or average concentration of the C atoms / C ions at the interstitial sites is at least 10 19 cm -3 may be at most 20 nm and at least 10 nm.According to a further embodiment, the maximum and / or average concentration of carbon vacancies, or C vacancies for short, in the second semiconductor layer is at most 10 12 cm -3 or at most 10 11 cm -3. This relates in particular to Z 1 / 2- blanks.According to a further embodiment, the average charge carrier mobility in the second semiconductor layer is at least 100 cm 2 / Vs or at least 120 cm 2 / Vs or at least 150 cm 2 / Vs at room temperature.The indicated concentration of C vacancies and the indicated mobility in the second semiconductor layer can also apply to the first semiconductor layer. In the case of a third semiconductor layer grown on the second semiconductor layer, these values can additionally or alternatively apply to the third semiconductor layer.Next, the power semiconductor device is specified.The power semiconductor device comprises a semiconductor body according to one of the embodiments described herein. Further, the power semiconductor device includes electrodes in electrical contact with the semiconductor body. The electrodes may be formed of metal and / or highly doped polysilicon. The power semiconductor device is, for example, a transistor such as a MOSFET or an IGBT, or a thyristor.Hereinafter, the method for manufacturing a semiconductor body, the semiconductor body, and the power semiconductor device will be described in detail according to exemplary embodiments with reference to the drawings. The enclosed figures serve for better understanding. In the figures, elements of the same structure and / or functionality may be denoted by the same reference numerals. It will be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. Insofar as elements or components in different figures correspond in function, their description is not repeated for each of the following figures. For reasons of clarity, it may occur that elements do not appear with the corresponding reference numerals in all figures. FIGS. 1 to 8 show different positions in a first exemplary embodiment of the method, different exemplary embodiments of the semiconductor body and an exemplary embodiment of the power semiconductor device, FIG. 9 shows DLTS measurement curves, FIG. 10 shows curves of the concentration of C atoms or C ions at interstitial sites in a C-rich region produced by means of PIII, FIG. 11 shows a graph of the concentration of C atoms at interstitial sites in a C-rich region formed by deep ion implantation, FIGS. 12 to 14 show different positions in a second exemplary embodiment of the method, as well as exemplary embodiments of the semiconductor body and an exemplary embodiment of the power semiconductor device, FIGS. 15 to 18 show different positions in a third exemplary embodiment of the method and further exemplary embodiments of the semiconductor body, FIG. 19 shows a further exemplary embodiment of the semiconductor body.In the position according to FIG. 1, a substrate 4, for example an n-doped 4H-SiC substrate 4, is formed. The substrate 4 may be a standard 4° Off substrate.In the position of FIG. 2, a first semiconductor layer of SiC, e.g. 4H-SiC, is epitaxially grown on the substrate 4. The growth can be carried out by chemical vapor deposition, CVD for short, for example by hot wall chemical vapor deposition, HWCVD for short. The first semiconductor layer 1 is grown to a thickness of about 10 μm, for example. During growth, the first semiconductor layer 1 may be doped with dopants of the second type, which in this case are n-dopants.In the position of FIG. 3, the growth process is interrupted and carbon is introduced into the first semiconductor layer 1, whereby a part of the first semiconductor layer 1 becomes a C-rich region 11. In the C-rich region 11, C atoms or C ions accumulate at interstitial sites. The C-rich region 11 is formed only in the region of the exposed surface of the first semiconductor layer 1, i.e., at a very small depth, so that the C-rich region 11 does not extend over the entire thickness of the first semiconductor layer 1. This is achieved, for example, by implanting the C ions by means of plasma ion immersion implantation (PIII). This implantation technique actually allows very shallow and well-defined implantation regions to be formed.In FIG. 3, the C-rich region 11 extends continuously over the entire exposed surface of the first semiconductor layer 1.In the position according to FIG. 4, a second semiconductor layer 2 is grown on the first semiconductor layer 1, namely directly on the C-rich region 11, until the desired thickness of the semiconductor layer sequence is reached. The second semiconductor layer 2 is also made of SiC, e.g., 4H-SiC. The growth of the second semiconductor layer 2 can be carried out with the same method as in the case of the first semiconductor layer 1.In the position according to FIG. 5, an implantation process is performed in which dopants of the second type, namely n-dopants, are implanted into the second semiconductor layer 2 so that a buffer region 20 is formed which adjoins the C-rich region 11. The buffer region 20 has a higher average doping concentration than the first semiconductor layer 1 or the rest of the second semiconductor layer 2, which buffer region 20 compensates for the voltages induced by the carbon in the C-rich region 11.Unlike the illustration in FIG. 5, the buffer region 20 can already be produced during the growth of the second semiconductor layer 2.In the position according to FIG. 6, a further implantation process is carried out, in which dopants of the first type (in the present case p-dopants) are implanted. As a result, so-called p-type wells are formed in the second semiconductor layer 2.In the position of FIG. 7, a tempering process is performed. The semiconductor body 10 is heated to a temperature in the range between 1500° C. and 1700° C. in order to activate the previously implanted dopants of the first type. At this time, the C atoms or C ions in the C-rich region 11 are partially released at interstitial sites and fill the carbon vacancies in the semiconductor body 10.FIG. 8 shows a finished power semiconductor device 100 in the form of a MOSFET. This device 100 was produced by further implanting dopants of the second type into the p-wells to produce contact regions and by applying main electrodes 5, 6 and a gate electrode 7 to the semiconductor body 10.In FIG. 9, the signal of depth transient spectroscopy, DLTS for short, for different semiconductor bodies is shown as a function of temperature. Curve S 9_ 1 shows the case of a semiconductor body made of SiC, in which no measures for reducing carbon vacancies have been applied. Curve S 9_ 1 shows a prominent peak indicating Z 1 / 2- spaces. Curve S 9_ 2 shows the case that the semiconductor body is treated by oxidation. The carbon vacancies are eliminated. Curve S 9_ 3 shows the results obtained in the manufacture of the semiconductor body 10 as described above, i.e. by forming a C-rich region 11 by means of PIII. In this case too, the carbon vacancies are removed.FIG. 10 shows the concentration of C atoms / C ions at interstitial locations in a C-rich region 11 created in a SiC layer using PIII as a function of depth, i.e., as a function of distance from the surface of the SiC layer over which the carbon is implanted. Curve S 10_ 1 shows the concentration of the C atoms / C ions at the interstitial sites before heating to temperatures between 1500° C. and 1700° C., and curve S 10_ 2 shows the concentration after this heating. As a result of the heating, some of the C atoms / C ions have joined themselves again to C vacancies at the interstitials, with the result that the concentration of the C atoms / C ions at the interstitials is reduced. As can be seen, the PIII technique gives a very flat and strongly decreasing concentration profile with the concentration maximum at the surface of the SiC layer where the carbon penetrates into the SiC layer.Fig. 11 shows, for comparison, the concentration of C atoms / C ions at interstitial sites when the C-rich region is formed by deep ion implantation using much higher ion energies than in PIII. In this case, the concentration maximum lies within the SiC layer. The area is thicker and the profile is less steep than in Fig. 10.FIG. 12 shows a position in the second exemplary embodiment of the method. In this position, a plurality of laterally spaced C-rich regions 11 are formed on the exposed surface of the first semiconductor layer 1. This pattern of C-rich regions 11 may be achieved, for example, by using a mask on the first semiconductor layer 1 during the implantation of carbon. The mask is not shown in FIG. 12.In the position according to FIG. 13, a second semiconductor layer 2 is then again grown on the first semiconductor layer 1.FIG. 14 shows an exemplary embodiment of the finished power semiconductor device 100 as manufactured by the method described in connection with FIGS. 12 and 13. Also in this case, the power semiconductor device 100 is a power MOSFET.FIG. 15 shows a position in the third exemplary embodiment of the method that is identical to the position in FIG. 12.In FIG. 16, a second semiconductor layer 2 is grown on the first semiconductor layer 1.In FIG. 17, carbon is introduced into the second semiconductor layer 2, for example again by PIII, such that laterally spaced-apart C-rich regions 22 are formed in the second semiconductor layer 2. Here again, a mask, not shown, may be used to obtain this pattern of C-rich regions.As seen in FIG. 17, the C-rich regions 22 of the second semiconductor layer 2 and the C-rich regions 11 of the first semiconductor layer 1 are arranged in an offset configuration in which the regions 11 do not overlap the regions 22 in a lateral direction.FIG. 18 shows a position where a third semiconductor layer 3 is grown on the second semiconductor layer 2. The third semiconductor layer 3 is also formed of SiC and can be grown by the same method as the first and second semiconductor layers 2.FIG. 19 shows a further exemplary embodiment of the semiconductor body 10, which is similar to that according to FIG. 18. However, in this case, the regions 22 of the second semiconductor layer 2 and the regions 11 of the first semiconductor layer 1 are closer to each other in the vertical direction.The embodiments shown in FIGS. 1-19 are exemplary; thus, they do not represent a complete list of all embodiments of the improved method, semiconductor body, and power semiconductor device. Actual methods, semiconductor bodies, and power semiconductor devices may vary from the exemplary embodiments shown, e.g., in terms of arrangements, elements, and layer thicknesses.Reference numerals denote reference numerals1 First semiconductor layer 2 Second semiconductor layer 3 Third semiconductor layer 4 Substrate 5 Main electrode 6 Main electrode 7 Gate electrode 10 Semiconductor body 11 C-rich region 20 Buffer region 21 C-rich region 100 Power semiconductor device S 9_ 1 to S 9_ 3 Curves S 10_ 1, S 10_ 2 Curves

Claims

Method for producing a semiconductor body (10), comprising: - providing a first semiconductor layer (1) made of SiC, - introducing carbon into the first semiconductor layer (1) such that at least a part of the first semiconductor layer (1) becomes at least one C-rich region (11), - growing a second semiconductor layer (2) made of SiC on the first semiconductor layer (1) which comprises the at least one C-rich region (11).Method according to claim 1, wherein - the C-rich region (11) is formed on an exposed side of the first semiconductor layer (1) and such that the C-rich region (11) lies between the second semiconductor layer (2) and a remaining part of the first semiconductor layer (1) that has not become C-rich after the growth of the second semiconductor layer (2).Method according to claim 1 or 2, wherein - the carbon is introduced into the first semiconductor layer by means of plasma ion immersion implantation.The method according to any of the preceding claims, further comprising: - implanting dopants of the first type into the semiconductor layer sequence, wherein the semiconductor layer sequence comprises the first (1) and the second (2) semiconductor layers.The method of claim 4, further comprising: - activating the dopants of the first type at a temperature of at least 1500°C.Method according to claim 3 or any of claims 4 and 5 when dependent on claim 3, wherein - the implantation is performed with an energy of the C ions in the range between 1 keV inclusive and 50 keV inclusive, - in the C-rich region (11), the average concentration of C atoms or C ions at interstitial sites is at least 10 14 cm -3.Method according to one of the preceding claims, wherein - at least one buffer region (20) of the second semiconductor layer (2) adjoins the C-rich region (11) and is doped with dopants of the second type, wherein an average concentration of the dopants of the second type in the buffer region (20) is greater than an average concentration of dopants of the second type in the first semiconductor layer (1).Method according to one of the preceding claims, wherein - in the first semiconductor layer (1) a plurality of C-rich regions (11) is formed which are laterally spaced apart from one another.Method according to one of the preceding claims, further comprising: - introducing carbon into the second semiconductor layer (2) such that at least a part of the second semiconductor layer (2) becomes at least one C-rich region (21), - growing a third semiconductor layer (3) made of SiC on the second semiconductor layer (2).The method according to claim 9 when dependent on claim 8, wherein - in the second semiconductor layer (2) a plurality of C-rich regions (21) are formed which are laterally spaced apart from each other, - the C-rich regions (11) in the first semiconductor layer (1) and the C-rich regions (21) in the second semiconductor layer (2) are arranged in an offset configuration.Semiconductor body (10) comprising: - a first semiconductor layer (1) made of SiC, - a second semiconductor layer (2) made of SiC on the first semiconductor layer (1), - at least one C-rich region (11) in the first semiconductor layer (1), wherein - the at least one C-rich region (11) adjoins the second semiconductor layer (2), - in the C-rich region (11) the average concentration of C atoms or C ions at interstitial sites is at least 10 17 cm -3 and - the thickness of the C-rich region (11) is at most 100 nm.Semiconductor body (10) according to claim 11, wherein - the at least one C-rich region (11) has its maximum concentration of C atoms or C ions at interstitial sites at the interface to the second semiconductor layer (2).Semiconductor body (10) according to claim 11 or 12, wherein - the average concentration of the C vacancies in the second semiconductor layer (2) is at most 10 12 cm -3.The semiconductor body (10) according to any one of claims 11 to 13, wherein - the average charge carrier mobility in the second semiconductor layer (2) at room temperature is at least 100 cm 2 / Vs.Power semiconductor device (100) comprising: - a semiconductor body (10) according to any one of claims 11 to 14, - electrodes (5, 6, 7) in electrical contact with the semiconductor body (10).

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