Method for improving channel mobility in a SiC MOSFET

Abstract

A method for manufacturing a SiC semiconductor device (10), comprising the steps of: providing a SiC substrate (20) having a SiC epitaxial layer (30) thereon, treating the SiC epitaxial layer (30) with plasma immersion ion implantation (PIII) using dopants of a first material (35). The method further comprises thermally oxidizing a top surface (31) of the SiC epitaxial layer (30) to grow a thermal oxide layer (40), and etching the thermal oxide layer (40). The method further comprises implanting dopants of a second material (36) into the SiC epitaxial layer (30) to create a drain (50) and a source (60), activating the dopants with an activation anneal, and depositing a metal gate (70).

Description

[0001] The present disclosure relates to a method for manufacturing a silicon carbide (SiC) semiconductor element. The present disclosure further relates to a silicon carbide (SiC) semiconductor element for high-power switching applications.

[0002] Silicon carbide (SiC) is the only compound semiconductor that, like silicon, can be thermally oxidized. For this reason, thermally grown oxides on SiC can be used as a gate dielectric to form metal-oxide-semiconductor (MOS) devices. SiC MOS field-effect transistors (MOSFETs) are promising candidates for high-power switching applications. Low on-resistance and large load currents make them ideal for use as a switching device.

[0003] A lateral MOSFET consists of a source and a drain, two highly conducting p-type semiconductor regions isolated from the n-type substrate by reverse-biased pn diodes. A metal gate covers the region between the source and drain and is separated from the semiconductor by the gate oxide. The flow of charge carriers from the source to the drain, also known as the channel, is controlled by the voltage applied to the gate.

[0004] However, with the development of electronics technology, high temperatures and high frequencies have increased the requirements for semiconductor devices and circuits. Silicon (Si) cannot meet these requirements, especially for power switches, due to its material properties, and therefore SiC materials have been developed for semiconductor devices operating at high power, high temperatures, and high frequencies. Insulated-gate bipolar transistors (IGBTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used for power switching applications. These devices have a structure in which the gate electrode portion is electrically isolated from the device body. Since it is only necessary to charge and discharge the capacitor formed by the gate electrode and the device body, the gate control current is significantly smaller than that of, for example, a gate-turn-off transistor.

[0005] Despite the high bulk mobility of SiC, low inversion channel mobilities have been reported in SiC MOSFETs, leading to much higher on-state resistance than expected from bulk SiC properties. These were attributed to the high density of interface states D it at the SiO 2 / SiC interface. D it a SiO 2 / SiC interfaces are in the range between 10e11 and 10e13 cm -2 eV -1 , whereas in SiO 2 / Si less than 10e10 cm -2 eV -1 is. The nature of D it near the edge of the conduction band is generally attributed to the presence of C-related defects and intrinsic oxide acceptor defects, whereas the nature of D itnear the valence band is mainly attributed to C-related donor defects. The presence of carbon in the SiC epitaxial layer is due to injection during oxidation, which gives rise to immobile C clusters, such as the di-interstitial carbon vacancies (Ci)_2.

[0006] However, standard ion implantation in SiC also creates electrically active defects that can trap charge carriers. In addition to C-related defects formed during oxidation, these defects reduce charge carrier mobility in the channel.

[0007] For an n-type channel MOSFET, various ways to reduce D itproposed, such as post-oxidation annealing (POA) and pre-oxidation implantation (POI). The use of POA, in either an N2O or POCl3 environment, or POI, by either N-, P-, or Sb-donor impurities, leads to a decrease in D it in the upper part of the SiC band gap (1e11 cm -2 eV -1 for POA, low range of 1e12 cm -2 eV -1 for POI) and an increase in charge carrier mobility (90 cm 2 V -1 s -1 for POA and 20-100 cm 2 V -1 s -1 for POI). The reason for the reduction of D itand a subsequent increase in charge carrier mobility has been explained in terms of N (or P) atoms passivating the C clusters. The increase in charge carrier mobility has also been explained in terms of counter-doping. By this mechanism, an accumulation of N, P, or Sb in the channel region near the surface passivates interface defects and increases electron mobility in the n-channel by converting the epitaxial layer doping from p- to n-type. Nevertheless, both POA and POI have some disadvantages that can affect the reliability of the fabricated devices: The concentration of incorporated N or P is difficult to control by POA, and a flat-band voltage shift may occur due to the introduction of N, P, or Sb into SiO2. Furthermore, since P is more easily incorporated into SiC than N, self-conducting devices can be obtained.

[0008] It is a goal to achieve a high density of interface states at the SiO 2 / SiC interface to be avoided.

[0009] Another goal is to increase the charge carrier mobility in the channel of the SiC semiconductor element.

[0010] These objectives are met by the features of the independent claims.

[0011] Therefore, a method for manufacturing a SiC semiconductor element is provided, which requires neither post-oxidation annealing nor pre-oxidation implantation. Furthermore, a corresponding SiC semiconductor element is provided.

[0012] Plasma immersion ion implantation (PIII) or pulsed plasma doping (pulsed PIII) is a surface modification technique for extracting accelerated ions from a plasma by applying a pulsed DC or pure DC high-voltage power supply and directing them onto a suitable substrate or electrode, with a semiconductor wafer placed over it so that suitable dopants are implanted into it. The electrode is a cathode for an electropositive plasma, while it is an anode for an electronegative plasma.Plasma can be generated in a suitably designed vacuum chamber using various plasma sources, such as an electron cyclotron resonance plasma source, which produces plasma with the highest ion density and the lowest impurity level, a helicon plasma source, a capacitively coupled plasma source, an inductively coupled plasma source, a DC glow discharge, and a metal vapor arc. There are two types of vacuum chambers—diode and triode, depending on whether the power supply is applied to the substrate, as in the former case, or to the perforated grid, as in the latter case.

[0013] Accordingly, the method for fabricating a SiC semiconductor device comprises the steps of providing a SiC substrate having a SiC epitaxial layer thereon, treating the SiC epitaxial layer with plasma immersion ion implantation (PIII) using dopants of a first material. The method further comprises thermally oxidizing the surface of the SiC epitaxial layer to grow a thermal oxide layer (40), and etching the thermal oxide layer (40). The method further comprises implanting dopants of a second material into the SiC epitaxial layer to create a drain and a source, activating the dopants with an activation anneal, and depositing a metal gate.

[0014] The method for manufacturing a SiC semiconductor device includes an optional step of further plasma immersion ion implantation using Si.

[0015] The method for manufacturing a SiC semiconductor device comprises a further optional step of plasma immersion ion implantation using Ar to pre-amorphize the SiC epitaxial layer before treating the SiC epitaxial layer with plasma immersion ion implantation (PIII) using dopants of the first material.

[0016] By using the described method for manufacturing a SiC semiconductor element, it is possible to counteract the aforementioned adverse effects due to the specially performed plasma immersion ion implantation.

[0017] It is possible to determine the density of interface states D it at the SiO 2 / SiC interface and subsequently increase charge carrier mobility.

[0018] In addition, the optional Si-PIII step further improves charge carrier mobility. During oxidation, such a Si-rich layer is oxidized and the formation of C clusters is minimized, leading to an increase in charge carrier mobility in the channel of the SiC semiconductor device.

[0019] The additional step of an Ar-PIII makes it possible to make the channel area deeper.

[0020] A silicon carbide (SiC) semiconductor device comprises a SiC semiconductor substrate having a top surface and a bottom surface, wherein a SiC epitaxial layer has a top surface and a bottom surface. The SiC epitaxial layer is formed on the top surface of the SiC semiconductor substrate. The SiC semiconductor device further comprises a source and drain structure formed in the top surface of the SiC epitaxial layer, a thermal oxide and a metal gate, and a first region containing dopants of a first material that may be part of a channel. The thermal oxide covers the first region, at least a portion of the source structure, and at least a portion of the drain structure. Accordingly, the metal gate is electrically insulated from the first region, the source structure, and the drain structure by the thermal oxide and overlaps the first region and at least a portion of the source and drain structure.

[0021] The SiC semiconductor element optionally comprises a second region treated with PIII containing Si.

[0022] The SiC semiconductor element optionally comprises a SiC epitaxial layer pre-amorphized with Ar.

[0023] The SiC semiconductor substrate is a 3C-SiC substrate, a 4H-SiC substrate or a 6H-SiC substrate.

[0024] The SiC substrate is n-doped or p-doped and the SiC epitaxial layer is n-doped or p-doped in the same way as the SiC substrate.

[0025] The SiC semiconductor element can be used as a SiC transistor. The SiC transistor can be, for example, an insulated-gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a SiC junction field-effect transistor (SiC-JFET), or a SiC bipolar transistor (SiC-BJT).

[0026] Finally, it is noted that all proposed features and methods can be used alone, but also in a combination of two or more.

[0027] The present disclosure relates to an implantation of dopants in SiC semiconductor elements XYZXYZ.

[0028] Because the described SiC semiconductor element can be manufactured by the described embodiments of the method, described features and characteristics of the method are also disclosed with respect to the SiC semiconductor element, and vice versa. Accordingly, the present disclosure encompasses several aspects, wherein each feature described with respect to one of the aspects is also disclosed herein with respect to the other aspect, even if the respective feature is not explicitly mentioned in the context of the specific aspect.

[0029] Exemplary embodiments are explained below with the help of schematic drawings and reference numbers. The figures show: Fig. 1a-1g Steps of manufacturing a SiC semiconductor element, Fig. 2 DLTS spectra of as-grown and PIII-treated 4H-SiC. Fig. 3a, Fig. 3b Transfer and output characteristics of a MOSFET.

[0030] The accompanying figures are included to provide further understanding. It should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. Identical reference numerals designate elements or components with identical functions. To the extent that elements or components correspond to one another in function in different figures, the description thereof will not be repeated for each of the following figures. For clarity, elements may not appear with corresponding reference numerals in all possible figures.

[0031] Fig. 1a to Fig. 1g show the steps of the method for producing a semiconductor element 10.

[0032] In this regard, terms such as “above”, “below”, “top”, “upper” and “bottom” refer to an orientation or direction, as illustrated in the figures, and with reference to the stacking direction A. Accordingly, a height or thickness of the described elements is related to the stacking direction A, whereas a lateral direction B is oriented perpendicular to the stacking direction A (see Fig. 1a to 1g).

[0033] In Fig. 1a, a SiC substrate 20 is provided with an upper surface 21 and a lower surface 22. On the upper surface 21 of the SiC substrate 20, there is a SiC epitaxial layer 30 with a lower surface 31 and an upper surface 32. The lower surface 31 of the SiC epitaxial layer 30 faces the upper surface 21 of the SiC substrate 20. The SiC substrate 20 can have a concentration of at least 1e18 cm -3be n-doped or p-doped. The SiC epitaxial layer 30 is doped in the same way as the SiC substrate 20 and can also be doped with a concentration between 1e14 cm -3 and 1e16 cm -3 n-doped or p-doped. The SiC substrate 20 can be, for example, a 3C-SiC substrate, a 4H-SiC substrate, or a 6H-SiC substrate. In the case of a 3C-SiC epitaxial layer, the SiC substrate 20 can be replaced, for example, by a silicon (Si) substrate.

[0034] Fig. Figure 1b illustrates the treatment of the SiC epitaxial layer 30 with plasma immersion ion implantation (PIII), wherein a first region 33 is formed in the SiC epitaxial layer 30 with dopants of a first material 35. The doping concentration of the dopants of the first material 35 in the SiC epitaxial layer 30 is in the range of 1e16-1e20 cm -3The dopants of the first material 35 for n-doped semiconductor elements 10 can, for example, be an element derived from group 2 elements (Be, Mg, Ca, Sr, Ba, Ra) or from group 13 elements (B, Al, Ga, In, Tl, Nh). Alternatively, the dopants of the first material 35 for p-doped semiconductor elements 10 can, for example, be an element derived from group 15 elements (N, P, As, Sb, Bi, Mc) or from group 16 elements (O, S, Se, Te, Po, Lv). For the PIII, for example, an energy in the range of 1-30 keV and aluminum dopants can be used. The implantation is carried out at room temperature RT (approximately 20°C - 22°C) or at a temperature between 300°C and 500°C.

[0035] Fig. Figure 1c shows an optional step of a further PIII after implantation of dopants of the first material 35. For this PIII step, an energy in the range of 1-15 keV and silicon as a further dopant 37 are used, creating a second region 34 in the SiC epitaxial layer 30. The doping concentration of the dopants in the SiC epitaxial layer 30 is in the range of 1e15-1e18 cm -3 . The implantation is performed at room temperature (RT) or at a temperature between 300 °C and 500 °C. In this way, such a Si-rich layer 34 is oxidized during oxidation and the formation of C clusters is minimized, leading to an increase in charge carrier mobility.

[0036] Fig. Figure 1d shows the manufacturing step after the implantation step of either a dopant of a first material 35, such as Al, or a dopant of a first material 35 and silicon. This step shows a thermal oxidation of the upper surface 31 of the SiC epitaxial layer 30, so that a thermal oxide layer 40 of SiO2 is grown on the SiC epitaxial layer 30. The oxide layer 40 has an upper surface 41 and a lower surface 42. An SiO 2 / SiC interface 45 is created between the upper surface 31 of the SiC epitaxial layer 30 and the lower surface 42 of the thermal oxide layer 40. The thermal oxidation is performed at a temperature between 1100 °C and 1400 °C.

[0037] The density of interface states D it at the SiO 2 / SiC interface 45 is in the order of approximately 1e12-1e13 cm for a typical MOSFET standard implantation-2 eV -1 If both Al- and Si-PIII are used, the density of interface states D it less than 1e12 cm -2 eV -1 and the ON resistance R_on decreases by 8-10%.

[0038] The charge carrier mobility in the channel in a typical standard MOSFET implantation is approximately 20-50 cm 2 / Vs. If both Al- and Si-PIII are used, the charge carrier mobility in the channel is higher than 100 cm 2 / Vs.

[0039] After a standard channel implantation, the concentration of carbon vacancies (Vc) in the SiC epitaxial layer is higher than 1e14 cm -3 If Al-PIII is used, the concentration of carbon vacancies (Vc) is lower than 1e11 cm -3 If Si-PIII is added to Al-PIII, the concentration of carbon vacancies (Vc) is even lower.

[0040] Furthermore, the SiC epitaxial layer 30 can be treated with plasma immersion ion implantation (PIII) using Ar with an energy in the range of 5-10 keV to pre-amorphize the SiC epitaxial layer 30 before treating the SiC epitaxial layer 30 with plasma immersion ion implantation (PIII) using dopants of the first material 35 and / or Si. The Ar PIII contributes to making the channel deeper.

[0041] Fig. 1e shows a thermal oxide layer 40 being etched back at the edge of the thermal oxide layer 40 until the SiC epitaxial layer 30 with the doped first region 33 becomes visible underneath.

[0042] Fig. Figure 1f shows an implantation of dopants of a second material 36 in the SiC epitaxial layer 30, creating a drain 50 and a source 60. The implantation takes place at RT or at a temperature between 300 °C and 500 °C. The concentration of the dopants of the second material 36 is in the range of 1e17-1e21 cm -3 , but at least an order of magnitude greater than the dopant concentration of the first material used in the PIII, for example with Al. The implantation can, for example, be an n + -Implantation with n-type dopants. The implantation is followed by an activation anneal for 30 minutes at a temperature between 1600 °C and 1700 °C. The activation anneal is a heat treatment that compensates for the implantation damage caused by the dopants.

[0043] In the Fig. In the step shown in Figure 1g, a metal gate 50 is deposited on the top side 41 of the etched-back thermal oxide layer 40.

[0044] This is a basic lateral structure, but the disclosure of the embodiments extends its application to vertical SiC MOSFET devices. The SiC semiconductor element 10 can be used as a SiC transistor. The SiC transistor can be, for example, an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field-effect transistor (MOSFET), a SiC junction field-effect transistor (SiC JFET), or a SiC bipolar transistor (SiC BJT).

[0045] Fig. Figure 2 shows a plot of FT-DLTS (Fourier-Transformed Deep-Level Transient Spectroscopy) spectra of as-grown SiC (solid line) and PIII-treated SiC (dashed line). Capacitance (pF) is plotted against temperature (K).

[0046] The idea is to use plasma immersion ion implantation (PIII) to form the channel. By using standard ion implantation on as-grown SiC, several electrically active levels are created, such as EH1 (Ec-0.4 eV), Z1 / 2 (Ec-0.65 eV), EH3 (Ec-0.72 eV), EH4 (Ec-0.8 eV), EH5 (Ec-1.0 eV), and EH6 / 7 (Ec-1.6 eV). The concentrations of these levels are in the range of 1e13–1e15 cm³. -3These electron traps contribute to inhibiting charge carrier mobility in the channel. On the other hand, PIII does not lead to the formation of electrically active levels, with the exception of two levels labeled ON1 and ON2, which have no influence on device functionality. This allows for the seamless flow of charge carriers in the channel without any trapping effect from electrotraps.

[0047] Fig. 3a and Fig. 3b show simulated output and transfer characteristics for a MOSFET with the channel formed by standard ion implantation (solid line) and PIII (dashed line).

[0048] Fig. Figure 3a shows that the simulated devices have the same threshold voltage (V_th). Accordingly, the increase in the ON resistance R_on is attributed only to the lower defect density.

[0049] Fig. Figure 3b shows the output characteristics when PIII is used. It can be seen that the curve of the PIII-treated MOSFET (dashed line) shows an improvement relative to a standard ion implantation (solid line), indicating that the R_in has decreased.

[0050] The Fig. The embodiments shown in Figures 1 to 3 represent, as indicated, exemplary embodiments of the improved SiC semiconductor element 10 and the manufacturing method thereof; therefore, they do not represent a complete list of all embodiments. Actual arrangements and methods may differ from the illustrated embodiments, for example, with respect to SiC semiconductor elements 10. Reference symbol 10 SiC semiconductor element 20 SiC substrate 21 upper surface of the SiC substrate 22 bottom surface of the SiC substrate 30 SiC epitaxial layer 31 upper surface of the SiC epitaxial layer 32 lower surface of the SiC epitaxial layer 33 first area of the SiC epitaxial layer 34 second area of the SiC epitaxial layer 35 dopants of a first material 36 dopants of a second material 37 additional dopant Si 40 Thermal oxide layer 41 upper surface of the thermal oxide layer 42 lower surface of the thermal oxide layer 45 SiO 2 / SiC interface 50 Drain 60 Source 70 metal gate

Claims

[1] A method for producing a SiC semiconductor element (10), comprising the following steps: - providing a SiC substrate (20) with a SiC epitaxial layer (30) thereon, - treating the SiC epitaxial layer (30) with plasma immersion ion implantation (PIII) using dopants of a first material (35), - thermally oxidizing an upper surface (31) of the SiC epitaxial layer (30) so that a thermal oxide layer (40) is grown, - Etching the thermal oxide layer (40), - implanting dopants of a second material (36) in the SiC epitaxial layer (30) so that a drain (50) and a source (60) are created, - activating the dopants with an activation anneal, and - Depositing a metal gate (70). [2] A method for manufacturing a SiC semiconductor element (10) according to claim 1, wherein - the PIII with an energy in the range of 1-30 keV using dopants of the first material (35) with a doping concentration in the SiC epitaxial layer (30) in the range of 1e16-1e20 cm -3 at room temperature RT or at a temperature between 300 °C and 500 °C. [3] A method for manufacturing a SiC semiconductor element (10) according to claim 1 or 2, wherein - the implantation at room temperature RT or a temperature between 300 °C and 500 °C using dopants of the second material (36) with a doping concentration in the SiC epitaxial layer (20) in the range of 1e17-1e21 cm -3 is carried out, and wherein the doping concentration of the dopants of the second material (36) in the SiC epitaxial layer (20) is at least one order of magnitude greater than the doping concentration of the dopants of the first material (35) in the SiC epitaxial layer (20). [4] A method for manufacturing a SiC semiconductor element (10) according to claim 1, 2 or 3, wherein - the activation tempering is carried out for 30 min at a temperature between 1600 °C and 1700 °C. [5] A method for producing a SiC semiconductor element (10) according to any one of the preceding claims, comprising: - treating the SiC epitaxial layer (30) with a further plasma immersion ion implantation (PIII) with an energy in the range of 1-15 keV using Si with a doping concentration of Si in the SiC epitaxial layer (30) in the range of 1e15-1e18 cm -3 at room temperature RT or at a temperature between 300 °C and 500 °C. [6] A method for producing a SiC semiconductor element (10) according to any one of the preceding claims, comprising: - treating the SiC epitaxial layer (30) with plasma immersion ion implantation (PIII) with an energy in the range of 5-10 keV using Ar to pre-amorphize the SiC epitaxial layer (30) before treating the SiC epitaxial layer (30) with plasma immersion ion implantation (PIII) using dopants of the first material (35). [7] SiC semiconductor element (10) comprising: - a SiC substrate (20), - a SiC epitaxial layer (30) comprising: - a first region (33) treated by plasma immersion ion implantation (PIII) with dopants of a first material (35), - a thermal oxide layer (40), - a drain (50), - a source (60), and - a metal gate (70). [8] Semiconductor element (10) according to claim 7, wherein - the dopants of the first material (35) used for PIII originate from group 2 elements (Be, Mg, Ca, Sr, Ba, Ra) or from group 13 elements (B, Al, Ga, In, Tl, Nh). [9] SiC semiconductor element (10) according to claim 8, wherein - the dopants of the first material (35) used for PIII are Al with an energy in the range of 1-30 keV and with a doping concentration in the SiC epitaxial layer (30) in the range of 1e16-1e20 cm -3 are. [10] SiC semiconductor element (10) according to claim 7, wherein - the dopants of the first material (35) used for PIII originate from group 15 elements (N, P, As, Sb, Bi, Mc) or from group 16 elements (O, S, Se, Te, Po, Lv). [11] SiC semiconductor element (10) according to one of claims 7 to 10, comprising: - a second area (34) treated with PIII with Si. [12] SiC semiconductor element (10) according to claim 11, wherein - the Si from the second region (34) with an energy in the range of 1-15 keV and with a doping concentration in the SiC epitaxial layer (30) in the range of 1e15-1e18 cm -3 is implanted. [13] SiC semiconductor element (10) according to claim 7, wherein - Ar is implanted with an energy in the range of 5-10 keV in the SiC epitaxial layer (30) for pre-amorphizing the SiC epitaxial layer (30). [14] SiC semiconductor element (10) according to one of claims 7 to 13, wherein - the SiC substrate (20) is a 3C-SiC substrate, a 4H-SiC substrate or a 6H-SiC substrate. [15] SiC semiconductor element (10) according to one of claims 7 to 14, wherein - the SiC substrate (20) with a doping concentration of at least 1e18 cm -3 is n-doped or p-doped, and - the SiC epitaxial layer (30) in the same way as the SiC substrate (30) with a doping concentration in the range of 1e14-1e16 cm -3 n-doped or p-doped.

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