SEMICONDUCTOR COMPONENT

Abstract

A semiconductor device (10) is equipped with: a semiconductor layer (12); a gate trench (14) formed in the semiconductor layer (12) and arranged in a mesh configuration in a top view; a field plate trench (42) formed in the semiconductor layer (12) and surrounded by the gate trench (14) and spaced apart from the gate trench (14) in a top view; an insulating layer formed on the semiconductor layer (12); a gate electrode arranged in the gate trench (14); a first field plate electrode arranged below a base surface of the gate electrode in the gate trench (14); a second field plate electrode arranged in the field plate trench (42); and a source electrode formed on the insulating layer. The first field plate electrode and the second field plate electrode are electrically connected to the source electrode.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device. STATE OF THE ART

[0002] Patent Literature 1 discloses a MISFET having a trench-gate structure. The trench-gate structure includes a gate trench, an insulating layer, a bottom electrode, and an exposed electrode. Patent Literature 1 describes that when a reference voltage is applied to the bottom electrode and a gate voltage is applied to the exposed electrode, the switching speed is increased without reducing the breakdown voltage of the MISFET. CITATION LISTPatent literature

[0003] Patent Literature 1: Japanese Laid-Open Patent Publication No. 2020-072158 OVERVIEW OF THE INVENTIONTechnical Problem

[0004] For a MISFET having a trench gate structure, it is desirable to further increase the breakdown voltage without increasing the parasitic gate-drain capacitance and the parasitic gate-source capacitance. Solution to the problem

[0005] A semiconductor device includes a semiconductor layer, a gate trench formed in the semiconductor layer and arranged in a mesh pattern in a plan view, and a field plate trench formed in the semiconductor layer. The field plate trench is surrounded by the gate trench in a plan view and is spaced or separated from the gate trench. An insulating layer is formed on the semiconductor layer. A gate electrode is arranged in the gate trench. The gate electrode includes an upper surface covered by the insulating layer and a bottom surface opposite the upper surface. A first field plate electrode is arranged in the gate trench below the bottom surface of the gate electrode. A second field plate electrode is arranged in the field plate trench. The second field plate electrode includes an upper surface covered by the insulating layer.A source electrode is formed on the insulating layer. The first field plate electrode and the second field plate electrode are electrically connected to the source electrode. Advantageous effects of the invention

[0006] The semiconductor device of the present disclosure increases the breakdown voltage without increasing the gate-drain parasitic capacitance and the gate-source parasitic capacitance. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic top view of an exemplary semiconductor device according to an embodiment. Fig. 2 is a schematic cross-sectional view of a gate trench along a line F2-F2 in Fig. 1. Fig. 3 is an enlarged plan view of the semiconductor device shown in Fig. 1 is shown. Fig. Figure 4 is a schematic cross-sectional view of a field plate trench along a line F4-F4 in Fig. 3. Fig. 5 is a schematic plan view showing a semiconductor device of a comparative example. Fig. 6 is a schematic cross-sectional view showing a field plate trench of a semiconductor device according to a first modified example. Fig. 7 is a schematic plan view of an exemplary semiconductor device according to a second modified example. Fig. 8 is a schematic plan view of an exemplary semiconductor device according to a third modified example. Fig. 9 is an enlarged plan view of the semiconductor device shown in Fig. 8 is shown. Fig. 10 is a schematic plan view of an exemplary semiconductor device according to a fourth modified example. DESCRIPTION OF EMBODIMENTS

[0007] Some embodiments of a semiconductor device according to the present disclosure will now be described with reference to the accompanying drawings. Elements are illustrated in the figures for simplicity and clarity and are not necessarily drawn to scale. For clarity, dashed lines or hatched lines may be omitted from the cross-sectional views. The accompanying drawings illustrate exemplary embodiments according to the present disclosure and are not intended to limit the present disclosure.

[0008] This detailed description provides a comprehensive understanding of exemplary methods, devices, and / or systems according to the present disclosure. This detailed description is illustrative and is not intended to limit embodiments of the present disclosure or the application and uses of the embodiments. Mesh arrangement of the gate trench

[0009] Fig. 1 is a schematic top view of an exemplary semiconductor device 10 according to an embodiment. In the present specification, the X-axis, the Y-axis, and the Z-axis are orthogonal to each other, as shown in Fig. 1. The term "top view" as used in this specification is a view of the semiconductor device 10 from the Z-axis direction. Unless otherwise stated, the term "top view" refers to a view from above along the Z-axis of the semiconductor device 10.

[0010] The semiconductor device 10 is, for example, a metal-insulator-semiconductor field-effect transistor (MISFET) with a trench-gate structure. The semiconductor device 10 includes a semiconductor layer 12 and a gate trench 14 formed in the semiconductor layer 12. Fig. 1 shows an active region of the semiconductor device 10. In one example, the semiconductor layer 12 is made of silicon (Si). The semiconductor layer 12 includes a first surface 12A that is orthogonal to the Fig. 1, and a second surface 12B which is opposite to the first surface 12A (see Fig. 2).

[0011] The gate trench 14 is formed in the semiconductor layer 12 and is arranged in a mesh pattern in plan view. The gate trench 14 includes lateral gate trench portions 14X, which extend in the X-axis direction in plan view and have a width in the Y-axis direction, and longitudinal gate trench portions 14Y, which extend in the Y-axis direction in plan view and have a width in the X-axis direction. The lateral gate trench portions 14X and the longitudinal gate trench portions 14Y are interconnected, so that the gate trench 14 Fig. 1. In this specification, the Y-axis direction is referred to as the first direction, and the X-axis direction is referred to as the second direction. Therefore, the second direction is orthogonal to the first direction.

[0012] The semiconductor layer 12 includes mesh cells M that are surrounded by the gate trench 14, which is arranged in a mesh pattern in plan view. In one example, the mesh cells M may each be square in plan view. In the Fig. In the example shown in Figure 1, the mesh cells M are aligned in the X-axis direction and arranged offset from each other in the Y-axis direction. As a result, the lateral gate trench sections 14X and the longitudinal gate trench sections 14Y each form T-junctions and do not intersect crosswise. Such a mesh pattern is advantageous in the manufacturing process of the semiconductor device 10. In another example, the mesh cells M may be aligned in both the X-axis direction and the Y-axis direction. Details of the gate trench

[0013] With reference to Fig. 2, the gate trench 14 of the semiconductor device 10 will now be described in detail. Fig. 2 is a schematic cross-sectional view of the semiconductor device 10 along the line F2-F2 in Fig. 1. Fig. 2 shows a cross-sectional view of a longitudinal gate trench portion 14Y cut in a width direction (X-axis direction). Although not shown, it should be understood that a cross-sectional view of a lateral gate trench portion 14X cut in a width direction (Y-axis direction) is the same as that shown in Fig. 2, and differs only in that the cross-sectional view is rotated by 90° in an XY plane.

[0014] The semiconductor layer 12 may include the semiconductor substrate 16, which includes the first surface 12A of the semiconductor layer 12, and an epitaxial layer 18 formed on the semiconductor substrate 16 and which includes the second surface 12B of the semiconductor layer 12. The semiconductor substrate 16 may be a Si substrate. The semiconductor substrate 16 corresponds to a drain region of a MISFET. The epitaxial layer 18 may be a Si layer epitaxially grown on a Si substrate. The epitaxial layer 18 may include a drift region 20, a body region 22 formed on the drift region 20, and a source region 24 formed on the body region 22. The source region 24 may include the second surface 12B of the semiconductor layer 12.

[0015] The drain region (semiconductor substrate 16) may be an n-type region containing n-type impurities. The drain region (semiconductor substrate 16) may have an n-type impurity concentration in a range of 1×10 18 cm -3 up to 1×10 20 cm -3 , inclusive. The drain region (semiconductor substrate 16) may have a thickness in a range of 50 µm to 450 µm, inclusive.

[0016] The drift region 20 may be an n-type region containing n-type impurities at a lower concentration than the drain region (semiconductor substrate 16). The drift region 20 may have an n-type impurity concentration in a range of 1×10 15 cm -3 up to 1×10 18 cm -3 The drift region 20 may have a thickness in a range from 1 µm to 25 µm, inclusive.

[0017] The body region 22 may be a p-type region containing p-type impurities. The body region 22 may have a p-type impurity concentration in a range of 1×10 16 cm -3 up to 1×10 18 cm -3 , inclusive. The body region 22 may have a thickness in a range of 0.2 µm to 1.0 µm, inclusive.

[0018] The source region 24 may be an n-type region containing n-type impurities at a higher concentration than the drift region 20. The source region 24 may have an n-type impurity concentration in a range of 1×10 19 cm -3 up to 1×10 21 cm -3 , inclusive. The source region 24 may have a thickness in a range of 0.1 µm to 1 µm, inclusive.

[0019] In the present disclosure, the n-type is also referred to as a first conductivity type, and the p-type is also referred to as a second conductivity type. The n-type impurities may be, for example, phosphorus (P), arsenic (As), or the like. The p-type impurities may be, for example, boron (B), aluminum (Al), or the like.

[0020] The gate trench 14 opens in the second surface 12B of the semiconductor layer 12 and has a depth in the Z-axis direction. The gate trench 14 extends through the source region 24 and the body region 22 of the semiconductor layer 12 to or into the drift region 20. The gate trench 14 includes a sidewall 14A and a bottom wall 14B. The bottom wall 14B is adjacent to the drift region 20. The gate trench 14 can have a depth in a range of 1 µm to 10 µm, inclusive.

[0021] The sidewall 14A of the gate trench 14 may extend in a direction orthogonal to the second surface 12B of the semiconductor layer 12 (Z-axis direction) or may be inclined relative to the second surface 12B. In one example, the sidewall 14A may be inclined relative to the Z-axis direction such that the width of the gate trench 14 decreases toward the bottom wall 14B. Furthermore, the bottom wall 14B of the gate trench 14 does not necessarily have to be flat and may be partially or completely curved.

[0022] The semiconductor device 10 further includes an insulating layer 26 formed on the semiconductor layer 12. In one example, the insulating layer 26 may be formed by a film of silicon oxide (SiO2). In addition to or instead of the silicon oxide film, the insulating layer 26 may include a layer composed of an insulating material other than SiO2, for example, silicon nitride (SiN).

[0023] The semiconductor device 10 further includes a gate electrode 28 and a first field plate electrode 30 arranged in the gate trench 14. The gate electrode 28 is an electrode to which a gate voltage is applied, and the first field plate electrode 30 is an electrode to which a reference voltage (or source voltage) is applied. In this specification, the trench in which the gate electrode 28 is arranged is referred to as the gate trench 14.

[0024] The gate electrode 28 includes a top surface 28A covered by the insulating layer 26 and a bottom surface 28B opposite the top surface 28A. The first field plate electrode 30 is disposed in the gate trench 14 below the bottom surface 28B of the gate electrode 28 (between the bottom surface 28B of the gate electrode 28 and the bottom wall 14B of the gate trench 14). At least a portion of the bottom surface 28B of the gate electrode 28 faces the first field plate electrode 30, with the insulating layer 26 disposed therebetween.

[0025] The upper surface 28A of the gate electrode 28 may be disposed below the second surface 12B of the semiconductor layer 12. The upper surface 28A and the bottom surface 28B of the gate electrode 28 may be flat or curved. Furthermore, the gate electrode 28 may have a uniform width across the entire Z-axis direction, but the width need not be uniform throughout. For example, the bottom portion of the gate electrode 28, including the bottom surface 28B, may have a smaller width than other portions.

[0026] The first field plate electrode 30 is surrounded by the insulating layer 26 (lower insulator 34, described later). The first field plate electrode 30 may have a smaller width than the gate electrode 28. When the first field plate electrode 30 has a relatively narrow width, the insulating layer 26 (lower insulator 34) surrounding the first field plate electrode 30 has a relatively large thickness. This mitigates electric field concentration in the gate trench 14.

[0027] The gate electrode 28 may be positioned such that the interface of the drift region 20 and the body region 22 is not located below the bottom surface 28B of the gate electrode 28, as viewed in the Z-axis direction. The interface of the drift region 20 and the body region 22 may be located at the same position as the bottom surface 28B of the gate electrode 28, or may be located above the bottom surface 28B, as viewed in the Z-axis direction.

[0028] In one example, the gate electrode 28 and the first field plate electrode 30 are constructed of a polysilicon that is conductive.

[0029] The insulating layer 26 may include a gate insulator 32 disposed between the gate electrode 28 and the semiconductor layer 12 and covering the sidewall 14A of the gate trench 14. The gate insulator 32 separates the gate electrode 28 and the semiconductor layer 12 from each other. A predetermined voltage is applied to the gate electrode 28 to form a channel in the p-type body region 22 adjacent to the gate insulator 32. The semiconductor device 10 controls the flow of electrons in the Z-axis direction through the channel between the n-type source region 24 and the n-type drift region 20.

[0030] The insulating layer 26 may further include the lower insulator 34 disposed between the first field plate electrode 30 and the semiconductor layer 12 and covering the sidewall 14A and bottom wall 14B of the gate trench 14. The lower insulator 34 on the sidewall 14A of the gate trench 14 may be thicker than the gate insulator 32. The insulating layer 26 may further include an intermediate insulator 36 disposed between the top surface 30A of the first field plate electrode 30 and the bottom surface 28B of the gate electrode 28.

[0031] The semiconductor device 10 further includes a source electrode 38 formed on the insulating layer 26. In the semiconductor device 10, the source electrode 38 is not formed directly on the source region 24 of the semiconductor layer 12, but is formed on the insulating layer 26. This is advantageous in that the effect of voltage fluctuations in the source region 24 is limited.

[0032] The first field plate electrode 30 may be coupled to the source electrode 38 in a region not shown in the drawings (e.g., peripheral region containing the Fig. 1). This electrically connects the first field plate electrode 30 to the source electrode 38. The source electrode 38 may be constructed or composed of at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a Cu alloy, and an Al alloy.

[0033] The semiconductor device 10 further includes a drain electrode 40 formed on the first surface 12A of the semiconductor layer 12. The drain electrode 40 is adjacent to and electrically connected to the drain region (semiconductor substrate 16). The drain electrode 40 may be constructed of at least one of Ti, Ni, Au, Ag, Cu, Al, a Cu alloy, and an Al alloy.

[0034] Elements arranged in a mesh cell With reference to Fig. 3, the elements arranged in the mesh cells M are now described, which are shown in Fig. 1 are shown. Fig. 3 is an enlarged plan view of the semiconductor device 10 shown in Fig. 1 is shown. Fig. 3 shows a region F3 which in Fig. 1 is surrounded by single-dashed lines, and which includes one of the mesh cells M surrounded by the gate trench 14. The following description is also applicable to the other mesh cells M.

[0035] The semiconductor device 10 further includes a field plate trench 42 formed in the semiconductor layer 12. The field plate trench 42 may be one of a plurality of field plate trenches 42 each arranged in the mesh cells M included in the semiconductor layer 12. Each field plate trench 42 is surrounded by the gate trench 14 and is separated or spaced from the gate trench 14. Accordingly, the field plate trench 42 and the gate trench 14 are not connected to each other. In one example, the field plate trench 42 of each mesh cell M may be cross-shaped in plan view. In the example of the Fig. 1, the field plate trench 42 includes lateral field plate trench sections 42X that extend in the X-axis direction in plan view and have a width in the Y-axis direction, and longitudinal field plate trench sections 42Y that extend in the Y-axis direction in plan view and have a width in the X-axis direction. The lateral field plate trench sections 42X intersect the longitudinal field plate trench sections 42Y in a central part of each mesh cell M, such that the field plate trench 42 has a cross-shaped pattern or structure, as shown in Fig. 3 is shown.

[0036] As described above, the gate trench 14 includes the longitudinal gate trench portions 14Y extending in the Y-axis direction. Each field plate trench 42 is surrounded by the gate trench 14. Accordingly, the longitudinal field plate trench portions 42Y and the longitudinal gate trench portions 14Y are alternately arranged in the X-axis direction. In other words, the gate trench 14 and the field plate trenches 42 each include portions extending in the Y-axis direction, with such portions being alternately arranged in the X-axis direction, which is orthogonal to the Y-axis direction.

[0037] As described above, the gate trench 14 further includes the lateral gate trench portions 14X extending in the X-axis direction. Each field plate trench 42 is surrounded by the gate trench 14 in plan view. Accordingly, the lateral field plate trench portions 42X and the lateral gate trench portions 14X are alternately arranged in the Y-axis direction. In other words, the gate trench 14 and the field plate trenches 42 each include portions extending in the X-axis direction, with such portions being alternately arranged in the Y-axis direction, which is orthogonal to the X-axis direction.

[0038] The semiconductor device 10 includes first contact plugs 44 and second contact plugs 46. The first contact plugs 44 are arranged to overlap the field plate trenches 42 in a top view. In one example, each first contact plug 44 may be arranged in the corresponding field plate trench 42 in a top view. The second contact plugs 46 are arranged between the gate trench 14 and each field plate trench 42 in a top view.

[0039] In the example of Fig. 1, the first contact plug 44 may be cross-shaped in plan view, in the same way as the field plate trench 42. The first contact plugs 44 are not limited to the configuration shown in the example of Fig. 1 and may assume other shapes and arrangements. For example, one or more rectangular first contact plugs 44 may be arranged in the field plate trench 42, which has a cross-shaped configuration in plan view.

[0040] In the example of Fig. 1, four second contact plugs 46 are arranged point-symmetrically with respect to the center of each mesh cell M. The second contact plugs 46 may each be square in plan view. The second contact plugs 46 are not limited to the configuration shown in the example of Fig. 1 and may assume other shapes and arrangements. For example, the second contact plugs 46 may be arranged closer to the field plate trench 42 than in the example of Fig. 1.

[0041] Each first contact plug 44 and each second contact plug 46 may be constructed from any metal material. In one example, contact plugs 44 and 46 may be constructed from or composed of at least one of tungsten (W), Ti, and titanium nitride (TiN). Details of the field plate trench

[0042] With reference to Fig. 4, the field plate trench 42 of the semiconductor component 10 is now described. Fig. 4 is a schematic cross-sectional view of the semiconductor device 10 along a line F4-F4 in Fig. 3. Fig. 4 shows a cross-sectional view along the width direction (X-axis direction) of the longitudinal field plate trench portion 42Y. Although not shown in the drawings, a cross-sectional view along the length direction (Y-axis direction) of the lateral field plate trench portion 42X is the same as that shown in Fig. 4, except that the cross section is rotated by 90° in an XY plane. The cross section of the Fig. 4 shows two second contact plugs 46.

[0043] The semiconductor layer 12 including the field plate trench 42 is the same as that described with reference to Fig. 2. The semiconductor layer 12 further includes contact regions 48 arranged adjacent to the second contact plugs 46.

[0044] The contact regions 48 may be p-type regions containing p-type impurities. The contact regions 48 may have a p-type impurity concentration in a range of 1×10 19 cm -3 up to 1×10 21 cm -3 , including, which is higher than that of body region 22.

[0045] The field plate trench 42 opens in the second surface 12B of the semiconductor layer 12 and has a depth in the Z-axis direction. The field plate trench 42 extends through the source region 24 of the semiconductor layer 12 and the body region 22 to the drift region 20. The field plate trench 42 includes a sidewall 42A and a bottom wall 42B. The bottom wall 42B is adjacent to the drift region 20. The field plate trench 42 can have a depth in a range of 1 µm to 10 µm, inclusive.

[0046] The sidewall 42A of the field plate trench 42 may, but need not, extend in a direction orthogonal to the second surface 12B of the semiconductor layer 12 (Z-axis direction). In one example, the sidewall 42A may be inclined relative to the Z-axis direction such that the width of the field plate trench 42 decreases toward the bottom wall 42B. Furthermore, the bottom wall 42B of the field plate trench 42 does not necessarily have to be flat and may be partially or completely curved.

[0047] The field plate trench 42 and the gate trench 14 may have the same width or different widths. Furthermore, the field plate trench 42 and the gate trench 14 may have the same depth or different depths. In one example, the field plate trench 42 may have a greater width than the gate trench 14, and the field plate trench 42 may have a greater depth than the gate trench 14.

[0048] The semiconductor device 10 further includes a second field plate electrode 50 arranged in the field plate trench 42. A reference voltage (or source voltage) can be applied to the second field plate electrode 50. In the present specification, a trench in which the second field plate electrode 50 is arranged is referred to as the field plate trench 42. A trench in which the gate electrode 28 (see Fig. 2) is not arranged, can also be referred to as the field plate trench 42.

[0049] The second field plate electrode 50 includes an upper surface 50A covered by the insulating layer 26 and a bottom surface 50B opposite the upper surface 50A. The upper surface 50A of the second field plate electrode 50 may be disposed below the second surface 12B of the semiconductor layer 12. The second field plate electrode 50 is surrounded by the insulating layer 26.

[0050] The upper surface 50A and the bottom surface 50B of the second field plate electrode 50 may be flat or curved. Furthermore, the second field plate electrode 50 may have a uniform width in the Z-axis direction overall, but the width does not have to be uniform. For example, the second field plate electrode 50 may have a width that decreases toward the bottom wall 42B of the field plate trench 42. Furthermore, the second field plate electrode 50 may have a smaller width than the gate electrode 28 (see Fig. 2). In one example, the second field plate electrode 50 is constructed of polysilicon, which is conductive.

[0051] The first contact plug 44 is configured to couple the second field plate electrode 50 to the source electrode 38. The first contact plug 44 extends through the insulating layer 26, specifically between the top surface 50A of the second field plate electrode 50 and the source electrode 38. Accordingly, the second field plate electrode 50 is electrically connected to the source electrode 38. In one example, the first contact plug 44 may have a smaller width than the second field plate electrode 50.

[0052] The second contact plugs 46 are configured to connect the semiconductor layer 12 to the source electrode 38. The second contact plugs 46 are in contact with the contact regions 48 formed in the semiconductor layer 12. The second contact plugs 46 electrically connect the corresponding contact regions 48 to the source electrode 38. The second contact plugs 46 extend through the insulating layer 26, specifically between the semiconductor layer 12 and the source electrode 38. The second contact plugs 46 extend through the source region 24 in the semiconductor layer 12 to the body region 22. Operating mode

[0053] The operation of the semiconductor device 10 according to the present embodiment will now be described.

[0054] The semiconductor device 10 of the present embodiment includes the gate trench 14, which is arranged in a mesh pattern in plan view, and the field plate trenches 42, which are surrounded by the gate trench 14 in plan view and spaced apart from the gate trench 14. The gate electrode 28 and the first field plate electrode 30 are arranged in the gate trench 14. The second field plate electrode 50 is arranged in each field plate trench 42. The first field plate electrode 30 and each second field plate electrode 50 are electrically connected to the source electrode 38.

[0055] The first field plate electrode 30, which is electrically connected to the source electrode 38, is arranged in the gate trench 14. This reduces the concentration of a local electric field in the semiconductor layer 12 around the gate trench 14. In the same way, the second field plate electrode 50, which is electrically connected to the source electrode 38, is arranged in each field plate trench 42. This reduces the concentration of a local electric field in the semiconductor layer 12 around the field plate trenches 42. Consequently, the arrangement of the field plate trenches 42 in addition to the gate trench 14 increases the breakdown voltage of the semiconductor device 10.

[0056] Furthermore, the gate electrodes 28 are not disposed in the field plate trenches 42. Consequently, the field plate trenches 42 limit increases in the parasitic gate-drain capacitance and the parasitic gate-source capacitance while increasing the breakdown voltage of the semiconductor device 10. Comparison example

[0057] The parasitic gate-drain capacitance and the parasitic gate-source capacitance of the semiconductor device 10 will now be described with reference to a comparative example.

[0058] Fig. 5 is a schematic plan view showing a semiconductor device 100 of the comparative example. The semiconductor device 100 includes a gate trench 102 arranged in a mesh pattern in plan view, in the same manner as the gate trench 14 of the semiconductor device 10. The semiconductor device 100 does not have a trench including only one electrode to which a reference voltage (or source voltage) is applied, like the field plate trench 42 of the semiconductor device 10. Accordingly, the gate trench 102 has a relatively high density. In other words, in the semiconductor device 100, each mesh cell M' surrounded by the gate trench 102 has sides each having a relatively small dimension (shown at A). The second contact plug 46 may be arranged in each mesh cell M'.

[0059] The gate electrode 28 and the first field plate electrode 30, which are similar to those shown in Fig. 2 are arranged in the gate trench 102. The first field plate electrode 30, arranged in the gate trench 102, surrounds the mesh cells M' and increases the breakdown voltage of the semiconductor device 100. The gate electrode 28 is also arranged in the gate trench 102. Consequently, the parasitic gate-drain capacitance and the parasitic gate-source capacitance in the semiconductor device 100 are relatively large.

[0060] In this regard, the semiconductor component 10, which is shown in Fig. 1, the distance of A between the gate trench 14 and the field plate trench 42, which extend parallel to each other, that the breakdown voltage is approximately the same as that of the semiconductor device 100 shown in Fig. 5. This is because the first field plate electrode 30 in the gate trench 14 and the second field plate electrode 50 in each field plate trench 42 surround a region whose area is approximately the same as that of each mesh cell M'. The gate electrode 28 is not arranged in the field plate trench 42 of the semiconductor device 10. Consequently, the parasitic gate-drain capacitance and the parasitic gate-source capacitance are smaller in the semiconductor device 10 than in the semiconductor device 100. Advantages

[0061] The semiconductor device 10 of the present embodiment has the advantages described below. (1) The semiconductor device 10 includes the gate trench 14, which is arranged in a mesh pattern in plan view, and the field plate trenches 42 surrounded by the gate trench 14 and spaced apart from the gate trench 14. The gate electrode 28 and the first field plate electrode 30 are arranged in the gate trench 14. The second field plate electrode 50 is arranged in each field plate trench 42. The first field plate electrode 30 and each second field plate electrode 50 are electrically connected to the source electrode 38. This limits increases in the parasitic gate-drain capacitance and the parasitic gate-source capacitance while increasing the breakdown voltage of the semiconductor device 10. (2) The semiconductor device 10 may further include the first contact plugs 44, each configured to couple the corresponding second field plate electrode 50 to the source electrode 38. The first contact plug 44 extends between the top surface 50A of the second field plate electrode 50 and the source electrode 38 through the insulating layer 26. The first contact plug 44, which extends through the insulating layer 26, is used to couple the second field plate electrode 50 to the source electrode 38. This limits increases in the breakdown voltage of the semiconductor device 10 and ensures electrical connection between the second field plate electrode 50 and the source electrode 38. (3) The field plate trench 42 may be cross-shaped in plan view. This reduces the local concentration of an electric field at the mesh cells M, so that the electric field becomes relatively uniform. (4) The semiconductor layer 12 includes the contact regions 48 of the first conductivity type, and the contact regions 48 are in contact with the second contact plugs 46. This ensures an electrical connection between the source electrode 38 and the semiconductor layer 12 via the second contact plugs 46. First modified example

[0062] Fig. 6 is a schematic cross-sectional view showing the field plate trench 42 of a semiconductor device 200 according to a first modified example. In Fig. 6, those elements that are the same as the corresponding elements in the semiconductor device 10 are provided with the same reference numerals. Components that are the same as the corresponding components of the semiconductor device 10 will not be described in detail.

[0063] The semiconductor device 200 further includes third field plate electrodes 202. Each third field plate electrode 202 is arranged in a corresponding one of the field plate trenches 42 below the bottom surface 50B of the second field plate electrode 50. More specifically, each third field plate electrode 202 is arranged between the bottom surface 50B of the second field plate electrode 50 and the bottom wall 42B of the field plate trench 42. The second field plate electrode 50 and the third field plate electrode 202 of the semiconductor device 200 each have the same shape as the gate electrode 28 and the first field plate electrode 30, which are arranged in Fig. 2 are shown.

[0064] In the semiconductor device 200, the first contact plug 44 is further configured to couple the corresponding third field plate electrode 202 to the source electrode 38. The first contact plug 44 extends through the corresponding second field plate electrode 50 to the third field plate electrode 202. The first contact plug 44 extends downward from a top surface 202A of the third field plate electrode 202.

[0065] In semiconductor device 200, the second field plate electrode 50 and the third field plate electrode 202 are electrically connected to the source electrode 38. This increases the breakdown voltage in the same manner as in semiconductor device 10. Furthermore, the second field plate electrode 50 and the third field plate electrode 202 can be formed in each field plate trench 42 using a manufacturing process similar to that of the gate electrode 28 and the first field plate electrode 30 in the gate trench 14. Accordingly, the semiconductor device 200 can be manufactured using a relatively simple process. Second modified example

[0066] Fig. 7 is a schematic plan view of a semiconductor device 300 according to a second modified example. In Fig. 7, those elements that are the same as the corresponding elements in the semiconductor device 10 are provided with the same reference numerals. Components that are the same as the corresponding components of the semiconductor device 10 will not be described in detail. Fig. 7 shows a region including a single mesh cell M surrounded by the gate trench 14.

[0067] In the semiconductor device 300, each field plate trench 42 includes a first trench 302 extending in the Y-axis direction in plan view, and a second trench 304 and a third trench 306 extending in the X-axis direction and spaced apart from the first trench 302. Each first trench 302 extends between the second trench 304 and the third trench 306 in plan view.

[0068] In this way, the field plate trench 42 may include the trenches 302, 304, and 306, which are independent of each other in each mesh cell M. In this case, the first contact plugs 44 may be arranged to overlap the trenches 302, 304, and 306 in plan view.

[0069] The electric field distribution in the mesh cells M can be changed according to the shape and arrangement of the field plate trench 42 to obtain the desired breakdown voltage or operating characteristic of the semiconductor device 300. Third modified example

[0070] Fig. 8 is a schematic plan view of a semiconductor device 400 according to a third modified example. In Fig. 8, those elements that are the same as the corresponding elements in the semiconductor device 10 are provided with the same reference numerals. Components that are the same as the corresponding components of the semiconductor device 10 will not be described in detail.

[0071] In the semiconductor device 400, the mesh cells M, which are surrounded by the gate trench 14 arranged in a mesh pattern, are rectangular in plan view. In the example of the Fig. 8, each mesh cell M has a dimension in the X-axis direction that is smaller than that in the Y-axis direction.

[0072] Fig. 9 is an enlarged plan view of the semiconductor device 400 shown in Fig. 8 is shown. Fig. 9 shows a region F9 which in Fig. 8 is enclosed by single-dashed lines, and includes one of the mesh cells M surrounded by the gate trench 14.

[0073] In each mesh cell M of the semiconductor device 400, the field plate trench 42 is rectangular in plan view. In the example of Fig. 9, the field plate trench 42 extends in the X-axis direction in plan view and has a width in the Y-axis direction. That is, the longitudinal direction of the field plate trench 42 is the X-axis direction. The field plate trench 42 is arranged in a central part of the mesh cell M.

[0074] The first contact plugs 44 are arranged so that they overlap with the field plate trench 42 in plan view. In the example of the Fig. 9, the first contact plug 44 extends in the X-axis direction in plan view and has a width in the Y-axis direction in the same manner as the field plate trench 42.

[0075] The second contact plugs 46 are arranged in plan view between the gate trench 14 and the field plate trench 42. In the example of Fig. 9, the second contact plugs 46 are each square and are arranged midway between the gate trench 14 and the field plate trench 42 in the Y-axis direction. Each mesh cell M includes two second contact plugs 46.

[0076] The semiconductor device 400, which includes the rectangular mesh cells M arranged in Fig. 8 and Fig. 9, limits increases in the parasitic gate-drain capacitance and the parasitic gate-source capacitance while increasing the breakdown voltage. Fourth modified example

[0077] Fig. 10 is a schematic plan view of a semiconductor device 500 according to a fourth modified example. In Fig. 10, those elements that are the same as the corresponding elements in the semiconductor device 10 are provided with the same reference numerals. Components that are the same as the corresponding components of the semiconductor device 10 will not be described in detail. Fig. 10 shows a region including one of the mesh cells M surrounded by the gate trench 14.

[0078] In the semiconductor device 500, the second contact plugs 46 extend in the Y-axis direction and have a width in the X-axis direction. That is, the longitudinal direction of the second contact plugs 46 is the Y-axis direction. In the example of Fig. 10, the linear second contact plugs 46 are arranged between the gate trench 14 and the field plate trench 42, closer to the field plate trench 42. Each mesh cell M includes two second contact plugs 46.

[0079] In this way, the electric field distribution in the mesh cells M can be changed according to the shape and arrangement of the second contact plugs 46 to obtain the desired breakdown voltage or operating characteristic of the semiconductor device 500. Further modified examples

[0080] The above-described embodiments and modified examples may be modified as described below.

[0081] The mesh cells M do not have to be rectangular in plan view. For example, the mesh cells M can be triangular or hexagonal in plan view.

[0082] The conductivity type of any region can be reversed in the semiconductor layer 12. That is, a p-type region can be changed to an n-type region, and an n-type region can be changed to a p-type region.

[0083] The above embodiment and the modified examples described above and below can be combined with each other as long as there is no technical contradiction.

[0084] In this specification, “at least one of A and B” means “only A, only B, or both A and B”.

[0085] In this specification, the word "on" includes the meaning of "above" in addition to the meaning of "on," unless the context indicates otherwise. Accordingly, the phrase "first layer formed on second layer" may mean that the first layer is formed in direct contact with the second layer in one embodiment, and / or that the first layer is disposed above the second layer without contacting the second layer in another embodiment. Accordingly, the word "on" also allows for a structure in which another layer is disposed between the first layer and the second layer.

[0086] Terms used in this specification to indicate directions, such as vertical, horizontal, upward, downward, up, down, forward, backward, sideways, left, right, front, and back, refer to specific directions of the described and illustrated component. In this disclosure, a variety of alternative directions are available for any given direction. Accordingly, directional terms should not be interpreted narrowly.

[0087] For example, the Z-axis direction specified in this specification does not necessarily have to be the vertical direction and does not necessarily have to completely coincide with the vertical direction. For example, the X-axis direction may be the vertical direction. Alternatively, the Y-axis direction may be the vertical direction. Clauses

[0088] Technical concepts that can be understood from the above embodiments and modified examples will now be described. Reference numerals used in the described embodiment are added to corresponding elements in the clauses to facilitate understanding, but without any intention of imposing limitations on these elements. The reference numerals are provided as examples to facilitate understanding and are not intended to limit the elements to those indicated by the reference numerals. [Clause 1]

[0089] Semiconductor component with: a semiconductor layer (12); a gate trench (14) formed in the semiconductor layer (12) and arranged in a mesh pattern in a plan view; a field plate trench (42) formed in the semiconductor layer (12), the field plate trench (42) being surrounded by the gate trench (14) in plan view and being spaced from the gate trench (14); an insulating layer (26) formed on the semiconductor layer (12); a gate electrode (28) disposed in the gate trench (14), the gate electrode (28) having an upper surface (28A) covered by the insulating layer (26) and a bottom surface (28B) opposite the upper surface (28A); a first field plate electrode (30) arranged in the gate trench (14), below the bottom surface (28B) of the gate electrode (28); a second field plate electrode (50) arranged in the field plate trench (42), the second field plate electrode (50) having an upper surface (50A) covered by the insulating layer (26); and a source electrode (38) formed on the insulating layer (26), wherein the first field plate electrode (30) and the second field plate electrode (50) are electrically connected to the source electrode (38). [Clause 2]

[0090] Semiconductor component according to clause 1, further comprising: a first contact plug (44) configured to couple the second field plate electrode (50) to the source electrode (38), wherein the first contact plug (44) extends between the upper surface (50A) of the second field plate electrode (50) and the source electrode (38) through the insulating layer (26). [Clause 3]

[0091] A semiconductor device according to clause 2, wherein the first contact plug (44) overlaps the field plate trench (42) in plan view. [Clause 4]

[0092] A semiconductor device according to any one of clauses 1 to 3, wherein the field plate trench (42) is cross-shaped in plan view. [Clause 5]

[0093] A semiconductor device according to any one of clauses 1 to 3, wherein the field plate trench (42) is rectangular in plan view. [Clause 6]

[0094] A semiconductor device according to any one of clauses 1 to 3, wherein the field plate trench (42) comprises a first trench (302) extending in a first direction in plan view, and a second trench (304) and a third trench (306) spaced from the first trench (302) and extending in a second direction orthogonal to the first direction, in plan view, wherein the first trench (302) extends in plan view between the second trench (304) and the third trench (306). [Clause 7]

[0095] A semiconductor device according to any one of clauses 1 to 6, wherein the semiconductor layer (12) has a drift region (20) of a second conductivity type, a body region (22) of a first conductivity type formed on the drift region (20), and a source region (24) of the second conductivity type formed on the body region (22), and wherein the gate trench (14) and the field plate trench (42) extend through the source region (24) and the body region (22) to the drift region (20). [Clause 8]

[0096] A semiconductor device according to any one of clauses 1 to 7, further comprising: a second contact plug (46) configured to couple the semiconductor layer (12) to the source electrode (38), the second contact plug (46) extending through the insulating layer (26) between the semiconductor layer (12) and the source electrode (38). [Clause 9]

[0097] A semiconductor device according to clause 8, wherein the semiconductor layer (12) has a contact region (48) of a first conductivity type and wherein the contact region (48) is in contact with the second contact plug (46). [Clause 10]

[0098] A semiconductor device according to clause 8 or 9, wherein the second contact plug (46) is arranged between the gate trench (14) and the field plate trench (42) in plan view. [Clause 11]

[0099] A semiconductor device according to any one of clauses 2 to 10, wherein the second field plate electrode (50) has a bottom surface (50B) opposite the upper surface (50A) and the semiconductor component further comprises a third field plate electrode (202) arranged below the bottom surface (50B) of the second field plate electrode (50) in the field plate trench (42). [Clause 12]

[0100] The semiconductor device of clause 11, wherein the first contact plug (44) is further configured to couple the third field plate electrode (202) to the source electrode (38) and extends through the second field plate electrode (50). [Clause 13]

[0101] A semiconductor device according to any one of clauses 1 to 12, wherein the semiconductor layer (12) comprises mesh cells (M) surrounded by the gate trench (14), and wherein the mesh cells (M) are each rectangular in plan view. [Clause 14]

[0102] A semiconductor device according to any one of clauses 1 to 12, wherein the semiconductor layer (12) comprises mesh cells (M) surrounded by the gate trench (14), and wherein the mesh cells (M) are each square in plan view. [Clause 15]

[0103] A semiconductor device according to clause 13 or 14, wherein the field plate trench (42) is one of multiple field plate trenches (42) each arranged in the mesh cells (M).

[0104] Exemplary descriptions are provided above. In addition to the elements and methods (manufacturing processes) described to illustrate the technology of the present disclosure, those skilled in the art will recognize the potential for a wide variety of combinations and substitutions. All substitutions, modifications, and variations within the scope of the claims are intended to be included in the present disclosure. LIST OF REFERENCE SYMBOLS 10, 100, 200, 300, 400, 500 semiconductor component 12 semiconductor layer 12) first area 12) second area 14 Gate Trench 14X lateral gate trench section 14Y longitudinal gate trench section 14A side wall 14B floor wall 16 Semiconductor substrate (drain region) 18 epitaxial layer 20 Drift Region 22 body regions 24 Source Region 26 Insulating layer 28 Gate electrode 28A upper surface 28B floor area 30 first field plate electrode 30A upper surface 32 Gate insulator 34 lower insulator 36 Intermediate insulator 38 Source electrode 40 Drain electrode 42 Feldplattegraben 44 first contact plug 46 second contact plug 48 Contact region 50 second field plate electrode 202 third field plate electrode 302 first ditch 304 second ditch 306 third ditch M Mesh Cell QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2020-072158

[0003]

Claims

[1] Semiconductor component with: a semiconductor layer; a gate trench formed in the semiconductor layer and arranged in a mesh pattern in a plan view; a field plate trench formed in the semiconductor layer, the field plate trench being surrounded by the gate trench in plan view and being spaced from the gate trench; an insulating layer formed on the semiconductor layer; a gate electrode disposed in the gate trench, the gate electrode having an upper surface covered by the insulating layer and a bottom surface opposite the upper surface; a first field plate electrode disposed in the gate trench below the bottom surface of the gate electrode; a second field plate electrode arranged in the field plate trench, the second field plate electrode having an upper surface covered by the insulating layer; and a source electrode formed on the insulating layer, wherein the first field plate electrode and the second field plate electrode are electrically connected to the source electrode. [2] A semiconductor device according to claim 1, further comprising: a first contact plug configured to couple the second field plate electrode to the source electrode, wherein the first contact plug extends between the upper surface of the second field plate electrode and the source electrode through the insulating layer. [3] The semiconductor device according to claim 2, wherein the first contact plug overlaps the field plate trench in plan view. [4] A semiconductor device according to any one of claims 1 to 3, wherein the field plate trench is cross-shaped in plan view. [5] A semiconductor device according to any one of claims 1 to 3, wherein the field plate trench is rectangular in plan view. [6] A semiconductor device according to any one of claims 1 to 3, wherein the field plate trench comprises: a first trench extending in a first direction in plan view, and a second trench and a third trench spaced from the first trench and extending in a second direction orthogonal to the first direction in plan view, the first trench extending between the second trench and the third trench in plan view. [7] A semiconductor device according to any one of claims 1 to 6, wherein the semiconductor layer has a drift region of a second conductivity type, a body region of a first conductivity type formed on the drift region, and a source region of the second conductivity type formed on the body region, and wherein the gate trench and the field plate trench extend through the source region and the body region to the drift region. [8] A semiconductor device according to any one of claims 1 to 7, further comprising: a second contact plug configured to couple the semiconductor layer to the source electrode, the second contact plug extending between the semiconductor layer and the source electrode through the insulating layer. [9] A semiconductor device according to claim 8, wherein the semiconductor layer has a contact region of a first conductivity type and wherein the contact region is in contact with the second contact plug. [10] A semiconductor device according to claim 8 or 9, wherein the second contact plug is arranged between the gate trench and the field plate trench in plan view. [11] A semiconductor device according to any one of claims 2 to 10, wherein the second field plate electrode has a bottom surface opposite the top surface and the semiconductor component further comprises a third field plate electrode arranged below the bottom surface of the second field plate electrode in the field plate trench. [12] The semiconductor device of claim 11, wherein the first contact plug is further configured to couple the third field plate electrode to the source electrode and extends through the second field plate electrode. [13] A semiconductor device according to any one of claims 1 to 12, wherein the semiconductor layer comprises mesh cells surrounded by the gate trench, and wherein the mesh cells are each rectangular in plan view. [14] A semiconductor device according to any one of claims 1 to 12, wherein the semiconductor layer comprises mesh cells surrounded by the gate trench, and wherein the mesh cells are each square in plan view. [15] A semiconductor device according to claim 13 or 14, wherein the field plate trench is one of multiple field plate trenches each arranged in the mesh cells.

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