POWER OUTPUT DIGITAL-TO-ANALOGUE CONVERTER

Abstract

A current-output DAC is disclosed. In one example, a voltage-output DAC with a resistance string is followed by a voltage-to-current conversion stage to generate a first current. In some cases, an auxiliary current generator produces a second current, which is summed with the first current to extend the first current range and compensate for temperature and / or process variations. The auxiliary current generator can be correlated with both the voltage-output DAC and the transconductance stage, so that process / temperature variations affect each of the components essentially equally. The second current generated by the auxiliary current generator can act as the MSB (Most Significant Bit) range of the total current output. In some examples, the current-output DAC exhibits an extended output current range without modifying the transfer characteristic gain or the size of the least significant bit of the DAC.

Description

BACKGROUND

[0001] Digital-to-analog converters (DACs) are widely used in many applications to process incoming digital signals and convert them into the analog domain. A given DAC can be configured as a voltage-output DAC or a current-output DAC. Both of these DAC types are similar in that they both produce an output that is a function of a digital input code. A key difference between the two DAC types is that voltage-output DACs use a resistive or capacitive network to transmit a digital quantity (as represented by the input code) in the form of a voltage, while current-output DACs use fully decoded controlled current sources to transmit the digital quantity in the form of a current.Current-output DACs can be used in any number of applications, but due to their ability to drive low output impedances, they are commonly used in high-speed applications. However, non-trivial problems remain associated with current-output DACs. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Features and advantages of embodiments of the claimed subject matter will become apparent in the course of the following detailed description and with reference to the drawings, in which: Fig. 1a illustrates a block diagram of an exemplary current output DAC configured according to an embodiment of the present disclosure; Fig. 1b illustrates the adverse effect that temperature and / or process fluctuations have on the output current range of the current output DAC. Fig. 1a can have; Fig. 2 a block diagram of another exemplary current output DAC, which is designed to be less susceptible to changes in the output current range due to temperature and / or process variations, according to an embodiment of the present disclosure; Fig. 3 a schematic diagram of a voltage output DAC and an auxiliary current generator made of Fig. 2 illustrated according to some embodiments of the present disclosure; Fig. 4 a schematic diagram of a voltage-current transconductance stage made of Fig. 2 illustrated according to an embodiment of the present disclosure; Fig. 5 a schematic diagram using a coarse-fine DAC and the auxiliary current generator from Fig. 2 illustrated according to an embodiment of the present disclosure; and Fig. Figure 6 illustrates a block diagram for a photon counting system that connects the current output DAC to the power supply. Fig. 2 according to one embodiment of the present disclosure.

[0003] Although the following detailed description continues with reference to illustrative embodiments, many alternatives, modifications and variations thereof become obvious in light of this disclosure. DETAILED DESCRIPTION

[0004] A current-output DAC is disclosed. Although the DAC design can be used in any number of applications, it is particularly useful in applications requiring an extended output current range. As explained, it is worth noting that such an extended output current range can be achieved without modifying the transfer characteristic gain or the size of the least significant bit (LSB) of the DAC, as is the case in some embodiments. In one example according to the present disclosure, the current-output DAC comprises a voltage-output DAC with a resistance string, followed by a transconductance or voltage-to-current converter stage for generating a first current. In some such embodiments, this first current can be used as the output current of the DAC.In other such embodiments, such as those where the output current range of the DAC is susceptible to changes due to temperature and / or process variations, the current-output DAC further comprises an auxiliary current generator that produces a second current which is summed with the first current to provide the output current. As is recognized in light of this disclosure, summing the first current with the second extends the range of the DAC's output current and compensates for temperature and / or process variations. It should be noted that both the second current and the resulting output current can be scaled arbitrarily by a constant to suit a given application. The auxiliary current generator is correlated with both the voltage-output DAC and the voltage-to-current converter stage, so process / temperature variations affect each of the components essentially equally.According to some such embodiments, the second current generated by the auxiliary current generator acts as the MSB (Most Significant Bit) portion of the total current output or a combination of the most weighted bits. Other advantages and embodiments become apparent in light of this disclosure. General overview

[0005] As noted above, non-trivial problems remain associated with current-based DACs. For example, the output current range of a current-output DAC tends to be very sensitive to process and temperature variations, which can make such DACs unreliable in certain applications. More precisely, the output current of a current-output DAC depends essentially linearly on the magnitude of the digital input signal, making the current range approximately equal to the difference between the output current for the maximum digital input signal and the output current for the minimum digital input signal. However, this range can end up lower than expected due to various semiconductor process variations that occur during the manufacturing process and / or temperature variations that occur during operation. Such an impact on the output current range can have negative consequences for some applications.For example, an incorrect current output range can cause errors in downstream processing, potentially leading to the failure or malfunction of certain applications. In one specific example, a current output DAC might be used to compensate for leakage current in a photon counter, and an incorrect output current range from the DAC will not adequately compensate for the leakage current, which in turn can cause counting errors. One possible solution to increase the output current range of the DAC involves adjusting or trimming the transconductor gain to achieve the required range, while another possible solution involves using additional active circuitry to reduce process and temperature variations affecting the resistors.However, such solutions would require a relatively large chip area, implementing and / or adversely affecting the DAC-LSB granularity, and are therefore possibly not suitable for all applications.

[0006] This document provides current-output DAC designs that include a current DAC design with an increased output current range. According to one embodiment, the current-output DAC uses a voltage-output DAC coupled to a transconductance stage to convert the voltage output from the voltage-output DAC into a current. In some such examples, the range of this DAC output current is amplified using an auxiliary current generator correlated with the voltage-output DAC to ensure that process / temperature variations affect both substantially equally. The generated auxiliary current can be scaled before being added to the DAC current. By generating a separate correlated current (Iaux) to add to the DAC current (Idac), the LSB granularity and gain of the DAC remain consistent over a relatively large output current range.The current-output DAC with an extended output current range is particularly useful in applications where outputting a lower-than-expected current is detrimental. One such example is using the current-output DAC to generate a current that compensates for leakage current generated by a photodetector.

[0007] In some embodiments, the voltage-output DAC includes a buffer stage for generating a current through a resistor string with outputs coupled to a multiplexer. The multiplexer is controlled via select lines that receive the digital input signal or digital input code to select an output voltage corresponding to the digital input signal. In some embodiments, an auxiliary current generator includes a first transistor with a gate node coupled to a gate node of a second transistor in the buffer stage of the voltage-output DAC. The voltage output from the voltage-output DAC is received by a transconductance stage comprising both (1) a resistor matched to the resistor string and (2) a series of current mirrors for converting the voltage into a DAC current output.According to some embodiments, the transconductance stage also receives the auxiliary current generated by the first transistor and adds a scaled version of this auxiliary current to the DAC current output to produce the final output current with an extended range due to the addition of the auxiliary current. The final output current can also be scaled using a current mirror arrangement, according to some embodiments.

[0008] In one specific embodiment, a circuit comprises a voltage-output DAC, a transconductance stage, and an auxiliary current generator. The voltage-output DAC is designed to receive a binary input signal and provide an output voltage corresponding to a magnitude of the binary input signal. The transconductance stage is designed to receive the output voltage from the voltage-output DAC and generate a DAC current based on a magnitude of the output voltage. The auxiliary current generator is designed to generate an auxiliary current, which in some examples corresponds to a string current used within the voltage-output DAC. The resulting DAC current and the auxiliary current are summed to produce an output current with an extended range relative to the DAC current provided by the transconductance stage.

[0009] In another embodiment, a current-output DAC circuit with an extended output current range comprises a voltage-output DAC, a transconductance stage, and an auxiliary current generator. The voltage-output DAC is designed to receive a binary input signal and includes a multiplexer, a resistor string, and a buffer stage. The buffer stage includes a first transistor designed to provide a string current across the resistor string. The transconductance stage is designed to receive an output voltage from the voltage-output DAC and to generate a DAC current based on the magnitude of the output voltage. The auxiliary current generator includes a second transistor with a gate node coupled to a gate node of the first transistor. The second transistor is designed to provide an auxiliary current.The DAC current and the auxiliary current are summed to produce an output current of the current-output DAC circuit, with the output current having an extension relative to the DAC current provided by the transconductance stage.

[0010] In another embodiment, a photon counting system comprises a photon detector configured to generate a current pulse in response to the reception of one or more photons, a current-output DAC configured to compensate for a leakage current associated with the photon detector, a front-end circuit configured to convert the current pulse into a voltage pulse, a discriminator circuit comprising a plurality of comparators configured to receive the voltage pulse and determine a relative amplitude of the voltage pulse, and one or more counters configured to count a number of received voltage pulses of varying amplitudes. The current-output DAC comprises a voltage-output DAC, a transconductance stage, and an auxiliary current generator.The voltage-output DAC is designed to receive a binary input signal and provide an output voltage corresponding to a magnitude of that binary input signal. The transconductance stage is designed to receive the output voltage from the voltage-output DAC and generate a DAC current based on a magnitude of that output voltage. The auxiliary current generator is designed to generate an auxiliary current corresponding to a string current used within the voltage-output DAC. The resulting DAC current and the auxiliary current are summed to produce an output current used to compensate for leakage current.

[0011] Numerous variations and alternative embodiments are recognized in light of this disclosure. The description uses the phrases "in one embodiment" or "in embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "encompassing," "exhibiting," and the like, as used in relation to embodiments of the present disclosure, are synonymous. When used to describe a range of dimensions, the phrase "between X and Y" represents a range encompassing X and Y.

[0012] Furthermore, it should be noted that referring to transistor features such as gate, source, or drain is not intended to exclude any transistor technologies. For example, features such as source, drain, and gate are typically used to refer to a field-effect transistor (FET), while emitter, collector, and base are typically used to refer to a bipolar junction transistor (BJT). Such features can be used interchangeably here, as can be seen. For example, referring to the gate of a transistor can also be understood to refer to either the gate of a FET or the base of a BJT, and vice versa. Any other suitable transistor technologies can be used.As can further be seen, any such transistor can be used as a switch, with the gate or base or some other comparable feature acting as a switch selection input which can be driven to connect the source and drain (or the emitter and collector, as may be the case). Power output DAC configuration

[0013] As mentioned above, the output current range of a current-output DAC depends on the range of digital input signals (e.g., binary codes) and also on manufacturing process variations and / or operating temperature variations. Fig. Figure 1a illustrates a block diagram of an exemplary current-output DAC configured according to an embodiment of the present disclosure. As can be seen, the current-output DAC comprises a voltage-output DAC 102 followed by a transconductor or voltage-to-current converter 104. During operation, a digital input code is received at the input of the DAC 102, causing the DAC 102 to generate a corresponding output voltage (Vdac). The output voltage Vdac is received at the input of the transconductor 104, causing the transconductor 104 to generate a corresponding current output (Idac). Fig. Figure 1b illustrates an example diagram of the output current (Idac) over a range of received digital input codes from code_min to code_max for the current output DAC. Fig. 1a. Due in part to the closed-loop feedback operation in transconductor 104, the output current depends essentially linearly on the magnitude of the received digital signal. The current range output of the current-output DAC is generally provided by Iout(code_max) - Iout(code_min). In some examples, the current output at code_min is at or near zero, making the output current range essentially equal to Iout(code_max).

[0014] The expected Iout target when code_max is received is shown by the middle dashed line. This is achieved in the ideal scenario, represented by the middle data line. However, process and temperature variations can cause the current output to shift up or down. The upper data line represents a scenario where the output current was increased due to these variations and still remained within the desired current output range (e.g., above the middle dashed line). The lower data line, however, represents a scenario where the output current was decreased due to these variations. If the output current is lower than expected, this can have adverse effects for many applications.In such cases, a current output DAC design configured with an auxiliary current generator, as provided in various forms herein, can be used to ensure that the desired output current range is maintained despite variations in the manufacturing process and / or operating temperature.

[0015] Fig. Figure 2 illustrates a DAC circuit 200 with an extended output current range according to a further embodiment of the present disclosure. The DAC circuit 200 comprises a voltage output DAC 202, a transconductance stage 204, and an auxiliary current generator 206. The voltage output DAC 202 is correlated with both the transconductance stage 204 and the auxiliary current generator 206 (generally indicated by dashed lines), such that process and temperature variations affect each of the components substantially equally in some examples. As further shown in this example, the DAC circuit 200 also includes a first amplification stage 208 and a second amplification stage 210. The voltage output DAC 202 receives a digital signal input (e.g., a binary code input) and outputs an analog voltage signal Vdac corresponding to a magnitude of the received code input.The transconductance stage 204 receives Vdac and uses one or more current mirrors coupled to one or more resistors to convert the voltage into an output current Idac. As can be seen, the transconductance stage 204 can be implemented as a transconductance operational amplifier, which is a voltage-to-current converter, such that Idac equals Gm·Vdac, where Gm is the transconductance gain.

[0016] According to some embodiments, the auxiliary current generator 206 produces an auxiliary current Iaux which corresponds to the current generated within the voltage output DAC 202 through its string of resistors, as referred to in Fig. 3 is discussed in more detail. In some examples, the auxiliary current correlates with the LSB (step) size of the voltage DAC. Accordingly, process and / or temperature variations that affect the operation of the voltage output DAC 202 (and its string current) also affect the operation of the auxiliary current generator 206 (and its auxiliary current Iaux) in essentially the same way. As can be seen further in this example, the first gain stage 208 can be used to set Iaux by a constant. It should be noted that the constant can provide a fractional gain (less than 1) for downscaling, or a full gain (greater than one) for upscaling, or a unity gain (gain of 1). In some embodiments, the auxiliary current generator 206 includes a transconductor for generating the auxiliary current Iaux.One such example of a transconductor is a field-effect transistor, as referenced in . Fig. 3 discussed in more detail.

[0017] As can be seen further in this exemplary embodiment, Idac is added to Iaux, and the resulting summed current Iout can be amplified by a constant at the second amplification stage 210. Due to the addition of Iaux, Iout has a wider range compared to Idac. Each of the components of the DAC circuit 200 can, for example, be located on a single chip or within a single chip package. In other embodiments, components of the DAC circuit 200 can be mounted on a printed circuit board.

[0018] Fig. Figure 3 illustrates a more detailed circuit diagram of the voltage-output DAC 202 and the auxiliary current generator 206 according to some embodiments. The voltage-output DAC 202 may include a first buffer stage that receives a reference voltage Vrefp at the positive input of a transconductance operational amplifier 302 to set the positive voltage reference of the resistor string 306. The output of the transconductance operational amplifier 302 is coupled to a gate node of a first transistor 304, which in this example is a FET, to generate a string current Istr that flows through a resistor string 306. The negative reference voltage Vrefn of the resistor string 306 is received at the operational amplifier 303 at a second buffer stage, so that the string current Istr is equal to (Vrefp - Vrefn) / Rstring, where Rstring is the combined resistance of the series of resistors in the resistor string 306.

[0019] According to some embodiments, the resistor string 306 comprises a series of resistors for generating different voltage levels between each resistor in the string. Each of the different voltage levels is coupled to inputs of a multiplexer 308, which has select lines that receive the digital code (e.g., a 3-digit binary code, but any digital code can be used). Accordingly, the received digital code selects one of the voltage levels generated by the string current Istr flowing through the resistor string 306. The selected voltage is buffered using the operational amplifier 310 and is output as Vdac.

[0020] According to some embodiments, the gate node of the first transistor 304 within the voltage-output DAC 202 is also coupled to a gate node of a second transistor 312 within the auxiliary current generator 206. In some exemplary embodiments, the first transistor 304, with a width-to-length (W / L) ratio represented by n1, and the second transistor 312, with a W / L ratio represented by n2, are matched transistors (e.g., having the same W / L ratios or ratios within 0.5% of each other). In the example where n1 = n2, then the current Iaux1 provided by the second transistor 312 is essentially equal to the string current Istr provided by the first transistor 304.In some other exemplary embodiments, Iaux1 is a scaled version of Istr based on the difference between the W / L ratios of the first transistor 304 and the second transistor 312. In such cases, it should be noted that Iaux1 can be scaled up or down depending on whether n2 is greater or less than n1.

[0021] According to some embodiments, the auxiliary current generator 206 also includes a current mirror arrangement 314 with transistors having a first W / L ratio (k1) and a second W / L ratio (k2) to provide a scaling factor for Iaux1. Accordingly, in one example where k1 = k2, Iaux2 is equal to Iaux1. In other examples, Iaux2 is a scaled version (upward or downward) of Iaux1 based on the ratio between k1 and k2. In some embodiments, Iaux2 has the opposite sign to Iaux1.

[0022] Fig. Figure 4 illustrates a more detailed circuit diagram of the transconductance stage 204 according to some embodiments. The transconductance stage 204 receives the voltage output (Vdac) from the voltage-output DAC 202 at a first buffer stage, which, for example, comprises the transconductance operational amplifier 402. The lower voltage reference Vrefn is received at a second buffer stage, which, for example, comprises the operational amplifier 403. The output of the transconductance operational amplifier 402 is received at the gate node of two interconnected transistors with a first W / L ratio (k3) and a second W / L ratio (k4). The first transistor with the first W / L ratio k3 generates the current Idac through a resistor 404, which is essentially the same as the series resistance of the resistor string 306 of the voltage-output DAC 202.Accordingly, Idac equals (Vdac - Vrefn) / Rdac, where Rdac is the resistance of resistor 404 and is essentially equal to Rstring. Depending on the ratio between k3 and k4, Idac, or a scaled version of Idac, also flows into another current mirror with two connected transistors having a first W / L ratio (k5) and a second W / L ratio (k6). The mirrored current resulting from this current mirror is added to the auxiliary current Iaux2, which is generated by the auxiliary current generator 206 at node 406. If k3 = k4 and k5 = k6, then Iaux2 is combined with Idac at node 406. Otherwise, a scaled version of Idac is combined with Iaux2 at node 406. The combined currents can flow through another current mirror arrangement with two connected transistors having a first W / L ratio (k7) and a second W / L ratio (k8) according to some embodiments.

[0023] According to some such embodiments, based on the various current mirror arrangements for providing current scaling, the total range of the final output current Iout is given by the following equation 1. ((Vrefp−Vrefn)∗k4∗k6Rdac∗k3∗k5+Iaux1∗k1∗n2k2∗n1)∗k8k7

[0024] As can be seen, Equation 1 provides the magnitude of the current range by taking into account the difference between the maximum voltage output of the voltage-output DAC (Vrefp) and the minimum voltage output of the voltage-output DAC (Vrefn). Determining the output current Iout for a given DAC voltage Vdac can be done by substituting Vrefp for Vdac in Equation 1.

[0025] The transistors from the circuit diagrams in Fig. 3 or Fig. Four are illustrated as either p-channel or n-channel FETs. However, this is just one example, and transistors of any type can be used throughout.

[0026] The auxiliary current generator 206 can be used with many different types of voltage output DAC designs. Fig. Figure 5 illustrates an exemplary coarse-fine voltage output DAC 500, which uses transistor 304 to provide an auxiliary current Iaux, as discussed above, according to one embodiment. The coarse-fine voltage output DAC 500 (also known as a two-stage voltage output DAC) is similar in operation to the voltage output DAC 202, except that it uses two stages of resistor strings, each coupled to a corresponding multiplexer. As can be seen, a first coarse stage comprises a coarse resistor string 502 coupled to a coarse multiplexer 504, which operates in the same way as the resistor string 306 and the multiplexer 308. Fig. 3. The output from the coarse stage is buffered via the operational amplifier 512 (similar to the operational amplifier 310) and received by a plurality of fine stages 505, each comprising a fine resistor string 506 coupled to a fine multiplexer 508. The coarse-to-fine voltage output DAC 500 ultimately produces a voltage output (Vdac) with a finer granularity or resolution than that produced by the voltage output DAC 202. According to some embodiments, the voltage is converted into a current using the same transconductance stage 204.

[0027] According to some embodiments, the coarse-fine voltage output DAC 500 includes the same auxiliary current generator 206 with transistor 304 coupled to the coarse-fine voltage output DAC 500. As discussed above, the gate node of transistor 304 is coupled to the gate node of transistor 510 within a first buffer stage of the coarse-fine voltage output DAC 500. Due to the correlation between transistors 304 and 510, process and / or temperature variations affect the current output of each transistor essentially equally. The auxiliary current generated by transistor 304 in the coarse-fine voltage output DAC 500 can be scaled and added to the transconductance current (Idac) derived from the coarse-fine DAC output voltage (Vdac), with the final output current being calculated with an extended range (e.g., the sum of Iaux and Idac) in the same manner as described above. Fig. 4 is shown being generated.

[0028] Current output DACs find many uses in high-speed applications and can be used to compensate for leakage currents in sensor devices. Fig.Figure 6 illustrates an exemplary photon counting system 600 comprising an integrated circuit (IC) 602 and a photon detector 604. The process technology by which the IC 602 is formed can be, for example, a complementary metal-oxide semiconductor (CMOS), although other process technologies can also be used. The photon detector 604 can, for example, comprise any number of special material layers that convert photons of a specific energy into charge. When a photon strikes the material in the photon detector 604, a square-wave current pulse can be generated. In some embodiments, the photon detector 604 is configured with material suitable for generating charge when photons with X-ray energy strike the material, although any spectrum of radiation can be detected for a given application.

[0029] The current pulses generated by the photon detector 604 are received by the front-end circuit 606. In some embodiments, the front-end circuit 606 is designed to filter the received current pulses and convert them into output voltage pulses. The output voltage pulses are received by a discriminator 608, which comprises a plurality of operational amplifier comparators that apply different predetermined voltage levels (VDS(on)) to the received voltage pulses. th 1 - V th N ) compare. A series of counters 610 is used to track the amplitudes of the received voltage pulses depending on how they compare with the predetermined voltage levels. The different received voltage pulse amplitudes correspond to a number of photons received at the photon detector 604 according to some embodiments.

[0030] According to some embodiments, the photon detector 604 can also generate a leakage current, which can be any generated current that differs from the photon current. This leakage current should be compensated in some way; otherwise, it can lead to incorrect photon counts. Thus, according to some embodiments, the current-output DAC circuit 200 with an extended output current range is included on IC 602 to provide an output current that can compensate for any leakage current generated by the photon counter 604. The output current (Iout) from the DAC circuit 200 is added to any leakage current from the photon detector 604 before the current is received by the CMOS front end 606, according to some embodiments.

[0031] The IC 602 can be a single chip made of silicon or another semiconductor material, or it can represent a system-on-a-chip architecture. In some other examples, the components of the IC 602 can be manufactured on multiple chips that are packed together in a multi-chip package.

[0032] Unless specifically stated otherwise, terms such as "processing," "calculating," "determining," or the like are understood to refer to the action and / or process of a computer or computing system or similar electronic computing device that manipulates and / or converts data represented as physical quantities (for example, electronically) within the registers and / or storage units of the computer system into other data similarly represented as physical quantities within the registers, storage units, or other such information storage transfers or displays of the computer system. The embodiments are not limited in this context.

[0033] The terms "circuit" or "circuit," as used herein in any embodiment, may, for example, individually or in any combination, refer to a hard-wired circuit, a programmable circuit such as computer processors having one or more individual instruction-processing cores, a state machine circuit, and / or firmware that stores instructions to be executed by a programmable circuit. The circuit may include a processor and / or controller configured to execute one or more instructions to perform one or more operations described herein. The instructions may, for example, be implemented as an application, software, firmware, etc., configured to cause the circuit to perform any one of the foregoing operations.Software can be implemented as a software package, code, instructions, instruction sets, and / or data recorded on a computer-readable storage device. Software can be implemented or executed to encompass any number of processes, and processes can, in turn, be implemented or executed to encompass any number of threads, and so on, in a hierarchical manner. Firmware can be implemented as code, instructions or instruction sets, and / or data hard-coded (e.g., non-volatile) on storage devices. The circuit can be implemented, collectively or individually, as a circuit that forms part of a larger system, for example, an integrated circuit (IC), an application-specific integrated circuit (ASIC), a system-on-a-chip (SoC), desktop computers, laptop computers, tablet computers, servers, smartphones, etc.Other embodiments may be implemented as software executed by a programmable control device. As described herein, various embodiments may be implemented using hardware elements, software elements, or any combination thereof. Examples of hardware elements may include processors, microprocessors, circuits, circuit components (e.g., transistors, resistors, capacitors, inductors, and so on), integrated circuits, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), logic gates, registers, semiconductor devices, chips, microchips, chipsets, and so on.

[0034] Numerous specific details have been set forth herein to provide a thorough understanding of the embodiments. However, a person skilled in the art will understand that the embodiments can be carried out without these specific details. In other cases, well-known operations, components, and circuits have not been described in detail to avoid obscuring the embodiments. It is understood that the specific structural and functional details disclosed herein may be representative and do not necessarily limit the scope of the embodiments. Although the subject matter has additionally been described in language specific to structural features and / or methodological actions, it is understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described herein.Rather, the specific characteristics and actions described herein are revealed as exemplary forms of implementing the claims.

Claims

[1] Circuit comprising: a digital-to-analog converter (DAC) configured to receive a binary input signal and to provide an output voltage corresponding to a magnitude of the binary input signal; a transconductance stage configured to receive the output voltage from the DAC and to generate a DAC current based on a magnitude of the output voltage; and an auxiliary power generator arranged to generate an auxiliary power; where the DAC current and the auxiliary current are summed to produce an output current. [2] The circuit of claim 1, wherein the DAC comprises a buffer stage including a first transistor configured to generate a string current flowing through a resistor string, the auxiliary current corresponding to the string current. [3] The circuit of claim 2, wherein the DAC comprises a multiplexer having a plurality of inputs coupled along the resistor string and select inputs configured to receive the binary input signal. [4] The circuit of claim 2, wherein the transconductance stage has a resistance matched to a combined resistance of the resistor string. [5] The circuit of claim 2, wherein the auxiliary current generator comprises a second transistor having a gate node coupled to a gate node of the first transistor. [6] The circuit of claim 5, wherein the first transistor is matched to the second transistor. [7] The circuit of claim 1, wherein the auxiliary current correlates with the LSB(Step) size of the voltage DAC. [8] The circuit of claim 1, wherein the auxiliary current generator comprises a current mirror having a first transistor with a first width / length (W / L) ratio and a second transistor with a second W / L ratio different from the first W / L ratio, the current mirror being configured to scale the auxiliary current by a constant based on a ratio between the first and second W / L ratios. [9] The circuit of claim 1, further comprising an amplification stage configured to receive the output current. [10] The circuit of claim 9, wherein the amplification stage comprises a current mirror arrangement having a first transistor with a first width / length (W / L) ratio and a second transistor with a second W / L ratio different from the first W / L ratio, the current mirror being configured to scale the output current by a constant based on a ratio between the first and second W / L ratios. [11] The circuit of claim 1, wherein the DAC is a coarse-fine DAC comprising a coarse stage and a fine stage. [12] The circuit of claim 1, wherein the auxiliary current generator comprises a transconductor configured to generate the auxiliary current. [13] A photon counting device comprising the circuit of claim 1. [14] Digital-to-analog converter (DAC) circuit comprising: a voltage output DAC configured to receive a binary input signal and generate a corresponding output voltage, the voltage output DAC comprising a multiplexer, a resistor string, and a buffer stage, the buffer stage comprising a first transistor configured to provide a string current across the resistor string; a transconductance stage configured to receive the output voltage from the voltage output DAC and to generate a DAC current based on a magnitude of the output voltage; and an auxiliary current generator having a second transistor configured to provide an auxiliary current; where the DAC current and the auxiliary current are summed to produce an output current. [15] The DAC circuit of claim 14, wherein the multiplexer comprises a plurality of inputs coupled along the resistor string and select inputs configured to receive the binary input signal. [16] The DAC circuit of claim 14, wherein the transconductance stage has a resistance matched to a combined resistance of the resistor string. [17] The DAC circuit of claim 14, wherein a gate node of the first transistor is coupled to a gate node of the second transistor. [18] The DAC circuit of claim 14, wherein the auxiliary current generator comprises a current mirror having a first transistor with a first width / length (W / L) ratio and a second transistor with a second W / L ratio different from the first W / L ratio, the current mirror being configured to scale the auxiliary current by a constant based on a ratio between the first and second W / L ratios. [19] The DAC circuit of claim 14, further comprising an amplification stage configured to receive the output current. [20] The DAC circuit of claim 19, wherein the gain stage comprises a current mirror arrangement having a first transistor with a first width / length (W / L) ratio and a second transistor with a second W / L ratio different from the first W / L ratio, the current mirror being configured to scale the output current by a constant based on a ratio between the first and second W / L ratios. [21] The DAC circuit of claim 12, wherein the voltage output DAC is a coarse-to-fine voltage output DAC. [22] A photon counting device comprising the DAC circuit of claim 12. [23] Photon counting system comprising: a photon detector arranged to generate a current pulse in response to receiving one or more photons; and a current output digital-to-analog converter (DAC) configured to compensate for a leakage current associated with the photon detector; where the current output DAC has: a voltage output DAC configured to receive a binary input signal and to provide an output voltage corresponding to a magnitude of the binary input signal, a transconductance stage configured to receive the output voltage from the DAC and to generate a DAC current based on a magnitude of the output voltage, and an auxiliary power generator arranged to generate an auxiliary power, where the DAC current and the auxiliary current are summed to produce an output current that is used to compensate for the leakage current. [24] A photon counting system according to claim 23, further comprising: a front-end circuit configured to convert the current pulse into a voltage pulse; a discriminator circuit having a plurality of comparators and configured to receive the voltage pulse and to determine a relative amplitude of the voltage pulse; and one or more counters configured to count a number of received voltage pulses of different magnitudes. [25] The photon counting system of claim 23, wherein the voltage output DAC comprises: a resistance string; a buffer stage having a first transistor configured to generate a string current across the resistor string, wherein the auxiliary current corresponds to the string current; and a multiplexer having a plurality of inputs coupled along the resistor string and selection inputs configured to receive the binary input signal. [26] The photon counting system of claim 25, wherein the transconductance stage has a resistance matched to a combined resistance of the resistor string. [27] The photon counting system of claim 25, wherein the auxiliary current generator comprises a second transistor having a gate node coupled to a gate node of the first transistor. [28] The photon counting system of claim 27, wherein the first transistor is matched to the second transistor. [29] The photon counting system of claim 23, wherein the auxiliary current generator comprises a current mirror having a first transistor with a first width / length (W / L) ratio and a second transistor with a second W / L ratio different from the first W / L ratio, the current mirror being configured to scale the auxiliary current by a constant based on a ratio between the first and second W / L ratios. [30] A photon counting system according to claim 23, further comprising an amplification stage arranged to receive the output current. [31] The photon counting system of claim 30, wherein the amplification stage comprises a current mirror arrangement having a first transistor with a first width / length (W / L) ratio and a second transistor with a second W / L ratio different from the first W / L ratio, the current mirror being configured to scale the output current by a constant based on a ratio between the first and second W / L ratios. [32] The photon counting system of claim 23, wherein the voltage output DAC is a coarse-to-fine voltage output DAC. [33] The photon counting system of claim 23, wherein the auxiliary current generator comprises a transconductor configured to generate the auxiliary current.

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