Method and device for determining the running time

Abstract

A first communication device receives an analog receive signal over a communication medium. An ADC of the first communication device converts the analog receive signal into a digital receive signal. Logic circuitry of the first communication device detects a plurality of timing signals from a second communication device based on an analysis of the digital receive signal. The logic circuitry adjusts a sampling phase of the ADC in association with at least some of the timing signals such that the ADC uses different sampling phases when different ones of the timing signals are detected. The logic circuitry determines timing information based on the detection of the plurality of timing signals when the ADC uses different sampling phases when different ones of the timing signals are detected.The first communication device determines a propagation time between the first communication device and the second communication device based on the timing information.

Description

Cross-references to related applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 417,984, entitled "Clock-Based Topology Discovery," filed October 20, 2022, the disclosure of which is expressly incorporated herein by reference in its entirety. field of technology

[0002] The present disclosure relates essentially to in-vehicle communication networks and, in particular, to topology detection in in-vehicle communication networks. background

[0003] In-vehicle communication networks enable data exchange between a vehicle's components. The IEEE (Institute for Electrical and Electronics Engineers) standard 802.3cg defines a communication protocol for communication over a single twisted-pair cable at speeds of up to 10 megabits per second (Mbps), sometimes referred to as 10BASE-T1S, intended for use in vehicles. The 10BASE-T1S standard supports both point-to-point and multidrop communication. Multidrop communication allows three or more communication devices to communicate over a single cable.

[0004] In a multidrop network using the 10BASE-T1S standard, multiple identical devices can be connected to a single twisted-pair cable, with the function of each device depending on its physical location within the vehicle. For example, multiple identical radar sensors can be connected to a single twisted-pair cable, with a first radar located at the rear of the vehicle, a second radar at the front of the vehicle, a third radar near the driver's side, and a fourth radar near the passenger side. Due to its position, the first radar is used to detect objects behind the vehicle (e.g.,when the vehicle is reversing); the second radar is used to detect objects in front of the vehicle; the third radar is used to detect objects in a side view from the driver's side of the vehicle; and the fourth radar is used to detect objects in a side view from the passenger side of the vehicle.

[0005] If the general physical layout of the cable within the vehicle is known, a control unit connected to the cable can identify the devices connected to the cable based on the respective distances of the devices along the cable from the control unit. Fig. 1 is a simplified illustration of a vehicle 100 having an in-vehicle communications network 102 including an electronic control unit (ECU) 104 and sensors 108, 112, 116, and 120 (e.g., radar sensors, lidar sensors, etc.) electrically connected by a cable 124. Sensor 108 is located a first distance D1 along cable 124 from the ECU 104; sensor 112 is located a second distance D2 along cable 124 from the ECU 104; sensor 116 is located a third distance D3 along cable 124 from the ECU 104; and sensor 120 is located a fourth distance D4 along cable 124 from ECU 104. If ECU 104 knows the general physical layout of cable 124 within the vehicle and the respective distances of sensors 108, 112, 116, and 120 along cable 124 from ECU 104, ECU 104 can determine the respective functions of sensors 108, 112, 116, and 120.For example, if sensors 108, 112, 116, and 120 are radar sensors, ECU 104 may determine based on their respective distances from ECU 104 that: i) the radar sensor 108 is a rear-looking radar; ii) the sensor 112 is a side-looking radar on the driver's side; iii) the sensor 116 is a forward-looking radar; and iv) the sensor 120 is a side-looking radar on the passenger side.

[0006] Although Fig. 1 shows a communication network comprising a control unit and sensors, a communication network also includes other suitable components such as actuators (e.g. for door locks, windows, sunroof / moon roof, side mirrors, etc.), buttons, lights, etc.

[0007] One technique for determining the distance between two devices in a network such as the in-vehicle communications network 102 is to measure the time it takes for a signal (e.g., a pulse) to travel from a first device to a second device over a communications medium (sometimes referred to as "propagation time"). For example, the first device may transmit a forward pulse to the second device, and in response to receiving the forward pulse, the second device sends a reverse pulse back to the first device. The first device measures the time between the transmission of the forward pulse and the receipt of the reverse pulse and uses the time to calculate the distance between the first device and the second device.To improve accuracy, the first device and the second device may repeatedly transmit forward pulses and reverse pulses and measure a total time for transmitting and receiving the forward and reverse pulses. For example, in response to the received reverse pulse, the first device transmits another forward pulse to the second device, which then transmits another reverse pulse to the first device, and so on. The first device then measures a time between the transmission of the first forward pulse and the reception of the last reverse pulse and uses this time to calculate the distance between the first device and the second device. Summary

[0008] In one embodiment, a transceiver associated with a first communication device comprises: an analog-to-digital converter (ADC) configured to generate a digital receive signal based on an analog receive signal received over a communication medium; timing signal detection circuitry coupled to the ADC, the timing signal detection circuitry configured to detect a plurality of timing signals from a second communication device based on an analysis of the digital receive signal; sampling phase generation circuitry coupled to the ADC, the sampling phase generation circuitry configured to adjust a sampling phase used by the ADC in connection with at least some of the timing signals such that the ADC uses different sampling phases when different ones of the timing signals are detected;a timing information determination circuit configured to determine timing information based on the detection of the plurality of timing signals when the ADC uses different sampling phases when different ones of the timing signals are detected; and a processor configured to determine the propagation time based on the timing information.

[0009] In another embodiment, a method for measuring a propagation time between a first communication device and a second communication device comprises: receiving an analog receive signal over a communication medium in the first communication device; converting the analog receive signal into a digital receive signal in an ADC of the first communication device; detecting a plurality of timing signals from the second communication device based on an analysis of the digital receive signal in a logic circuit of the first communication device; adjusting, in the logic circuit, a sampling phase of the ADC in association with at least some of the timing signals such that the ADC uses different sampling phases when different ones of the timing signals are detected;Determining, in the logic circuit, timing information based on the detection of the plurality of timing signals when the ADC uses different sampling phases when different ones of the timing signals are detected; and determining, in the first communication device, the propagation time based on the timing information.

[0010] In another embodiment, a transceiver associated with a first communication device comprises: a forward signal generation circuit configured to generate a digital transmit signal including a plurality of forward timing signals; a digital-to-analog converter (DAC) configured to generate an analog transmit signal based on the digital transmit signal; a clock phase adjustment circuit configured to adjust a phase of a clock provided to the DAC in association with at least some of the forward timing signals such that the DAC uses different phases of the clock when transmitting different ones of the forward timing signals;a driver circuit configured to transmit the analog transmission signal over the communication medium, wherein each forward timing signal causes the second communication device to transmit a corresponding reverse timing signal, and wherein the DAC's use of the different phases of the clock when transmitting different ones of the forward timing signals affects the timing of the corresponding transmissions of the corresponding reverse timing signals; an analog-to-digital converter (ADC) configured to generate a digital receive signal based on an analog receive signal received over the communication medium;a timing signal detection circuit coupled to the ADC, the timing signal detection circuit configured to detect a plurality of reverse timing signals from the second communication device based on the analysis of the digital received signal; a timing information determination circuit configured to determine timing information based on the detection of the plurality of reverse timing signals; and a processor configured to determine the propagation time based on the timing information.

[0011] In another embodiment, a method for measuring a propagation delay between a first communication device and a second communication device comprises: generating, in the first communication device, a digital transmit signal including a plurality of forward timing signals; generating, in a DAC of the first communication device, an analog transmit signal based on the digital transmit signal; adjusting, in a logic circuit of the first communication device, a phase of a clock provided to the DAC in association with at least some of the forward timing signals such that the DAC uses different phases of the clock when transmitting different ones of the forward timing signals;Transmitting the analog transmit signal by the first communication device over the communication medium, wherein each forward timing signal causes the second communication device to transmit a respective reverse timing signal, and wherein the use of the different phases of the clock by the DAC when transmitting different ones of the forward timing signals affects the timing of the respective transmissions of the respective reverse timing signals; Receiving an analog receive signal over the communication medium at the first communication device; Converting the analog receive signal to a digital receive signal at an analog-to-digital converter (ADC) of the first communication device; Acquiring a plurality of reverse timing signals from the second communication device based on the analysis of the digital receive signal at the logic circuit;Determining timing information based on the detection of the plurality of reverse timing signals at the logic circuit; and determining the propagation time based on the timing information at the first communication device. Short description of the figures Fig. 1 is a simplified diagram illustrating an exemplary vehicle having an in-vehicle communications network in which various aspects, features, and elements described herein are implemented in accordance with embodiments of this disclosure. Fig. 2 is a simplified diagram of an example communications network in which various aspects, features, and elements described herein are implemented in accordance with embodiments of this disclosure. Fig. 3 is a simplified diagram of an exemplary communication device in which various aspects, features, and elements described herein are implemented in accordance with embodiments of this disclosure. Fig. 4 is a diagram of an illustrative example of a sampling phase generated by a phase generator of the communication device of Fig. 3 depending on the amount of data transmitted by the communication device Fig. 3 received backward pulses, according to one embodiment. Fig. 5 is a simplified diagram of an exemplary phase generator of the communication device of Fig. 3 according to one embodiment. Fig. Figure 6 is a set of diagrams illustrating several reverse pulses generated by the communication device of Fig. 3, while an analog-to-digital converter (ADC) of the communication device of Fig. 3 other sampling phases are used, according to one embodiment. Fig. 7 is a flowchart of an exemplary method for measuring a propagation time between a first communication device and a second communication device according to an embodiment. Fig. 8 is a simplified diagram of another example communication device in which various aspects, features, and elements described herein are implemented in accordance with embodiments of this disclosure. Fig. Figure 9 is a set of diagrams illustrating several reverse pulses generated by the communication device of Fig. 8 in conjunction with a digital-to-analog converter (DAC) that uses different clock phases when transmitting respective forward pulses that caused the reverse pulses, according to one embodiment. Fig. 10 is a flowchart of another exemplary method for measuring a propagation delay between a first communication device and a second communication device according to another embodiment. Detailed description

[0012] The OPEN Alliance in "TC14 - 10BASE-T1S Topology Discovery" proposed a method for measuring distances between devices using the 10BASE-T1S standard in a multidrop configuration. A first device initializes a counter to zero and transmits a first forward pulse over a twisted-pair cable to a second device. In response to receiving the forward pulse, the second device transmits a reverse pulse over the cable to the first device. In conjunction with receiving the reverse pulse, the first device increments the counter. In response to receiving the reverse pulse, the first device transmits another forward pulse over the cable to the second device. In response to receiving the forward pulse, the second device transmits a reverse pulse over the cable to the first device.The transmission of pulses in this manner continues for a predetermined period of time. The distance between the first device and the second device is then calculated based on i) the number of reverse pulses received by the first device, as indicated by the counter, and ii) the time required to receive the reverse pulses.

[0013] The OPEN Alliance has also proposed a distance measurement accuracy of ± 15 centimeters (cm), corresponding to a temporal measurement resolution on the order of 100 picoseconds (ps). When pulse detection is implemented in the digital domain, this measurement accuracy requires that an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) of a transceiver performing the process be clocked to provide a sampling rate of 10 gigahertz (GHz). However, the 10BASE-T1S standard specifies transmission speeds corresponding to clock rates of 10–100 megahertz (MHz), several orders of magnitude less than 10 GHz.In a transceiver intended to operate at transmission speeds of 10-100 MHz, incorporating an ADC and a DAC capable of operating at a sampling rate of 10 GHz results in a significant increase in cost compared to an ADC and a DAC capable of operating at a sampling rate of, for example, 10-100 MHz.

[0014] In the embodiments described below, techniques for achieving relatively high measurement accuracy at relatively low sampling rates are used for measuring the time it takes for a signal to travel across a communication medium between devices (a "time of flight"). For example, in some embodiments, the sampling phase of an ADC is adjusted in association with the reception of multiple timing signals (e.g., pulses) such that the ADC uses different sampling phases in association with the reception of different timing signals. By calculating the time of flight based on the reception of multiple timing signals (received when the ADC used different sampling phases), at least in some embodiments, significantly higher resolution is achieved than if the sampling phase of the ADC were controlled according to prior art methods.

[0015] In other embodiments, the phase of a clock used by a DAC is adjusted in conjunction with the transmission of multiple timing signals (e.g., pulses) such that different phases of the clock are provided to the DAC in conjunction with the transmission of different timing signals. When calculating a propagation time based on the transmission of the multiple timing signals (which correspond to times at which the clock provided to the DAC had different phases), at least some embodiments achieve significantly higher resolution than with a constant phase of the clock provided to the DAC.

[0016] In at least some embodiments, the use of different sampling phases and / or different clock phases, as described above, achieves a relatively high measurement resolution at a relatively low clock rate. This can reduce costs by allowing the use of ADCs and DACs operating at relatively low speeds.

[0017] Fig. 2 is a simplified diagram of an exemplary communications network 200 (sometimes referred to herein as "the network 200") in which various aspects, features, and elements described herein are implemented according to embodiments of this disclosure. The network includes a first communications device 204 and a second communications device 208 communicatively coupled via a cable 212. In one embodiment, the network 200 includes one or more other communications devices (not shown) electrically connected to the cable 212. The cable 212 is a simple twisted pair cable, and the first communications device 204 and the second communications device 208 are configured to operate according to 10BASE-T1S, in one embodiment. In other embodiments, the cable 212 is another suitable cable type (e.g., multiple twisted pairs, a coaxial cable, a fiber optic cable, etc.).In other embodiments, the cable 212 is omitted, and the first communication device 204 and the second communication device 208 communicate wirelessly. In some embodiments, the first communication device 204 and the second communication device 208 communicate using another suitable communication protocol other than 10BASE-T1S.

[0018] The network 200 corresponds in one embodiment to the network 102 of Fig. 1, and Fig. 2 is explained with reference to Fig. 1. For example, in one embodiment, the first communication device 204 corresponds to the controller 104 and the second communication device 208 corresponds to one of the sensors 108, 112, 116, and 120. However, in other embodiments, the first communication device 204 is one of the sensors 108, 112, 116, and 120, and the second communication device 208 is the controller 104. In other embodiments, the network 200 corresponds to another suitable network different from the network 102.

[0019] The first communication device 204 and the second communication device 208 are configured to perform a method for determining a distance between the first communication device 204 and the second communication device 208 along the cable 212. The procedure includes, for example, exchanging timing signals (e.g., pulses or other suitable timing signals) and using the exchange of timing signals to measure a time of flight between the first communication device 204 and the second communication device 208. The first communication device 204 and / or the second communication device 208 are configured to determine the distance between the first communication device 204 and the second communication device 208 based on the time of flight.

[0020] As part of the method for determining the distance, the first communication device 204 is configured to transmit an initial forward timing signal 220 (e.g., a pulse) to the second communication device 208 over the cable 212. In response to receiving the forward timing signal 220, the second device transmits a reverse timing signal 224 (e.g., a pulse) to the second communication device 208 over the cable 212. The forward timing signal 220 and the reverse timing signal 224 are pulses in one embodiment and are sometimes referred to herein as "forward pulse 220" and "backward pulse 224" for convenience. However, according to other embodiments, the forward timing signal 220 and the reverse timing signal 224 are also suitable for timing signals other than pulses.

[0021] In conjunction with receiving the reverse pulse 224, the first communication device 204 transmits another forward pulse 220 to the second communication device 208 via the cable 212. In response to receiving the forward pulse 220, the second communication device 208 transmits a reverse pulse 224 to the first communication device 204 via the cable 212. The transmission of the pulses 220, 224 continues in this manner until a time period ends, a first number of forward pulses 220 are transmitted by the first communication device 204, and / or the first communication device 204 receives a second number of reverse pulses 224, etc.

[0022] The first communication device 204 includes a front-end circuit 240 coupled to the cable 212. The front-end circuit 240 includes an ADC 244 that converts an analog receive signal into a digital receive signal. The front-end circuit 240 also includes a DAC 248 that converts a digital transmit signal into an analog transmit signal. The ADC 244 and the DAC 248 are communicatively coupled to the cable 212. In some embodiments, the front-end circuit 240 includes additional circuitry (e.g., one or more hybrid circuits, an amplifier, a driver, a filter, etc.) that is not shown for brevity. In some embodiments where the cable 212 is not a single twisted pair cable or is omitted entirely, the front-end circuit 240 has a different structure appropriate for the communication medium being used.

[0023] In some embodiments, a sampling phase of the ADC 244 is adjusted in conjunction with the reception of multiple backward pulses 224 such that the ADC uses different sampling phases in conjunction with the reception of different timing signals. When calculating a time of flight based on the reception of the multiple backward pulses 224 (received when the ADC 244 used different sampling phases), at least in some embodiments, significantly higher resolution is achieved than if the sampling phase of the ADC 244 were controlled according to prior art methods.

[0024] In other embodiments, the phase of a clock used by DAC 248 is adjusted in conjunction with the transmission of multiple forward pulses 220 such that different phases of the clock are provided to DAC 248 in conjunction with the transmission of different forward pulses 220. When calculating a propagation delay based on the transmission of multiple forward pulses 220 (corresponding to times at which the clock provided to DAC 248 had different phases), at least some embodiments achieve significantly higher resolution than when the phase of the clock provided to DAC 248 is constant.

[0025] Fig. 3 is a simplified diagram of an exemplary communication device 300 according to one embodiment. The communication device 300 is implemented in the network 200 of Fig. 2 used, and Fig. 3 is for explanatory purposes with reference to Fig. 2. For example, in one embodiment, the communication device 300 corresponds to the first communication device 204 of Fig. 2. In other embodiments, the first communication device 204 has a different suitable structure than the communication device 300 and / or the communication device 300 is used in a different suitable communication network than the network 200.

[0026] The communication device 300 includes a transmit circuit 308 and a receive circuit 312, both coupled to an analog front-end circuit 316. The front-end circuit 316 is communicatively coupled to a cable 320. The cable 320 is a simple twisted pair cable, and in one embodiment, the communication device 300 is configured to operate according to 10BASE-T1S. In other embodiments, the cable 320 is another suitable cable type (e.g., multiple twisted pairs, a coaxial cable, a fiber optic cable, etc.). In other embodiments, the cable 320 is omitted and the communication device 300 communicates wirelessly. In some embodiments, the communication device 300 is configured to operate according to a suitable communication protocol other than 10BASE-T1S.

[0027] The front-side circuit 316 includes an ADC 324 that converts an analog receive signal received over the cable 320 into a digital receive signal. The front-side circuit 316 also includes a DAC 328 that converts a digital transmit signal into an analog transmit signal for transmission over the cable 320. The front-side circuit 316 further includes a driver circuit 332 coupled to an output of the DAC 328. The driver circuit 332 and the ADC 324 are coupled to the cable 320 via a hybrid circuit 336. In some embodiments, the front-side circuit 316 includes additional circuitry (e.g., one or more amplifiers, drivers, filters, etc.) that is not shown for clarity.In some embodiments where cable 320 is not a single twisted pair cable or is omitted entirely, front-end circuitry 316 has a different structure appropriate for the communication medium being used.

[0028] The communication device 300 includes a timing measurement system 340 configured to determine a propagation time relative to another communication device (not shown) based on timing signals received from the other communication device over the cable 320.

[0029] The transmit circuit 308 and the timing measurement system 340 are selectively coupled to the DAC 328 via a switch 344. The receive circuit 312 and the timing measurement system 340 are selectively coupled to the ADC 324 via a switch 348 and a switch 352. During normal operation (e.g., when the communication device 300 is transmitting user information over the cable 320), the switches 344, 348, 352 are controlled to i) couple the transmit circuit 308 and the receive circuit 312 to the analog front end 316 and ii) isolate the timing measurement system 340 from the analog front end 316. However, during a runtime measurement, switches 344, 348, 352 are controlled to i) couple timing measurement system 340 to analog front end 316 and ii) isolate transmit circuitry 308 and receive circuitry 312 from analog front end 316.

[0030] The timing measurement system 340 includes a pulse generator 368 whose output is coupled to an input of switch 344. The pulse generator 368 is configured to generate a digital transmit signal including a plurality of forward pulses, such as the forward pulses 220. When the pulse generator 368 is coupled to the DAC 328 via the switch 344, the DAC 328 converts the digital transmit signal into an analog transmit signal including a plurality of analog forward pulses for transmission over the cable 320.

[0031] The timing measurement system 340 also includes a pulse detector 360, whose input is coupled to an output of switch 348. The pulse detector 360 is configured to analyze a digital receive signal output by the ADC 324 to detect a plurality of backward pulses, such as the backward pulses 224, in the digital receive signal. Thus, when the pulse detector 360 is coupled to the ADC 324 via the switch 348, the pulse detector 360 analyzes the digital receive signal output by the ADC 324 to detect the plurality of backward pulses received from the other communication device via the cable 320. When the pulse detector 360 detects a pulse in the digital receive signal, the pulse detector generates a pulse detection signal.

[0032] A counter 364 (referred to herein as "pulse counter 364") is coupled to pulse detector 360. Pulse counter 364 counts backward pulses detected by pulse detector 360. Pulse counter 364 is configured to increment the counter value upon each pulse detection signal output by pulse detector 360.

[0033] Pulse generator 368 is also coupled to pulse detector 360. Pulse generator 368 is configured to generate a forward pulse in the digital transmission signal in response to each of at least some of the pulse detection signals output by pulse detector 360. In one embodiment, pulse generator 368 is configured to introduce a time delay between the time the pulse detection signal is output by pulse detector 360 and the beginning of the corresponding forward pulse output by pulse generator 368. Thus, when communication device 300 receives a reverse pulse over cable 320, communication device 300 transmits a forward pulse.

[0034] The timing measurement system 340 also includes a processor 372. The processor 372 is configured to control the operation of the timing measurement system 340 during the time-of-flight measurement. For example, in one embodiment, the processor 372 is configured to request the pulse generator 368 to transmit a first forward pulse during the time-of-flight measurement. In conjunction with the end of the time-of-flight measurement, the processor 372 is also configured to calculate a time-of-flight based on i) the number of backward pulses output by the pulse counter 364 and ii) a time duration between the time the first forward pulse was transmitted and the time a last backward pulse was received.In one embodiment, processor 372 includes a counter 376 operable to count a number of clock cycles between the time the first forward pulse was transmitted and the time a last reverse pulse was received. The number of clock cycles output by counter 376 indicates the amount of time between the time the first forward pulse was transmitted and the time a last reverse pulse was received. In one embodiment, processor 372 starts counter 376 in conjunction with communication device 300 transmitting the first forward pulse of the time-of-flight measurement and stops counter 376 in conjunction with communication device 300 receiving a last reverse pulse of the time-of-flight measurement.In one embodiment, processor 372 starts counter 376 in response to the start of the time-of-flight measurement and stops counter 376 in response to the pulse detector 360 detecting the last backward pulse of the time-of-flight measurement.

[0035] In another embodiment, counter 376 is a countdown timer, and processor 372 starts counter 376 in response to the start of the runtime measurement. When counter 376 reaches a predetermined value (e.g., zero), processor 372 determines that the runtime measurement is complete.

[0036] The timing measurement system 340 also includes a phase generator 380, the output of which is coupled to an input of the switch 352. During normal operation, the switch 352 couples an output of the receive circuit 312 to a sampling phase input of the ADC 324, and the receive circuit 312 controls the sampling phase of the ADC 324 to match a clock at which the other communication device (not shown) sends transmit symbols to the communication device 300. On the other hand, during the propagation time measurement, the sampling phase of the ADC 324 is adjusted by the phase generator 380.

[0037] The phase generator 380 is configured to provide different sampling phases to the ADC 324 in conjunction with the communication device 300 receiving backward pulses, such that the ADC 324 uses different sampling phases in conjunction with the reception of different backward pulses. In one embodiment, the phase generator 380 is coupled to the pulse detector 360 and configured to change the sampling phase in response to the detection of backward pulses by the pulse detector 360. In one embodiment, the phase generator 380 changes the sampling phase in response to each backward pulse detected by the pulse detector 360. In other embodiments, the phase generator 380 changes the sampling phase at another suitable frequency, such asi) every N pulses detected backward by pulse detector 360, where N is a suitable integer greater than one, ii) every M cycles of the clock, where M is a suitable positive integer, iii) a suitable time frequency, etc. In one embodiment, phase generator 380 is configured to change the sampling phase by incrementing the sampling phase by a fixed amount at a suitable frequency, as described above. In one embodiment, phase generator 380 modularly increments the sampling phase such that the sampling phase remains within a predetermined range of sampling phases. For example, phase generator 380 modularly increases the sampling phase by a predetermined amount at a suitable frequency, as described above.

[0038] In some embodiments, timing measurement system 340 includes logic circuitry configured to perform actions such as those described above. In some embodiments, processor 372 includes, for example, logic circuitry such as a hardware state machine configured to perform actions such as those described above. In other embodiments, timing measurement system 340 also includes a processor executing machine-readable instructions stored in memory coupled to the processor, wherein the machine-readable instructions, when executed by the processor, cause the processor to perform actions such as those described above. For example, processor 372 includes a processor executing machine-readable instructions that, when executed by the processor, cause the processor to perform actions corresponding to processor 372, as described above.

[0039] Fig. Figure 4 is a diagram of an illustrative example of the sampling phase output by phase generator 380 as a function of the amount of reverse pulses received by communication device 300, according to one embodiment. In other embodiments, phase generator 380 outputs other suitable sampling phases that differ from the example in Fig. 4. As in Fig. As shown in Figure 4, the sampling phase increases modularly with increasing number of backward pulses, so that the sampling phase remains within a fixed range of sampling phases.

[0040] Fig. Figure 5 is a simplified illustration of an exemplary phase generator 500 according to one embodiment. The phase generator 500 corresponds in one embodiment to the phase generator 380 of Fig. 3, and Fig. 5 is explained with reference to Fig. 3. In other embodiments, phase generator 380 has a different suitable structure than phase generator 500 and / or phase generator 500 is used in a different suitable communication device than communication device 300.

[0041] The phase generator 500 includes a multiplexer 504 with a first input set to zero and a second input set to a value by which the sampling phase is to be adjusted ("phase delta"). A select input of the multiplexer 504 is coupled to the output of the pulse detector 360. If the pulse detector 360 does not detect a backward pulse, the multiplexer 504 outputs the value zero. If, however, the pulse detector 360 detects a backward pulse, the multiplexer 504 outputs the phase delta.

[0042] The output of multiplexer 504 is coupled to a first input of an adder 508. An output of adder 508 is coupled to an input of a register 512. An output of register 512 is coupled to a second input of adder 508.

[0043] In operation, the phase generator 500 starts with a zero output. For each detected backward pulse, the output of the phase generator 500 increases by a phase delta. Since the adder 508 and the register 512 have a limited number of bits, the sampling phase (e.g., the output of the register 512) is determined similarly to the sampling phase in Fig. 4. In one embodiment, the phase generator 500 thus increases the sampling phase modularly so that the sampling phase remains within a fixed range of sampling phases.

[0044] Again with reference to Fig. 3, in other embodiments, the phase generator 380 is configured to adjust the sampling phase in a various suitable manner such that the sampling phase output by the phase generator 380 does not increment, as described above with reference to the Fig. 4 and Fig. 5. For example, the phase generator 380 adjusts the sampling phase so that the sampling phase output by the phase generator 380 is decremented modularly, similar to the steps described above with reference to the Fig. 4 and Fig. 5. As another example, the phase generator 380 adjusts the sampling phase in a predetermined manner (e.g., according to a pseudorandom sequence of different sampling phases, according to a repeating fixed sequence of different sampling phases, etc.) such that each sampling phase from a set of sampling phases is used in connection with detecting an approximately equal number of timing signals during the measurement procedure (i.e., no sampling phase is used in connection with detecting more than one additional timing signal compared to any other sampling phase during the measurement procedure), according to one embodiment.In other words, each sampling phase is used in connection with detecting at least X timing signals during the measurement procedure, and no sampling phase is used in connection with detecting more than X+1 timing signals during the measurement procedure, where X is a suitable positive integer greater than one, according to one embodiment.

[0045] As an illustrative example, the measurement procedure has a duration spanning multiple time intervals, and the phase generator 380 adjusts the sampling phase in a predetermined manner such that each sampling phase from the set of sampling phases is used in connection with detecting only an equal number (e.g., one, two, three, etc.) of timing signals during each time interval, according to one embodiment.

[0046] Essentially, the measurement procedure has a duration spanning multiple time intervals, and the phase generator 380 adjusts the sampling phase such that each sampling phase from the set of sampling phases is used in conjunction with detecting only an equal number (e.g., one, two, three, etc.) of timing signals during each time interval, according to some embodiments.

[0047] Fig. 6 is a set of diagrams illustrating multiple backward pulses received by communication device 300 while ADC 324 uses different sampling phases, according to one embodiment.

[0048] Diagram 604 illustrates a backward pulse 1 received while the ADC 324 is using a zero sampling phase. The rising edge of the backward pulse 1 occurs between a clock edge L and a clock edge L+1. As a result, the backward pulse 1 is not reflected in an output of the ADC 324 until after the clock edge L+1, and the pulse detector 360 does not detect the backward pulse 1 until after the clock edge L+1.

[0049] Diagram 608 illustrates a backward pulse 2 received while the ADC 324 is using a sampling phase of Δ. Again, the rising edge of backward pulse 2 occurs between the L clock edge and the L+1 clock edge. As a result, backward pulse 2 is not reflected at the output of the ADC 324 until after the L+1 clock edge, and pulse detector 360 does not detect backward pulse 2 until after the L+1 clock edge.

[0050] Diagram 612 illustrates a backward pulse 3 received while the ADC 324 is using a sampling phase of 2Δ. Again, the rising edge of backward pulse 3 lies between the L clock edge and the L+1 clock edge. As a result, backward pulse 3 is not reflected at the output of the ADC 324 until after the L+1 clock edge, and pulse detector 360 does not detect backward pulse 3 until after the L+1 clock edge.

[0051] Diagram 616 illustrates a backward pulse 4 received while the ADC 324 is using a sampling phase of 3Δ. Again, the rising edge of backward pulse 4 lies between the L clock edge and the L+1 clock edge. As a result, backward pulse 4 is not reflected at the output of the ADC 324 until after the L+1 clock edge, and pulse detector 360 detects backward pulse 4 until after the L+1 clock edge.

[0052] Diagram 620 illustrates a backward pulse 5 received while the ADC 324 is using a sampling phase of 4Δ. The rising edge of the backward pulse 5 occurs before the clock edge L. Consequently, the backward pulse 5 is reflected at the output of the ADC 324 on the clock edge L, and the pulse detector 360 detects the backward pulse 5 in conjunction with the clock edge L.

[0053] Diagram 624 shows a backward pulse 6 received while the ADC 324 is using a sampling phase of 5Δ. The rising edge of the backward pulse 6 occurs before the clock edge L. Therefore, the backward pulse 6 is reflected at the output of the ADC 324 on the clock edge L, and the pulse detector 360 detects the backward pulse 6 in conjunction with the clock edge L.

[0054] Essentially, in a timing measurement where the sampling phase of the ADC 324 is adjusted as described above, m backward pulses are detected associated with the clock edge L and n backward pulses are detected associated with the clock edge L+1, where the ratio of m to n depends on how far from the sampling edge L the backward pulse occurs when the sampling phase is zero.

[0055] The total measurement time related to the reception of m + n multiple backward pulses can be represented as follows: (m*L+n*(L+1))*T where T is a period of the sampling clock. The average time to receive each backward pulse can be represented as follows: (L+n / (m+n))*T

[0056] As can be seen from Equation 2, adjusting the sampling phase of ADC 324 as described above while receiving multiple backward pulses provides a higher-resolution timing measurement compared to receiving multiple backward pulses while keeping the sampling phase of ADC 324 constant, at least in some embodiments. For example, the expression n / (m+n) indicates where the backward pulse occurs between clock edges L and L+1 when the sampling phase is zero.

[0057] Fig. 7 is a flowchart of an exemplary method 700 for measuring a propagation time between a first communication device and a second communication device, according to one embodiment. The method 700 is, according to one embodiment, implemented in the network 102 of the vehicle 100 of Fig. 1. Additionally or alternatively, in some embodiments, the method 700 is implemented by a communication device having a structure such as the communication device 300 of Fig. 3. Fig. 7 is, for the sake of simplicity, explained with reference to Fig. 3. In other embodiments, the method 700 is performed in another suitable vehicle that is different from the vehicle 100 in Fig. 1, and / or in another suitable communication device that differs from the communication device 300 in Fig. 3 is carried out.

[0058] In block 704, the first communication device receives an analog receive signal over a communication medium. For example, communication device 300 receives an analog receive signal over cable 320.

[0059] In block 708, an ADC of the first communication device converts the analog receive signal into a digital receive signal. For example, ADC 324 converts the analog receive signal received via cable 320 into a digital receive signal.

[0060] In block 712, the logic circuit of the first communication device detects a plurality of timing signals from the second communication device based on the analysis of the digital receive signal. For example, the pulse detector 360 detects a plurality of reverse pulses from the second communication device based on the analysis of the digital receive signal received from the ADC 324. In other embodiments, the timing signals are suitable signals other than pulses. In other embodiments, for example, the timing signal comprises a predetermined pattern, and the logic circuit includes a correlation or autocorrelation circuit used to detect the predetermined pattern.

[0061] In block 716, the logic circuit adjusts a sampling phase of the ADC in conjunction with at least some of the timing signals, such that the ADC uses different sampling phases when different timing signals are detected. For example, the output of phase generator 380 is used to adjust the sampling phase of ADC 324.

[0062] Adjusting the sampling phase of the ADC in block 716 includes adjusting the sampling phase in conjunction with detecting at least some of the timing signals. For example, phase generator 380 adjusts the sampling phase when pulse detector 360 detects a backward pulse. In one embodiment, phase generator 380 increases the sampling phase by a predetermined amount in response to pulse detector 360 detecting a backward pulse. In one embodiment, phase generator 380 increases the sampling phase in modules such that the sampling phase remains within a predetermined range of sampling phases.

[0063] In one embodiment, adjusting the sampling phase in block 716 comprises adjusting the sampling phase in response to each timing signal detected in block 712. In other embodiments, adjusting the sampling phase in block 716 comprises adjusting the sampling phase at another suitable frequency, such as i) every N timing signals detected in block 712, where N is a suitable integer greater than one, ii) every M cycles of the clock, where M is a suitable positive integer, iii) a suitable timing frequency, etc.

[0064] In one embodiment, adjusting the sampling phase in block 716 comprises increasing the sampling phase by a fixed amount at an appropriate frequency, as described above. In one embodiment, the sampling phase is incremented modularly so that the sampling phase remains within a predetermined range of sampling phases.

[0065] In one embodiment, adjusting the sampling phase in block 716 includes adjusting the sampling phase in response to detecting each of the at least some timing signals in block 712.

[0066] In block 720, the logic circuit determines timing information based on the detection of the plurality of timing signals in block 712 if the ADC uses different sampling phases when different timing signals are detected. For example, pulse counter 364 counts the detected backward pulses, and counter 376 measures a time period (e.g., a number of clock cycles) during which the detected backward pulses were received by communication device 300.

[0067] In block 724, the first communication device determines the propagation time based on the timing information. For example, processor 372 determines the propagation time based on the number of detected reverse pulses (measured by pulse counter 364) and the duration (measured by counter 376) during which the detected reverse pulses were received by communication device 300.

[0068] In one embodiment, determining the timing information in block 720 comprises counting the timing signals detected by the logic circuit and determining a time period in the first communication device until a number of timing signals are detected; and determining the propagation time in block 724 comprises determining the propagation time based on i) the number of timing signals and ii) the time period. In one embodiment, determining the time period comprises counting a number of cycles of a clock until the number of timing signals are detected; and determining the propagation time comprises determining the propagation time based on i) the number of timing signals and ii) the number of cycles of the clock.

[0069] In another embodiment, the timing signals are reverse timing signals; and the method 700 further comprises: generating an analog transmit signal at the first communication device that includes a plurality of forward timing signals; and transmitting the analog transmit signal by the first communication device over the communication medium, wherein each forward timing signal causes the second communication device to transmit a corresponding reverse timing signal.

[0070] In some embodiments, the phase of the clock provided to a DAC of the communication device is adjusted in association with the transmission of forward timing signals, rather than adjusting the sampling phase of an ADC in association with the reception of reverse timing signals.

[0071] Fig. Figure 8 is a simplified diagram of another exemplary communication device 800 according to another embodiment. The communication device 800 is implemented in one embodiment in the network 200 of Fig. 2 used, and Fig. 8 is explained with reference to Fig. 2. For example, in one embodiment, the communication device 800 corresponds to the first communication device 204 of Fig. 2. In other embodiments, the first communication device 204 has a different suitable structure than the communication device 800 and / or the communication device 800 is used in a different suitable communication network than the network 200.

[0072] The communication device 800 is similar to the communication device 300 of Fig. 3 and contains identically numbered elements which, for the sake of brevity, are not described in detail again.

[0073] In contrast to communication device 300, communication device 800 omits phase generator 380, and instead, an input of switch 352 receives a constant phase input. During normal operation, switch 352 couples the output of receive circuit 312 to the sampling phase input of ADC 324, and receive circuit 312 controls the sampling phase of ADC 324 to match a clock at which the other communication device (not shown) sends transmit symbols to communication device 300. On the other hand, in one embodiment, the sampling phase of ADC 324 is set to the fixed sampling phase during the time-of-flight measurement.

[0074] Also unlike communication device 300, communication device 800 includes a phase generator 824 having i) an input that receives a clock, and ii) an output coupled to a clock input of DAC 328. Phase generator 824 includes another input coupled to pulse detector 360. During normal operation, phase generator 824 provides the clock to DAC 328 without adjusting the phase of the clock, as provided in one embodiment. On the other hand, during the time-of-flight measurement, phase generator 824 adjusts a phase of the clock supplied to DAC 328.

[0075] The phase generator 824 is configured to provide different clock phases to the DAC 328 in conjunction with the communication device 800 transmitting forward pulses, such that the DAC 328 uses different clock phases in conjunction with the transmission of different forward pulses. In one embodiment, the phase generator 824 is configured to change the clock phase in response to the detection of backward pulses by the pulse detector 360. In one embodiment, the phase generator 824 changes the clock phase in response to each pulse detected backward by the pulse detector 360. In other embodiments, the phase generator 824 changes the clock phase at another suitable frequency, such as i) every N pulses detected backward by the pulse detector 360, where N is a suitable integer greater than one, ii) every M cycles of the clock, where M is a suitable positive integer, iii) a suitable time frequency, etc.In one embodiment, phase generator 824 is configured to change the clock phase by incrementing the clock phase by a fixed amount at an appropriate frequency, as described above. In one embodiment, phase generator 824 increments the clock phase modularly so that the clock phase remains within a predetermined range of clock phases. For example, phase generator 824 increments the clock phase by a predetermined amount modularly at an appropriate frequency, as described above.

[0076] In some embodiments, the timing measurement system 820 includes logic circuitry configured to perform actions such as those described above. For example, in some embodiments, the processor 372 includes logic circuitry such as a hardware state machine configured to perform actions such as those described above. In other embodiments, the timing measurement system 820 also includes a processor executing machine-readable instructions stored in memory coupled to the processor, wherein the machine-readable instructions, when executed by the processor, cause the processor to perform actions such as those described above. For example, the processor 372 includes a processor executing machine-readable instructions that, when executed by the processor, cause the processor to perform actions corresponding to the processor 372, as described above.

[0077] In embodiments where another communication device transmits reverse timing signals (e.g., reverse pulses) in response to the forward timing signals (e.g., forward pulses), the use of the different phases of the clock by the DAC 328 when transmitting different ones of the forward timing signals affects the timing of the respective transmissions of the respective reverse timing signals in a similar manner as described above with reference to the Fig. 3 and Fig. 6 described.

[0078] Fig. 9 is a set of diagrams illustrating multiple backward pulses received by the communication device 800 in conjunction with the DAC 328 using different clock phases when transmitting corresponding forward pulses that triggered the backward pulses, according to one embodiment.

[0079] Diagram 904 shows a backward pulse 1 corresponding to DAC 328 using a zero sampling phase in conjunction with transmitting a transmit pulse 1 that caused backward pulse 1. The rising edge of backward pulse 1 lies between a clock edge L and a clock edge L+1. As a result, backward pulse 1 is not reflected in an output of ADC 324 until after clock edge L+1, and pulse detector 360 detects backward pulse 1 only after clock edge L+1.

[0080] Diagram 908 shows a backward pulse 2 corresponding to DAC 328 using a sampling phase of -Δ in conjunction with transmitting a transmit pulse 2 that caused backward pulse 2. Again, the rising edge of backward pulse 2 lies between clock edge L and clock edge L+1. As a result, backward pulse 2 is not reflected at the output of ADC 324 until after clock edge L+1, and pulse detector 360 detects backward pulse 2 only after clock edge L+1.

[0081] Diagram 912 shows a backward pulse 3 corresponding to DAC 328 using a sampling phase of -2Δ in conjunction with transmitting a transmit pulse 3 that caused backward pulse 3. Again, the rising edge of backward pulse 3 lies between clock edge L and clock edge L+1. As a result, backward pulse 3 is not reflected at the output of ADC 324 until after clock edge L+1, and pulse detector 360 does not detect backward pulse 3 until after clock edge L+1.

[0082] Diagram 916 shows a backward pulse 4 corresponding to DAC 328 using a sampling phase of -3Δ in conjunction with transmitting a transmit pulse 4 that caused backward pulse 4. Again, the rising edge of backward pulse 4 lies between clock edge L and clock edge L+1. As a result, backward pulse 4 is not reflected at the output of ADC 324 until after clock edge L+1, and pulse detector 360 detects backward pulse 4 only after clock edge L+1.

[0083] Diagram 920 shows a backward pulse 5 corresponding to DAC 328 using a sampling phase of -4Δ in conjunction with transmitting a transmit pulse 5 that caused backward pulse 5. The rising edge of backward pulse 5 now occurs before clock edge L. Consequently, backward pulse 5 is reflected at the output of ADC 324 at clock edge L, and pulse detector 360 detects backward pulse 5 in conjunction with clock edge L.

[0084] Diagram 924 shows a backward pulse 6 corresponding to DAC 328 using a sampling phase of -5Δ in conjunction with transmitting a transmit pulse 6 that caused backward pulse 6. The rising edge of backward pulse 6 occurs before clock edge L. Consequently, backward pulse 6 is reflected at the output of ADC 324 at clock edge L, and pulse detector 360 detects backward pulse 6 in conjunction with clock edge L.

[0085] Essentially, in a timing measurement procedure where the sampling phase of the DAC 328 is adjusted as described above, m backward pulses are detected in association with the clock edge L and n backward pulses are detected in association with the clock edge L+1, where the ratio of m to n depends on how far from the sampling edge L the backward pulse occurs when the sampling phase is zero.

[0086] The total measurement time (in terms of clock cycles) to receive m + n backward pulses can be represented as given in Eq. 1, and the average time (in terms of clock cycles) to receive each backward pulse can be represented as given in Eq. 2. As can be seen in Eq. 2, adjusting the clock phase of the DAC 328 as described above when transmitting multiple forward pulses provides a higher-resolution time measurement compared to transmitting multiple forward pulses while keeping the clock phase of the DAC 328 constant, at least in some embodiments. For example, the expression n / (m+n) indicates where, between clock edges L and L+1, the backward pulse occurs when the sample phase is zero.

[0087] Fig. 10 is a flowchart of an exemplary method 1000 for measuring a propagation time between a first communication device and a second communication device, according to one embodiment. The method 1000 is implemented in the network 102 of the vehicle 100 of Fig. 1. Additionally or alternatively, in some embodiments, the method 1000 is implemented by a communication device having a structure such as the

[0088] Communication device 800 from Fig. 8. Fig. 10 is for simplicity explained with reference to Fig. 8. In other embodiments, the method 1000 is performed in another suitable vehicle that is separate from the vehicle 100. Fig. 1, and / or in another suitable communication device that differs from the communication device 800 Fig. 8 is carried out.

[0089] In block 1004, the first communication device generates a digital transmission signal including a plurality of forward timing signals. For example, pulse generator 368 generates a digital transmission signal including a plurality of forward pulses. In other embodiments, the forward timing signals are suitable signals other than pulses. In other embodiments, for example, the forward timing signal comprises a predetermined pattern, and the first communication device includes circuitry configured to generate each forward timing signal according to the predetermined pattern.

[0090] In block 1008, a DAC of the first communication device generates an analog transmit signal based on the digital transmit signal. For example, DAC 328 generates an analog transmit signal based on the digital transmit signal. The analog transmit signal is intended for transmission over cable 320, according to one embodiment. The analog transmit signal includes analog versions of the forward timing signals in the digital transmit signal.

[0091] In block 1012, the logic circuitry of the first communication device adjusts a phase of a clock provided to the DAC in association with at least some of the forward timing signals, such that the DAC uses different phases of the clock when different ones of the forward timing signals are transmitted from the first communication device. Adjusting the phase of the clock in block 2008 is discussed further below.

[0092] In block 1016, the first communication device transmits the analog transmission signal over the communication medium. For example, communication device 800 transmits the analog transmission signal over cable 320. The analog version of each forward timing signal, in one embodiment, causes the second communication device to transmit a corresponding reverse timing signal. The DAC's use of the different phases of the clock when transmitting different analog versions of the forward timing signals, in one embodiment, affects the timing of the respective transmissions of the respective reverse timing signals.

[0093] In block 1020, the first communication device receives an analog receive signal over the communication medium. For example, communication device 800 receives the analog receive signal over cable 320.

[0094] In block 1024, an ADC of the first communication device converts the analog receive signal into a digital receive signal. For example, ADC 324 converts the analog receive signal received via cable 320 into a digital receive signal.

[0095] In block 1028, the logic circuit detects a plurality of backward timing signals from the second communication device based on the analysis of the digital receive signal. For example, pulse detector 360 detects a plurality of backward pulses from the second communication device based on the analysis of the digital receive signal received from ADC 324. In other embodiments, the timing signals are suitable signals other than pulses. In other embodiments, for example, the timing signal comprises a predetermined pattern, and the logic circuit includes a correlation or autocorrelation circuit used to detect the predetermined pattern.

[0096] Referring again to block 1012, adjusting the phase of the clock provided to the DAC in block 1012 includes adjusting the phase of the clock in conjunction with detecting at least some of the backward timing signals in block 1028. For example, the phase generator 380 adjusts the phase of the clock when the pulse detector 360 detects a backward pulse. In one embodiment, the phase generator 380 increases the phase of the clock by a predetermined amount in response to the pulse detector 360 detecting a backward pulse. In one embodiment, the phase generator 380 modularly increments the phase of the clock such that the phase of the clock remains within a predetermined range of clock phases.

[0097] In one embodiment, adjusting the clock phase in block 1012 comprises adjusting the phase of the clock in response to each reverse timing signal detected in block 1028. In other embodiments, adjusting the clock phase in block 1012 comprises adjusting the clock phase at another suitable frequency, such as i) every N reverse timing signals detected in block 1028, where N is a suitable integer greater than one, ii) every M cycles of the clock, where M is a suitable positive integer, iii) a suitable timing frequency, etc.

[0098] In one embodiment, adjusting the phase of the clock in block 1012 comprises incrementing the phase of the clock by a fixed amount at an appropriate frequency, as described above. In one embodiment, the phase of the clock is incremented modularly such that the phase of the clock remains within a predetermined range of sample phases.

[0099] In one embodiment, adjusting the clock phase in block 1012 includes adjusting the clock phase in response to detecting each of at least some of the backward timing signals in block 1028.

[0100] In block 1032, the logic circuit determines timing information based on the detection of the plurality of backward timing signals in block 1028. For example, the pulse counter 364 counts the detected backward pulses and the counter 376 measures a period of time (e.g., a number of clock cycles) during which the detected backward pulses were received by the communication device 300.

[0101] In block 1036, the first communication device determines the propagation time based on the timing information determined in block 1032. For example, processor 372 determines the propagation time based on the number of detected reverse pulses (measured by pulse counter 364) and the duration (measured by counter 376) during which the detected reverse pulses were received by communication device 800.

[0102] In one embodiment, determining the timing information in block 1036 comprises counting, in the logic circuit, backward timing signals detected by the logic circuit, and determining, in the first communication device, a time duration until a number of backward timing signals are detected; and determining the propagation time in block 1036 comprises determining the propagation time based on i) the number of backward timing signals, and ii) the time duration. In one embodiment, determining the time duration comprises counting a number of ticks of a clock until the number of backward timing signals are detected; and determining the propagation time comprises determining the propagation time based on i) the number of backward timing signals, and ii) the number of ticks of the clock.

[0103] Although the time-of-flight measurement techniques have been described above in the context of in-vehicle communication networks for illustrative purposes, similar time-of-flight measurement techniques are also used in other suitable environments, such as industrial communication networks (e.g., within a process plant, a manufacturing facility, etc.), sensor networks, remote sensing applications, indoor or outdoor positioning applications, etc.

[0104] Some of the blocks, operations, and techniques described above may be implemented using hardware, a processor executing firmware instructions, a processor executing software instructions, or a suitable combination thereof. When using a processor executing software or firmware instructions, the software or firmware instructions may be stored in any suitable computer-readable memory, such as random access memory (RAM), read-only memory (ROM), solid-state memory (e.g., flash memory), etc. The software or firmware instructions may include machine-readable instructions that, when executed by one or more processors, cause the one or more processors to perform various acts as described above.

[0105] Embodiment 1: A transceiver associated with a first communication device, comprising: an analog-to-digital converter (ADC) configured to generate a digital receive signal based on an analog receive signal received over a communication medium; timing signal detection circuitry coupled to the ADC, the timing signal detection circuitry configured to detect a plurality of timing signals from a second communication device based on an analysis of the digital receive signal; sampling phase generation circuitry coupled to the ADC, the sampling phase generation circuitry configured to adjust a sampling phase used by the ADC in connection with at least some of the timing signals such that the ADC uses different sampling phases when different ones of the timing signals are detected;a timing information determination circuit configured to determine timing information based on the detection of the plurality of timing signals when the ADC uses different sampling phases when different ones of the timing signals are detected; and a processor configured to determine the propagation time based on the timing information.

[0106] Embodiment 2: The transceiver of Embodiment 1, wherein the sampling phase generation circuit is configured to adjust the sampling phase in conjunction with detecting each of the at least some timing signals.

[0107] Embodiment 3: The transceiver of Embodiment 2, wherein the sampling phase generation circuit is configured to adjust the sampling phase in response to detecting each of the at least some timing signals.

[0108] Embodiment 4: The transceiver of any of Embodiments 1-3, wherein the sampling phase generation circuit is configured to adjust the sampling phase such that, for each of a plurality of time intervals during a time-of-flight measurement period, each sampling phase from a set of a plurality of sampling phases is used by the ADC in conjunction with detecting only an equal number of timing signals.

[0109] Embodiment 5: The transceiver of Embodiment 4, wherein the sampling phase generation circuit is configured to adjust the sampling phase such that, for each of a plurality of time intervals during the time-of-flight measurement period, each sampling phase from the set of a plurality of sampling phases is used by the ADC in conjunction with detecting only one respective timing signal.

[0110] Embodiment 6: The transceiver of any one of embodiments 1-5, wherein the sampling phase generation circuit is configured to adjust the sampling phase such that, during a time-of-flight measurement period, each sampling phase from a set of multiple sampling phases is used by the ADC in conjunction with detecting at least X timing signals during the measurement procedure, and no sampling phase is used by the ADC in conjunction with detecting more than X+1 timing signals during the measurement procedure, where X is a suitable positive integer greater than one.

[0111] Embodiment 7: The transceiver according to any one of embodiments 1-6, wherein the sampling phase generation circuit is configured to adjust the sampling phase at least by modularly increasing the sampling phase by the same amount.

[0112] Embodiment 8: The transceiver according to any one of embodiments 1-6, wherein the sampling phase generation circuit is configured to adjust the sampling phase at least by modularly decrementing the sampling phase by the same amount.

[0113] Embodiment 9: The transceiver according to any one of Embodiments 1-8, wherein the sampling phase generation circuit is configured to adjust the sampling phase according to a repeating fixed sequence of different sampling phases.

[0114] Embodiment 10: The transceiver of any one of embodiments 1-6, wherein the sampling phase generation circuit is configured to pseudorandomly adjust the sampling phase.

[0115] Embodiment 11: The transceiver of any of Embodiments 1-10, wherein: the timing information determination circuit comprises a counter configured to count timing signals detected by the timing signal detection circuit; and the processor is configured to: determine a time period until a number of timing signals are detected, and determine the propagation time based on i) the number of timing signals and ii) the time period.

[0116] Embodiment 12: The transceiver of Embodiment 11, wherein the counter is a first counter, and wherein: the processor comprises a second counter configured to count the number of cycles of a clock until the number of timing signals is detected, wherein the number of cycles of the clock indicates the time duration; and the processor is configured to determine the propagation time based on i) the number of timing signals and ii) the number of cycles of the clock.

[0117] Embodiment 13: The transceiver of any one of Embodiments 1-12, wherein the timing signals are reverse timing signals, and wherein the transceiver further comprises a transmission circuit configured to: generate an analog transmit signal including a plurality of forward timing signals; and transmit the analog transmit signal over the communication medium, wherein each forward timing signal causes the second communication device to transmit a corresponding reverse timing signal.

[0118] Embodiment 14: A communication system comprising the transceiver of Embodiment 13, the communication system further comprising the second communication device.

[0119] Embodiment 15: A communication system comprising the transceiver of any of Embodiments 1-13 and / or the communication system of Embodiment 14, the communication system further comprising the communication medium.

[0120] Embodiment 16: A method for measuring a propagation time between a first communication device and a second communication device, the method comprising: receiving an analog receive signal over a communication medium at the first communication device; converting the analog receive signal into a digital receive signal at an analog-to-digital converter (ADC) of the first communication device; detecting a plurality of timing signals from the second communication device based on the analysis of the digital receive signal at a logic circuit of the first communication device; adjusting, in the logic circuit, a sampling phase of the ADC in association with at least some of the timing signals such that the ADC uses different sampling phases when different ones of the timing signals are detected;Determining, in the logic circuit, timing information based on the detection of the plurality of timing signals when the ADC uses different sampling phases when different ones of the timing signals are detected; and determining, in the first communication device, the propagation time based on the timing information.

[0121] Embodiment 17: The method of embodiment 16, wherein adjusting the sampling phase of the ADC comprises adjusting the sampling phase in conjunction with detecting each of at least some of the timing signals.

[0122] Embodiment 18: The method of Embodiment 17, wherein adjusting the sampling phase in conjunction with detecting each of the at least some timing signals comprises adjusting the sampling phase in response to detecting each of the at least some timing signals.

[0123] Embodiment 19: The method of any of Embodiments 16-18, wherein adjusting the sampling phase of the ADC comprises adjusting the sampling phase such that, for each of a plurality of time intervals during a time-of-flight measurement period, each sampling phase of a set of a plurality of sampling phases is used by the ADC in conjunction with detecting only an equal number of timing signals.

[0124] Embodiment 20: The method of embodiment 19, wherein adjusting the sampling phase of the ADC comprises adjusting the sampling phase such that, for each of a plurality of time intervals during the time-of-flight measurement period, each sampling phase from the set of a plurality of sampling phases is used by the ADC in conjunction with detecting only one respective timing signal.

[0125] Embodiment 21: The method of any of Embodiments 16-20, wherein adjusting the sampling phase of the ADC comprises adjusting the sampling phase such that, during a time-of-flight measurement period, each sampling phase of a set of multiple sampling phases is used by the ADC in connection with detecting at least X timing signals during the measurement procedure and no sampling phase is used by the ADC in connection with detecting more than X+1 timing signals during the measurement procedure, where X is a suitable positive integer greater than one.

[0126] Embodiment 22: The method of any of Embodiments 16-21, wherein adjusting the sampling phase of the ADC comprises adjusting the sampling phase at least by modularly increasing the sampling phase by the same amount.

[0127] Embodiment 23: The method of any of Embodiments 16-21, wherein adjusting the sampling phase of the ADC comprises adjusting the sampling phase at least by modularly decrementing the sampling phase by the same amount.

[0128] Embodiment 24: The method of any of Embodiments 16-23, wherein adjusting the sampling phase of the ADC comprises adjusting the sampling phase according to a repeating fixed sequence of different sampling phases.

[0129] Embodiment 25: The method of any of Embodiments 16-21, wherein adjusting the sampling phase of the ADC comprises pseudorandomly adjusting the sampling phase.

[0130] Embodiment 26: The method of any of Embodiments 16-25, wherein: determining the timing information comprises: counting the timing signals detected by the logic circuit in the logic circuit and determining a time period in the first communication device until a number of timing signals have been detected; and determining the propagation time comprises determining the propagation time based on i) the number of timing signals and ii) the time period.

[0131] Embodiment 27: The method of embodiment 26, wherein: determining the time period comprises counting a number of cycles of a clock until the number of timing signals is detected; and determining the propagation time comprises determining the propagation time based on i) the number of timing signals and ii) the number of cycles of the clock.

[0132] Embodiment 28: The method of any of Embodiments 16-27, wherein the timing signals are reverse timing signals, and wherein the method further comprises: generating an analog transmission signal at the first communication device that includes a plurality of forward timing signals; transmitting the analog transmission signal by the first communication device over the communication medium, wherein each forward timing signal causes the second communication device to transmit a corresponding reverse timing signal.

[0133] Embodiment 29: The method of any of Embodiments 16-28 further comprises: receiving the plurality of forward timing signals over the communication medium at the second communication device; detecting at least some forward timing signals from the plurality of forward timing signals at the second communication device; and in response to receiving each of the at least some forward timing signals, transmitting, by the first communication device, the respective reverse timing signal.

[0134] Embodiment 30: A transceiver associated with a first communication device, comprising: a forward signal generation circuit configured to generate a digital transmit signal including a plurality of forward timing signals; a digital-to-analog converter (DAC) configured to generate an analog transmit signal based on the digital transmit signal; a clock phase adjustment circuit configured to adjust a phase of a clock provided to the DAC in association with at least some of the forward timing signals such that the DAC uses different phases of the clock when transmitting different ones of the forward timing signals;a driver circuit configured to transmit the analog transmission signal over the communication medium, wherein each forward timing signal causes the second communication device to transmit a corresponding reverse timing signal, and wherein the DAC's use of the different phases of the clock when transmitting different ones of the forward timing signals affects the timing of the corresponding transmissions of the corresponding reverse timing signals; an analog-to-digital converter (ADC) configured to generate a digital receive signal based on an analog receive signal received over the communication medium;a timing signal detection circuit coupled to the ADC, the timing signal detection circuit configured to detect a plurality of reverse timing signals from the second communication device based on the analysis of the digital received signal; a timing information determination circuit configured to determine timing information based on the detection of the plurality of reverse timing signals; and a processor configured to determine the propagation time based on the timing information.

[0135] Embodiment 31: The transceiver of embodiment 30, wherein the clock phase adjustment circuit is configured to adjust the clock phase in conjunction with the transceiver transmitting each of the at least some forward timing signals.

[0136] Embodiment 32: The transceiver of embodiment 31, wherein the clock phase adjustment circuit is configured to adjust the clock phase in response to the transceiver transmitting each of at least some of the forward timing signals.

[0137] Embodiment 33: The transceiver of embodiment 30, wherein the clock phase adjustment circuit is configured to adjust the clock phase in conjunction with the timing signal detection circuit that detects each of at least some of the backward timing signals.

[0138] Embodiment 34: The transceiver of embodiment 33, wherein the clock phase adjustment circuit is configured to adjust the phase of the clock in response to the timing signal detection circuit detecting each of at least some of the backward timing signals.

[0139] Embodiment 35: The transceiver of any of embodiments 30-34, wherein the clock phase adjustment circuit is configured to adjust the phase of the clock such that, for each of a plurality of time intervals during a time-of-flight measurement period, each phase of a set of a plurality of clock phases is used by the DAC in conjunction with the transmission of only an equal number of forward timing signals.

[0140] Embodiment 36: The transceiver of embodiment 35, wherein the clock phase adjustment circuit is configured to adjust the phase of the clock such that, for each of a plurality of time intervals during the time-of-flight measurement period, each phase from the set of a plurality of clock phases is used by the DAC in conjunction with the transmission of only one forward timing signal.

[0141] Embodiment 37: The transceiver of any of Embodiments 30-36, wherein the clock phase adjustment circuit is configured to adjust the phase of the clock such that, during a time-of-flight measurement period, any clock phase of a set of multiple clock phases is used by the DAC in connection with the transmission of at least X forward timing signals during the measurement procedure, and no clock phase is used by the DAC in connection with the transmission of more than X+1 forward timing signals during the measurement procedure, where X is a suitable positive integer greater than one.

[0142] Embodiment 38: The transceiver of any of embodiments 30-37, wherein the clock phase adjustment circuit is configured to adjust the phase of the clock at least by modularly increasing the phase of the clock by the same amount.

[0143] Embodiment 39: The transceiver of any of embodiments 30-37, wherein the clock phase adjustment circuit is configured to adjust the phase of the clock at least by modularly decrementing the phase of the clock by the same amount.

[0144] Embodiment 40: The transceiver of any of Embodiments 30-39, wherein the clock phase adjustment circuit is configured to adjust the phase of the clock according to a repeating fixed sequence of different clock phases.

[0145] Embodiment 41: The transceiver of any of embodiments 30-37, wherein the clock phase adjustment circuit is configured to pseudorandomly adjust the phase of the clock.

[0146] Embodiment 42: The transceiver of any of Embodiments 30-41, wherein: the timing information determination circuit comprises a counter configured to count the backward timing signals detected by the timing signal detection circuit; and the processor is configured to: determine a time period until a number of backward timing signals are detected, and determine the propagation time based on i) the number of backward timing signals and ii) the time period.

[0147] Embodiment 43: The transceiver of embodiment 42, wherein the counter is a first counter, and wherein: the processor comprises a second counter configured to count a number of cycles of the clock until the number of backward timing signals is detected, the number of cycles of the clock indicating the time duration; and the processor is configured to determine the propagation time based on i) the number of backward timing signals and ii) the number of cycles of the clock.

[0148] Embodiment 44: A communication system comprising the transceiver of any of embodiments 30-43, the communication system further comprising the second communication device.

[0149] Embodiment 45: A communication system comprising the transceiver of any of embodiments 30-43 and / or the communication system of embodiment 44, wherein the communication system further comprises the communication medium.

[0150] Embodiment 46: A method for measuring a propagation delay between a first communication device and a second communication device, the method comprising: generating, in the first communication device, a digital transmit signal including a plurality of forward timing signals; generating, in a digital-to-analog converter (DAC) of the first communication device, an analog transmit signal based on the digital transmit signal; adjusting, in a logic circuit of the first communication device, a phase of a clock provided to the DAC in association with at least some of the forward timing signals such that the DAC uses different phases of the clock when transmitting different ones of the forward timing signals;Transmitting the analog transmit signal by the first communication device over the communication medium, wherein each forward timing signal causes the second communication device to transmit a corresponding reverse timing signal, and wherein the use of the different phases of the clock by the DAC when transmitting different ones of the forward timing signals affects the timing of the corresponding transmissions of the corresponding reverse timing signals; Receiving an analog receive signal at the first communication device over the communication medium; Converting the analog receive signal at an analog-to-digital converter (ADC) of the first communication device into a digital receive signal; Detecting a plurality of reverse timing signals from the second communication device based on the analysis of the digital receive signal at the logic circuit;Determining timing information based on the detection of the plurality of reverse timing signals at the logic circuit; and determining the propagation time based on the timing information at the first communication device.

[0151] Embodiment 47: The method of embodiment 46, wherein adjusting the phase of the clock provided to the DAC comprises adjusting the phase of the clock in conjunction with transmitting each of at least some of the forward timing signals.

[0152] Embodiment 48: The method of embodiment 47, wherein adjusting the phase of the clock provided to the DAC comprises adjusting the phase of the clock in response to transmitting each of at least some of the forward timing signals.

[0153] Embodiment 49: The method of embodiment 46, wherein adjusting the phase of the clock provided to the DAC comprises adjusting the phase of the clock in conjunction with detecting each of at least some of the reverse timing signals.

[0154] Embodiment 50: The method of embodiment 49, wherein adjusting the clock phase in conjunction with detecting each of at least some of the backward timing signals comprises adjusting the phase of the clock in response to detecting each of at least some of the backward timing signals.

[0155] Embodiment 51: The method of any of embodiments 46-50, wherein adjusting the clock phase comprises adjusting the clock phase such that, for each of a plurality of time intervals during a time-of-flight measurement period, each clock phase of a set of a plurality of clock phases is used by the DAC in connection with the transmission of only a like number of forward timing signals.

[0156] Embodiment 52: The method of embodiment 51, wherein adjusting the clock phase comprises adjusting the clock phase such that, for each of a plurality of time intervals during a time-of-flight measurement period, each clock phase from a set of a plurality of clock phases is used by the DAC in conjunction with transmitting only one forward timing signal.

[0157] Embodiment 53: The method of any of Embodiments 46-52, wherein adjusting the clock phase comprises adjusting the clock phase such that, during a time-of-flight measurement period, each clock phase of a set of multiple clock phases is used by the DAC in connection with transmitting at least X forward timing signals during the measurement, and no clock phase is used by the DAC in connection with transmitting more than X+1 forward timing signals during the measurement procedure, where X is a suitable positive integer greater than one.

[0158] Embodiment 54: The method of any of embodiments 46-53, wherein adjusting the phase of the clock comprises adjusting the phase of the clock at least by modularly increasing the phase of the clock by the same amount.

[0159] Embodiment 55: The method of any of embodiments 46-53, wherein adjusting the phase of the clock comprises adjusting the phase of the clock by modularly decrementing the phase of the clock by the same amount.

[0160] Embodiment 56: The method of any of embodiments 46-55, wherein adjusting the phase of the clock comprises adjusting the phase of the clock according to a repeating fixed sequence of different sampling phases.

[0161] Embodiment 57: The method of any of embodiments 46-53, wherein adjusting the phase of the clock comprises pseudorandomly adjusting the phase of the clock.

[0162] Embodiment 58: The method of any of Embodiments 46-57, wherein: determining the timing information comprises counting the backward timing signals detected by the logic circuit and determining a time duration until detecting a number of backward timing signals at the first communication device; and determining the propagation time comprises determining the propagation time based on i) the number of backward timing signals and ii) the time duration.

[0163] Embodiment 59: The method of embodiment 58, wherein: determining the time period comprises counting a number of cycles of a clock until the number of backward timing signals is detected; and determining the propagation time comprises determining the propagation time based on i) the number of backward timing signals and ii) the number of cycles of the clock.

[0164] Embodiment 60: The method of any of Embodiments 46-59 further comprises: receiving the plurality of forward timing signals over the communication medium at the second communication device; detecting at least some forward timing signals from the plurality of forward timing signals at the second communication device; and in response to receiving each of the at least some forward timing signals, transmitting, by the first communication device, the respective reverse timing signal.

[0165] Embodiment 61: A first communication device comprising a transceiver configured to perform the method of any of embodiments 46-60.

[0166] Embodiment 62: A communication system comprising the first communication device according to Embodiment 61, the communication system further comprising the second communication device.

[0167] Embodiment 63: A communication system comprising the first communication device according to embodiment 61 and / or the communication system according to embodiment 62, the communication system further comprising the communication medium.

[0168] Embodiment 64: A first communication device comprising a transceiver configured to perform the method of any of Embodiments 16-29.

[0169] Embodiment 65: A communication system comprising the first communication device according to Embodiment 64, the communication system further comprising the second communication device.

[0170] Embodiment 66: A communication system comprising the first communication device according to embodiment 64 and / or the communication system according to embodiment 65, the communication system further comprising the communication medium.

[0171] When implemented in hardware, the hardware may include one or more discrete components, an integrated circuit, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), etc.

[0172] While the present invention has been described with reference to specific examples which are intended to be illustrative only and not limiting of the invention, changes, additions and / or deletions may be made to the disclosed embodiments without departing from the scope of the invention. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited non-patent literature

[0000] Clock-Based Topology Discovery” on October 20, 2022

[0001] IEEE standard 802.3cg (Institute for Electrical and Electronics Engineers

[0003]

Claims

[1] A transceiver connected to a first communication device, comprising: an analog-to-digital converter (ADC) configured to generate a digital receive signal based on an analog receive signal received over a communication medium; a timing signal detection circuit coupled to the ADC, the timing signal detection circuit configured to detect a plurality of timing signals from a second communication device based on an analysis of the digital receive signal; a sampling phase generation circuit coupled to the ADC, the sampling phase generation circuit configured to adjust a sampling phase used by the ADC in connection with at least some of the timing signals such that the ADC uses different sampling phases when different ones of the timing signals are acquired; a timing information determination circuit configured to determine timing information based on the detection of the plurality of timing signals when the ADC uses different sampling phases when different ones of the timing signals are detected; and a processor configured to determine the runtime based on the timing information. [2] The transceiver of claim 1, wherein the sampling phase generation circuit is configured to adjust the sampling phase in conjunction with the detection of each of the at least some timing signals. [3] The transceiver of claim 2, wherein the sampling phase generation circuit is configured to adjust the sampling phase in response to detection of each of the at least some timing signals. [4] The transceiver of claim 1, wherein: the timing information determination circuit comprises a counter configured to that it counts the timing signals detected by the timing signal detection circuit; and the processor is configured to: to determine a time period until a number of timing signals are detected, and to determine the runtime based on i) the number of timing signals and ii) the time duration. [5] The transceiver of claim 4, wherein the counter is a first counter, and wherein: the processor comprises a second counter configured to count a number of cycles of a clock until the number of timing signals is detected, the number of cycles of the clock indicating the time period; and the processor is configured to determine the runtime based on i) the number of timing signals and ii) the number of cycles of the clock. [6] The transceiver of claim 1, wherein the timing signals are reverse timing signals, and wherein the transceiver further comprises a transmit circuit configured to: to generate an analog transmission signal containing a plurality of forward timing signals; and transmit the analog transmission signal over the communication medium, wherein each forward timing signal causes the second communication device to transmit a corresponding reverse timing signal. [7] A method for measuring a propagation time between a first communication device and a second communication device, the method comprising: Receiving an analog receive signal in the first communication device via a communication medium; Converting the analog received signal into a digital received signal in an analog-to-digital converter (ADC) of the first communication device; Detecting, in a logic circuit of the first communication device, a plurality of timing signals from the second communication device based on the analysis of the digital received signal; adjusting, in the logic circuit, a sampling phase of the ADC in association with at least some of the timing signals such that the ADC uses different sampling phases when different ones of the timing signals are detected; Determining, in the logic circuit, timing information based on the detection of the plurality of timing signals when the ADC uses different sampling phases when different ones of the timing signals are detected; and Determining the propagation time in the first communication device based on the timing information. [8] The method of claim 7, wherein adjusting the sampling phase of the ADC comprises adjusting the sampling phase in conjunction with detecting each of the at least some of the timing signals. [9] The method of claim 8, wherein adjusting the sampling phase in association with detecting each of the at least some timing signals comprises adjusting the sampling phase in response to detecting each of the at least some timing signals. [10] The method of claim 7, wherein: Determining the timing information includes: Counting timing signals detected by the logic circuit in the logic circuit, and Determining, in the first communication device, a time period until a number of timing signals are detected; and Determining the runtime includes determining the runtime based on i) the number of timing signals and ii) the time duration. [11] The method of claim 10, wherein: determining the time period comprises counting a number of cycles of a clock until the number of timing signals is detected; and determining the propagation time comprises determining the propagation time based on i) the number of timing signals and ii) the number of cycles of the clock. [12] The method of claim 7, wherein the timing signals are reversed timing signals, and the method further comprises: generating an analog transmission signal in the first communication device that includes a plurality of forward timing signals; Transmitting the analog transmission signal by the first communication device over the communication medium, wherein each forward timing signal causes the second communication device to transmit a corresponding reverse timing signal. [13] A transceiver associated with a first communication device and comprising: a forward signal generating circuit configured to generate a digital transmission signal including a plurality of forward timing signals; a digital-to-analog converter (DAC) configured to generate an analog transmission signal based on the digital transmission signal; a clock phase adjustment circuit configured to adjust a phase of a clock provided to the DAC in association with at least some of the forward timing signals such that the DAC uses different phases of the clock when different ones of the forward timing signals are transmitted; a driver circuit configured to transmit the analog transmission signal over the communication medium, wherein each forward timing signal causes the second communication device to transmit a corresponding reverse timing signal, and wherein the DAC's use of the different phases of the clock when transmitting different ones of the forward timing signals affects the timing of the corresponding transmissions of corresponding ones of the reverse timing signals; an analog-to-digital converter (ADC) configured to generate a digital receive signal based on an analog receive signal received over the communication medium; a timing signal detection circuit coupled to the ADC, the timing signal detection circuit configured to detect a plurality of backward timing signals from the second communication device based on an analysis of the digital receive signal; a timing information determination circuit configured to determine timing information based on the detection of the plurality of reverse timing signals; and a processor configured to determine the runtime based on the timing information. [14] The transceiver of claim 13, wherein the clock phase adjustment circuit is configured to adjust the clock phase in conjunction with the transceiver transmitting each of at least some of the forward timing signals. [15] The transceiver of claim 14, wherein the clock phase adjustment circuit is configured to adjust the clock phase in response to the transceiver transmitting each of the at least some of the forward timing signals. [16] The transceiver of claim 13, wherein the clock phase adjustment circuit is configured to adjust the clock phase in conjunction with the timing signal detection circuit that detects each of at least some of the reverse timing signals. [17] The transceiver of claim 16, wherein the clock phase adjustment circuit is configured to adjust the phase of the clock in response to the timing signal detection circuit detecting each of at least some of the backward timing signals. [18] The transceiver of claim 13, wherein: the timing information determination circuit comprises a counter configured to that it counts backward timing signals detected by the timing signal detection circuit; and the processor is configured to: to determine a time period until a number of backward timing signals are detected, and to determine the runtime based on i) the number of reverse timing signals and ii) the time duration. [19] The transceiver of claim 18, wherein the counter is a first counter, and wherein: the processor comprises a second counter configured to count a number of cycles of the clock until the number of backward timing signals is detected, the number of cycles of the clock indicating the time period; and the processor is configured to determine the runtime based on i) the number of backward timing signals and ii) the number of cycles of the clock. [20] A method for measuring a propagation time between a first communication device and a second communication device, the method comprising: generating, in the first communication device, a digital transmission signal including a plurality of forward timing signals; Generating an analog transmission signal based on the digital transmission signal in a digital-to-analog converter (DAC) of the first communication device; adjusting, in a logic circuit of the first communication device, a phase of a clock provided to the DAC in association with at least some of the forward timing signals such that the DAC uses different phases of the clock when different ones of the forward timing signals are transmitted; Transmitting the analog transmission signal by the first communication device over the communication medium, wherein each forward timing signal causes the second communication device to transmit a corresponding reverse timing signal, and wherein the use of the different phases of the clock by the DAC when transmitting different ones of the forward timing signals affects the timing of the corresponding transmissions of corresponding ones of the reverse timing signals; Receiving an analog receive signal in the first communication device via the communication medium; Converting the analog received signal into a digital received signal in an analog-to-digital converter (ADC) of the first communication device; Detecting a plurality of backward timing signals from the second communication device based on an analysis of the digital receive signal in the logic circuit; Determining timing information in the logic circuit based on the detection of the plurality of reverse timing signals; and Determining the propagation time in the first communication device based on the timing information. [21] The method of claim 20, wherein adjusting the phase of the clock provided to the DAC comprises adjusting the phase of the clock in conjunction with transmitting each of the at least some of the forward timing signals. [22] The method of claim 21, wherein adjusting the phase of the clock provided to the DAC comprises adjusting the phase of the clock in conjunction with transmitting each of the at least some forward timing signals. [23] The method of claim 20, wherein: Determining the timing information includes: Counting backward timing signals detected by the logic circuit in the logic circuit, and Determining, in the first communication device, a time period until a number of backward timing signals are detected; and Determining the propagation time includes determining the propagation time based on i) the number of reverse timing signals and ii) the time duration. [24] The method of claim 23, wherein: determining the time period comprises counting a number of cycles of the clock until the number of backward timing signals is detected; and determining the propagation time comprises determining the propagation time based on i) the number of reverse timing signals and ii) the number of cycles of the clock.

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