EARLY EXIT FAULT LOCATION POLYNOMAL

Abstract

A method may include generating a status signal, the status signal indicating a status of the determination of an error locating polynomial (ELP) by an ELP determination circuit; and controlling the ELP determination by the ELP determination circuit responsive at least in part to a value of the status signal.

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims the benefit pursuant to 35 USC § 119(e) of the priority date of the preliminary US patent application serial number 63 / 387,639, filed on December 15, 2022, entitled “EARLY EXIT FROM ERROR-LOCATOR POLYNOMIAL CALCULATION”, the contents and disclosure of which are fully incorporated herein by reference. AREA

[0002] Examples generally relate to determining error-locating polynomials and decoders that use them. More specifically, one or more examples relate to early exit from an ELP determination based on the status of the ELP determination. If, in one or more examples, it is determined that the estimated ELP is the final ELP, further iterations of the ELP determination can be omitted. BACKGROUND

[0003] An error-locating polynomial (ELP) is a polynomial expression where the roots of the expression represent the error pattern in a block of data. ELPs are used in a variety of operational contexts, including Reed-Solomon decoders (RS decoders) and Bose-Chaudhuri-Hocquenghem decoders (BCH decoders). BRIEF DESCRIPTION OF THE DRAWINGS

[0004] To make it easy to identify the discussion of a specific element or action, the principal number(s) in a reference sign refer to the figure number in which that element is first introduced. Fig. Figure 1 is a block diagram representing a device for determining a fault location polynomial (ELP) at least partially based on a status signal, where the status signal indicates the status of an ELP determination according to one or more examples. Fig. 2 represents a matrix equation for determining discrepancy values ​​according to one or more examples. Fig. Figure 3 is a flowchart that represents a process for determining a fault location polynomial (ELP) at least partially based on a status signal according to one or more examples. Fig. Figure 4 is a flowchart that represents a process for determining the status of an ELP determination, according to one or more examples. Fig. Figure 5 is a flowchart that depicts a process for setting a status signal indicating the status of an ELP determination according to one or more examples. Fig. Figure 6 is a flowchart that illustrates a process for controlling an ELP determination according to one or more examples. Fig. Figure 7 illustrates an example process for controlling an ELP determination according to one or more examples. Fig. Figure 8 illustrates an example process for correcting a codeword according to one or more examples. Fig. Figure 9 is a block diagram representing an RS decoder for Reed-Solomon decoding, which, according to one or more examples, provides an early exit from the ELP determination. Fig. 10 illustrates a process according to one or more examples. Fig. Figure 11 is a block diagram of a switching logic that can be used in some examples to implement various functions, operations, actions, processes or procedures disclosed herein. METHODS OF EXECUTING THE INVENTION

[0005] The following detailed description refers to the accompanying drawings, which form part of this document and illustrate specific examples of how the present disclosure can be put into practice. These examples are described in sufficient detail to enable those skilled in the art to put the present disclosure into practice. However, other examples may also be used, and structural, material, and procedural modifications may be made without altering the scope of protection afforded by the disclosure.

[0006] The illustrations shown herein are not intended to be actual views of any particular process or system, or of any particular device or structure, but are merely idealized representations used to describe the examples of this disclosure. The drawings shown herein are not necessarily to scale. Similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, the similarity in numbering does not imply that the structures or components are necessarily identical in size, composition, configuration, or any other property.

[0007] The following description may include examples to enable those skilled in the art to put the disclosed examples into practice. The use of the terms "exemplary", "as an example", and "for instance" means that the accompanying description is explanatory, and although the scope of protection of the disclosure is intended to include the examples and their legal equivalents, the use of these terms is not intended to limit the scope of protection of any example of this disclosure to the specified components, steps, features, functions, or the like.

[0008] It is readily apparent that the components of the examples described here in general terms and illustrated in the drawing can be arranged and designed in a multitude of different configurations. Therefore, the following description of various examples is not intended to limit the scope of protection of this disclosure, but is merely representative of various examples. While the different aspects of the examples may be illustrated in drawings, these drawings are not necessarily drawn to scale unless expressly stated otherwise.

[0009] Furthermore, the specific implementations shown and described are only examples and should not be interpreted as the only way to implement the present disclosure unless otherwise stated herein. Elements, circuits, and functions may be shown in block diagram form to avoid obscuring the present disclosure with unnecessary details. Conversely, the specific implementations shown and described are only examples and should not be interpreted as the only way to implement the present disclosure unless otherwise stated herein. Additionally, block definitions and the distribution of logic between different blocks are examples of a specific implementation. It is readily apparent to those skilled in the art that the present disclosure can be implemented in practice through numerous other distribution solutions.Details concerning timing considerations and the like have been largely omitted, insofar as such details are not necessary for a complete understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0010] Experts will understand that information and signals can be represented using a variety of different technologies and techniques. Some drawings may illustrate signals as a single signal for the clarity of representation and description. Experts will understand that the signal can represent a bus of signals, where the bus can have a variety of bit widths, and that the present disclosure can be implemented with any number of data signals, including a single data signal.

[0011] The various illustrative logic blocks, modules, and circuits described in connection with the examples disclosed herein may be implemented or carried out using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein.A general-purpose processor (which may herein also be referred to as a host processor or simply a host) may be a microprocessor, but alternatively it may be any conventional processor, control unit, microcontroller, or state machine. A processor may also be implemented as a combination of data processing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer, while the general-purpose computer is configured to execute computational instructions (e.g., software code) relating to examples of the present disclosure.

[0012] The examples may be described in terms of a process represented as a flowchart, flow diagram, structure diagram, or block diagram. Although a flowchart may describe process actions as a sequential process, many of these actions may be performed in a different order, in parallel, or substantially simultaneously. Furthermore, the order of the actions may be changed. A process may correspond, without limitation, to a method, thread, function, procedure, subroutine, or subprogram. Moreover, the methods disclosed herein may be implemented in hardware, software, or both. When implemented in software, the functions may be stored or transmitted as one or more instructions or as code on computer-readable media.Computer-readable media include both computer storage media and communication media, including all media that support the transfer of a computer program from one location to another.

[0013] Any reference to an element herein using a label such as "first," "second," etc., does not restrict the set or order of such elements unless such restriction is expressly stated. Rather, these labels herein may be used as a convenient method for distinguishing between two or more elements or instances of an element. Thus, a reference to a first and a second element does not mean that only two elements may be inserted there, or that the first element must in any way precede the second element. Furthermore, unless otherwise stated, a set of elements may comprise one or more elements.

[0014] In the sense used herein, the term "essentially" means, with respect to a given parameter, property, or condition, and includes, to an extent understandable to a person skilled in the art, that the given parameter, property, or condition is satisfied with a small degree of variance, such as within acceptable manufacturing tolerances. For example, depending on the specified parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be satisfied to at least 90%, at least 95%, or even at least 99%.

[0015] As used herein, relational terms such as “above”, “below”, “on”, “underlying”, “above”, “below” are used without restriction for the sake of clarity and expediency in understanding the revelation and the accompanying drawings, and are not associated with or dependent on any particular preference, orientation or order, unless the context clearly indicates otherwise.

[0016] In this description, the term "coupled" and derivatives thereof may be used to indicate that two elements work together or interact with each other. When an element is described as "coupled" to another element, the elements may be in direct physical or electrical contact, or intermediate elements or layers may be present. Conversely, when an element is described as "directly coupled" to another element, no intermediate elements or layers are present. The term "connected" may be used interchangeably with the term "coupled" in this description and has the same meaning unless explicitly stated otherwise or the context would indicate otherwise to a person skilled in the art.

[0017] A typical approach to solving the fault location polynomial (ELP) is to complete every 2*t iterations of a Berlekamp-Massey algorithm ("Berlekamp"), where t is the highest number of faults that can be corrected by a given instance of the Berlekamp algorithm. The Berlekamp algorithm also continues to develop an ELP even after convergence to a new ELP.

[0018] This allows the ELP determination to exhibit consistent latency (e.g., always the same latency, without restriction), reducing the effort required for integration into any overall circuit flow within a device. Typical RS decoders attempt to maintain a constant latency regardless of the number of errors in a forward error corrected (FEC) data block ("FEC block"). In real-world system operation, FEC blocks with a low error count (0 or 1 faulty symbols) are most common, while those with t or t-1 errors are rare.

[0019] Nevertheless, a standard Reed-Solomon decoder must normally maintain the full system throughput, even for the FEC blocks with t- or t-1 errors.

[0020] The latency of a typical RS decoder is usually related to the highest number of errors the decoder could correct for a given application. ELP calculations generally use 2*t iterations, where t is the decoder's maximum error correction capacity. For latency-critical systems, reducing RS decoder latency is desirable.

[0021] During each iteration of an ELP determination, the Berlekamp algorithm determines a discrepancy value (also referred to here as the "Berlekamp discrepancy value") that represents a difference between the error pattern detectable by a current version of the ELP (respective current versions of an ELP across different iterations are referred to here as "estimated ELP" or "respective ELP") and an error pattern indicated by a syndrome.

[0022] If the discrepancy value is zero at any given iteration and all future discrepancy values ​​are zero, then the estimated ELP is the final ELP. If the state of the ELP determination is stable at an iteration prior to the 2*t iteration, it may be desirable to exit the ELP determination before all 2*t iterations of the Berlekamp algorithm are performed.

[0023] One or more examples generally relate to determining an early exit condition from a Berlekamp algorithm. An estimated ELP is used to determine whether the totality of discrepancy values ​​for later iterations of the Berlekamp algorithm will be zero or not.

[0024] An ELP determination block or an RS decoder that includes the same and offers the early exit described herein can exhibit reduced latency (e.g., the time from input of a codeword to the corresponding output, without restriction). For example, if the number of errors is v, the latency of the ELP determination with the early exit option is 2*v instead of 2*t as in the typical case.

[0025] Fig. Figure 1 is a block diagram representing a device 100 for determining a fault location polynomial (ELP) at least partially based on a status signal, wherein the status signal indicates the status of the ELP determination according to one or more examples.

[0026] The device 100 includes an ELP determination circuit 102 and an early exit logic circuit 122. The early exit logic circuit 122 includes a state of an ELP determination logic 104 and an exit condition logic 110.

[0027] In one or more examples, the ELP Determination Circuit 102 generates an ELP 112 that is based at least partially on a Syndrome 114. The ELP Determination Circuit 102 receives Syndromes 114, determines an ELP 112 associated with the Syndromes 114, and provides the determined ELP 112. A "codeword" is a sequence of symbols. The ELP Determination Circuit 102 determines an ELP 112 based on Syndromes 114 with coefficients that specify the locations of one or more errors in a codeword associated with the Syndromes 114, as discussed below. An "error" is a difference between the actual form of a codeword and the original or intended form of the codeword. Non-restrictive examples of errors include symbol errors, burst errors, or erase errors, without limitation. Such differences can be considered non-restrictive examples during transmission (e.g.,caused by the transmission (e.g., via an electronic communication system, without limitation) or the storage (e.g., via a data storage device, without limitation) of a codeword associated with Syndrome 114.

[0028] In one or more examples, Syndrome 114 is a vector of syndromes (e.g., a vector of syndromes includes one or more syndromes, without restriction). Syndrome 114 indicates the presence of errors (and implicitly or explicitly the absence of errors) in a codeword and the locations of the errors within the codeword. The locations of the errors in a codeword can also be referred to here as "error patterns." Each syndrome corresponds to specific error patterns. For a given code (e.g., FEC coding technique, without restriction) that can correct up to t errors, 2*t Syndrome 114 is determined for a codeword.

[0029] The respective syndromes 114 can be received by a syndrome calculator (syndrome calculator not shown). The ELP determination circuit 102 determines ELP 112 through one or more iterations, at least partially based on the syndromes 114. The coefficients of ELP 112 are set such that the locations of errors in the codeword associated with the syndromes 114 can be determined, at least partially, based on them, as discussed below.

[0030] In one or more examples, the ELP determination circuit 102 can determine ELP 112 at least partially based on a Berlekamp algorithm. During an ELP determination, the Berlekamp algorithm iteratively refines an ELP, including modifying the coefficients of the ELP. The Berlekamp algorithm requires 2*t iterations to complete the ELP determination. At the end of the i-th iteration, the Berlekamp algorithm has further developed (i.e., modified, without restriction) the ELP such that the discrepancy value (V*ELP - S) i ) = 0, where S i the i-th syndrome is, syndromes (e.g., syndromes 114, without restriction) a vector of v syndromes [S i-1 S i-2 ,...,S i-v ] are characterized by their low numbers, and the ELP (e.g. ELP 112, without restriction) is a vector of v coefficients [σ1, σ2,..., σ v ] of the ELP is.

[0031] During each iteration, the Berlekamp algorithm determines discrepancy values ​​(hereinafter also referred to as the "Berlekamp discrepancy value") that represent a difference between an error pattern indicated by a current version of the ELP (the current version of an ELP across various iterations may also be referred to hereinafter as the "estimated ELP") and an error pattern indicated by Syndrome 114. As a non-restrictive example, a discrepancy value of zero indicates no difference, while a non-zero discrepancy value indicates a difference. A zero discrepancy value implies that all errors represented by a current syndrome are detectable by the estimated ELP. A non-zero discrepancy value implies that all errors represented by a current syndrome are not detectable by the estimated ELP.

[0032] The Berlekamp algorithm modifies the coefficients of the estimated ELP to account for discrepancies, i.e., to reduce the difference between the error patterns indicated by the estimated ELP and those indicated by Syndrome 114. The iterative process continues until the Berlekamp algorithm converges to an ELP that accurately detects the error patterns indicated by Syndrome 114. If the Berlekamp algorithm of the ELP determination circuit 102 determines that an estimated ELP accurately detects the error patterns indicated by Syndrome 114, the Berlekamp algorithm does not modify the coefficients of the estimated ELPs.In one or more examples, the ELP determination circuit 102 can stop the change in the coefficients of the ELP and provide this as ELP 112, in response to the completion of all 2*t iterations of a Berlekamp algorithm or in response to the acknowledgment of the ELP completion signal 120, regardless of whether all 2*t iterations of the Berlekamp algorithm are completed or not, as discussed below. The ELP 112 can be used to locate and correct errors in a codeword associated with the syndromes 114. As a non-restrictive example, the reciprocal roots of the coefficients of ELP 112 indicate the locations of the errors in the codeword; therefore, as a non-restrictive example, a correction circuit (correction circuit in ) Fig. (1 not shown) can determine the reciprocal roots of ELP 112 and can apply an error correction to the locations in the codeword specified by the roots of ELP 112.

[0033] The early exit logic circuit 122 receives the syndromes 114 and the estimated ELP 108 and sets the ELP completion signal 120 at least partially based on them. The exit condition logic 110 of the early exit logic circuit 122 controls an ELP determination in the ELP determination circuit 102 via the ELP completion signal 120. When the ELP completion signal 120 is enabled, it instructs the ELP determination circuit 102 to stop determining the estimated ELP (regardless of whether all 2*t iterations of the Berlekamp algorithm are complete or not), and when it is disabled, the ELP completion signal 120 instructs the ELP determination circuit 102 to continue determining the estimated ELP. The exit condition logic 110 sets the ELP completion signal 120 (e.g., to enabled or disabled, without restriction) at least partially in response to a value of the status signal 106.The status signal 106 indicates the status of an ELP determination in the ELP determination circuit 102. In one or more examples, a first value represents a stable state, and a second, different value represents an unstable state. In one or more examples, the exit condition logic 110 can instruct a conditional exit from an ELP determination via the ELP completion signal 120. The exit condition logic 110 can activate the ELP completion signal 120, at least partially, in response to a first value of the status signal 106 indicating that the ELP determination has reached a stable state, and can deactivate the ELP completion signal 120, at least partially, in response to a second, different value of the status signal 106 indicating that the ELP determination has not reached a stable state.In response to the exit condition logic 110 activating the ELP ready signal 120, the ELP determination circuit 102 stops an ELP determination and provides the estimated ELP as ELP 112 for the syndromes 114.

[0034] The logic 104 for determining the ELP state receives an estimated ELP 108 from the ELP determination circuit 102 and the syndromes 114. The estimated ELP 108 is an estimated ELP determined by the ELP determination circuit 102 and is associated with a specific iteration of an estimated ELP determination performed in the ELP determination circuit 102.

[0035] The ELP state determination logic 104 receives a signal, determines at least a partial status of an ELP determination by the ELP determination circuit 102, and sets the status signal 106 at least a partial status of the ELP determination, as discussed below. In general, the ELP state determination logic 104 determines whether an ELP determination by the ELP determination circuit 102 is in a stable state or not. In one or more examples, the ELP state determination logic 104 can determine that an ELP determination is in a stable state in response to the determination that no changes will occur in the coefficients of the estimated ELP in further (e.g., future, without limitation) iterations of the ELP determination, as discussed below.The logic 104 for determining the ELP state sets the status signal 106 to a value representing the determined status of the ELP determination, sets the status signal 106 to the first value indicating that the ELP determination is in a stable state, and sets the status signal 106 to the second, different value to indicate that the ELP determination is in an unstable state.

[0036] Fig. Figure 1 presents the ELP determination circuit 102 and the early exit logic circuit 122 in separate logic blocks, but this is not intended to limit the disclosure in any way. In one or more examples, the logic 104 for determining the ELP state and / or the exit condition logic 110 may be or form part of the logic circuit of the ELP determination circuit 102, or may form part of a separate logic circuit with one or more connections (e.g., one or more pins, terminals, wires, data paths, without limitation) between the logic 104 for determining the ELP state and the logic 104 for determining the ELP state for communicating the estimated ELP 108 and the status signal 106.

[0037] In each iteration, the Berlekamp algorithm of the ELP determination circuit 102 determines the estimated ELP 108 for that iteration and provides the estimated ELP 108 to the early exit logic circuit 122, and in particular to the logic 104, for determining the ELP state. In one or more examples, the logic 104 determines discrepancy values ​​for the current and subsequent iterations of the ELP determination based on the syndromes 114 and the estimated ELP 108, determines whether the totality of the determined discrepancy values ​​is zero, and determines a value for setting the status signal 106 based on whether the totality of the discrepancy values ​​is zero.

[0038] Fig. 2 represents an expression 200, which is a discrepancy value analysis according to one or more examples. In one or more examples, the logic 104 can determine discrepancy values ​​according to expression 200 to determine the ELP state and use the determined discrepancy values ​​to determine the status of an ELP determination. The expression 200 includes a matrix 202 with (2*t-2*v) rows, where each row 210, 212... 214 contains the syndromes (taken from syndromes 114); a matrix 204 of coefficients σ1 to σ v of the estimated ELP 108; a matrix 206 of syndromes 114; and a matrix 224 with discrepancy values. The result of multiplying matrix 202 with matrix 204 is a value matrix.

[0039] The result of multiplying matrix 202 by matrix 204 is added to the values ​​in matrix 206 (in Fig. (2, denoted by a "+"), and if the values ​​are equal, the matrix 224 yields zero values. If the values ​​are different, the result in matrix 224 is non-zero. In this specific example, the addition operation refers to checking whether two sets are equal or not.

[0040] If the quantities are equal, the discrepancy value in matrix 224 is 0; otherwise, the discrepancy value is non-zero. The expression 200 in Fig. Figure 2 presents a considered, non-restrictive example where the determined discrepancy values ​​are all zeros. Here, "v" is an integral greater than or equal to 1 and also represents a current iteration, which is evaluated by logic 104 to determine the ELP state.

[0041] In one or more examples, estimated ELPs determined by the ELP determination circuit 102 during even iterations of a respective ELP determination are provided to the early exit logic circuit 122, and estimated ELPs determined during odd iterations of the respective ELP determination are not (e.g., never, without restriction) provided to the

[0042] Early exit logic circuit 122 is provided. This is because the number of iterations required to determine a correct ELP is at least twice the number of errors present in a codeword, so a correct ELP is determined on an even iteration of the Berlekamp algorithm. In one or more examples, the iterations evaluated by expression 200 are the totality of even iterations from the current iteration v to the last iteration t by logic 104 for determining the ELP state using the estimated ELP 108 and syndromes 114.If the totality of discrepancy values ​​for all such even iterations from v to t is zero, then logic 104 for determining the ELP state sets the status signal 106 to indicate the stable state of the ELP determination, and if there are any discrepancy values ​​other than zero, then logic 104 for determining the ELP state sets the status signal 106 to indicate the unstable state of the ELP determination.

[0043] As a non-restrictive example, for a syndrome vector S and an estimated ELP C of grade L, the Berlekamp discrepancy value at an nth iteration of a Berlekamp algorithm can be expressed as follows: For n=0:13 (L=1, using 14 multipliers), the discrepancy value is obtained from equation 1: dn…C[0]*S[n+1]+S[n+2] For n=0:11 (L=2, using 24 multipliers), the discrepancy value is obtained from equation 2: dn−C[1]*S[n+2]+C[0]*S[n+3]+S[n+4] For n=0:9 (L=3, using 30 multipliers), the discrepancy value is obtained from equation 3: dn=C[2]*S[n+3]+C[1]*S[n+4]+C[2]*S[n+5]+S[n+6] For n=0:7 (L=4, using 32 multipliers), the discrepancy value is obtained from equation 4: dn=C[3]*S[n+4]+C[2]*S[n+5]+C[1]*S[n+6]+C[0]*S[n+7]+S[n+8] For n=0:5 (L=5, 30 multipliers) the discrepancy value is obtained from equation 5: dn=C[4]*S[n+5]+C[3]*S[n+6]+C[3]*S[n+7]+C[1]*S[n+8]+C[0]*S[n+9]+S[n+10]

[0044] As a non-restrictive example, if the current iteration n = 2 and the estimated ELP is a degree 1 ELP, the discrepancy values ​​dn for n = 0 to 13 are determined according to Equation 1. If the totality of the discrepancy values ​​is zero, then the estimated ELP reveals an error pattern represented by the syndrome vector S. This determination is performed using the estimated ELP 108 and the syndromes 114 for the current and subsequent iterations. If the totality of the discrepancy values ​​is zero, the logic 104 for determining the ELP state determines that the ELP determination is in a stable state and sets the status signal 106 to indicate this. If any of the discrepancy values ​​is not equal to zero, the logic 104 for determining the ELP state determines that the ELP determination is in an unstable state and sets the status signal 106 to indicate this.

[0045] In one or more examples, the logic 104 for determining the ELP state can determine discrepancy values ​​for respective iterations in parallel (e.g., during substantially the same duration, during the same iteration of the Berlekamp algorithm in the ELP determination circuit 102, during the same clock cycle, the same series of clock cycles, without limitation). In one or more examples, the respective determinations of the discrepancy values ​​for rows 210, 212, ..., 214 of matrix 202 can take place in parallel. In one or more examples, the respective determinations can be performed in parallel. In one or more examples, a bank of multipliers (and optionally summers, inverters, without limitation) in the logic 104 for determining the ELP state can be provided and used to perform corresponding discrepancy value determinations in parallel.As a non-restrictive example, parallel determination reduces the time (and thus the latency) used by logic 104 to determine the ELP state compared to sequential determination. In one or more examples, parallel determination of discrepancy values ​​may occur during (e.g., essentially all, without restriction) odd iterations of an ELP determination in the ELP determination circuit 102, immediately following the even iteration that generated the estimated ELP 108 used by logic 104 to determine the ELP state.

[0046] Fig. Figure 3 is a flowchart that represents a process 300 for determining a fault location polynomial (ELP) at least partially based on a status signal according to one or more examples.

[0047] Although the exemplary process 300 represents a specific sequence of operations, this sequence can be modified without deviating from the scope of protection of this disclosure. For example, some of the operations shown can be performed in parallel or in a different sequence that does not substantially affect the function of process 300. In other examples, different components of an exemplary device or system implementing process 300 can perform functions essentially at the same time or in a specific sequence. Some or all of the operations of process 300 can be performed, as non-limiting examples, by one or more of the device 100, the ELP determination circuit 102, the exit condition logic 110, or the logic 104 for determining the ELP state.

[0048] According to one or more examples, process 300 may include generating a status signal, where the status signal indicates a status of the fault location polynomial (ELP) determination by an ELP determination circuit at process 302.

[0049] According to one or more examples, process 300 can include controlling the ELP determination by the ELP determination circuit, which responds at least partially to a value of the status signal at process 304.

[0050] Fig. Figure 4 is a flowchart that represents a Process 400 for determining the status of an ELP determination, according to one or more examples.

[0051] Although the exemplary process 400 represents a specific sequence of operations, this sequence can be modified without deviating from the scope of protection of this disclosure. For example, some of the operations shown can be performed in parallel or in a different sequence that does not substantially affect the function of process 400. In other examples, different components of an exemplary device or system implementing process 400 can perform functions essentially at the same time or in a specific sequence. Some or all of the operations of process 300 can, as non-limiting examples, be performed by one or more of the device 100, the ELP determination circuit 102, or the logic 104 for determining the ELP state.

[0052] According to one or more examples, process 400 can determine Berlekamp discrepancy values ​​(e.g., determining Berlekamp discrepancy values ​​via expression 200 of Fig. 2, without limitation) at least partially based on a respective ELP generated by the ELP determination circuit (e.g., an estimated ELP 108 of Fig. 1, without restriction) and a vector of syndromes (e.g., Syndrome 114 of Fig. 1, without restriction) in operation 402.

[0053] According to one or more examples, process 400 can include determining the status of the ELP determination, at least partially, based on the determined Berlekamp discrepancy values, in operation 404. As discussed above, the status of the ELP determination can be determined as stable if all discrepancy values ​​are zero, and if any of the discrepancy values ​​is non-zero, the status of the ELP determination can be determined as unstable.

[0054] Fig. Figure 5 is a flowchart that represents a process 500 for setting a status signal that indicates the status of an ELP determination according to one or more examples.

[0055] Although the exemplary process 500 represents a specific sequence of operations, this sequence can be modified without infringing upon the scope of protection afforded by this disclosure. For example, some of the operations shown can be performed in parallel or in a different sequence that does not substantially affect the function of process 500. In other examples, different components of an exemplary device or system implementing process 500 can perform functions essentially at the same time or in a specific sequence. Some or all of the operations of process 300 can, as non-limiting examples, be performed by one or more of the device 100, the ELP determination circuit 102, the exit condition logic 110, or the logic 104 for determining the ELP state.

[0056] According to one or more examples, process 500 may include determining that the status of an ELP determination is a stable state, at least partially based on an entirety of the determined Berlekamp discrepancy values ​​that are zero for a given ELP and the vector of syndromes, in process 502.

[0057] According to one or more examples, process 500 may include setting the status signal to an initial value to indicate the stable state at process 504.

[0058] According to one or more examples, process 500 may include determining that the status of the ELP determination is an unstable state, at least partially based on at least one specific Berlekamp discrepancy value that is non-zero for a given ELP and the vector of syndromes, in process 506.

[0059] According to one or more examples, process 500 may include setting the status signal to a second value to indicate the unstable state, where the second value differs from the first value, as in process 508.

[0060] Fig. Figure 6 is a flowchart that depicts a process 600 for controlling an ELP determination according to one or more examples.

[0061] Although the exemplary process 600 illustrates a specific sequence of operations, this sequence can be modified without deviating from the scope of protection of this disclosure. For example, some of the illustrated operations can be performed in parallel or in a different sequence that does not substantially affect the function of process 600. In other examples, different components of an exemplary device or system implementing process 600 can perform functions essentially at the same time or in a specific sequence. Some or all of the operations of process 300 can, as non-limiting examples, be performed by one or more of the device 100, the ELP determination circuit 102, the exit condition logic 110, or the logic 104 for determining the ELP state.

[0062] According to one or more examples, process 600 may include receiving a status signal, where the status signal indicates a status of the fault location polynomial (ELP) determination by an ELP determination circuit at process 602.

[0063] According to one or more examples, process 600 may, at least in part, in response to a status signal having an initial value, include stopping the further determination of an ELP at operation 604.

[0064] According to one or more examples, the procedure includes issuing an ELP at operation 606.

[0065] According to one or more examples, process 600 may, at least in part, in response to the fact that the status signal has a second value, continue determining an ELP where the second value differs from the first value, at operation 608.

[0066] Fig. Figure 7 illustrates an example process 700 for controlling an ELP determination according to one or more examples.

[0067] Although the exemplary process 700 represents a specific sequence of operations, this sequence can be modified without deviating from the scope of protection of this disclosure. For example, some of the operations shown can be performed in parallel or in a different sequence that does not substantially affect the function of process 700. In other examples, different components of an exemplary device or system implementing process 700 can perform functions essentially at the same time or in a specific sequence. Some or all of the operations of process 300 can, as non-limiting examples, be performed by one or more of the device 100, the ELP determination circuit 102, the exit condition logic 110, or the logic 104 for determining the ELP state.

[0068] According to one or more examples, process 700 may include generating a status signal, the status signal being used to indicate a status of the fault location polynomial (ELP) determination by an ELP determination circuit at process 702.

[0069] According to one or more examples, process 700 can include controlling the ELP determination by the ELP determination circuit, which responds at least partially to a value of the status signal, in operation 704.

[0070] According to one or more examples, process 700 may include updating the status signal at least partially based on estimated ELPs generated during even iterations of the ELP determination by the ELP determination circuit at process 706.

[0071] According to one or more examples, process 700 may include not updating the status signal based on estimated ELPs generated during odd iterations of the ELP determination by the ELP determination circuit in process 708. In one or more examples, the estimated ELPs determined during odd iterations of the Berlekamp algorithm are not used to determine the state of an ELP determination, where, as a non-restrictive example, these are not passed from the ELP determination circuit 102 to the early exit logic circuit 122. Fig. 1 will be provided.

[0072] In one or more examples, updating the status signal on even iterations refers to updating the status signal based on versions of the estimated ELP determined during even iterations of the ELP determination. As a non-restrictive example, even iterations could correspond to even iterations of a for loop executed by the ELP determination circuit 102 or to even iterations of a clock cycle. No update of the status signal occurs (e.g., it is skipped or omitted, without restriction) based on versions of the estimated ELP determined during odd iterations of the ELP determination.

[0073] If a block has e errors (where "e" is an integer), the ELP generation process takes exactly 2*e iterations of the Berlekamp algorithm. At this point, the polynomial order (degree) is e and it has e+1 terms (coefficients). Thus, a correct ELP occurs during even cycles of the Berlekamp algorithm, since such a process updates the status signal and / or checks the early exit condition during even iterations. Estimated ELPs generated during even iterations of the ELP determination are used to update the status signal or check the early exit condition, while estimated ELPs generated during odd iterations are not used to update the status signal or check the early exit condition.The estimated ELP generated during the event iterations of the ELP determination can be used to determine and update the status signal while the next odd iteration of the Berlekamp algorithm takes place.

[0074] Fig. Figure 8 illustrates an example process 800 for correcting a codeword according to one or more examples.

[0075] Although the exemplary process 800 represents a specific sequence of operations, this sequence can be modified without infringing upon the scope of protection afforded by this disclosure. For example, some of the operations shown can be performed in parallel or in a different sequence that does not substantially affect the function of the process 800. In other examples, different components of an exemplary device or system implementing the process 800 can perform functions essentially at the same time or in a specific sequence. Some or all of the operations of the process 800 can be performed, as non-limiting examples, by one or more of the device 100, the ELP determination circuit 102, the exit condition logic 110, the ELP state determination logic 104, or the decoder 900.

[0076] According to one or more examples, process 800 may include generating a status signal, where the status signal indicates a status of the fault location polynomial (ELP) determination by an ELP determination circuit at process 802.

[0077] According to one or more examples, process 800 can include controlling the ELP determination by the ELP determination circuit, which responds at least partially to a value of the status signal at process 804.

[0078] According to one or more examples, process 800 may include the use of an ELP generated via the ELP determination by the ELP determination circuit to correct the errors of a codeword in process 806.

[0079] Fig. Figure 9 illustrates an example process 90 according to one or more examples.

[0080] Although the exemplary process 900 represents a specific sequence of operations, this sequence can be modified without deviating from the scope of protection of this disclosure. For example, some of the described operations can be performed in parallel or in a different sequence that does not substantially affect the function of process 900. In other examples, different components of an exemplary device or system implementing process 900 can perform functions essentially at the same time or in a specific sequence.

[0081] According to one or more examples, process 900 may include the generation of a status signal, the status signal being used to indicate a status of the fault location polynomial (ELP) determination by an ELP determination circuit at process 902.

[0082] According to one or more examples, process 900 can include controlling the ELP determination by the ELP determination circuit, which responds at least partially to a value of the status signal, during operation 904. Controlling the ELP determination can include prematurely exiting or continuing an ELP determination, as discussed above.

[0083] According to one or more examples, process 900 may include setting the status signal to indicate an unstable state, at least partially based on a determination that the degree of a given ELP is not at least twice the current iteration number of the ELP determination by the ELP determination circuit, as described in process 906. In general, the degree of a correct ELP should be at least twice the iteration number, and if this is not the case, the ELP state determination logic may, in one or more examples, determine that the status of the current ELP determination is an unstable state and set the value of the status signal accordingly.

[0084] Fig. Figure 10 is a functional block diagram representing a System 1000 for Reed-Solomon decoding, which, according to one or more examples, provides an early exit from the ELP determination. The System 1000 may also be referred to here as "Reed-Solomon Decoder 1000" or "RS Decoder 1000". The in Fig. The system shown in Figure 10 can be used in Chaudhuri-Hocquenghem decoding or any other polynomial-based decoding with modifications that are obvious to a person skilled in the art who is familiar with this disclosure.

[0085] An FEC block 1002 containing errors (e.g., bit errors, symbol errors, burst errors, without limitation) is received in a first-in-first-out (FIFO) memory 1014 ("Block FIFO Memory 1014"). Simultaneously, syndrome 1004 is calculated, at least partially, based on FEC block 1002. The FIFO memory stores future FEC blocks because the processing time for each block can vary, with those with fewer errors requiring fewer clock cycles and those with many errors requiring more. While slow FEC blocks (i.e., those with a higher error count) are being processed, the FIFO memory can continue to receive other FEC blocks. The decoder's output rate is higher than the total input rate due to the early exit. This allows decoder 1000 to clear the FIFO memory even as new blocks arrive at the input.It should be noted that this assumes that almost all input blocks have 0 or perhaps 1 symbol errors, and that blocks with a high number of errors are also rare in an electronic communication or storage system.

[0086] An ELP 1006 is determined at least partially based on the syndrome 1004 and a BK early-exit signal 1010. The BK early-exit signal 1010 can be, as a non-restrictive example, a status signal 106 discussed above or a signal generated by the exit condition logic 110 to stop an ELP determination. Chein roots 1008 are generated at least partially based on the ELP 1006. The Chein roots 1008 are roots of the ELP 1006 determined using a Chein search algorithm.

[0087] A Forney size signal 1012 is generated at least partially based on the Chein roots 1008. The Forney size signal 1012 can be determined based on the Forney algorithm. The value of the Forney size signal 1012 represents the size of the errors at the locations specified by the Chein roots 1008. In one or more examples, the Forney size signal 1012 can be determined at least partially based on the Chein roots 1008, the syndrome 1004, and an error size polynomial. The corrections represented by one or more of the Forney signal 1012, Chein roots 1008, ELP 1006, or syndrome 1004 are applied in block 1016 to produce output blocks that include the corrected FEC block 1018.

[0088] It is understood by experts that functional elements of the examples disclosed herein (e.g. functions, operations, actions, processes and / or procedures) can be implemented in any suitable hardware, software, firmware or combinations thereof. Fig. Figure 11 illustrates non-restrictive examples of implementations of functional elements disclosed herein. In some examples, some or all sections of the functional elements disclosed herein can be performed by hardware specifically configured to perform the functional elements.

[0089] Fig.Figure 11 is a block diagram of a switching logic 1100, which can be used in some examples to implement various functions, operations, actions, processes, or procedures disclosed herein. The switching logic 1100 includes one or more processors 1102 (hereafter sometimes referred to as "processors 1102") that are operatively coupled to one or more data storage devices 1104 (hereafter sometimes referred to as "storage 1104"). The storage 1104 includes machine-executable code 1106 stored thereon, and the processors 1102 include the logic circuit 1108. The machine-executable code 1106 includes information describing functional elements that can be implemented (e.g., performed) by the logic circuit 1108. The logic circuit 1108 is adapted to implement (e.g., perform) the functional elements described by the machine-executable code 1106.The switching logic 1100 should be considered as special hardware configured to execute the functional elements described by the machine-executable code 1106. In some examples, the processors 1102 may be configured to execute the functional elements described by the machine-executable code 1106 sequentially, concurrently (e.g., on one or more different hardware platforms), or in one or more parallel process streams.

[0090] When implemented by the logic circuit 1108 of the processors 1102, the machine-executable code 1106 is configured to adapt the processors 1102 to perform operations from examples disclosed herein. As a non-restrictive example, the machine-executable code 1106 can be configured to adapt the processors 1102 to perform some or all of the operations of Setup 100, Expression 200, Process 300, Process 400, Process 500, Process 600, Process 700, Process 800, RS Decoder 1000, or Process 900.

[0091] The processors 1102 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, another programmable device, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer with one or more processors 1102 shall be considered a special-purpose computer at least if the general-purpose computer executes functional elements corresponding to the machine-executable code 1106 (e.g., software code, firmware code, configuration data, hardware descriptions, without limitation) that refers to examples in the present disclosure.It should be noted that a general-purpose processor (which may also be referred to herein as a host processor or simply as "host") may be a microprocessor; alternatively, a general-purpose processor of Processors 1102 may also include any conventional processor, controller, microcontroller, or state machine. An FPGA or other PLD of Processors 1102 may be configured with configuration data (e.g., programmed, without limitation) to perform functions disclosed herein, or may additionally or alternatively be capable of being configured or reconfigured with configuration data (e.g., programmable or reprogrammable, without limitation) to perform functions disclosed herein.The 1102 processors can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0092] In some examples, the memory 1104 includes volatile data storage (e.g., random access memory (RAM)) and non-volatile data storage (e.g., without limitation, flash memory, a hard disk drive, a solid-state drive, or erasable programmable read-only memory (EPROM)). In some examples, the processors 1102 and the memory 1104 can be implemented in a single device (e.g., in a semiconductor device product, in a system-on-chip (SoC), without limitation). In some examples, the processors 1102 and the memory 1104 can be implemented in separate devices.

[0093] In some examples, the machine-executable code 1106 can include computer-readable instructions (e.g., software code, firmware code). As a non-restrictive example, the computer-readable instructions can be stored by the memory 1104, directly called by the processors 1102, and executed by the processors 1102 using at least the logic circuit 1108. Also as a non-restrictive example, the computer-readable instructions can be stored on the memory 1104, transferred to a storage device (not shown) for execution, and executed by the processors 1102 using at least the logic circuit 1108. Accordingly, in some examples, the logic circuit 1108 includes an electrically configurable logic circuit 1108.

[0094] In some examples, the machine-executable code 1106 can describe hardware (e.g., switching logic) that is to be implemented in the logic circuit 1108 to execute the functional elements. This hardware can be described at a variety of abstraction levels, from low-level transistor layouts to high-level description languages. At a high abstraction level, a hardware description language (HDL), such as an IEEE standard hardware description language (HDL), can be used. Non-restrictive examples include Verilog, System Verilog™, or Very Large Scale Integration (VLSI) hardware description languages ​​(VHDL).

[0095] HDL descriptions can be transformed at will into descriptions at any of numerous other levels of abstraction. As a non-restrictive example, a high-level description can be transformed into a logic-level description, such as a register-transfer language (RTL), a gate-level (GL), a layout-level, or a mask-level description. As another non-restrictive example, microoperations performed by hardware logic circuits (e.g.,The operation of the logic circuit 1108 (gates, flip-flops, registers, without limitation) is to be performed, described in an RTL, and then converted into a GL description by a synthesis tool. The GL description can be converted into a layout-level description corresponding to a physical layout of an integrated circuit, a programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof by a placement and routing tool. Accordingly, in some examples, the machine-executable code 1106 may include an HDL, an RTL, a GL description, a mask-level description, another hardware description, or any combination thereof.

[0096] In examples where the machine-executable code 1106 includes a hardware description (at any level of abstraction), a system (not shown, but including memory 1104) can be configured to implement the hardware description provided by the machine-executable code 1106. As a non-restrictive example, the processors 1102 can include a programmable logic device (e.g., an FPGA or a PLC), and the logic circuit 1108 can be electrically controlled to implement a circuit corresponding to the hardware description within the logic circuit 1108. Also as a non-restrictive example, the logic circuit 1108 can include hard-wired logic that is manufactured by a fabrication system (not shown, but including memory 1104) according to the hardware description of the machine-executable code 1106.

[0097] Regardless of whether the machine-executable code 1106 includes computer-readable instructions or a hardware description, the logic circuit 1108 is adapted to perform the functional elements described by the machine-executable code 1106 when the functional elements of the machine-executable code 1106 are implemented. It should be noted that, although a hardware description may not directly describe functional elements, a hardware description indirectly describes functional elements that can perform the hardware elements described by the hardware description.

[0098] As used in this disclosure, the terms “module” or “component” may refer to specific hardware implementations configured to perform the actions of the module or component and / or software objects or routines that can be stored on and / or executed by general-purpose hardware (e.g., computer-readable media, processing devices, but not limited to) of the computing system. In some examples, the various components, modules, engines, and services described in this disclosure may be implemented as objects or processes that run on the computing system (e.g., as separate threads).Although some of the systems and methods described in the present disclosure are generally described as being implemented in software (stored on and / or executed by universal hardware), specific hardware implementations or a combination of software and specific hardware implementations are also possible and are considered.

[0099] As used in the present revelation, the term “combination” in relation to a multitude of elements can include a combination of all the elements or any of several different subcombinations of some of the elements. For example, the phrase “A, B, C, D or combinations thereof” can refer to any one of A, B, C or D; the combination of each of A, B, C and D; and any subcombination of A, B, C or D, such as A, B and C; A, B and D; A, C and D; B, C and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0100] Terms used in this disclosure, and in particular in the accompanying claims (e.g., the main parts of the accompanying claims, without limitation), are generally to be understood as "open" terms (e.g., the term "including" should be interpreted as "including, without limitation," the term "having" should be interpreted as "having at least"; the term "includes" should be interpreted as "includes, without limitation"). As used herein, the term "each" means "some or a whole." As used herein, the term "all" means a "whole."

[0101] Furthermore, if a specific number of introduced claim terms is intended, this intention will be expressly stated in the claim, and in the absence of such a statement, no such intention exists. For example, the following attached claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim terms. However, the use of such phrases should not be interpreted to imply that introducing a claim term by the indefinite articles "one" or "a" limits a particular claim containing such an introduced claim term to examples that contain only one such term, even if the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "one" or "a" (e.g.,“A” and / or “an” should be interpreted as meaning “at least one” or “one or more”, without restriction); The same applies to the use of certain articles used to introduce claim statements.

[0102] Even if a specific number of an introduced claim statement is explicitly stated, the person skilled in the art will additionally recognize that such a statement should be interpreted as meaning at least the stated number (e.g., the mere statement of "two statements" without any other modifiers means at least two statements, or two or more statements without limitation). Furthermore, in cases where a convention is used analogously to "at least one of A, B, and C, without being limited thereto" or "one or more of A, B, and C, without being limited thereto," such a construction should generally include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, without being limited thereto.

[0103] Furthermore, any disjunctive word or phrase representing two or more alternative terms, whether in the description, claims, or drawings, should be understood as including either term, either term, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B".

[0104] Other non-restrictive examples include: Example 1: A setup comprising: a circuit for determining the fault location polynomial (ELP); and a logic circuit for setting a status signal, wherein the status signal indicates a status of the ELP determination by the ELP determination circuit, the ELP determination circuit being used for: Stopping the ELP determination at least partially in response to a first value of the status signal; and continuing the ELP determination at least partially in response to a second value of the status signal, the second value being different from the first value. Example 2: Setup according to Example 1, wherein the logic circuit serves to: determine the status of the ELP determination at least partially based on a given ELP generated by the ELP determination circuit and a vector of syndromes; and set the status signal at least partially based on the determined status of the ELP determination. Example 3: Setup according to one of Examples 1 and 2, wherein the logic circuit serves to: determine the Berlekamp discrepancy values ​​using ELPs generated by the ELP determination circuit and a vector of syndromes; and determine the status of the ELP determination at least partially based on the determined Berlekamp discrepancy values. Example 4: Setup according to one of Examples 1 to 3, wherein the logic circuit serves to: determine that the status of an ELP determination is a stable state, at least partially based on an aggregate of the determined Berlekamp discrepancy values ​​that are zero for a given ELP and the vector of syndromes; and determine that the status of the ELP determination is an unstable state, at least partially based on at least one determined Berlekamp discrepancy value that is non-zero for a given ELP and the vector of syndromes. Example 5: Setup according to one of Examples 1 to 4, wherein the logic circuit serves to: set the status signal to the first value to indicate the stable state; and set the status signal to the second value to indicate the unstable state. Example 6: Setup according to one of Examples 1 to 5, wherein the ELP determination circuit serves to: stop further determination of an ELP at least partially in response to the status signal having the first value; stop further determination of an ELP; and provide the ELP and at least partially in response to the status signal having the second value: continue determination of the ELP. Example 7: Setup according to one of Examples 1 to 6, wherein the logic circuit includes two or more sub-logic circuits to determine Berlekamp discrepancy values ​​using an ELP generated by the ELP determination circuit and respective syndromes. Example 8: Setup according to one of Examples 1 to 7, wherein the two or more sub-logic circuits serve to determine respective Berlekamp discrepancy values ​​within an equal clock cycle. Example 9: Setup according to one of Examples 1 to 8, where the logic circuit serves to: update the status signal on even iterations of an ELP determination by the ELP determination circuit. Example 10: Setup according to one of Examples 1 to 9, where the logic circuit serves to: Not update the status signal on odd iterations of an ELP determination by the ELP determination circuit. Example 11: Setup according to any of Examples 1 to 10, wherein the logic circuit serves to: set the status signal to indicate an unstable state, at least partially based on a determination that a degree of any given ELP is not at least twice the current iteration number of the ELP determination by the ELP determination circuit. Example 12: Method comprising: generating a status signal, wherein the status signal indicates a status of the determination of a fault location polynomial (ELP) by an ELP determination circuit; and controlling the ELP determination by the ELP determination circuit, which responds at least partially to a value of the status signal. Example 13: Procedure according to Example 12, comprising: determining the status of the ELP determination at least partially based on a given ELP generated by the ELP determination circuit and a vector of syndromes; and setting the status signal at least partially based on the determined status of the ELP determination. Example 14: Procedure according to one of Examples 12 and 13, comprising: determining Berlekamp discrepancy values ​​at least partially based on a respective ELP generated by the ELP determination circuit and a vector of syndromes; and determining the status of the ELP determination at least partially based on the determined Berlekamp discrepancy values. Example 15: Procedure according to any one of Examples 12 to 14, comprising: determining that the status of an ELP determination is a stable state, at least partially based on an aggregate of the determined Berlekamp discrepancy values ​​that are zero for a given ELP and the vector of syndromes; and determining that the status of the ELP determination is an unstable state, at least partially based on at least one determined Berlekamp discrepancy value that is non-zero for a given ELP and the vector of syndromes. Example 16: A method according to any of Examples 12 to 15, comprising: setting the status signal to a first value to indicate the stable state; and setting the status signal to a second value to indicate the unstable state, the second value being different from the first value. Example 17: A procedure according to any of Examples 12 to 16, comprising: at least partially in response to the status signal having a first value: stopping the further determination of an ELP; and outputting the ELP, and at least partially in response to the status signal having a second value: continuing the determination of an ELP, wherein the second value differs from the first value. Example 18: Procedure according to one of Examples 12 to 17, comprising: Determining, during an equal clock cycle, two or more Berlekamp discrepancy values ​​using an ELP generated by the ELP determination circuit and the respective syndromes. Example 19: Procedure according to one of Examples 12 to 18, comprising: updating the status signal on even iterations of the ELP determination by the ELP determination circuit. Example 20: Procedure according to one of Examples 12 to 19, comprising: Use of an ELP generated by the ELP determination circuit for error correction of a codeword. Example 21: A procedure according to any of Examples 12 to 20, a procedure comprising: setting the status signal to indicate an unstable state, at least partially based on a determination that a degree of a given ELP is not at least twice the current iteration number of the ELP determination by the ELP determination circuit. Example 22: Decoder for Reed-Solomon decoding or Bose-Chaudhuri-Hocquenghem decoding, wherein the decoder includes a circuit for determining the fault location polynomial (ELP), wherein the ELP determination circuit terminates an ELP determination at least partially in response to a statement that a respective ELP has reached a stable state.

[0105] Although the present disclosure has been described herein with respect to certain illustrated examples, those skilled in the art will recognize and understand that the present invention is not limited to these. Rather, many additions, omissions, and modifications can be made to the illustrated and described examples without departing from the scope of protection of the invention as claimed below together with its legal equivalents. Furthermore, features of one example can be combined with features of another example and still remain within the scope of protection of the invention as envisaged by the inventor. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 387,639

[0001]

Claims

[1] Institution, encompassing: a circuit for determining the fault location polynomial (ELP); and a logic circuit for setting a status signal, wherein the status signal indicates a status of the ELP determination by the ELP determination circuit, where the ELP determination circuit serves to: Stopping the ELP determination at least partially in response to an initial value of the status signal; and Continuing the ELP determination at least partially in response to a second value of the status signal, where the second value differs from the first value. [2] Device according to claim 1, wherein the logic circuit serves to: Determining the status of the ELP determination at least partially based on a given ELP generated by the ELP determination circuit and a vector of syndromes; and Setting the status signal at least partially based on the determined status of the ELP determination. [3] Device according to claim 1, wherein the logic circuit serves to: Determining the Berlekamp discrepancy values ​​using ELPs generated by the ELP determination circuit and a vector of syndromes; and Determining the status of the ELP determination at least partially based on the determined Berlekamp discrepancy values. [4] Device according to claim 3, wherein the logic circuit serves to: Determine that the status of an ELP determination is a stable state, at least partially based on an aggregate of the determined Berlekamp discrepancy values ​​that are zero for a given ELP and the syndrome vector; and Determine that the status of the ELP determination is an unstable state, at least partially based on at least one specific Berlekamp discrepancy value that is non-zero for a given ELP and the syndrome vector. [5] Device according to claim 4, wherein the logic circuit serves to: Setting the status signal to the first value to indicate the stable state; and Setting the status signal to the second value indicates the unstable state. [6] Device according to claim 1, wherein the ELP determination circuit serves to: at least partly in response to the fact that the status signal has the first value: Stopping further determination of an ELP; and Provisioning the ELP and at least partly in response to the fact that the status signal has the second value: Continuing the determination of the ELP. [7] Device according to claim 1, wherein the logic circuit includes two or more sub-logic circuits to determine Berlekamp discrepancy values ​​using an ELP generated by the ELP determination circuit and respective syndromes. [8] Device according to claim 7, wherein the two or more sub-logic circuits serve to determine respective Berlekamp discrepancy values ​​within an equal clock cycle. [9] Device according to claim 1, wherein the logic circuit serves to: Updating the status signal on even iterations of an ELP determination by the ELP determination circuit. [10] Device according to claim 1, wherein the logic circuit serves to: The ELP determination circuit updates the status signal on odd iterations of an ELP determination. [11] Device according to claim 1, wherein the logic circuit serves to: Setting the status signal to indicate an unstable state, at least partially based on a determination that a degree of a given ELP is not at least twice the current iteration number of the ELP determination by the ELP determination circuit. [12] Procedures, including: Generating a status signal, wherein the status signal indicates a status of the determination of the fault location polynomial (ELP) by an ELP determination circuit; and Control of the ELP determination by the ELP determination circuit, at least partially in response to a value of the status signal. [13] The method of claim 12, comprising: Determining the status of an ELP determination at least partially based on a given ELP generated by the ELP determination circuit and a vector of syndromes; and and setting the status signal at least partially based on the determined status of the ELP determination. [14] The method of claim 12, comprising: Determining Berlekamp discrepancy scores at least partially based on a given ELP generated by the ELP determination circuit and a vector of syndromes; and Determining the status of the ELP determination at least partially based on the determined Berlekamp discrepancy values. [15] The method of claim 14, comprising: Determine that the status of an ELP determination is a stable state, at least partially based on an aggregate of the determined Berlekamp discrepancy values ​​that are zero for a given ELP and the syndrome vector; and Determine that the status of the ELP determination is an unstable state, at least partially based on at least one specific Berlekamp discrepancy value that is non-zero for a given ELP and the syndrome vector. [16] The method of claim 15, comprising: Setting the status signal to an initial value to indicate the stable state; and Setting the status signal to a second value to indicate the unstable state, where the second value differs from the first value. [17] The method of claim 12, comprising: at least partly in response to the fact that the status signal has an initial value: Stopping further determination of an ELP; and Issuing the ELP and at least partly in response to the fact that the status signal has a second value: Continuing the determination of an ELP, where the second value differs from the first value. [18] The method of claim 12, comprising: Determine, during the same clock cycle, two or more Berlekamp discrepancy values ​​using an ELP generated by the ELP determination circuit and the respective syndromes. [19] The method of claim 12, comprising: The ELP determination circuit updates the status signal on even iterations of the ELP determination. [20] The method of claim 12, comprising: Utilizing an ELP generated by the ELP determination circuit for error correction of a codeword. [21] The method of claim 12, comprising a method: Setting the status signal to indicate an unstable state, at least partially based on a determination that a degree of a given ELP is not at least twice the current iteration number of the ELP determination by the ELP determination circuit. [22] Decoder for Reed-Solomon decoding or Bose-Chaudhuri-Hocquenghem decoding, wherein the decoder includes a circuit for determining the fault location polynomial (ELP), wherein the ELP determination circuit terminates an ELP determination at least partially in response to a statement that a respective ELP has reached a stable state.

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