THREE-LEVEL INVERTER AND PROGRAM

Abstract

In a three-level inverter (30), the impedances of a plurality of upper-arm paths are configured to be at a similar level, each of the plurality of upper-arm paths being provided by a respective upper-arm diode and providing an electrical path connecting a connection point (72c) of a high-potential conduction element (72) and a positive bus (31) to a first end of a middle switch (SQU1 to SQW2) via the respective upper-arm diode (DUH1 to DWH2) and an intermediate conduction element (70), and the impedances of each of a plurality of sub-arm paths are configured to be at a similar level, each of the plurality of sub-arm paths being provided by a respective sub-arm diode and providing an electrical path,which connects a connection point of the low-potential conduction element (71) and a negative bus (32) to a middle switch (DUL1 to DWL2) via the sub-branch diode and the intermediate conduction element.,

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Application No. 2022-210644, filed on December 27, 2022, which is hereby incorporated by reference. TECHNICAL FIELD

[0002] This disclosure relates to a three-level inverter and a program. BACKGROUND

[0003] Conventionally, an inverter having two semiconductor switches (specifically, IGBTs) connected in parallel is known, as described in Patent Document 1. The inverter includes a gate drive circuit that drives the two semiconductor switches, a comparator, an AND circuit, and a transformer. When the two semiconductor switches are driven by the gate drive circuit, the comparator detects a differential value of the collector current flowing in the switch with the higher temperature among the two semiconductor switches, and the primary winding of the transformer is driven via the AND circuit. As a result, an induced voltage is generated in the secondary winding connected between the gates of the two semiconductor switching elements and forming part of the transformer, and the gate voltage of the semiconductor switch with the higher temperature rises.As a result, an imbalance of the collector currents flowing in the two semiconductor switches is suppressed. REFERENCES ACCORDING TO THE PRIOR ART PATENT DOCUMENT

[0004] Patent document 1: JP 2004 - 15 910 A1 SUMMARY OF THE INVENTION

[0005] A three-level inverter, like the inverter described above, is also known. The three-level inverter comprises a plurality of series-connected elements of an upper-branch switch and a lower-branch switch for each phase, with the plurality of series-connected elements connected in parallel. The three-level inverter comprises upper-branch diodes, each of which is reversely connected in parallel with each upper-branch switch, lower-branch diodes, each of which is reversely connected in parallel with one of the lower-branch switches, and a middle switch for each phase.

[0006] In each phase and in each branch of the three-level inverter, an imbalance of the recovery current flowing through each diode can occur. Therefore, it is desirable to have a configuration that can suppress this imbalance of recovery currents.

[0007] This disclosure aims to provide a three-level inverter and program that can suppress recovery current imbalance.

[0008] According to one aspect of this disclosure, a three-level inverter includes, for each phase, a plurality of series circuit elements connected in parallel. Each series circuit element includes an upper-branch switch and a lower-branch switch connected in series, an upper-branch diode connected in reverse parallel to the upper-branch switch, and a lower-branch diode connected in reverse parallel to the lower-branch switch.The three-level inverter further comprises: a middle switch, a high-potential conduction element that electrically connects the high-potential terminal of each of the upper-branch switches provided by the plurality of series-connected elements and a positive bus bar, a low-potential conduction element that electrically connects the low-potential terminal of each of the sub-branch switches provided by the plurality of series-connected elements and a negative bus, and an intermediate conduction element that electrically connects the low-potential terminal of each of the upper-branch switches provided by the plurality of series-connected elements, the high-potential terminal of each of the sub-branch switches provided by the plurality of series-connected elements, and a first end of the middle switch.The impedances of upper arm paths are configured to be at a similar level, each of the upper arm paths being provided by a respective upper arm diode and providing an electrical path connecting a connection point of the high potential conduction element and the positive bus to a first end of the middle switch via the respective upper arm diode and the intermediate conduction element, and the impedances of sub arm paths are configured to be at a similar level, each of the sub arm paths being provided by a respective sub arm diode and providing an electrical path connecting a connection point of the low potential conduction element and the negative bus to the middle switch via the sub arm diode and the intermediate conduction element.

[0009] According to this disclosure, it is possible to suppress an imbalance of recovery currents because the impedances of the upper arm paths are configured to be at a similar level and the impedances of the lower arm paths are configured to be at a similar level. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. In the drawings: Fig. 1 shows an overall configuration of a control system according to a first embodiment, Fig. 2 electrical connections of a U-phase circuit, Fig. 3 a representation of each module, Fig. 4 a top view of each module, Fig. 5 switching modes, Fig. 6 an unbalanced state of recovery flows, Fig. 7 an unbalanced state of recovery flows, Fig. 8 is a timing diagram illustrating an example of a gate voltage UUs, Fig. 9 a current distribution pattern in an oscillation suppression control, Fig. 10 a current distribution pattern in an oscillation suppression control, Fig. 11 a current distribution pattern in an oscillation suppression control, Fig. 12 a current distribution pattern in an oscillation suppression control, Fig. 13 a current distribution pattern in an oscillation suppression control, Fig. 14 a current distribution pattern in an oscillation suppression control, Fig. 15 a current distribution pattern in an oscillation suppression control, Fig. 16 is a timing chart illustrating switching control of the inverter for a comparative example, Fig. 17 a current distribution pattern for a comparison example, Fig. 18 a current distribution pattern for a comparison example, Fig. 19 a current distribution pattern for a comparison example, Fig. 20 a current distribution pattern for a comparison example, Fig. 21 a flowchart of an oscillation suppression control, Fig. 22 is a flowchart of an oscillation suppression control according to a second embodiment, Fig. 23 electrical connections of the U-phase circuit according to a third embodiment, and Fig. 24 is a flowchart of an oscillation suppression control according to the third embodiment. DESCRIPTION OF EMBODIMENTS

[0011] Several embodiments are described below with reference to the drawings. In the embodiments, functionally and / or structurally corresponding and / or related sections may be identified by the same reference numerals or by reference numerals that differ by the hundredth digit or higher. For corresponding and / or related sections, reference may be made to the description of other embodiments. First embodiment

[0012] A first embodiment of a three-level inverter according to the present disclosure will be described below with reference to the drawings. According to this embodiment, a control system equipped with the three-level inverter is installed in an electric vehicle, such as an electric vehicle or a hybrid vehicle.

[0013] As it is in Fig. 1, the control system includes a motor 10, a battery 20, which is a DC power source, and an inverter 30. The motor 10 is the main engine of the vehicle and has a rotor (not shown). The rotor and the drive wheels of the vehicle can transmit power to each other. The motor 10 is a three-phase synchronous machine. The motor 10 has a U-phase winding 11U, a V-phase winding 11V, and a W-phase winding 11W connected in star as stator windings. The winding 11U, the winding 11V, and the winding 11W of each phase are arranged with an offset of 120° in electrical angle therebetween. The motor 10 is, for example, a permanent magnet synchronous motor.

[0014] Battery 20 is electrically connected to winding 11U, winding 11V, and winding 11W for each phase of motor 10 via inverter 30. Battery 20 is, for example, a battery assembly with series-connected battery cells. Battery 20 is a chargeable and dischargeable secondary battery, for example, a lithium-ion battery.

[0015] The inverter 30 converts DC power supplied from the battery 20 into three-phase AC power through switching control and supplies the converted AC power to each of the winding 11U, the winding 11V, and the winding 11W. The inverter 30 is a three-level inverter. The inverter 30 includes a first capacitor 21 and a second capacitor 22. The first capacitor 21 and the second capacitor 22 are connected in series. The battery 20 is connected in parallel to the series circuit elements of the first capacitor 21 and the second capacitor 22. According to this embodiment, the capacitances of the first capacitor 21 and the second capacitor 22 have substantially the same value.

[0016] The inverter 30 has upper branch switches and lower branch switches for each of the three phases. According to this embodiment, each branch switch consists of a plurality of semiconductor switching devices connected in parallel, specifically, two semiconductor switching devices connected in parallel. The semiconductor switching devices according to this embodiment are IGBTs.

[0017] A U-phase upper-branch switch comprises a first U-phase upper-branch switch SUH1 and a second U-phase upper-branch switch SUH2. A U-phase lower-branch switch comprises a first U-phase lower-branch switch SUL1 and a second U-phase lower-branch switch SUL2. The first U-phase upper-branch switch SUH1 is connected in reverse parallel to a first U-phase upper-branch diode DUH1. The first U-phase lower-branch switch SUL1 is connected in reverse parallel to a first U-phase lower-branch diode DUL1. The second U-phase lower-branch switch SUL2 is connected in reverse parallel to a second U-phase lower-branch diode DUL2. The second U-phase lower-branch switch SUL2 is connected in reverse parallel to a second U-phase lower-branch diode DUL2. Each branch diode can be a freewheeling diode.

[0018] A V-phase upper arm switch comprises a first V-phase upper arm switch SVH1 and a second V-phase upper arm switch SVH2. A V-phase lower arm switch comprises a first V-phase lower arm switch SVL1 and a second V-phase lower arm switch SVL2. The first V-phase upper arm switch SVH1 is connected in reverse parallel to a first V-phase upper arm diode DVH1. The second V-phase upper arm switch SVH2 is connected in reverse parallel to a second V-phase upper arm diode DVH2. The first V-phase lower arm switch SVL1 is connected in reverse parallel to a first V-phase lower arm diode DVL1. The second V-phase lower arm switch SVL2 is connected in reverse parallel to a second V-phase lower arm diode DVL2.

[0019] A W-phase upper-arm switch comprises a first W-phase upper-arm switch SWH1 and a second W-phase upper-arm switch SWH2. A W-phase lower-arm switch comprises a first W-phase lower-arm switch SWL1 and a second W-phase lower-arm switch SWL2. The first W-phase upper-arm switch SWH1 is connected in reverse parallel to a first W-phase upper-arm diode DWH1. The second W-phase upper-arm switch SWH2 is connected in reverse parallel to a second W-phase upper-arm diode DWH2. The first W-phase lower-arm switch SWL1 is connected in reverse parallel to a first W-phase lower-arm diode DWL1. The second W-phase lower-arm switch SWL2 is connected in reverse parallel to a second W-phase lower-arm diode DWL2.

[0020] The electrical connections of the inverter 30, the battery 20, and the motor 10 are described using the U-phase as an example. A positive bus 31 is connected to a collector, which is the respective high-potential terminal of the first upper-arm switch SUH1 and the second upper-arm switch SUH2. The positive bus 31 is connected to the positive terminal of the battery 20 and the first end of the first capacitor 21. The second end of the first capacitor 21 is connected to the first end of the second capacitor 22. A negative bus 22 is connected to the emitters, which are the respective low-potential terminals of the first U-phase sub-arm switch SUL1 and the second U-phase sub-arm switch SUL2. The positive bus 31 and the negative bus 32 are each formed of a conductive member such as a bus bar.

[0021] The first end of the U-phase winding 11U is connected to the emitters of the first U-phase upper-branch switch SUH1 and the second U-phase upper-branch switch SUH2, and to the collectors of the first U-phase lower-branch switch SUL1 and the second U-phase lower-branch switch SUL2. The second ends of the winding 11U, the winding 11V, and the winding 11W are connected to each other. The connection point is a neutral point.

[0022] The inverter 30 has central switches for three phases. Each of the three central switches can conduct and interrupt current in both directions. According to this embodiment, each central switch consists of two semiconductor switching devices. Each of the two semiconductor switching devices can be an IGBT.

[0023] The middle V-phase switch includes a first U-phase switch SQU1 and a second switch SQU2. The first U-phase switch SQU1 is connected in reverse parallel to a first U-phase diode DQU1. The second U-phase switch SQU2 is connected in reverse parallel to a second U-phase diode DQU2. The middle V-phase switch includes a first V-phase switch SQV1 and a second V-phase switch SQV2. The first V-phase switch SQV1 is connected in reverse parallel to a first V-phase diode DQV1. The second V-phase switch SQV2 is connected in reverse parallel to a second V-phase diode DQV2. The middle W-phase switch includes a first W-phase switch SQW1 and a second switch SQW2. The first W-phase switch SW1 is connected in reverse parallel to a first W-phase diode DQW1. The second W-phase switch SQW2 is connected to a second W-phase diode DQW2. Each diode can be a freewheeling diode.

[0024] The electrical connection of the middle switch is described below using the U-phase as an example. The emitter of the first U-phase switch SQU1 is connected to the emitter of the second U-phase switch SQU2. The collector of the first U-phase switch SQU1 is connected to the second end of the first capacitor 21 and the second end of the second capacitor 22. The emitter of the second U-phase switch SQU2 is connected to the emitter of the first U-phase upper-branch switch SUH1, the emitter of the second U-phase upper-branch switch SUH2, the collector of the first U-phase lower-branch switch SQL1, and the collector of the second U-phase lower-branch switch SUL2.

[0025] The control system includes a current sensor 40 and a rotation angle sensor 41. The current sensor 40 detects the phase currents flowing in the winding 11U, the winding 11V, and the winding 11W. The rotation angle sensor 41 detects the rotation angle (specifically, the electrical angle) of the motor 10. The rotation angle sensor 41 can be a resolver. The detected values ​​of the current sensor 40 and the rotation angle sensor 41 are each input to a control device 50 provided by the control system.

[0026] The control device 50 is mainly composed of a microcontroller 51. The microcontroller 51 includes a CPU. The functions provided by the microcontroller 51 may be provided by software recorded in a non-volatile storage device and a computer that executes them, by software only, by hardware only, or a combination thereof. For example, when the microcontroller 51 is provided by an electronic circuit that is hardware, it may be provided by a digital or analog circuit that includes some logic circuits. For example, the microcontroller 51 executes a program stored in a non-volatile tangible storage medium as its own storage unit. The program includes, for example, a program for a Fig. 21. When the program installed in the control device 50 is executed, a process corresponding to the program is performed. The memory is, for example, a non-volatile memory. The program stored in a memory section can be downloaded and updated via a communication network such as the Internet using a method known as OTA (Over the Air).

[0027] The control device 50 generates a control signal for each switch SUH1 to SWL2 and SQU1 to SQW2 of the inverter 30 to cause a control variable of the motor 10 to approach a command value. The control signals include an ON command and an OFF command. The control device 50 turns each switch SUH1 to SWL2 and SQU1 to SQW2 on and off based on the generated control signals. In this system, the controlled variable is torque, and the command value is a command torque Trq*.

[0028] According to this embodiment, the inverter 30 is composed of switch modules. It is described below using the U phase as an example with reference to Fig. 2 to 4.

[0029] The circuit composing the U-phase of the inverter 30 consists of three switch modules. For example, the switch modules include a first module M1 and a second module M2 (each corresponding to a "branch module"), and an intermediate module MM. Each switch module M1, M2, and MM has a housing 60. Semiconductor switching elements and freewheeling diodes are housed in each of the housings 60. The shape of each housing 60 is flat rectangular. According to this embodiment, the shapes of the housing 60 of each module M1, M2, and MM are substantially identical.

[0030] The housing 60 of the first module M1 accommodates the U-phase upper-branch switch SUH1, the U-phase upper-branch diode UH1, the U-phase lower-branch switch SUL1, and the U-phase lower-branch diode DUL1. The collector of the U-phase upper-branch switch SUH1 is connected to an external high-potential terminal CP provided on the housing 60 of the first module M1. The emitter of the first U-phase lower-branch switch SUL1 is connected to an external low-potential terminal CN provided on the housing 60 of the first module M1. The emitter of the first U-phase upper-branch switch SUH1 and the collector of the first U-phase lower-branch switch SUL1 are connected to an external intermediate terminal CO provided on the housing 60 of the first module M1.

[0031] The housing 60 of the second module M2 houses the second U-phase upper-branch switch SUH2, the second U-phase upper-branch diode DUH2, the second U-phase lower-branch switch SUL2, and the second U-phase lower-branch diode DUL2. Since the configurations of the second module M2 and the first module M1 are the same in this system, a detailed description of the second module M2 is omitted.

[0032] According to this embodiment, the first module M1 and the second module M2 have the same specifications. Therefore, the internal configurations of the first module M1 and the second module M2 are identical. More specifically, the specifications of each switch SUH1, SUL1, SUH2, and SUL2 housed in the first and second modules M1 and M2 are identical, and the specifications of each diode DUH1, DUL1, DUH2, and DUL2 are identical. Therefore, the design values ​​of a threshold voltage Vth of each switch SUH1, SUL1, SUH2, and SUL2 are set to the same value, and the design values ​​of a rated current of each switch SUH1, SUL1, SUH2, and SUL2 are set to the same value.The design value of a reverse recovery time of each diode DUH1, DUL1, DUH2 and DUL2 is set to the same value, and the design value of an on-resistance of each diode DUH1, DUL1, DUH2 and DUL2 is set to the same value.

[0033] The housing 60 of the intermediate module MM houses the first U-phase switch SQU1, the second switch SQU2, the first U-phase diode DQU1, and the second U-phase diode DQU2. The collector of the first U-phase switch SQU1 is connected to a neutral point terminal CM2 provided on the housing 60 of the intermediate module MM. The collector of the second U-phase switch SQU2 is connected to an intermediate terminal CM1 provided on the housing 60 of the intermediate module MM.

[0034] As it is in Fig. 3 and Fig. As shown in Figure 4, the housing of each module M1, M2, and MM includes a pair of main plate portions 61 facing each other in the thickness direction (X direction), and a terminal installation surface 62 connecting the ends of each main plate portion 61. The modules M1, M2, and MM are arranged side by side in the thickness direction of the housing 60, with the main plate portions 61 facing each other. The terminal installation surfaces 62 of each module M1, M2, and MM face a common specific direction (Z direction) orthogonal to the X direction. The intermediate module is sandwiched between the first module M1 and the second module M2.

[0035] In the first module M1 and the second module M2, the external high-potential terminal CP, the external low-potential terminal CN, and the external intermediate terminal CO are arranged in the Y direction on the terminal installation surface 62. The Y direction is orthogonal to the X direction and the Z direction. In the intermediate module MM, the neutral point terminal CM2 and the intermediate terminal CM1 are arranged in the Y direction on the terminal installation surface 62. When the modules M1, M2, and MM are lined up, the external high-potential terminals CP and the neutral point terminal CM2 are arranged in the X direction, the two external intermediate terminals CO and the intermediate terminal CM1 are arranged in the X direction, and the two external low-potential terminals CN are arranged in the X direction.

[0036] As it is in Fig. 2 and Fig. 4, the external high-potential terminal CP of the first module M1 and the external high-potential terminal CP of the second module M2 are connected by a high-potential bus bar 72 (an example of a “conductive high-potential element”). As shown in Fig. 4, the high-potential bus bar 72 is symmetrical with respect to the reference axis BL passing through the center of the thickness direction of the casing 60 of the intermediate module MM in the front view of the terminal installation surface 62. The high-potential bus bar 62 has two terminal connections 72a, a first connection 72b, and a second connection 72c. In the front view of the terminal installation surface 62, the first connection 72b extends in the X direction. The terminal connection 72a extends in the Y direction from both ends in the longitudinal direction of the first connection 72b. One of the two terminal connections 72a is connected to the external high-potential terminal CP of the first module M1, and the other is connected to the external high-potential terminal CP of the second module M2.The second connection 72c extends from the longitudinal center of the first connection 72b in the direction opposite to that in which the terminal connection 72a extends with respect to the first connection 72b. The second connection 72c is connected to the positive bus 31.

[0037] The external high-potential terminals CP of the first and second modules M1 and M2 and the intermediate terminal CM1 of the intermediate module MM are connected by an intermediate busbar 70 (an example of a “conductive intermediate element”). The intermediate busbar 70 is symmetrical with respect to the reference axis BL in the front view of the terminal installation surface 62, as shown in Fig. 4. The intermediate busbar 70 has a first connection 70a and a second connection 70b. The first connection 70a extends in the X direction. The second connection 70b extends from the longitudinal center of the first connection 70a in the Y direction in the opposite direction to the high-potential busbar 72. The second connection 70b is connected to the neutral point terminal CN2 of the intermediate module MM and the first end of the windings of the motor 10.

[0038] The symmetrical structure of the high-potential busbar 62, the first and second modules M1 and M2 having the same specifications, and the symmetrical structure of the intermediate busbar 70 cause the impedances of the first and second upper-arm paths to be at similar levels (in other words, equal or equivalent). The first upper-arm path is an electrical path connecting the second connection 72c to the intermediate terminal CM1 of the intermediate module MM via the first connection 72b, the external high-potential terminal CP of the first module M1, the first U-phase upper-arm diode DUH1, the external intermediate terminal CO of the first module M1, the first connection 70a, and the second connection 70b. The first upper-arm path is an electrical path corresponding to the first U-phase upper-arm diode DUH1.The second upper-arm path is an electrical path connecting the second connection 72c to the intermediate terminal CM1 of the intermediate module MM via the first connection 72b, the external high-potential terminal CP of the second module M2, the second U-phase upper-arm diode DUH2, the external intermediate terminal CO of the second module M2, the first connection 70a, and the second connection 70b. The second upper-arm path is an electrical path corresponding to the second U-phase upper-arm diode DUH2.The “impedance of the first upper-arm path and the second upper-arm path are at similar levels” means, for example, that the value of an impedance deviation between the first upper-arm path and the second upper-arm path is within the range of plus or minus 20% of the larger impedance of the first upper-arm path and the second upper-arm path, or preferably that the value of the above-described deviation is within the range of plus or minus 15% of the larger impedance of the first upper-arm path and the second upper-arm path, or further preferably that the value of the above-described deviation is within the range of plus or minus 5% of the larger impedance of the first upper-arm path and the second upper-arm path.

[0039] The external low-potential terminal CN of the first module M1 and the external low-potential terminal CN of the second module M2 are connected by a low-potential busbar 71 (an example of a “low-potential conduction element”). As shown in Fig. As shown in Figure 4, the low-potential busbar 71 is symmetrical with respect to the reference axis BL in the front view of the terminal installation surface 62 and extends in the X direction. The center portion of the low-potential busbar 71 in the X direction is connected to the negative bus 32.

[0040] The symmetrical structure of the low-potential busbar 71, the fact that the first and second modules M1 and M2 have the same specifications, and the symmetrical structure of the intermediate busbar 70 cause the impedances of the first and second sub-branch paths to be at similar levels (in other words, equal or equivalent). The first sub-branch path is an electrical path connecting the center of the low-potential busbar 71 in the X direction to the intermediate terminal CM1 of the intermediate module MM via the external low-potential terminal CN of the module M1, the first U-phase sub-branch diode DUL1, the external intermediate terminal CO of the module M1, the first junction 70a, and the second junction 70b. The first sub-branch path is an electrical path corresponding to the first U-phase sub-branch diode DUL1.The second sub-branch path is an electrical path connecting the center of the low-potential busbar 71 in the X direction to the intermediate terminal CM1 of the intermediate module MM via the external low-potential terminal CN of the module M2, the second U-phase sub-branch diode DUL2, the external intermediate terminal CO of the module M2, the first connection 70a, and the second connection 70b. The second sub-branch path is an electrical path corresponding to the second U-phase sub-branch diode DUL2.The “impedances of the first sub-branch path and the second sub-branch path are at a similar level” means, for example, that the value of the impedance deviation between the first sub-branch path and the second sub-branch path is within a range of plus or minus 20% of the larger impedance of the first sub-branch path and the second sub-branch path, or preferably that the value of the above-described deviation is within a range of plus or minus 15% of the larger impedance of the first sub-branch path and the second sub-branch path, or further preferably that the value of the above-described deviation is within a range of plus or minus 5% of the larger impedance of the first sub-branch path and the second sub-branch path.

[0041] According to this embodiment, there are no external terminals between the intermediate terminal CM1 and the neutral point terminal CM2 on the terminal installation surface 62 of the intermediate module MM. This reduces the filling density of the external terminals when the three modules M1, M2 and MM are assembled in each phase, thereby improving heat dissipation.

[0042] The control device 50 has a control circuit 52 ( Fig. 6). For example, drive circuits 52 are provided individually for each switch SUH1 to SWL2 of the inverter 30.

[0043] When the drive circuit 52 determines that the input drive signal is the ON command, it supplies a charging current to the gate of the switch corresponding to it. As a result, the gate voltage of the switch becomes higher than the threshold voltage Vth, and the switch is turned on. Conversely, when the drive circuit 22 determines that the drive signal is the OFF command, it causes a discharge current to flow from the gate of the switch corresponding to it to the ground terminal. As a result, the gate voltage of the switch becomes lower than the threshold voltage Vth, and the switch is turned off.

[0044] With reference to Fig. 5, three levels of voltage that can be output from the inverter 30 are explained using the U phase as an example.

[0045] The inverter 30 can output three voltage levels: H, M, and L. When the L-level voltage is 0, the H-level voltage is equivalent to the voltage between both ends of the series connection element of the first capacitor 21 and the second capacitor 22, and the M-level voltage is equivalent to the voltage between both ends of the second capacitor 22.

[0046] When the H-level voltage is output, the control device 50 turns on the first U-phase upper arm switch SUH1 and the second U-phase upper arm switch SUH2, turns off the first U-phase lower arm switch SUL1 and the second U-phase lower arm switch SUL2, turns on the first U-phase switch SQU1, and turns off the second U-phase switch SQU2. The second U-phase switch SQU2 is turned off to prevent a short circuit between both ends of the first capacitor 21 via the first U-phase upper arm switch SUH1, the second U-phase upper arm switch SUH2, the second U-phase switch SQU2, and the first U-phase diode DQU1. Hereinafter, the switching mode for outputting the H-level voltage is occasionally referred to as the H-level mode.

[0047] When the M-level voltage is output, the control device 50 turns off the first U-phase upper-arm switch SUH1, the second U-phase upper-arm switch SUH2, the first U-phase lower-arm switch SUL1, and the second U-phase lower-arm switch SUL2, and turns on the first U-phase switch SQU1 and the second switch SQU2. Hereinafter, the switching mode for outputting the M-level voltage is occasionally referred to as the M-level mode.

[0048] When switching from the H-level mode to the M-level mode or from the M-level mode to the H-level mode, the control device 50 implements an HM dead-time mode during the switching. When implementing the HM dead-time mode, the control device 50 turns off the second U-phase upper-branch switch SUH2, the first U-phase lower-branch switch SUL1, the second U-phase lower-branch switch SUL2, and the second U-phase switch SQU2, and turns on the first U-phase switch SQU1.

[0049] When outputting the L-level voltage, the control device 50 turns off the first U-phase upper arm switch SUH1 and the second U-phase upper arm switch SUH2, turns on the first U-phase lower arm switch SUL1 and the second U-phase lower arm switch SUL2, turns off the first U-phase switch SQU1, and turns on the second U-phase switch SQU2. The first U-phase switch SQU1 is turned off to prevent a short circuit at both ends of the second capacitor 22 via the first U-phase lower arm switch SUL1, the second U-phase lower arm switch SUL2, the second U-phase switch SQU2, and the first U-phase diode DQU1. Hereinafter, the switching mode for outputting the L-level voltage is sometimes referred to as the L-level mode.

[0050] When switching from the M-level mode to the L-level mode or from the L-level mode to the M-level mode, the control device 50 implements an ML dead-time mode during switching. When implementing the ML dead-time mode, the control device 50 turns on the second U-phase upper-branch switch SUH2, the first U-phase lower-branch switch SUL1, the second U-phase lower-branch switch SUL2, and the first U-phase switch SQU1, and turns off the second U-phase switch SQU2.

[0051] When switching from the high-level mode to the low-level mode or from the low-level mode to the high-level mode, the control device 50 implements an HL dead-time mode during the switching. When implementing the HL dead-time mode, the control device 50 turns off the second U-phase upper-branch switch SUH2, the first U-phase lower-branch switch SUL1, the second U-phase lower-branch switch SUL2, the first U-phase switch SQU1, and the second U-phase switch SQU2.

[0052] In each phase, an imbalance of recovery currents can occur, flowing through the freewheeling diodes of each switch connected in parallel. If the imbalance occurs, the gate voltage of each switch can oscillate, and each switch can fail. This is explained below with reference to the U-phase upper branch as an example. Fig. 6 and Fig. 7 described. Fig. 6 and Fig. 7 shows the current distribution immediately after switching from the L-level mode to the H-level mode via the HL dead time mode when a current flows from the inverter 30 to the windings.

[0053] For example, a ground terminal GND1 of the drive circuit 52, which is electrically connected to the gate of the first U-phase upper-arm switch SUH1, is connected to a portion between the emitter of the first U-phase upper-arm switch SUH1 and the external intermediate terminal CO of the first module M1 in the first upper-arm path. The ground terminal GND2 of the drive circuit 52, which is electrically connected to the gate of the second U-phase upper-arm switch SUH2, is connected to a portion between the emitter of the second U-phase upper-arm switch SUH2 and the external intermediate terminal CO of the second module M2 in the second upper-arm path, for example.

[0054] In Fig. 6, R1 and L1 schematically show the resistance and inductance components present between the emitter of the first U-phase upper-arm switch SUH1 and the ground terminal GND1 in the first upper-arm path. R2 and L2 schematically show the resistance and inductance components present between the emitter of the second U-phase upper-arm switch SUH2 and the ground terminal GND2 in the second upper-arm path. ΔV1 is the voltage between the emitter of the first U-phase upper-arm switch SUH1 and the ground terminal GND1 (hereinafter referred to as the first voltage) in the first upper-arm path. ΔV2 is the voltage between the emitter of the second U-phase upper-arm switch SUH2 and the ground terminal GND2 in the second upper-arm path.

[0055] Due to variations in the threshold voltage Vth of the U-phase upper arm switch SUH1 and the U-phase upper arm switch SUH2, in the forward current reduction rate dif / dt of the U-phase sub-arm diode DUL1 and the U-phase sub-arm diode DUL2 when switching from the L-level mode to the HL dead-time mode, in the forward voltage of the U-phase sub-arm diode DUL1 and the U-phase sub-arm diode DUL2, in the forward voltage of the U-phase sub-arm diode DUL1 and the U-phase sub-arm diode DUL2, and in the forward voltage of the U-phase sub-arm diode DUL1 and the U-phase sub-arm diode DUL2, an imbalance of the recovery currents flowing in each of the U-phase upper arm diode DUH1 and the U-phase upper arm diode DUH2 may occur. occur. In the Fig. 6, the recovery current flowing in the first U-phase upper arm diode DUH1 is smaller than the recovery current flowing in the second U-phase upper arm diode DUH2, and the first voltage ΔV1 is smaller than the second voltage ΔV2.

[0056] In this case, the gate voltage of the first U-phase upper-arm switch SUH1, which is the smaller voltage of the switches SUH1 and SUH2, is higher than the gate voltage of the second U-phase upper-arm switch SUH2, which is the larger (higher) voltage. As a result, the on-resistance value of the first U-phase upper-arm switch SUH1 is smaller than the on-resistance value of the second U-phase upper-arm switch SUH2. Then, as shown in Fig. 7, the recovery current flowing in the first U-phase upper arm diode DUH1 is larger (higher) than the recovery current flowing in the second U-phase upper arm diode DUH2, and the second voltage ΔV2 becomes smaller than the first voltage ΔV1.

[0057] In this case, the gate voltage of the second U-phase upper-arm switch SUH2, which is the smaller voltage of each switch SUH1 and SUH2, is higher than the gate voltage of the first U-phase upper-arm switch SUH1, which is the larger (higher) voltage. As a result, the on-resistance value of the second U-phase upper-arm switch SUH2 becomes smaller than that of the first U-phase upper-arm switch SUH1. As a result, the recovery current flowing in the second U-phase upper-arm diode DUH2 is larger (higher) than the recovery current flowing in the first U-phase upper-arm diode DUH1.

[0058] Due to a repetition of such an event, the gate voltage of each switch SUH1 and SUH2 oscillates. When the gate voltage oscillates, the gate voltage may exceed the allowable upper gate voltage limit, leading to failure of the switches SUH1 and SUH2.

[0059] According to this embodiment, the characteristic structure of the inverter 30 and the characteristic control of the inverter 30 suppress the occurrence of the gate voltage oscillations and the unbalance of the recovery currents.

[0060] A characteristic structure, as mentioned above, is a structure in which the inductance of the first upper arm path and the second upper arm path are at similar levels, and the inductance of the first sub-arm path and the second sub-arm path are at similar levels.

[0061] The characteristic control is oscillation suppression control, which is described below. When the control device 50 determines that the magnitude of the phase current detected by the current sensor 40 exceeds a threshold current Ith in each phase, the control device 50 performs oscillation suppression control for that phase. Conversely, when the control device 50 determines that the magnitude of the phase current is less than the threshold current Ith, the control device 50 performs normal switching control for the inverter 30. The reason for performing oscillation suppression control when the magnitude of the phase current exceeds the threshold current Ith is to limit the oscillation suppression control to the situation where the degree of imbalance of the recovery currents is large and gate voltage oscillation is likely to occur.The following is an example of a case where the magnitude of the U-phase current among the U, V, and W phases exceeds the threshold current Ith and the oscillation suppression control is performed for the U-phase.

[0062] Fig. Figure 8 shows a phase current IU, a phase current IV, and a phase current IW flowing in the winding 11U, the winding 11V, and the winding 11W, respectively, and the switching modes of the U-phase, the V-phase, and the W-phase. For the phase current IU, the phase current IV, and the phase current IW, the case where the current flows in the direction from the inverter 30 to the winding is defined as positive.

[0063] As it is in Fig. As shown in FIG. 8, the control device 50 switches the switching mode from the L-level mode to the M-level mode at time t1 and from the M-level mode to the H-level mode at time t2. The control device 50 switches from the L-level mode to the H-level mode. In this case, the control device 50 prohibits the execution of the HL dead-time mode and implements the M-level mode during switching.

[0064] Fig. Figure 9 shows the current distribution when the L-level mode is performed before time t1. Fig. 10 shows the current distribution when the L-level mode is switched to the ML dead-time mode from the L-level mode immediately before time t1.

[0065] At time t1, the control device 50 switches from the ML dead time mode to the M level mode. As shown in Fig. As shown in Figure 11, this causes a reverse voltage to be applied to the first U-phase upper arm diode DUL1 and the second U-phase upper arm diode DUL2, after which a recovery current flows in the first U-phase upper arm diode DUL1 and the second U-phase upper arm diode DUL2. In this case, the recovery current flows only in the lower arm among the upper and lower arms. Therefore, the paths including the first U-phase upper arm diode DUH1, the second U-phase upper arm diode DUH2, and the high-potential bus bar 72 are excluded from the distribution path of the recovery current. As a result, the factors that cause variations in the impedance of the two paths through which the recovery current flows are reduced, and the imbalance of the recovery currents is suppressed. This suppresses gate voltage oscillation.

[0066] Fig. Figure 12 shows the current distribution when the M-level mode is executed before time t3. Fig. Figure 13 shows the current flow pattern when the M-level mode is switched to the HM dead-time mode immediately before time t3. It is desirable that the execution time of the HM dead-time mode be set to a longer time than the reverse recovery time of the upper and lower diodes DUH1, DUH2, DUL1, and DUL2.

[0067] At time t3, the control device 50 switches the switching mode from the HM dead time mode to the H-level mode. As shown in Fig. As shown in Figure 14, this causes a reverse voltage to be applied to the first U-phase upper arm diode DUH1 and the second U-phase upper arm diode DUH2, and then a recovery current flows in the first U-phase upper arm diode DUH1 and the second U-phase upper arm diode DUH2. In this case, the recovery current flows only in the upper arm among the upper arm and the lower arm. Therefore, the paths including the first U-phase upper arm diode DUL1, the second U-phase upper arm diode DUL2, and the low-potential bus bar 71 are excluded from the distribution path of the recovery current. As a result, the factors that cause variations in the impedance of the two paths through which the recovery current flows are reduced, and the imbalance of the recovery currents is suppressed. As a result, the oscillation of the gate voltage is suppressed. Fig. Figure 15 shows the current distribution paths after completion of recovery immediately after time t3.

[0068] In contrast, according to a comparative example of the control device that performs the HL dead time mode when switching from the L-level mode to the H-level mode and does not perform the M-level mode during the switching, the recovery current imbalance is larger than in the case of this embodiment. An explanation will be given below of the comparative example of the control device using the Fig. 16 to 20.

[0069] As it is in Fig. 16, the comparative example switches the switching mode from the L-level mode to the H-level mode for the U-phase at time t1 and switches the switching mode from the L-level mode to the H-level mode for the V-phase at time t2.

[0070] Fig. Figure 17 shows the current distribution when the L-level mode is performed before time t1. Fig. Figure 18 shows the current distribution when the L-level mode is switched to the HL dead-time mode immediately before time t1.

[0071] The comparative example switches the switching mode from the HL dead time mode to the H-level mode at time t1. As a result, as shown in Fig. As shown in Figure 19, recovery currents flow in the first U-phase upper-arm diode DUH1, the second U-phase upper-arm diode DUH2, the first U-phase lower-arm diode DUL1, and the second U-phase lower-arm diode DUL2. In this case, the distribution paths of the recovery currents include the paths of both the upper and lower arms. As a result, the factors causing impedance variations in the two paths through which the recovery current flows are not reduced. Fig. Figure 20 shows the current distribution paths after completion of recovery immediately after time t1.

[0072] Fig. Figure 21 shows a flowchart of the switching control of the inverter 30 performed by the control device 50. This switching control is performed in each phase.

[0073] In step S10, the control device 50 determines whether the magnitude of the phase current detected by the current sensor 40 exceeds the threshold current Ith.

[0074] If the control device 50 receives a negative determination result in step S10, the control device 50 proceeds to step S11 and performs the normal switching control of the inverter 30. On the other hand, if the control device 50 receives a positive determination in step S10, the control device 50 proceeds to step S12 and performs the oscillation suppression control, which is carried out using the Fig. 8 to 15.

[0075] As explained above, the M-level mode is realized amidst the switching from the L-level mode to the H-level mode. Specifically, when switching from the L-level mode to the H-level mode, the controller 50 prohibits the execution of the HL dead-time mode and switches the switching mode from the L-level mode to the H-level mode via the ML dead-time mode, the M-level mode, and the HM dead-time mode. This suppresses the imbalance of the recovery currents and gate voltage oscillation. Second embodiment

[0076] A second embodiment will be described below with reference to the drawings, focusing on the differences from the first embodiment. According to the embodiment, as shown in Fig. 22, the execution conditions for the oscillation suppression control are changed. More specifically, in step S13, it is determined whether the command torque Trq* exceeds a torque threshold Trqth. If an affirmative determination result is obtained in step S13, the oscillation suppression control is executed by proceeding to step S12.

[0077] According to the second embodiment, when the command torque Trq* exceeds the torque threshold Trqth, the oscillation suppression control is performed regardless of the magnitude of the phase current. This makes it possible to achieve the same effect as the first embodiment. Third embodiment

[0078] A third embodiment is described below with reference to the drawings, focusing on the differences from the first embodiment. According to this embodiment, the control system has individual current sensors that detect the collector current flowing in each switch. Fig. 23, as an example of the individual current sensors, a first current sensor 42 detects the collector current flowing to the first U-phase upper-arm switch SUH1 and a second current sensor 43 detects the collector current flowing to the second U-phase upper-arm switch SUH2 are provided. The detected values ​​of the current sensors 42 and 43 are input to the control device 50.

[0079] According to the third embodiment, the execution condition of the oscillation suppression control is changed as shown in Fig. 24. More specifically, in step S14, the current difference ΔI, which is the difference between the collector current detected by the first current sensor 42 and the collector current detected by the second current sensor 43, is calculated. The controller 50 determines whether the calculated current difference ΔI exceeds a predetermined current difference Ia (for example, 50 A). If an affirmative determination result is obtained in step S14, the controller 50 proceeds to step S12 and performs the oscillation suppression control.

[0080] For the first U-phase sub-branch switch SUL1 and the second U-phase sub-branch switch SUL2, individual current sensors can be provided in the same way as for the upper branch and the Fig. 24 shown process can be carried out.

[0081] According to the third embodiment, the oscillation suppression control is performed by accurately identifying the situation in which the degree of unbalance of the recovery currents becomes large. Further examples

[0082] The embodiments described above can each be modified as described below.

[0083] In the Fig.23, only one of the first and second current sensors 42 and 43 may be provided as individual current sensors at a position where the phase current flowing through the winding can be detected, for example, in the intermediate bus bar 70. In this case, the collector current flowing in the first U-phase upper arm switch SUH1 and the second U-phase upper arm switch SUH2, which is not provided with an individual current sensor, can be calculated based on the detected values ​​of the first and second current sensors 42 and 43.

[0084] The position of the first U-phase switch SQU1 and the position of the second U-phase switch SQU2 can be reversed, the same applies to the V- and W-phase middle switches.

[0085] The semiconductor switching devices that make up the inverter are not limited to IGBTs, but can be, for example, N-channel MOSFETs with body diodes. In this case, the high-potential terminal of the semiconductor switching element is the drain, and the low-potential terminal is the source. In this case, the middle switch of each phase can consist of two N-channel MOSFETs connected to each other at their sources or drains.

[0086] The three-level inverter can apply either only the characteristic structure that makes the impedance of each branch path at a similar level, or only the characteristic control, which is the oscillation suppression control.

[0087] The number of parallel switch connections for each phase and branch is not limited to two, but can be three or more.

[0088] The motors are not limited to star-connected motors, but can also be delta-connected motors.

[0089] The inverter, motor, and control device are not limited to vehicle mounting, but can also be mounted on mobile objects such as aircraft or ships. The purpose of the inverters, motors, and control devices is not limited to mobile vehicles.

[0090] The control unit and methods described in this disclosure may be implemented by a dedicated computer provided by having a processor and a memory programmed to perform one or more functions embodied in a computer program. Alternatively, the control section and methods described in this disclosure may be implemented by a dedicated computer provided by configuring the processor with one or more dedicated hardware logic circuits.Alternatively, the control section and its methods described in this disclosure may be implemented by one or more dedicated computers provided by a combination of a processor and memory programmed to perform one or more functions, and a processor configured by one or more dedicated hardware logic circuits. The computer program may also be stored in a computer-readable non-transitory recording medium as an instruction to be executed by a computer.

[0091] Described below are characteristic configurations extracted from each of the above-described embodiments. [Configuration 1] ▪ Three-level inverter (30) which has for each phase: a plurality of series circuit elements connected in parallel to one another, each series circuit element comprising: an upper branch switch (SUH1 to SWH2) and a lower branch switch (SUL1 to SWL2) connected in series, an upper arm diode (DUH1 to DWH2) connected in reverse parallel to the upper arm switch, and a sub-branch diode (DUL1 to DWL2) connected in reverse parallel to the sub-branch switch, where the three-level inverter also has: a middle switch (SQU1 to SQW2), a high-potential line element (72) connecting the high-potential terminal of each of the upper-branch switches provided by the plurality of series circuit elements and a positive busbar (31), a low-potential conduction element (71) electrically connecting the low-potential terminal of each of the sub-branch switches provided by the plurality of series circuit elements and a negative bus (32), and an intermediate line element (70) electrically connecting the low-potential terminal of each of the upper-branch switches provided by the plurality of series circuit elements, the high-potential terminal of each of the lower-branch switches provided by the plurality of series circuit elements, and a first end of the middle switch, where the impedances of upper arm paths are configured to be at a similar level, each of the upper arm paths being provided by a respective upper arm diode and providing an electrical path connecting a connection point (72c) of the high potential conduction element and the positive bus to a first end of the middle switch via the respective upper arm diode and the intermediate conduction element, and the impedances of sub-branch paths are configured to be at a similar level, wherein each of the sub-branch paths is provided by a respective sub-branch diode and provides an electrical path connecting a connection point of the low-potential conduction element and the negative bus to the middle switch via the sub-branch diode and the intermediate conduction element. [Configuration 2]

[0092] Three-level inverter according to configuration 1, further comprising a plurality of branch modules (M1, M2), each of the plurality of branch modules corresponding to a corresponding one of the plurality of series circuit elements, and wherein each of the branch modules comprises the respective one of the series connection elements and a first housing (60), and the respective one of the series circuit elements is housed in the first housing as an integrated assembly. [Configuration 3]

[0093] Three-level inverter according to configuration 2, where the middle switch comprises a first switch (SQU1), a first diode (DQU1) connected in reverse parallel to the first switch, a second switch (SQU2) connected in series to the first switch, and a second diode (DQU2) connected in reverse parallel to the second switch, the three-level inverter also has an intermediate module (MM), the intermediate module comprises the first switch, the first diode, the second switch, the second diode and a second housing (60), and the first switch, the first diode, the second switch and the second diode are housed in the second housing as an integrated assembly. [Configuration 4]

[0094] Three-level inverter according to configuration 3, where the three-level inverter has two series connection elements as the plurality of series connection elements for each phase, the shape of each of the two first housings and the second housing is flat rectangular, the two branch modules have the same specification, the intermediate module is positioned between the two branch modules, wherein the intermediate module and the two branch modules are arranged in a thickness direction of the first housing and the second housing, a terminal installation surface (62) of each of the two first housings and the second housing faces in a common direction, on each of the terminal installation surfaces of each of the two first housings, an external high-potential terminal (CP) connected to the high-potential terminal of the upper-branch switch, an electrical low-potential terminal (CN) electrically connected to the low-potential terminal of the lower-branch switch, and an external intermediate terminal (CO) electrically connected to the low-potential terminal of the upper-branch switch and the high-potential terminal of the lower-branch switch are installed, a neutral point terminal (CN2) electrically connected to the second switch is installed on the terminal installation surface of the second housing, the external intermediate terminals and the neutral point terminal are arranged in a thickness direction of the two first housings and the second housing, the external high-potential terminals are arranged in the thickness direction, the external low-potential terminals are arranged in the thickness direction, the high-potential line element connects the two external high-potential terminals, the low-potential conduction element electrically connects the two external low-potential terminals, the intermediate line element connects the external intermediate terminals and the neutral point terminal, and the shapes of each of the high-potential conduction element, the low-potential conduction element, and the intermediate conduction element are symmetrical about a reference axis (BL) passing through the center of the thickness direction of the second housing in a front view of the terminal installation surface of the second housing. [Configuration 5]

[0095] Three-level inverter according to one of the configurations 1 to 4, where the middle switch comprises a first switch (SQU1), a first diode (DQU1) connected in reverse parallel to the first switch, a second switch (SQU2) connected in series to the first switch, and a second diode (DQU2) connected in reverse parallel to the second switch, the three-level inverter further comprises a control device (50) which switches switching modes between an H-level mode, an M-level mode and an L-level mode, and a performs oscillation suppression control to realize the M-level mode during switching from the L-level mode to the H-level mode, the H-level mode is a switching mode in which the upper branch switch is turned on and the lower branch switch is turned off to output an H-level voltage, the M-level mode is a switching mode in which the first switch and the second switch are turned on and the upper branch switch and the lower branch switch are turned off to output an M-level voltage, and the L-level mode is a switching mode in which the lower branch switch is turned on and the upper branch switch is turned off to output an L-level voltage. [Configuration 6]

[0096] Three-level inverter according to configuration 5, where the oscillation suppression control includes prohibiting an HL dead time mode, which is a switching mode in which the upper branch switch, the lower branch switch, the first switch, and the second switch are turned off, and switching the switching mode from the L-level mode to the H-level mode via the M-level mode and the HM dead time mode, the HM dead time mode is a switching mode in which the upper branch switch, the lower branch switch and the second switch are turned off and the first switch is turned on, the execution time of the HM dead time mode is set to a longer time than the reverse recovery time of the upper arm diode and the lower arm diode. [Configuration 7]

[0097] Three-level inverter according to configuration 5, where the control device performs the oscillation suppression control when specified conditions are met, and the specific conditions are one of: the magnitude of the output current of the three-level inverter exceeds a threshold current (Ith), the magnitude of a command torque of the motor electrically connected to the three-level inverter exceeds a torque threshold (Trqth), the difference in the magnitude of the currents flowing between the high-potential terminal and the low-potential terminal of each of the parallel-connected upper-branch switches exceeds a specified current difference (Ia), the difference in the magnitude of the currents flowing between the high-potential terminal and the low-potential terminal of each of the parallel-connected sub-branch switches exceeds a predetermined current difference (Ia). [Configuration 8]

[0098] Three-level inverter according to one of the configurations 1 to 4, further with, for each phase: a first capacitor (21) electrically connecting the second end of the middle switch and the positive bus, and a second capacitor (22) electrically connecting the second end of the middle switch and the negative bus. [Configuration 9]

[0099] Three-level inverter (30) which has for each phase: a plurality of series circuit elements connected in parallel to one another, each series circuit element comprising: an upper branch switch (SUH1 to SWH2) and a lower branch switch (SUL1 to SWL2) connected in series, an upper arm diode (DUH1 to DWH2) connected in reverse parallel to the upper arm switch, and a sub-branch diode (DUL1 to DWL2) connected in reverse parallel to the sub-branch switch, where the three-level inverter also has: a middle switch (SQU1 to SQW2), a high-potential line element (72) connecting the high-potential terminal of each of the upper-branch switches provided by the plurality of series circuit elements and a positive busbar (31), a low-potential conduction element (71) electrically connecting the low-potential terminal of each of the sub-branch switches provided by the plurality of series circuit elements and a negative bus (32), an intermediate line element (70) electrically connecting the low-potential terminal of each of the upper-branch switches provided by the plurality of series circuit elements, the high-potential terminal of each of the lower-branch switches provided by the plurality of series circuit elements, and a first end of the middle switch, and a control device (50), wherein the middle switch comprises a first switch (SQU1), a first diode (DQU1) connected in reverse parallel to the first switch, a second switch (SQU2) connected in series to the first switch, and a second diode (DQU2) connected in reverse parallel to the second switch, and the control device switches switching modes between an H-level mode, an M-level mode, and an L-level mode, and performs oscillation suppression control to realize the M-level mode during switching from the L-level mode to the H-level mode, the H-level mode is a switching mode in which the upper branch switch is turned on and the lower branch switch is turned off to output an H-level voltage, the M-level mode is a switching mode in which the first switch and the second switch are turned on and the upper branch switch and the lower branch switch are turned off to output an M-level voltage, and the L-level mode is a switching mode in which the lower branch switch is turned on and the upper branch switch is turned off to output an L-level voltage. [Configuration 10]

[0100] Program applied to a three-level inverter (30) having for each phase: a plurality of series circuit elements connected in parallel to one another, each series circuit element comprising: an upper branch switch (SUH1 to SWH2) and a lower branch switch (SUL1 to SWL2) connected in series, an upper arm diode (DUH1 to DWH2) connected in reverse parallel to the upper arm switch, and a sub-branch diode (DUL1 to DWL2) connected in reverse parallel to the sub-branch switch, where the three-level inverter also has: a middle switch (SQU1 to SQW2), a high-potential line element (72) connecting the high-potential terminal of each of the upper-branch switches provided by the plurality of series circuit elements and a positive busbar (31), a low-potential conduction element (71) electrically connecting the low-potential terminal of each of the sub-branch switches provided by the plurality of series circuit elements and a negative bus (32), an intermediate line element (70) electrically connecting the low-potential terminal of each of the upper-branch switches provided by the plurality of series circuit elements, the high-potential terminal of each of the lower-branch switches provided by the plurality of series circuit elements, and a first end of the middle switch, and a control device (50), wherein the middle switch comprises a first switch (SQU1), a first diode (DQU1) connected in reverse parallel to the first switch, a second switch (SQU2) connected in series to the first switch, and a second diode (DQU2) connected in reverse parallel to the second switch, and the program causes the control device to switch switching modes between an H-level mode, an M-level mode, and an L-level mode, and performs oscillation suppression control to realize the M-level mode during switching from the L-level mode to the H-level mode, the H-level mode is a switching mode in which the upper branch switch is turned on and the lower branch switch is turned off to output an H-level voltage, the M-level mode is a switching mode in which the first switch and the second switch are turned on and the upper branch switch and the lower branch switch are turned off to output an M-level voltage, and the L-level mode is a switching mode in which the lower branch switch is turned on and the upper branch switch is turned off to output an L-level voltage.

[0101] Although this disclosure has been described according to examples, it should be understood that this disclosure is not limited to the examples or structures. The present disclosure also encompasses various variations and transformations within the scope of equivalence. In addition, various combinations and forms, as well as other combinations and forms including only one element thereof, are within the scope and spirit of this disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2022-210644

[0001] JP 2004 - 15 910 A1

[0004]

Claims

[1] Three-level inverter (30) having for each phase: a plurality of series circuit elements connected in parallel to one another, each series circuit element comprising: an upper branch switch (SUH1 to SWH2) and a lower branch switch (SUL1 to SWL2) connected in series, an upper arm diode (DUH1 to DWH2) connected in reverse parallel to the upper arm switch, and a sub-branch diode (DUL1 to DWL2) connected in reverse parallel to the sub-branch switch, where the three-level inverter also has: a middle switch (SQU1 to SQW2), a high-potential line element (72) connecting the high-potential terminal of each of the upper-branch switches provided by the plurality of series circuit elements and a positive busbar (31), a low-potential conduction element (71) electrically connecting the low-potential terminal of each of the sub-branch switches provided by the plurality of series circuit elements and a negative bus (32), and an intermediate line element (70) electrically connecting the low-potential terminal of each of the upper-branch switches provided by the plurality of series circuit elements, the high-potential terminal of each of the lower-branch switches provided by the plurality of series circuit elements, and a first end of the middle switch, wherein the impedances of upper arm paths are configured to be at a similar level, each of the upper arm paths being provided by a respective upper arm diode and providing an electrical path connecting a connection point (72c) of the high potential conduction element and the positive bus to a first end of the middle switch via the respective upper arm diode and the intermediate conduction element, and the impedances of sub-branch paths are configured to be at a similar level, wherein each of the sub-branch paths is provided by a respective sub-branch diode and provides an electrical path connecting a connection point of the low-potential conduction element and the negative bus to the middle switch via the sub-branch diode and the intermediate conduction element. [2] Three-level inverter according to claim 1, further comprising a plurality of branch modules (M1, M2), each of the plurality of branch modules corresponding to a corresponding one of the plurality of series circuit elements, and wherein each of the branch modules comprises the respective one of the series connection elements and a first housing (60), and the respective one of the series circuit elements is housed in the first housing as an integrated assembly. [3] Three-level inverter according to claim 2, wherein the middle switch comprises a first switch (SQU1), a first diode (DQU1) connected in reverse parallel to the first switch, a second switch (SQU2) connected in series to the first switch, and a second diode (DQU2) connected in reverse parallel to the second switch, the three-level inverter also has an intermediate module (MM), the intermediate module comprises the first switch, the first diode, the second switch, the second diode and a second housing (60), and the first switch, the first diode, the second switch and the second diode are housed in the second housing as an integrated assembly. [4] Three-level inverter according to claim 3, wherein the three-level inverter has two series connection elements as the plurality of series connection elements for each phase, the shape of each of the two first housings and the second housing is flat rectangular, the two branch modules have the same specification, the intermediate module is positioned between the two branch modules, wherein the intermediate module and the two branch modules are arranged in a thickness direction of the first housing and the second housing, a terminal installation surface (62) of each of the two first housings and the second housing faces in a common direction, on each of the terminal installation surfaces of each of the two first housings, an external high-potential terminal (CP) connected to the high-potential terminal of the upper-branch switch, an electrical low-potential terminal (CN) electrically connected to the low-potential terminal of the lower-branch switch, and an external intermediate terminal (CO) electrically connected to the low-potential terminal of the upper-branch switch and the high-potential terminal of the lower-branch switch are installed, a neutral point terminal (CN2) electrically connected to the second switch is installed on the terminal installation surface of the second housing, the external intermediate terminals and the neutral point terminal are arranged in a thickness direction of the two first housings and the second housing, the external high-potential terminals are arranged in the thickness direction, the external low-potential terminals are arranged in the thickness direction, the high-potential line element connects the two external high-potential terminals, the low-potential conduction element electrically connects the two external low-potential terminals, the intermediate line element connects the external intermediate terminals and the neutral point terminal, and the shapes of each of the high-potential conduction element, the low-potential conduction element, and the intermediate conduction element are symmetrical about a reference axis (BL) passing through the center of the thickness direction of the second housing in a front view of the terminal installation surface of the second housing. [5] Three-level inverter according to one of claims 1 to 4, wherein the middle switch comprises a first switch (SQU1), a first diode (DQU1) connected in reverse parallel to the first switch, a second switch (SQU2) connected in series to the first switch, and a second diode (DQU2) connected in reverse parallel to the second switch, the three-level inverter further comprises a control device (50) that switches switching modes between an H-level mode, an M-level mode and an L-level mode, and performs oscillation suppression control to realize the M-level mode during switching from the L-level mode to the H-level mode, the H-level mode is a switching mode in which the upper branch switch is turned on and the lower branch switch is turned off to output an H-level voltage, the M-level mode is a switching mode in which the first switch and the second switch are turned on and the upper branch switch and the lower branch switch are turned off to output an M-level voltage, and the L-level mode is a switching mode in which the lower branch switch is turned on and the upper branch switch is turned off to output an L-level voltage. [6] Three-level inverter according to claim 5, wherein the oscillation suppression control includes prohibiting an HL dead time mode, which is a switching mode in which the upper branch switch, the lower branch switch, the first switch, and the second switch are turned off, and switching the switching mode from the L-level mode to the H-level mode via the M-level mode and the HM dead time mode, the HM dead time mode is a switching mode in which the upper branch switch, the lower branch switch and the second switch are turned off and the first switch is turned on, the execution time of the HM dead time mode is set to a longer time than the reverse recovery time of the upper arm diode and the lower arm diode. [7] Three-level inverter according to claim 5, wherein the control device performs the oscillation suppression control when specified conditions are met, and the specific conditions are one of: the magnitude of the output current of the three-level inverter exceeds a threshold current (Ith), the magnitude of a command torque of the motor electrically connected to the three-level inverter exceeds a torque threshold (Trqth), the difference in the magnitude of the currents flowing between the high-potential terminal and the low-potential terminal of each of the parallel-connected upper-branch switches exceeds a specified current difference (Ia), the difference in the magnitude of the currents flowing between the high-potential terminal and the low-potential terminal of each of the parallel-connected sub-branch switches exceeds a predetermined current difference (Ia). [8] Three-level inverter according to one of claims 1 to 4, further comprising, for each phase: a first capacitor (21) electrically connecting the second end of the middle switch and the positive bus, and a second capacitor (22) electrically connecting the second end of the middle switch and the negative bus. [9] Three-level inverter (30) having for each phase: a plurality of series circuit elements connected in parallel to one another, each series circuit element comprising: an upper branch switch (SUH1 to SWH2) and a lower branch switch (SUL1 to SWL2) connected in series, an upper arm diode (DUH1 to DWH2) connected in reverse parallel to the upper arm switch, and a sub-branch diode (DUL1 to DWL2) connected in reverse parallel to the sub-branch switch, where the three-level inverter also has: a middle switch (SQU1 to SQW2), a high-potential line element (72) connecting the high-potential terminal of each of the upper-branch switches provided by the plurality of series circuit elements and a positive busbar (31), a low-potential conduction element (71) electrically connecting the low-potential terminal of each of the sub-branch switches provided by the plurality of series circuit elements and a negative bus (32), an intermediate line element (70) electrically connecting the low-potential terminal of each of the upper-branch switches provided by the plurality of series circuit elements, the high-potential terminal of each of the lower-branch switches provided by the plurality of series circuit elements, and a first end of the middle switch, and a control device (50), wherein the middle switch comprises a first switch (SQU1), a first diode (DQU1) connected in reverse parallel to the first switch, a second switch (SQU2) connected in series to the first switch, and a second diode (DQU2) connected in reverse parallel to the second switch, and the control device switches switching modes between an H-level mode, an M-level mode, and an L-level mode, and performs oscillation suppression control to realize the M-level mode during switching from the L-level mode to the H-level mode, the H-level mode is a switching mode in which the upper branch switch is turned on and the lower branch switch is turned off to output an H-level voltage, the M-level mode is a switching mode in which the first switch and the second switch are turned on and the upper branch switch and the lower branch switch are turned off to output an M-level voltage, and the L-level mode is a switching mode in which the lower branch switch is turned on and the upper branch switch is turned off to output an L-level voltage. [10] Program applied to a three-level inverter (30) having for each phase: a plurality of series circuit elements connected in parallel to one another, each series circuit element comprising: an upper branch switch (SUH1 to SWH2) and a lower branch switch (SUL1 to SWL2) connected in series, an upper arm diode (DUH1 to DWH2) connected in reverse parallel to the upper arm switch, and a sub-branch diode (DUL1 to DWL2) connected in reverse parallel to the sub-branch switch, where the three-level inverter also has: a middle switch (SQU1 to SQW2), a high-potential line element (72) connecting the high-potential terminal of each of the upper-branch switches provided by the plurality of series circuit elements and a positive busbar (31), a low-potential conduction element (71) electrically connecting the low-potential terminal of each of the sub-branch switches provided by the plurality of series circuit elements and a negative bus (32), an intermediate line element (70) electrically connecting the low-potential terminal of each of the upper-branch switches provided by the plurality of series circuit elements, the high-potential terminal of each of the lower-branch switches provided by the plurality of series circuit elements, and a first end of the middle switch, and a control device (50), wherein the middle switch comprises a first switch (SQU1), a first diode (DQU1) connected in reverse parallel to the first switch, a second switch (SQU2) connected in series to the first switch, and a second diode (DQU2) connected in reverse parallel to the second switch, and the program causes the control device to switch switching modes between an H-level mode, an M-level mode, and an L-level mode, and performs oscillation suppression control to realize the M-level mode during switching from the L-level mode to the H-level mode, the H-level mode is a switching mode in which the upper branch switch is turned on and the lower branch switch is turned off to output an H-level voltage, the M-level mode is a switching mode in which the first switch and the second switch are turned on and the upper branch switch and the lower branch switch are turned off to output an M-level voltage, and the L-level mode is a switching mode in which the lower branch switch is turned on and the upper branch switch is turned off to output an L-level voltage.

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