Computing system with state-based FSM control architecture

Abstract

Computing system for the explainable, transparent and modularly reconfigurable execution of arithmetic-logical operations, characterized in that the system comprises a plurality of logically completely decoupled computing units, wherein each computing unit is realized by a dedicated module with a deterministic finite state machine (FSM), each FSM exactly maps a defined computing operation, only one FSM module is active at a time at runtime, and each computing execution is carried out step by step, explicitly comprehensible and visually evaluable, wherein no purely combinatorial logic is used and the system is operated entirely on reconfigurable digital hardware.

Description

1. Technical area

[0001] The invention relates to computing circuits, in particular arithmetic logic units (ALUs), as used in a wide variety of applications, including safety-critical systems such as those in aviation and automotive engineering, embedded real-time controls in industrial automation, explainable artificial intelligence (XAI) in medical diagnostics or decision support, and in digital teaching for teaching computing architectures. The invention also offers practical advantages in the development and simulation of reconfigurable logic platforms (e.g., FPGAs) and in formal verification technology. In the context of the present invention, a finite state machine (FSM) refers to a deterministic logical control unit that runs through a defined sequence of states.Reconfigurable digital hardware refers specifically to field-programmable gate arrays (FPGAs), which provide flexible and programmable logic structures. Digital interfaces include standardized protocols such as UART, SPI, and USB for communication with external systems. 2. State of the art

[0002] Classic ALUs are mostly based on combinational logic, in which arithmetic operations such as addition, subtraction, or multiplication are performed using logical operations without intermediate storage of states. This architecture offers high speed but only limited traceability of individual calculation steps. This particularly complicates debugging, formal verification, and applicability in explainable and safety-critical systems.

[0003] There is therefore a need for computing systems that enable transparent, step-by-step execution of operations with explicit state management, for example for applications in explainable artificial intelligence (XAI), in safety-critical environments (e.g., aviation, automotive), in teaching, and in the prototypical development of reconfigurable logic systems. 3. Object of the invention

[0004] The aim of the invention is to provide an arithmetic logic unit that overcomes classic problems such as the difficulty of tracing individual calculation steps, particularly in safety-critical applications or in the context of formal verification. For example, debugging in conventional ALUs is problematic if, in the case of erroneous output, it is not possible to determine at which intermediate step an error occurred. Likewise, in areas such as machine learning with safety-relevant decision logic, it is necessary to be able to precisely document each processing step.

[0005] These challenges are to be solved by a stateful architecture in which each individual computational operation is implemented by its own, explicitly defined, deterministic state machine (FSM). The architecture is to be modular, easily extensible and reconfigurable, and enable the step-by-step execution and monitoring of computational processes. 4. Solution according to the invention

[0006] The invention comprises a computing system for executing arithmetic-logical operations, in which each operation is implemented by a separate module with a deterministically executed finite state machine (FSM). Each FSM module has a clearly defined state sequence, each of which describes exactly one arithmetic operation.

[0007] The modules are logically separated from each other, with only one module active at a time. The selection and activation of an FSM module can be achieved through various mechanisms, such as binary control data, switches, serial commands, or hardware-based control logic, such as clock and control signals.

[0008] The system allows the output of current states, which is particularly advantageous for real-time debugging, simulating complex computing processes, or for educational purposes, allowing the calculation steps to remain traceable during execution. Output can be provided via serial interfaces (e.g., UART) or via external digital display units, which visualize the internal states of the FSM modules for observation and analysis.

[0009] Implementation is preferably carried out in reconfigurable hardware, for example, on commercially available FPGA platforms such as Lattice iCE40UPSk, Xilinx Artix-7, or Intel MAX 10 (e.g., FPGA), with each operation integrated as a logically separable control unit. The architecture allows for easy expansion with new FSM modules without modifying existing ones.

[0010] As an alternative to sequentially activating a single FSM module, the computing system can also be designed so that multiple FSM modules are activated and executed in parallel. Synchronous or independent processing can occur, for example, to increase throughput or to simultaneously execute different computing operations in separate logical channels. The architecture can include centralized or distributed control logic to avoid conflicts between modules.

[0011] For interaction and observation of FSM states and intermediate results, the system supports various digital interfaces, including serial protocols such as UART, SPI, or USB, as well as external graphical output systems directly connected to the digital hardware. These interfaces are bidirectional and enable both the transmission of control commands and the reception and display of real-time data. This enables flexible integration into various development and test environments.

[0012] The control architecture is primarily hardware-based and uses FSM modules for deterministic state control. Software can also be used, for example, for runtime configuration, diagnostics, interface connection, or supporting control. However, there is no time-critical or complete implementation of the FSM logic in software.

[0013] It should be noted that software as a mere program sequence cannot be protected by a utility model, since utility models protect technical devices or devices. The present invention is therefore limited to a hardware-based FSM architecture, in which software is used only supplementarily for non-time-critical tasks such as configuration or diagnostics. Computer-implemented inventions with a technical focus, however, can be protected by patents, especially if they solve technical problems or control devices. 5. Advantages of the invention • Traceability: State-based execution makes calculation steps explicitly traceable. Each step is clearly defined and allows for a clear analysis of the calculation process. • Modularity: Each arithmetic-logical operation is represented by a separate FSM module. These modules are logically separated from each other and can be used independently. • Flexibility: The modules can be activated by various mechanisms, e.g. by binary control data, manual switches, external digital signals or hardware-connected input channels for controlling the logic functions. • Expandability: New FSMs can be integrated into the system without changing existing modules. This simplifies maintenance and allows for the gradual expansion of functionality. • Traceability: Explicit state output enables precise debugging, formal verification, and educational use. State sequences can be documented internally or output externally. • Hardware suitability: The system is optimized for reconfigurable digital logic (e.g. FPGAs) and can be implemented on common platforms such as iCE40UP5k or Xilinx Artix-7. • Parallelizability: The architecture allows for the simultaneous execution of multiple FSM modules if necessary, for example, to increase processing capacity or to simulate complex processes with multiple processing units. Synchronous or independent parallelism expands the application possibilities in high-performance or real-time scenarios. • Interface flexibility: System status output and control can be achieved through various digital channels, including UART, USB, SPI, or external graphical display units that reflect the hardware state. This facilitates debugging, real-time monitoring, and integration with modern development tools. 6. Example

[0014] Each computational operation in the system is implemented by a dedicated FSM (finite-state machine) module. The FSM consists of a finite set of states connected by well-defined transitions. These transitions occur depending on input values ​​and control signals such as start, clk (clock), and rst (reset). • IDLE state: The FSM waits for the activation signal start. In this state, all outputs are inactive, and internal registers are in a defined sleep mode. • LOAD state: The input values ​​(e.g., operands a and b) are accepted. Internal registers and control bits, such as the carry register, are initialized to ensure a defined starting state for the calculation. • CALCULATION states: The actual arithmetic-logic operation is executed step by step over several clock cycles. For example, in addition, the bits of a and b are processed sequentially, taking carries into account. Each calculation step corresponds to a unique state transition, which means the entire calculation is explicitly mapped into the state sequence. • DONE state: After the calculation is complete, the result is sent to the result output port. The done signal is activated to indicate the completion of the operation. The FSM then returns to the IDLE state, ready for the next activation.

[0015] Explicit control via defined states makes all computational steps transparent and traceable. The states can be output in real time via serial interfaces (e.g., UART) or external graphical output systems. This traceability is particularly important for applications in explainable artificial intelligence (XAI), formal verification, and safety-critical and certification-relevant systems. 7. Drawing explanation

[0016] Fig. 1 shows a computing system with modular FSM-based computing units that are activated and controlled via a central control logic.

[0017] The system includes: • an input register (to hold the operands), • a central control logic for interpreting the multi-bit opcode and for the targeted activation of an FSM module (e.g. fsm_add, fsm_sub, fsm_mul, fsm_mod), • several dedicated FSM modules, each performing an arithmetic-logical operation as a finite state machine, • and an output register that holds the result of the operation.

[0018] The FSMs are implemented logically separately from each other. Upon activation, the FSM control module coordinates the execution using a defined start sequence. Upon completion, the active FSM module signals the completion of the calculation with a "done" signal, after which the result is transferred to the output register.

[0019] Communication with external systems takes place via a digital interface (e.g. UART, SPI or USB), which is used for both configuration and status transmission.

[0020] The architecture allows for easy expansion with additional FSM modules (e.g., fsm_cmp, fsm_not, fsm_shift, fsm_collatz) without changing the existing control logic. Clear state management supports real-time output and enables transparent traceability of the calculation steps. OPCode Module name function 000 fsm_add addition 001 fsm_sub subtraction 010 fsm_mul multiplication 011 fsm_div division 100 fsm_mod Modulo 101 fsm_and Bitwise AND 110 fsm_or Bitwise OR

[0021] The OP codes are interpreted by the control logic, which then activates the corresponding FSM module. The FSM modules process the arithmetic operation deterministically and statefully, as described in Section 6. 8. Areas of application

[0022] The computing system is fully deterministic: Each computational step is governed by well-defined state transitions within a finite state machine (FSM). Due to the clear state definitions, the system is model-checkable, which enables formal verification of the execution logic, especially in safety-critical applications. • Explainable Hardware (XAI) • Digital learning systems • Embedded security & auditing • Symbolic computational analysis • FPGA prototyping (open source) • Post-quantum cryptography • Certifiable systems (ISO 26262 / DO-254) • Neuro-symbolic AI systems (Edge AI) 9. Implementation Note

[0023] A complete Verilog prototype is available. The FSMs are integrated modularly and can be activated via a central control module. Operation is via serial interfaces (e.g., UART) or external digital display units that visualize the sequence of FSM states in real time.

Claims

[1] Computing system for the explainable, transparent and modularly reconfigurable execution of arithmetic-logical operations, characterized by that the system comprises a large number of logically completely decoupled computing units, whereby each computing unit is implemented by a dedicated module with a deterministic finite state machine (FSM), each FSM exactly maps a defined computing operation, only one FSM module is active at a time, and each calculation is executed step by step, explicitly comprehensible and visually analyzable, whereby no purely combinatorial logic is used and the system is operated entirely on reconfigurable digital hardware. [2] Computing system according to claim 1, characterized by that each FSM module has its own, logically isolated state domain, which can be addressed, read out and visually displayed at runtime via a digital interface. [3] Computing system according to one of the preceding claims, characterized by that the internal state transition logic of the FSM modules is output in real time via a digital interface, whereby the interface can be open or proprietary, in particular UART, SPI or USB, and that the state data can be visualised via external systems, in particular graphical user interfaces. [4] Computing system according to one of the preceding claims, characterized by that the FSM modules can be reconfigured, replaced or expanded during operation without affecting the state of other FSM modules or the central control logic. [5] Computing system according to one of the preceding claims, characterized by that the control architecture interprets a multi-bit control word (opcode) to activate individual FSM modules, which is introduced via an external interface or generated by a central control logic. [6] Computing system according to one of the preceding claims, characterized by that in an alternative operating mode, several FSM modules can be activated in parallel, with their execution being either synchronized or independent of each other and the parallel execution being explicitly configurable and actively managed by the control architecture. [7] Computing system according to one of the preceding claims, characterized by that the state outputs of the FSM modules are intended for didactic, explainable or formal analytical purposes, in particular for application in areas such as explainable artificial intelligence (XAI), digital teaching, formal verification, security analysis or embedded certification, in particular according to standards such as ISO 26262 or DO-254. [8] Computing system according to one of the preceding claims, characterized bythat the entire architecture is fully implemented in reconfigurable digital hardware, in particular on FPGA platforms such as Lattice iCE40, Xilinx Artix or Intel MAX 10, and that the system is designed for time-critical applications with transparent execution. [9] Computing system according to one of the preceding claims, characterized by that new FSM modules can be dynamically registered at runtime and integrated into the control logic without interrupting the system or losing existing states.

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