SOLAR CELL

Description

[0001] The present invention relates to a solar cell produced by a method for producing a solar cell having a heterojunction, a front side provided for light incidence, and a back side located opposite the front side, the method comprising the following steps: providing a crystalline semiconductor substrate of a first conductivity type; forming at least one first amorphous, nano- and / or microcrystalline semiconductor layer or layer sequence on a front surface of the semiconductor substrate, either forming a front-side emitter of a second conductivity type opposite to the first conductivity type or forming a front-side surface field layer of the first conductivity type;Forming at least one second amorphous, nano- and / or microcrystalline semiconductor layer or layer sequence on a rear surface of the semiconductor substrate, either forming a rear surface field layer of the first conductivity type or forming a rear emitter of the second conductivity type; Forming at least one electrically conductive, transparent front electrode layer on the front emitter or the front surface field layer and forming at least one electrically conductive, transparent back electrode layer on the rear surface field layer or the rear emitter; Forming a front metallic contact layer grid structure for electrically contacting the front emitter or the front surface field layer;front-side PECVD deposition of an electrically non-conductive, transparent dielectric front-side cap layer after forming the front-side contact layer grid structure; and forming a back-side metallization on the back-side electrode layer.;

[0002] To form a contact layer grid structure, such as a silver finger structure as a collecting electrode, on a transparent dielectric front and / or back cover layer, such as a transparent conductive oxide (TCO) layer, of a solar cell, the prior art typically applies the silver fingers using electroplating technology with a mask, which is subsequently removed. The masking material, as well as the steps associated with its application and removal, are costly and can adversely affect the solar cell's characteristics.

[0003] Another problem with solar cells with exposed TCO coatings is that they can experience significant performance degradation under the influence of moisture, especially at elevated temperatures. The (electro)chemical decomposition or corrosion of the TCO layer that occurs under the influence of moisture leads to an increase in the series resistance (RS) and a subsequent degradation of the fill factor (FF) of the solar cell. The conversion efficiency of the solar cell (ETA) drops significantly. So-called bifacial solar cells with exposed TCO on both sides are particularly susceptible to such corrosion phenomena. However, the invention is also applicable to solar cells with monofacial TCO coatings.

[0004] To protect the TCO surface from corrosion, an insulating layer, such as a silicon oxide, silicon nitride, or silicon oxynitride layer, can be applied to the TCO. However, this layer must be removed again where the TCO layer is to be electrically contacted by the contact layer grid structure or the contact fingers, or it may not be deposited in these areas at all. For this purpose, a masking technology is typically used, or the dielectric layer deposited over the metallization is locally opened by laser ablation or masked etching in order to print metal structures or create them by plating. However, this has the disadvantage that opening the hermetic dielectric layer creates potential leak paths for later moisture penetration.

[0005] In order to form an insulator coating on the TCO and yet be able to make suitable electrical contact with the TCO in a technologically simple manner, EP 2 662 900 A1 proposes dispensing with the masking and forming the contact layer lattice structure from a first electrically conductive layer made of a material with a low melting point and a second electrically conductive layer. For this purpose, the first electrically conductive layer comprising the material with the low melting point is applied to a transparent dielectric front-side covering layer (TCO layer), an insulator layer is deposited over the entire surface, the first electrically conductive layer is melted by heating, and the insulator layer is thereby ruptured above the first conductive layer.The bursting process creates cracks in the insulating layer, into which the subsequently deposited second electrically conductive layer can penetrate and establish electrical contact with the first electrically conductive layer and thus with the TCO layer.

[0006] With this technology, it is unavoidable to form the first conductive layer only at the future contact points and to heat it only there. Therefore, at least one structured deposition or structuring is required here as well. Furthermore, the problem of how to achieve local heating is faced, and attempts must be made to keep the thermal stress on the solar cells during this heating step as low as possible to avoid negatively impacting the solar cell characteristics. WO 2014 / 192739 A1 discloses a method for producing a solar cell in which an existing contact structure is covered with a metal mask during the deposition of an insulating layer, so that the insulating layer is not deposited on the contact structure.

[0007] It is therefore the object of the present invention to provide a solar cell that, in a truly simple and efficient manner, ensures both the formation of suitable moisture protection for the TCO layer(s) of the solar cell and a simple, high-quality electrical contacting of the solar cell that does not negatively affect the solar cell properties. The invention is defined in claim 1.

[0008] Such a solar cell can be produced according to the invention by a method of the above-mentioned type, in which a surface-selective PECVD deposition is used for the deposition of the front-side covering layer and the front-side covering layer is deposited with such a thickness that the front-side covering layer forms a closed layer directly after its layer deposition, without additional heat and / or chemical treatment only on the areas surrounding the front-side contact layer lattice structure, but not on the front-side contact layer lattice structure.

[0009] Surprisingly, it has been found that, during PECVD deposition, the front-side covering layer is initially deposited only on the electrically conductive, transparent front-side electrode layer and not, or only minimally, on the contact layer grid structure, thus depositing it surface-selectively. This allows the front-side covering layer to be deposited even after the contact layer grid structure has already been formed, without the need for subsequent etching of the front-side covering layer from the contact layer grid structure. Thus, the solar cell can be fully metallized, and then the moisture-barrier, electrically non-conductive, transparent dielectric front-side covering layer can be deposited over the entire solar cell, sealing the front-side electrode layer.

[0010] Such surface selectivity during deposition cannot be achieved with other layer deposition processes, such as atomic layer deposition (ALD), sputtering or vapor deposition processes.

[0011] In the present invention, SiO / N layer(s), for example, are considered as the front-side covering layer, which are already commonly used as anti-reflective and passivation layers in solar cells. Moisture-affine AlO x layers, on the other hand, are less suitable as a front-side covering layer, but can be advantageously used, for example, as the upper layer of a front-side covering layer consisting of a silicon oxide and an aluminum oxide layer for moisture absorption and thus as a moisture barrier layer against the underlying silicon oxide layer.

[0012] The PECVD process, which is used according to the invention to form the front-side covering layer, also has the advantage that it works in the low-temperature range, i.e. at temperatures ≤ 200 °C, which makes the process according to the invention particularly suitable for use in temperature-sensitive solar cells, such as heterojunction solar cells with amorphous, nano- and / or microcrystalline silicon surface passivation layers.

[0013] According to one embodiment of the present invention, such a moisture barrier can also be provided on the back of the solar cell.The formation of the backside metallization comprises the following steps: forming a backside metallic contact layer grid structure for electrically contacting the backside emitter or the backside surface field layer; backside PECVD deposition of an electrically non-conductive, transparent dielectric backside cover layer after formation of the backside contact layer grid structure; wherein a surface-selective PECVD deposition is used for the deposition of the backside cover layer and the backside cover layer is deposited with such a thickness that the backside cover layer forms a closed layer directly after its layer deposition, without additional heat and / or chemical treatment, only on the regions surrounding the backside contact layer grid structure, but not on the backside contact layer grid structure.

[0014] Thus, the process can also be applied to bifacial solar cells, such as bifacial heterojunction back-emitter solar cells.

[0015] The front-side and / or rear-side contact layer grid structure can initially be formed as a seed layer structure, which is subsequently reinforced. For this purpose, one variant of the method provides for at least one front-side metallic contact thickness reinforcement layer to be galvanically deposited on the front-side contact layer grid structure using the material of the front-side cover layer as a galvanic masking layer without prior structuring and / or without at least partial removal of the front-side cover layer, and / or for at least one rear-side metallic contact thickness reinforcement layer to be galvanically deposited on the rear-side contact layer grid structure using the material of the rear-side cover layer as a galvanic masking layer without prior structuring and / or at least partial removal of the rear-side cover layer.

[0016] The front and / or rear contact layer grid structure is first applied as a seed layer or seed structure, a very thin metallization structure, for example, in the form of fingers or busbars, to the surface of the electrically conductive, transparent front and / or rear electrode layer, such as by printing and annealing. A paste, such as a silver paste, can be used as the material for the seed structure.

[0017] After the seed structure has been applied, the front and / or back cover layer is deposited onto the respective solar cell side(s) using PECVD deposition. As explained above, during this PECVD deposition, the seed structure is not coated or not coated over its entire surface. This allows the seed structure to be reinforced, for example, by electroplating after the deposition of the front and / or back cover layer, without having to remove the layer from the seed structure. The LIP (Light Induced Plating) process, for example, can be used for electroplating reinforcement. Silver, but also copper, can be considered as the material for the contact thickness reinforcement layer. The metallic contact thickness reinforcement layer, which is preferably but not exclusively produced by electroplating, adheres very well to the seed structure in this embodiment of the process and increases its electrical conductivity.

[0018] This variant of the process has the advantage that no SiON layer needs to be additionally deposited as a galvanic mask, since the front and / or back cover layer surrounding the seed structure, lying on the electrically conductive, transparent front and / or back electrode layer, already takes over the mask function.

[0019] Furthermore, this process can achieve better cell efficiency. This makes it possible to make the electrically conductive, transparent front and / or back electrode layer, which is, for example, an ITO layer, thinner or to replace a large part of the thickness of the front and / or back electrode layer with the front and / or back cover layer, i.e., a Si-ON layer. This makes the anti-reflective layer of the solar cell more transparent. The optics of the solar cell can be significantly improved both in the UV range, where absorption is reduced by a thinner TCO layer, and in the infrared range. Furthermore, using ITO (indium tin oxide) as the front and / or back electrode layer saves indium.

[0020] Furthermore, this variant of the process for producing the contact layer grid structure saves the silver paste used while still achieving very good electrical conductivity of the contact fingers of the contact layer grid structure. This process is suitable for module interconnections with and without busbars without risking additional efficiency losses. Despite the overcoating used according to the invention, the contact layer grid structure offers good contactability and / or solderability.

[0021] The front and back cover layers of the present invention are therefore multifunctional. They can be used as anti-reflective or anti-reflection coating(s), as corrosion protection or sealing coating(s), and / or as mask(s) for galvanic reinforcement of contact seed structures.

[0022] In expedient embodiments of the present invention, the front-side metallic contact layer grid structure is / are solidified by annealing before the deposition of the front-side cover layer and / or the back-side metallic contact layer grid structure is / are solidified by annealing before the deposition of the back-side cover layer.

[0023] It is particularly effective if the formation of the front-side covering layer and the back-side covering layer takes place immediately one after the other in one processing process in the same coating device.

[0024] Microwave-assisted PECVD deposition for producing the transparent dielectric front-side covering layer and / or the transparent dielectric back-side covering layer has proven to be particularly gentle. Alternatively, in the present invention, the PECVD deposition for producing the transparent dielectric front-side covering layer and / or the transparent dielectric back-side covering layer can be an HF (high-frequency) PECVD, a VHF (ultra-high frequency) PECVD, or a PECVD using an ETP (expanding thermal plasma) source. In principle, however, hotwire CVD can also be used instead of PECVD for producing the transparent dielectric front-side covering layer and / or the transparent dielectric back-side covering layer.

[0025] Preferably, at least one SiO x , SiN x , SiO x N y , AlO x , AlN x , TiO 2 layer, at least one electrically conductive oxide or a layer or layer sequence consisting of a combination of at least two of the aforementioned materials is used for the deposition of the front-side covering layer and / or the back-side covering layer.

[0026] Particularly preferably, at least one SiO x layer is used for the deposition of the front-side covering layer and / or at least one SiN x layer is used for the deposition of the back-side covering layer. For example, an SiO 2 layer with a thickness in the range of 70 to 100 nm can be applied to the front of the solar cell as the front-side covering layer, and / or an SiN x layer with a thickness in the range of 80 to 120 nm can be applied to the back of the solar cell as the back-side covering layer.

[0027] In an optional embodiment of the process, the front-side cover layer and / or the back-side cover layer is / are at least partially doped with carbon during deposition. For example, tetramethylsilane can be added to the silane chemistry used. Carbon doping can, for example, reduce the wet etching rate or chemical vulnerability of the front-side cover layer and / or the back-side cover layer.

[0028] Preferably, the front-side cover layer and / or the back-side cover layer are deposited at the lowest possible temperatures, i.e., in a temperature range between 50 °C and 250 °C, particularly preferably at temperatures ≤ 200 °C. The brief additional temperature application, for example, from 150 °C to 200 °C for 2 to 3 minutes, during PECVD improves the conductivity of the contact fingers and their contacting on the TCO. This results in a slight increase in the fill factor FF of the solar cell, for example, by +0.5%, and in the conversion efficiency ETA of the solar cell, for example, by +0.2%.

[0029] For the formation of the front-side and / or rear-side contact layer grid structure and the at least one front-side and / or at least one rear-side contact thickness reinforcement layer, at least one electrically conductive oxide, at least one metal, at least one metallic alloy or a combination of at least two of the aforementioned materials can advantageously be used.

[0030] For the formation of the front-side and / or the rear-side contact layer grid structure and the at least one front-side and / or the at least one rear-side contact thickness reinforcement layer, a material is preferably selected in the method which consists predominantly, i.e. more than 50%, of silver or copper.

[0031] It is particularly useful if the front and / or back contact layer grid structure is / are printed as a finger structure using a paste.

[0032] Preferably, transparent, electrically conductive oxide, i.e. a TCO layer, such as an ITO layer, is used in the method for forming the front-side electrode layer and / or the back-side electrode layer.

[0033] To achieve particularly effective cell protection against corrosion, it is recommended that the front-side covering layer be applied completely over the entire front side, including covering the edges of the semiconductor substrate, and / or that the back-side covering layer be applied completely over the entire back side, including covering the edges of the semiconductor substrate. The resulting complete, seamless, hermetic sealing of the already metallized TCO surfaces of the solar cell, including the wafer edge, effectively prevents moisture attack on the TCO at both the module and cell levels. The result is no or very minimal TCO degradation.

[0034] Such coverage, encompassing the edge of the semiconductor substrate, can only be achieved if a suitable substrate carrier is used. Therefore, a substrate carrier with a plate-shaped carrier grid is proposed, which has at least one hollow carrier nest surrounded by a nest frame for receiving a flat semiconductor substrate. Retaining hooks project into the carrier nest from all sides of the nest frame, and at least one retaining pin is provided on each retaining hook, which is aligned parallel to a surface of the semiconductor substrate to be received.

[0035] Preferably, the support grid has at least two adjacent support nests separated by a frame beam of the nest frame, and the retaining hooks are provided on retaining brackets fastened to the frame beam and projecting into one of the support nests on each side of the frame beam.

[0036] Preferred embodiments of the present invention, their course or structure, function and advantages are explained in more detail below with reference to figures, wherein Figures 1 to 3 schematically show a process sequence used to produce a solar cell according to the invention; Figure 4 schematically shows a plan view of an embodiment of a substrate carrier; and Figure 5 schematically shows a cross-section of a frame beam with a holding bracket of a substrate carrier, wherein two semiconductor substrates are schematically indicated resting on holding pins of the holding bracket.

[0037] As shown by Figure 1 As can be seen, the method initially provides at least one semiconductor substrate 2. The semiconductor substrate 2 is of a first conductivity type, i.e., it can be n- or p-doped. Typically, but not necessarily, the semiconductor substrate 2 is formed from n-doped silicon.

[0038] On both sides of the semiconductor substrate 2 there are Figure 1 In the embodiment shown, intrinsic amorphous semiconductor layers 3, 4, in the example shown, ia-Si layers a few nanometers thick, are provided. Instead of or in addition to the intrinsic amorphous semiconductor layers 3, 4, intrinsic nano- and / or microcrystalline semiconductor layers, for example made of silicon, can also be used in other embodiments of the present invention.

[0039] Electrically conductive amorphous doped semiconductor layers 5, 6 are provided on the intrinsic amorphous semiconductor layers 3, 4. Instead of or in addition to the amorphous doped semiconductor layers 5, 6, nano- and / or microcrystalline doped semiconductor layers, for example made of silicon, can also be used in other embodiments of the present invention. Figure 1In the embodiment shown, a p-doped amorphous silicon layer 5, which thus has a conductivity type opposite to that of the semiconductor substrate 2, is provided on the intrinsic amorphous silicon layer 3 located on the semiconductor front side, forming a front-side emitter. Furthermore, in the embodiment shown in Figure 1 In the embodiment shown, an n-doped amorphous silicon layer 6, which thus has the same conductivity type as the semiconductor substrate 2, is provided on the intrinsic amorphous silicon layer 5 located on the semiconductor backside, forming a backside surface field layer.

[0040] In other embodiments of the present invention not shown, a front surface field layer may also be provided on the front side of the semiconductor substrate 2 and a back emitter may be provided on the back side of the semiconductor substrate 2.

[0041] In the example of Figure 1An electrically conductive, transparent front-side electrode layer 7, which in the embodiment shown is a TCO layer, such as an ITO layer, is provided on the front-side emitter. Furthermore, an electrically conductive, transparent back-side electrode layer 8, which in the embodiment shown is a TCO layer, such as an ITO layer, is also provided on the back-side surface field layer.

[0042] In addition, a front-side metallic contact layer grid structure 9 is provided on the front-side electrode layer 7 for electrically contacting the front-side emitter, and a rear-side metallic contact layer grid structure 10 is provided on the rear-side electrode layer 8 for electrically contacting the rear-side surface field layer. In the illustrated embodiment, the front-side and rear-side metallic contact layer grid structures 9, 10 are thin, printed, finger-shaped silver seed structures.

[0043] As it is in Figure 2 can be seen, in a subsequent process step the entire surface is covered with Figure 1In the structure shown, an electrically non-conductive, transparent dielectric front-side covering layer 11 is deposited using a PECVD deposition. The front-side covering layer 11 is deposited only on the areas surrounding the contact layer grid structure 9, i.e., on the front-side electrode layer 7, but not, or only minimally, on the contact layer grid structure 9 itself.

[0044] Furthermore, on the back of the Figure 1 In the structure shown, an electrically non-conductive, transparent dielectric backside covering layer 12 is deposited using a PECVD deposition. The backside covering layer 12 is deposited only on the areas surrounding the contact layer grid structure 10, i.e., on the backside electrode layer 8, but not, or only minimally, on the contact layer grid structure 10 itself.

[0045] This means that there is an undisturbed layer growth of the front and back cover layers 11, 12 on the TCO of the front and back electrode layers 7, 8, respectively, but no or only slight growth on the silver paste fingers of the contact layer grid structures 9 and 10, respectively. This can be referred to as a self-aligned PECVD deposition.

[0046] The formation of the front-side covering layer 11 takes place completely over the entire front side, including the coverage 11' of the edges of the semiconductor substrate 2, and the formation of the back-side covering layer 12 takes place completely over the entire back side, including the coverage 12' of the edges of the semiconductor substrate 2. The coverages 11', 12' of the edges of the semiconductor substrate 2 run approximately wedge-shaped, starting from the front side 15 and the back side 16 of the semiconductor substrate 2, respectively, and can be adjacent to one another or overlap one another.

[0047] After deposition of the front-side covering layer 11, as in Figure 3 shown, a front-side metallic contact thickness reinforcement layer 13 is galvanically deposited onto the front-side contact layer grid structure 9 using the material of the front-side cover layer 11 as a galvanic masking layer without prior structuring and / or at least partial removal of the front-side cover layer 11. In addition, after deposition of the rear-side cover layer 12, as also in Figure 3As can be seen, a rear metallic contact thickness reinforcement layer 14 is galvanically deposited onto the rear contact layer grid structure 10 using the material of the rear cover layer 12 as a galvanic masking layer without prior structuring and / or at least partial removal of the rear cover layer 12. The contact thickness reinforcement layer 13 or 14 typically grows slightly laterally beyond the contact layer grid structure 9 or 10 used as the seed layer during electroplating.

[0048] The result is the schematically Figure 3 solar cell 1 shown in cross section with a front side 15 intended for light incidence and a back side 16 located opposite the front side 15.

[0049] The solar cell 1 produced using the method described above can be electrically contacted equally well before and after coating with the front and back cover layers 11, 12. The sealing layer formed by the front and back cover layers 11, 12 remains completely intact and does not need to be subsequently opened locally to establish electrical contact between the front-side contact layer lattice structure 9 and the associated contact thickness reinforcement layer 13, as well as between the back-side contact layer lattice structure 10 and the associated contact thickness reinforcement layer 14.

[0050] To form the front and back cover layers 11, 12, the present invention preferably uses SiO x and / or SiN x layers, which are optically transparent and, when optimal layer thicknesses are selected, even improve the anti-reflective properties of the solar cell 1. Thus, the double ARC function, such as that provided by TCO and SiO 2 , increases the short-circuit current I SC and the conversion efficiency ETA of the solar cell.

[0051] In principle, the steps for sealing TCO layers of the method according to the invention can also be applied to thin-film modules.

[0052] Figure 4shows a schematic plan view of an embodiment of a substrate carrier 17. The substrate carrier 17 is a so-called wafer carrier, which has a carrier grid 18 with several carrier nests 19 arranged in rows and columns. Each carrier nest 19 is surrounded by frame beams 22 forming a nest frame. The carrier nests 19 each serve to accommodate a flat semiconductor substrate 2.

[0053] From all sides of the nest frame, retaining hooks 20, which are attached to the frame beams 22 or connected to them in one piece, project downwards into the support nest 19. As shown in Figure 5As can be seen, a retaining pin 21 is provided on each retaining hook 20, which is aligned parallel to a surface 25 of the semiconductor substrate 2 to be accommodated. The semiconductor substrate 2 is placed in the carrier nest 19 in such a way that it is held on the retaining hooks 20 extending from each of the frame beams 22 surrounding the carrier nest 19, wherein the semiconductor substrate 2 rests on the retaining pins 21 in each case.

[0054] As it is in Figure 4 As can be seen, the support grid 18 has a plurality of adjacent support nests 19, each separated by a frame beam 22 of the nest frame. In these support nests 19, retaining brackets 24 with at least one retaining element 23 are fastened to the frame beams 22 in such a way that the retaining hooks 20 located on the retaining brackets 24, with the retaining pins 21 provided thereon, protrude into one of the support nests 19.

Claims

1. Solar cell (1) with a heterojunction, a front side (15) provided for an incident of light and a back side (16) located opposite the front side (15), comprising: - a crystalline semiconductor substrate (2) of a first conductivity type; - at least one amorphous, nano and / or microcrystalline semiconductor layer or layer sequence (3, 5) on a frontal surface of the semiconductor substrate (2), forming either a front side emitter of a second conductivity type opposite to the first conductivity type or a front side surface field layer of the first conductivity type; - at least one second amorphous, nano and / or micro crystalline semiconductor layer or layer sequence (4, 6) on a rearward surface of the semiconductor substrate (2), forming either a back side surface field layer of the first conductivity type or a back side emitter of the second conductivity type; - at least one electrically conductive, transparent front side electrode layer (7) on the front side emitter or the front side surface field layer and at least one electrically conductive, transparent back side electrode layer (8) on the back side surface field layer or the back side emitter; - a frontal metallic contact layer grid structure (9) for electrically contacting the front side emitter or the front side surface field layer; - an electrically non-conductive, transparent dielectric front side cover layer (11) deposited by PECVD deposition on its frontal face after forming the frontal contact layer grid structure (9); and - a back side metallization on the back side electrode layer (8); characterized in that, a surface selective PECVD deposition or a Hotwire-CVD is used for the deposition of the front side cover layer (11) and the front side cover layer (11) is deposited with such a thickness that the front side cover layer (11) forms a closed layer directly after its layer deposition, without additional heat and / or chemical treatment, only on the areas surrounding the frontal contact layer grid structure (9), but not on the frontal contact layer grid structure (9), wherein the electrically conductive, transparent front-side electrode layer (7) is a TCO layer; for the formation of the front side contact layer grid structure (9), a material is selected which consists predominantly of silver or copper and is printed as a finger structure using a paste; for the deposition of the front side cover layer (11) at least one SiOx, SiNx, SiOxNy layer or a layer or layer sequence consisting of a combination of at least two of the aforementioned materials is used; the front side cover layer (11) is deposited using a silane chemistry; and the front side cover layer (11) is deposited in a temperature range between 50°C and 250°C.

2. Solar cell according to claim 1, characterized in that the front side covering layer (11) is formed completely over the entire front side, including a covering (11') of the edges of the semiconductor substrate (2).

3. Solar cell according to claim 1 or 2, characterized in that a back side covering layer (12) is formed completely over the entire back side, including a covering (12') of the edges of the semiconductor substrate (2).

4. Solar cell according to claims 2 and 3, characterized in that the coverings (11', 12') of the edges of the semiconductor substrate (2) extend in a wedge shape starting from the front side (15) or the back side (16) of the semiconductor substrate (2).

5. Solar cell according to claim 4, characterized in that the coverings (11', 12') of the edges of the semiconductor substrate (2) adjoin one another or cover one another.

6. Solar cell according to one of the preceding claims, characterized in that the front side cover layer (11) and / or the back side cover layer (12) is / are at least partially doped with carbon during deposition.