Semiconductor component and method for uniting a semiconductor component with a PN junction

Description

[0001] The invention relates to a semiconductor component according to claim 1 and to a method for singulating a semiconductor component with a pn junction according to claim 6.

[0002] When manufacturing semiconductor components, it is often desirable to separate several semiconductor components produced on a substrate by separating the substrate along at least one separating surface, so that the semiconductor components are separated. This type of separation is necessary in the manufacture of computer processors, as a large number of computer processors are typically manufactured on a silicon wafer. In addition, the separation of photovoltaic solar cells is becoming increasingly common: Photovoltaic modules are now usually made from silicon solar cells with an edge length of approximately 156 mm. The interconnection is achieved by electrically conductive connections using conductive elements - usually so-called cell connectors - which alternately connect the solar cells on the front and back. A disadvantage of this interconnection is that the high current (up to approximately10 A) of the individual solar cells require a very high conductivity and thus high cable cross-sections of the cell connectors.

[0003] A known way to circumvent this disadvantage is to place two or more solar cells on a silicon wafer, thereby proportionally reducing the current per solar cell. These cells are separated only at the end of the processing to ensure the longevity of the large starting wafers, thus maintaining high productivity and allowing the use of established production equipment.

[0004] If the solar cells continue to be electrically connected using cell connectors as described above, space remains between the solar cells that is not photovoltaically active and therefore leads to a reduction in the module efficiency.

[0005] A well-known method to circumvent this disadvantage is the so-called shingling of solar cells, in which the top of one end of a solar cell is directly electrically connected to the underside of the next cell. For this purpose, the external contacts are implemented on the front and back, on the opposite edges of the solar cells. Since, in order to minimize shading, there are usually no very highly conductive contact elements in the solar cell and the distances through which the current must flow in the contact fingers to the external contacts become very large for the shingling concept based on large conventional solar cells, the silicon wafers are cut into narrow strips after the solar cells have been processed, thus creating several photovoltaic solar cells with a typically rectangular shape in order to minimize power losses in the finger contacts of the solar cell during shingling.

[0006] The singulation of semiconductor components manufactured on a substrate, particularly a silicon wafer, leads to an increase in the perimeter-to-area ratio and thus to an increase in area-normalized power losses due to edge recombination. Studies have shown (J. Dicker, "Analysis and Simulation of Highly Efficient Silicon Solar Cell Structures for Industrial Manufacturing Technologies," dissertation, University of Konstanz, 2003) that the area where a pn junction meets a separation surface, where singulation occurred, leads to power losses. One reason for this is edge recombination in the quasi-neutral regions of the emitter and base, and, as previously described, particularly in the space charge region. In addition, the separation of the singulated semiconductor components at the generated edges leads to a significant increase in the recombination rate itself.This influence is particularly relevant if the semiconductor component has a high electronic quality on the other surfaces, in particular a lower recombination rate due to passivation layers or other passivation mechanisms.

[0007] There is therefore a need to isolate semiconductor components without significantly reducing the electronic quality of the semiconductor component through the separation surface, in particular through recombination effects at the separation surface.

[0008] It is known that, in silicon solar cells, a silicon dioxide layer grown natively at the edge of the cell interface reduces the negative impact at low illumination levels (M. Hermle, J. Dicker, W. Warta, SW Glunz, and G. Willeke, "Analysis of edge recombination for high-efficiency solar cells at low illumination densities," 2003, pp. 1009-1012). However, this only results in a slight improvement for silicon solar cells under standard illumination. Nico Wöhrle et al., "Solar cell demand for bifacial and singulated-cell module architectures," Photovoltaics International, Vol. 36, June 16, 2017, pages 48-62, discloses solar cell modules formed with strip-like solar cells, which are obtained by singulating the solar cells starting from a solar cell substrate.

[0009] The present invention is therefore based on the object of providing a semiconductor component and a method for separating a semiconductor component, so that a negative influence of the separation surface on the electronic quality is reduced.

[0010] This object is achieved by a semiconductor component according to claim 1 and a method according to claim 6. Advantageous embodiments can be found in the dependent claims.

[0011] The method according to the invention is preferably designed for producing a semiconductor component according to the invention, in particular a preferred embodiment thereof. The semiconductor component according to the invention is preferably formed by means of the method according to the invention, in particular a preferred embodiment thereof.

[0012] The semiconductor component according to the invention has a front side and an opposite rear side, as well as side surfaces. Furthermore, the semiconductor component has at least one emitter and at least one base, with a pn junction formed between the emitter and the base. The emitter extends parallel to the front and / or rear side. The semiconductor component is designed as a photovoltaic solar cell. The emitter can be designed in a conventional manner.

[0013] In particular, emitters produced by diffusion and / or implantation as well as heteroemitters and epitaxially produced emitters are within the scope of the invention.

[0014] It is essential that at least one side surface is a separation surface on which an separation surface passivation layer is arranged. The separation surface passivation layer has stationary charges with a surface charge density of greater than or equal to 10 12< cm -2<. The surface charge density can thus be electrically positive or negative. It is essential that the surface charge density is greater than or equal to 10 12< cm -2<, i.e., for a positive charge, it is greater than or equal to 10 12< cm -2< and for a negative charge, it is less than or equal to -1×10 12< cm -2<.

[0015] The invention is based on the finding that the negative effects occurring at an interface can be particularly efficiently reduced by an interface passivation layer with a surface charge density of ≥ 10 12< cm -2<. Passivation layers that reduce the surface recombination rate of charge carriers are known in semiconductor components, and in particular in photovoltaic solar cells. However, investigations by the applicant show that the negative effects at the interface are particularly efficiently reduced by the interface passivation layer described above. This is primarily due to the fact that stationary charges in the interface passivation layer prevent charge carriers in the semiconductor component, in particular a silicon layer of the semiconductor component, from reaching the interface.Particularly in the case of a silicon layer, these are kept away from the separation surface up to a depth of approximately 20 nm into the silicon. This has the advantage that near-surface damage to the separation surface caused by the separation process is tolerable up to a depth of approximately 20 nm. Mechanical separation is generally not possible without damaging several atomic layers of the surface of the semiconductor volume. However, it can be limited to a depth of less than 20 nm by selecting a suitable process. The process is therefore advantageously carried out so that the separation is carried out using one of the following processes: TLS, LIC, or LDC, since these processes have a comparatively low damage depth.

[0016] Advantageously, the interface passivation layer covers at least the area in which the pn junction borders the interface.

[0017] A particularly advantageous passivation of the separating surface is achieved in that, in an advantageous embodiment, the separating surface passivation layer extends over the entire separating surface.

[0018] The semiconductor component according to the invention has the advantage that, due to the passivation of the interface by the interface passivation layer, the area of ​​the semiconductor component can be used efficiently, allowing the emitter to reach the interface. In particular, previously known methods for avoiding negative influences of an interface, which involve insulation by means of insulation trenches and / or spacing the pn junction from the interface by forming emitter windows, are not necessary, or at least not absolutely necessary. While the positive effect can be enhanced by not extending the pn junction directly to the interface, a slight spacing is sufficient for such an enhancement. According to the invention, the pn junction borders the interface. This results in a simplified manufacturing process.

[0019] The interface passivation layer is preferably formed as a dielectric layer, in particular as an aluminum oxide layer, a silicon nitride layer, or a silicon oxynitride layer. These layers can be produced in a conventional manner and provided with high surface charge densities. In particular, it is within the scope of the invention to form the interface passivation layer using one of the following methods: CVD (see below); ALD (see below); printing technologies, in particular printing by screen printing, inkjet, extrusion or dispenser; spray coating; application of layer material to the parting surface using a medium;

[0020] The semiconductor component is designed as a photovoltaic solar cell. Especially in photovoltaic solar cells, long lifetimes of minority charge carriers in the emitter and base are necessary for high efficiencies, so the passivation of an interface is particularly relevant here.

[0021] Advantageously, the semiconductor component is therefore designed as a photovoltaic solar cell, which has at least one silicon layer in which at least the base is formed. It is within the scope of the invention for both the emitter and the base to be formed in the silicon layer. Likewise, the arrangement of a separate layer, in particular a separate silicon layer, for forming the emitter on the base is within the scope of the invention.

[0022] Advantageously, the separation of the semiconductor component at the separation surface occurs in such a way that a damage zone with a shallow depth is created. In particular, it is advantageous for the semiconductor component to have a damage zone at the separation surface with a charge carrier lifetime of < 1 µs, at least in the base, wherein the damage zone has a thickness of < 20 nm perpendicular to the separation surface. In particular, it is advantageous for the charge carrier lifetime to have a charge carrier lifetime of > 10 µs, at least in the base in an area adjacent to the damage zone, as is common in photovoltaic solar cells.

[0023] The method according to the invention for singulating a semiconductor component with a pn junction has the following method steps: In a method step A, a semiconductor component is provided which has at least one emitter and at least one base, wherein a pn junction is formed between the emitter and the base.

[0024] In a method step B, the semiconductor component is singulated by separating it into at least two sub-elements at at least one separation surface. In method step B, the singulation takes place such that the pn junction is adjacent to the separation surface, wherein a passivating layer is applied to a front and / or a rear side of the semiconductor component prior to method step B, and wherein one or more metallic contact structures are applied to a front and / or a rear side of the semiconductor component prior to method step B, wherein the semiconductor component is formed as a photovoltaic solar cell.

[0025] It is essential that, after process step B, an interface passivation layer is applied to the interface, which is formed with a surface charge density greater than or equal to 10 12< cm -2<. This results in the advantages mentioned in the description of the semiconductor component according to the invention.

[0026] The interface passivation layer is preferably designed to cover the entire interface in order to achieve the most efficient possible reduction of the negative influences of the interface on the electronic quality of the semiconductor component.

[0027] It is within the scope of the invention to carry out the singulation in process step B by separating the semiconductor component using a method known per se. The singulation of the semiconductor component in process step B can thus be carried out in a manner known per se, in particular by means of one or more of the methods described below: a) Chip sawing (WP Mulligan, A. Terao, DD Smith, PJ Verlinden, and RM Swanson, "Development of chip-size silicon solar cells", in Proceedings of the 28th IEEE Photovoltaic Specialists Conference, Anchorage, USA, 2000, pp. 158-163); b) Laser trenching followed by mechanical breaking (M. Oswald, M. Turek, J. Schneider, and S. Schönfelder, "Evaluation of silicon solar cell separation techniques for advanced module concepts", in Proceedings of the 28th European Photovoltaic Solar Energy Conference and Exhibition, Paris, France, 2013, pp. 1807-1812); c) Thermal Laser Separation (TLS): M. Oswald, M. Turek, J. Schneider, and S. Schönfelder, "Evaluation of silicon solar cell separation techniques for advanced module concepts", in Proceedings of the 28th European Photovoltaic Solar Energy Conference and Exhibition, Paris, France, 2013, pp. 1807-1812; S. Eiternick, F. Kaule, H.-U. Zühlke, T. Kießling, M. Grimm, S. Schoenfelder, and M.Turek, "High quality half-cell processing using thermal laser separation", Energy Procedia, vol. 77, pp. 340-345, 2015. d) Laser induced Cutting (LIC): S. Weinhold, A. Gruner, R. Ebert, J. Schille, and H. Exner, "Study of fast laser induced cutting of silicon materials", in Proc. SPIE 8967, Laser Applications in Microelectronic and Optoelectronic Manufacturing (LAMOM), San Francisco, USA, 2014, 89671J. .

[0028] Studies show that it is particularly advantageous to perform the singulation in process step B using TLS or LIC. The TLS process is based on the creation of a short laser trench using a first laser beam, which then leads to a separation of the wafer based on simultaneous heating (e.g., using a second laser beam) and cooling (e.g., using an air-water mixture) along the edge to be created in any direction by means of introduced thermomechanical stress. This makes it possible, in particular, to create a separation surface independent of the crystal orientation of the wafer to be separated. The LIC process is very similar to the TLS process, although in LIC there is no active cooling following the heating (e.g., using a laser beam). The LIC process is also known as the LDC process (Laser Direct Cleaving).

[0029] The method according to the invention has the particular advantage that the singulation can take place after completion or at least substantial completion of the semiconductor component. According to the invention, a passivating layer is therefore applied to a front and / or back side of the semiconductor component before process step B. According to the invention, one or more metallic contact structures for supplying and / or removing charge carriers are applied to a front and / or back side of the semiconductor component before process step B.

[0030] In order to improve the passivation quality of the interface passivation layer, it is advantageous that after application of the interface passivation layer, a temperature treatment of the interface passivation layer takes place, in particular heating to a temperature greater than or equal to 150 °C for a period of at least 1 minute.

[0031] To improve the passivation quality, it may also be advantageous to carry out this in a defined atmosphere, especially in a hydrogen-containing atmosphere.

[0032] The thermal treatment can be performed globally by heating the entire semiconductor component. In an advantageous embodiment, the thermal treatment of the interface passivation layer is performed by successive local heating, in particular by means of a laser. In this case, local subregions of the interface passivation layer are heated one after the other, particularly preferably, as mentioned above, in a hydrogen-containing atmosphere.

[0033] As described above, the method according to the invention is particularly advantageous for singulating photovoltaic solar cells. The semiconductor component is therefore designed as a photovoltaic solar cell; in particular, at least the base is preferably formed in a silicon layer.

[0034] In a further advantageous embodiment, the interface passivation layer is additionally formed on at least the front or at least the back of the semiconductor component. This has the advantage that the interface passivation layer can additionally be used with a further function on the front and / or back. In particular, when the semiconductor component is designed as a photovoltaic solar cell, applying the interface passivation layer to the side facing the incident radiation when the solar cell is used, in particular the front, as a further optical layer can increase the light coupling in the solar module. In the method according to the invention, the interface passivation layer is therefore preferably formed additionally on the front and / or back of the semiconductor component, in particular during production of the interface passivation layer on the interface.

[0035] In particular, it is advantageous that, as described above, a passivating layer is applied to at least one side of the semiconductor component, and the interface passivation layer is applied to the passivating layer and to the interface to be passivated. In particular, it is advantageous to additionally form the passivating layer as a charge carrier barrier layer. This prevents the formation of stationary charges in the interface passivation layer at the surface where the interface passivation layer covers the charge carrier barrier layer. This is because the charge carrier barrier layer acts as a tunnel barrier; no charge carriers from the semiconductor can penetrate into the interface passivation layer, and thus the interface passivation layer cannot form stationary charges.Advantageously, the charge carrier barrier layer is formed as a dielectric layer, in particular as a silicon nitride layer, silicon oxide layer, silicon oxynitride layer or aluminum oxide layer.

[0036] A further advantage of the present method is that the separation surface does not necessarily have to be parallel to a preferred direction in which a semiconductor substrate of the semiconductor component has the weakest bonds. In single-crystal silicon wafers, fracture typically results in a fracture line at a 45° angle to an edge of the silicon wafer, since weaker bonds exist in this direction due to the crystal orientation. However, the present method allows for separation surfaces at any angle, in particular separation surfaces parallel to an edge of the silicon wafer.

[0037] Preferably, the separation surface is therefore parallel to an edge of the semiconductor component, in particular, a silicon wafer of the semiconductor component.

[0038] Further advantageous features and embodiments of the present invention are explained below with reference to exemplary embodiments and the figures. Herein: Figure 1 shows two embodiments of semiconductor components according to the invention and partial steps of two embodiments of methods according to the invention, and Figure 2 shows a plan view from above of a semiconductor wafer to illustrate the position of the separating surfaces.

[0039] The figures are schematic representations, not to scale. In particular, the widths and thicknesses of the individual layers do not correspond to the actual dimensions for clarity.

[0040] In Figure 1Two embodiments A and B are shown, each with partial steps of an embodiment of a method according to the invention. In Figure 1a , iii is a first embodiment of a semiconductor component according to the invention and in Figure 1b , iii shows a second embodiment of a semiconductor component according to the invention. The semiconductor component is designed as a photovoltaic solar cell.

[0041] Based on the Figure 1aThe first exemplary embodiment of a method according to the invention is explained using the sub-steps shown: In a method step A, the semiconductor component 1a is provided. In the present case, this has an emitter 2a of the n-doping type formed by diffusion from the gas phase and correspondingly a base 3a which is doped with a dopant of the p-doping type. Accordingly, a pn junction 4a forms between the emitter 2a and the base 3a. The emitter and base were formed in a silicon wafer. Furthermore, additional, known components of a solar cell have already been produced: This includes passivation layers on the upper front side and on the lower back side, metallization structures on the front and back sides for dissipating charge carriers, and anti-reflective layers on the front side and optionally back side to increase light absorption.In a modification of the exemplary embodiment, the emitter is formed by diffusion from a pre-applied doping layer or by implantation. Likewise, the doping types of the emitter and base can be interchanged.

[0042] Subsequently, in a process step B, the previously described TLS process is used to separate the parts by separating them at the separating surface T. The separating surface T is perpendicular to the drawing surface in Figure 1 and thus penetrates the base 3a and emitter 2a.

[0043] The TLS process is carried out starting from the back side, i.e., first, an initial trench is formed using a laser on the underlying back side in the area where the separation line T intersects the back side. The initial trench begins at an edge of the semiconductor component. The initial trench does not extend across the entire width of the semiconductor component. Typical initial trenches have a length in the range of 200 µm to 4 mm, typically less than 2 mm. Subsequently, the semiconductor component is separated as described above by simultaneous heating and cooling. In a modification of the exemplary embodiment, the TLS process is carried out starting from the front side, so that the solar cell does not have to be rotated during the process.

[0044] The result is in Figure 1a, ii: Thus, two mirror-image symmetrical semiconductor components are produced, each having a pn junction 4a adjacent to the separation surface T.

[0045] After process step B, an interface passivation layer 6a is formed on the interface T. The formation takes place by means of industry-typical chemical vapor deposition (CVD) or, in a modification, by means of atomic layer deposition (ALD).

[0046] The interface passivation layer 6a thus extends over the entire interface T. The interface passivation layer is formed as an aluminum oxide layer with a surface charge density of ≥ 10 12< cm -2< , in this case -3×10 12< cm -2< at the interface to the interface T and has a thickness of a few atomic layers over a few nm up to several 10 nm, in this case 6 nm.

[0047] In Figure 1b A second embodiment of a method according to the invention is shown. To avoid repetition, only the essential differences are discussed below: The semiconductor component 1b also has an emitter 2b and a base 3b, so that a pn junction 4b is formed between the emitter and the base. However, between the method steps A and B as described above, that is to say in particular before the singulation, a cross-conduction avoidance region 5b is formed in a method step B0. As in Figure 1b, iAs can be seen, a cross-conduction avoidance region 5b, designed as a separation trench, is formed by laser ablation. This region completely penetrates the emitter 2b and the pn junction 4b. This prevents cross-conduction of charge carriers through the emitter to the separation surface T, thus further reducing the negative influence of the separation surface, which reduces the electronic quality of the semiconductor component.

[0048] As in Figure 1b, 2ii As can be seen, analogously to the first embodiment, the semiconductor component is then separated and thus isolated at the separation surface T. In this embodiment, the separation is carried out using the LIC method described above.

[0049] As in Figure 1b, 3iiiAs can be seen, the interface passivation layer 6b is then applied. In the present case, this is formed as an aluminum oxide layer with a surface charge density of greater than or equal to 10 12< cm -2< , in the present case approximately -3×10 12< cm -2< at the interface to the base and emitter, and has a thickness of a few atomic layers, ranging from a few nm to several tens of nm, in the present case 6 nm. The interface passivation layer 6b was produced by ALD. As a result, it is formed not only at the interface T, but also on the walls of the cross-conduction avoidance region 5b, which is designed as a separation trench.

[0050] In Figure 1 For the sake of clarity, only one dividing surface is shown.

[0051] When singulating photovoltaic solar cells, for example to form modules according to the shingling technique mentioned above, a plurality of solar cells are usually singulated starting from a silicon wafer.

[0052] In Figure 2 This is a schematic top view of a silicon wafer in which photovoltaic solar cells have been formed. One of the previously described processes is performed at several, in this case four, separation surfaces T, so that after separation, five semiconductor components are obtained. List of reference symbols

[0053] 1a, 1bSemiconductor component 2a, 2bEmitter 3a, 3bBase 4a, 4bpn junction 5bCross-conduction avoidance region 6a, 6bInterface passivation layer TTeparation area

Claims

1. Semiconductor component (1a, 1b) with: a front side and an opposite back side as well as side faces, as well as at least one emitter (2a, 2b) and at least one base (3a, 3b), wherein a pn junction (4a, 4b) is formed between the emitter (2a, 2b) and base (3a, 3b) and the emitter (2a, 2b) extends parallel to the front side and / or back side, wherein the pn junction (4a, 4b) is adjacent to the separating surface (T) and the semiconductor component (1a, 1b) is formed as a photovoltaic solar cell, characterized in that at least one side face is a passivated separating surface (T) on which a separating surface passivation layer (6a, 6b) is arranged which has fixed charges with a surface charge density at the separating surface (T) which is greater than or equal to 1012cm-2, the pn junction (4a, 4b) being adjacent to the passivated separating surface (T).

2. Semiconductor component (1a, 1b) according to claim 1, characterized in that the separating surface passivation layer (6a, 6b) extends over the entire separating surface (T).

3. Semiconductor component (1a, 1b) according to any one of the preceding claims, characterized in that the separating surface passivation layer (6a, 6b) is formed as a dielectric layer, in particular an aluminum oxide layer, silicon nitride layer or silicon oxynitride layer.

4. Semiconductor component (1a, 1b), characterized in that the semiconductor component (1a, 1b) is formed as a photovoltaic solar cell with at least one silicon layer, in which at least the base (3a, 3b) is formed.

5. Semiconductor component (1a, 1b) according to any one of the preceding claims, characterized in that the semiconductor component (1a, 1b) has a damage zone at the separating surface (T) with a charge carrier lifetime of at least less than 1 µs in the base (3a, 3b), wherein the damage zone perpendicular to the separating surface (T) has a thickness of less than 20 nm, in particular in that the charge carrier lifetime, at least in the base (3a, 3b), has a charge carrier lifetime of more than 10 µs in an area adjoining the damage zone.

6. Method for singulating a semiconductor component (1a, 1b) with a pn junction (4a, 4b), with the method steps: A. providing a semiconductor component (1a, 1b) which has at least one emitter (2a, 2b) and at least one base (3a, 3b), wherein a pn junction (4a, 4b) is formed between the emitter (2a, 2b) and base (3a, 3b), B. singulating the semiconductor component (1a, 1b) by separating into at least two part elements at at least one separating surface (T), wherein in method step B the singulation occurs in such a way that the pn-junction (4a, 4b) is adjacent to the separating surface (T), wherein before method step B a passivating layer is applied to a front and / or a rear side of the semiconductor component (1a, 1b) and wherein before method step B one or more metallic contacting structures are applied to a front side and / or a rear side of the semiconductor component (1a, 1b), wherein the semiconductor component (1a, 1b) is formed as a photovoltaic solar cell, characterized in that after method step B a separating surface passivation layer (6a, 6b) is arranged on the separating surface (T), which layer is formed with fixed charges with a surface charge denisty which is greater than or equal to 1012 cm-2.

7. Method according to claim 6, characterized in that the separating surface passivation layer (6a, 6b) is formed to cover the entire separating surface (T).

8. Method according to any one of claims 6 to 7, characterized in that in method step B the singulation occurs by means of thermal laser separation (TLS, LIC or LDC).

9. Method according to any one of claims 6 to 8, characterized in that following the application of the separating surface passivation layer (6a, 6b), a temperature treatment of the separating surface passivation layer (6a, 6b) occurs, in particular heating to a temperature that is greater than or equal to 150°C for a period of at least 1 minute.

10. Method according to claim 9, characterized in that the temperature treatment occurs by means of successive local heating, in particular by means of a laser.

11. Method according to claim 10, characterized in that the temperature treatment is performed within a hydrogen-containing atmosphere, in particular a hydrogen atmosphere or a hydrogen / nitrogen atmosphere.

12. Method according to any one of the preceding claims 6 to 11, characterized in that the separating surface passivation layer is additionally applied to at least one side of a front side or back side of the semiconductor component, preferably on the front side.

13. Method according to any one of claims 6 to 11, characterized in that at least the base (3a, 3b) is formed in a silicon layer.