SYSTEM AND METHOD FOR DETECTING NON-SWITCHING SEMI-CONDUCTOR SWITCHES

Description

[0001] The present invention generally relates to the detection of a non-switching semiconductor switch among semiconductor switches connected in parallel. More specifically, the present invention relates to a system and a method for detecting a non-switching semiconductor switch among at least two semiconductor switches connected in parallel.

[0002] In electronic power distribution systems, particularly those with high functional safety requirements, it is particularly important that the state of health (SoH) of the power semiconductors used is known at any time, if possible. For this purpose, it is important to know whether a power semiconductor serving as a switch is capable of safe switching, in particular switching off, during operation. If this is not possible, the only option is to connect a second power semiconductor in series with the power semiconductor. However, this increases the costs, space requirements, and power dissipation of the channel. Furthermore, connecting a second power semiconductor in series only statistically reduces the probability of a fault.An actual verification and / or diagnosis of a successful switching process of the semiconductor is only possible by switching off the semiconductor.

[0003] DE 43 01 605 C1 discloses a method and a device for monitoring the switching on and off of a controllable power semiconductor component in a power electronic circuit. When a control signal is applied to switch on the power semiconductor component, counting signals are generated from level changes of the signal applied to the gate electrode and the level changes at an output electrode when switching the power semiconductor component. The counting signals are summed in a first counter and compared with a predetermined count value associated with the proper operation of the power semiconductor component. If there is a difference between the sum of the counting signals and the predetermined count value, an error is reported.

[0004] This method and the associated arrangement are disadvantageous, at least in that they only work with continuously switching switches. In static operation, the system cannot immediately diagnose a fault. Therefore, the method and arrangement of DE 43 01 605 C1 are not sufficiently reliable for fault detection, especially in static operation.

[0005] A system and method for detecting a non-switching semiconductor switch according to the preamble of claims 1 and 10 are known from WO 2010 / 087745 A1. Therefore, there is a need for a reliable and accurate detection of non-switching semiconductor switches. In particular, detection should be possible without having to disconnect an associated load.

[0006] According to a first aspect of the invention, a system for detecting a non-switching semiconductor switch according to claim 1 is provided.

[0007] In other words, the detection unit is designed to detect an output signal based on the (temporal) profile of the electrical variable of the first semiconductor switch and the (temporal) profile of the electrical variable of the second semiconductor switch, which allows / enables detection of an error in the switching of the first semiconductor switch and / or the second semiconductor switch. The system for detecting a non-switching semiconductor switch can therefore alternatively also be referred to as a system for detecting an error in the switching of a semiconductor switch. The error can be detected manually, for example, by examining the detected output signal or a signal derived from the detected output signal. Alternatively, the error can be detected automatically by a detection component based on the detected output signal or a signal derived from the detected output signal.

[0008] The electrical quantity can be an electrical current, an electrical voltage, an electrical resistance, and / or an electrical power. The curve is, in particular, a temporal curve.

[0009] The first semiconductor switch can assume an open / open switching state and a closed switching state. The first semiconductor switch can be transitioned from the open switching state to the closed switching state and vice versa by means of the first control signal. The second semiconductor switch can assume an open / open switching state and a closed switching state. The second semiconductor switch can be transitioned from the open switching state to the closed switching state and vice versa by means of the second control signal.

[0010] The first and / or second semiconductor switches may be part of the system or, as separate components from the system, may be monitored by the system. In other words, the system may include the first and / or second semiconductor switches or monitor the first and / or second semiconductor switches as external units.

[0011] Although a first and a second semiconductor switch are referred to herein, the invention is not limited to the detection of a non-switching semiconductor switch from exactly two semiconductor switches connected in parallel. For example, three or more semiconductor switches can also be connected in parallel. In other words, according to the first aspect of the invention, a system is provided for detecting a non-switching semiconductor switch from at least two semiconductor switches connected in parallel.

[0012] For example, the first semiconductor switch, the second semiconductor switch, and at least one third semiconductor switch can be connected in parallel. In this case, the system can detect a non-switching semiconductor switch from the first semiconductor switch, the second semiconductor switch, and the at least one third semiconductor switch. The first and / or second and / or at least one third semiconductor switch can be part of the system or can be monitored by the system as components separate from the system. In other words, the system can comprise the first and / or second and / or at least one third semiconductor switch or monitor the first and / or second and / or at least one third semiconductor switch as external unit(s).

[0013] If the first and / or second semiconductor switch can no longer be converted from an open to a closed state, a type of emergency operation can be ensured by means of the at least one third semiconductor switch. Without the at least one third semiconductor switch, a load would be switched off, at least briefly, in the aforementioned case.

[0014] The system can be part of a power distribution system, such as a power distribution system with high functional safety and / or reliability requirements. For power distribution systems in general, and for those with high safety requirements in particular, it is important to be able to detect and / or verify the functionality of the semiconductor switches used, especially without impairing a load that is preferably connected downstream of a semiconductor switch during operation.

[0015] The first detection component can have a first measuring amplifier or be designed as a first measuring amplifier. The first measuring amplifier can, for example, be designed to determine, as the profile of the electrical variable of the first semiconductor switch, a profile of an electrical current through a first current measuring resistor connected in series with the first semiconductor switch. The first measuring amplifier can, for example, be designed as a voltmeter to determine, as the profile of the electrical variable of the first semiconductor switch, a profile of an electrical voltage dropping across a first current measuring resistor connected in series with the first semiconductor switch. From this electrical voltage, the electrical current through the first current measuring resistor can be deduced from a known resistance value.If, for example, an electric current is determined as an electrical quantity or derived from the voltage, due to the series connection, the electric current through the first current measuring resistor corresponds to the electric current through the first semiconductor switch, for example a drain current through the first semiconductor switch if the first semiconductor switch is designed as a field-effect transistor.

[0016] The second detection component can have a second measuring amplifier or be designed as a second measuring amplifier. The second measuring amplifier can, for example, be designed to determine a profile of an electrical current through a second current measuring resistor connected in series with the second semiconductor switch as the profile of the electrical variable of the second semiconductor switch. The second measuring amplifier can, for example, be designed as a voltmeter to determine a profile of an electrical voltage dropping across a second current measuring resistor connected in series with the second semiconductor switch as the profile of the electrical variable of the second semiconductor switch. From this electrical voltage, the electrical current through the second current measuring resistor can be deduced from a known resistance value.If, for example, an electric current is determined as an electrical quantity or derived from the voltage, due to the series connection, the electric current through the second current measuring resistor corresponds to the electric current through the second semiconductor switch, for example a drain current through the second semiconductor switch if the second semiconductor switch is designed as a field-effect transistor.

[0017] The first and / or second current measuring resistors can be designed as a shunt or can have a shunt. Accordingly, the first and / or second current measuring resistors can be designed as a low-ohm electrical measuring resistor, e.g., equipped with separate current and voltage terminals, or can have such a measuring resistor. A mostly negligible current can be diverted by a voltmeter connected in parallel to the shunt, for example, as an example of the first and / or second measuring amplifier.

[0018] The output signal determined by the detection unit can permit / enable detection of an error when switching the first semiconductor switch from a closed to an open switching state. Additionally or alternatively, the output signal determined by the detection unit can permit / enable detection of an error when switching the second semiconductor switch from a closed to an open switching state. In other words, it can be deduced from the output signal determined by the detection unit whether or not the first and / or second semiconductor switch can be (correctly) converted from a closed to an open switching state.

[0019] Furthermore, the output signal determined by the detection unit can permit / enable detection of an error when switching the first semiconductor switch from an open to a closed switching state. Additionally or alternatively, the output signal determined by the detection unit can permit / enable detection of an error when switching the second semiconductor switch from an open to a closed switching state. In other words, it can be deduced from the output signal determined by the detection unit whether or not the first and / or the second semiconductor switch can be (correctly) converted from an open to a closed switching state.

[0020] The system may further comprise a detection component. The detection component may be configured to detect the error in the switching of the first semiconductor switch based on the output signal. Additionally or alternatively, the detection component may be configured to detect the error in the switching of the second semiconductor switch based on the output signal.

[0021] The system may further comprise a time delay element, also referred to herein as a delay element. The delay element may be configured to detect an error signal by combining the output signal with a switch-on delay. With the aid of the delay element, misdiagnoses caused by signal propagation times and switching delays can be at least reduced, if not completely prevented.

[0022] The determination unit has a first comparison component and a second comparison component. The first comparison component is designed to determine a first comparison curve of the electrical variable of the first semiconductor switch with a reference value or reference value curve. The comparison curve is determined by comparing the curve of the electrical variable of the first semiconductor switch with a curve of an average value from the curve of the electrical variable of the first semiconductor switch and the curve of the electrical variable of the second semiconductor switch. The second comparison component is designed to determine a second comparison curve of the electrical variable of the second semiconductor switch with a reference value or reference value curve.The second comparison curve is determined by comparing the curve of the electrical quantity of the second semiconductor switch with the curve of the mean value of the curve of the electrical quantity of the first semiconductor switch and the curve of the electrical quantity of the second semiconductor switch.

[0023] The first comparison component may comprise a comparator. Alternatively, the first comparison component may be designed as a comparator. The second comparison component may comprise a comparator. Alternatively, the second comparison component may be designed as a comparator. The comparator may also be referred to as an operational amplifier.

[0024] The determination unit can have a first linking component, a second linking component, and a third linking component. The first linking component can be configured to determine a first linking signal by linking the first comparison curve with the first control signal. The second linking component can be configured to determine a second linking signal by linking the second comparison curve with the second control signal. The third linking component can be configured to determine the output signal by linking the first linking signal and the second linking signal.

[0025] The first linking component can be designed as an exclusive-OR gate (XOR gate). Additionally or alternatively, the second linking component can be designed as an XOR gate. Additionally or alternatively, the third linking component can be designed as an OR gate.

[0026] The system may include a phase generator. The phase generator may be configured to generate the first control signal. Additionally or alternatively, the phase generator may be configured to generate the second control signal. The phase generator may thus be configured to ensure that at least one of the parallel-connected semiconductor switches, i.e., the first semiconductor switch and the second semiconductor switch, and optionally at least one further semiconductor switch, is switched on.

[0027] The first semiconductor switch can be designed as a power semiconductor / power semiconductor switch. Additionally or alternatively, the second semiconductor switch can be designed as a power semiconductor / power semiconductor switch. The system can be embedded in a power distributor of an overall system, such as being part of a power distributor of an overall system. The overall system can have a power supply and at least one load. The power distributor can be located between the power supply and the at least one load. The power distributor can distribute the power provided by the power supply to the at least one load. The first semiconductor switch and / or the second semiconductor switch can be arranged in the power distributor to switch the at least one load on (connect it to the power supply) or off (disconnect it from the power supply).

[0028] According to a second aspect of the invention, a method for detecting a non-switching semiconductor switch is provided. The method comprises detecting a profile of an electrical variable of a first semiconductor switch controlled by a first control signal. The method further comprises detecting a profile of an electrical variable of a second semiconductor switch controlled by a second control signal and connected in parallel to the first semiconductor switch. The method further comprises determining an output signal based on the profile of the electrical variable of the first semiconductor switch and the profile of the electrical variable of the second semiconductor switch.The output signal allows / enables the detection of a non-switching semiconductor switch of the first semiconductor switch and / or the second semiconductor switch (a non-switching semiconductor switch from the first semiconductor switch and / or the second semiconductor switch). In other words, the output signal allows / enables the detection of an error in the switching of the first semiconductor switch and / or the second semiconductor switch. In other words, an error in the switching of the first semiconductor switch and / or the second semiconductor switch can be derived from the output signal. The error can be derived from the output signal, for example, automatically or manually.

[0029] The present disclosure will be further explained with reference to figures. These figures schematically show: Figure 1: a complete system with power supply, power distributor and electrical consumer; Figure 2: a possible design of a power distributor from Figure 1 ; Figure 3 shows a possible design of a power distributor made of Figure 2 applicable switching system according to an embodiment; and Figures 4a, b show exemplary signal waveforms of electrical quantities for use in the system of Figure 3 .

[0030] Specific details are set forth below, but are not intended to be limiting, in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be utilized in other embodiments that may differ from the details set forth below. For example, specific configurations and embodiments of a system are described below and are not intended to be limiting.

[0031] Figure 1shows a schematic of a power distribution system with a power supply 10, a power distributor 20, and an electrical load 40. The power supply 10 has a positive terminal 12 and a negative terminal 14. The power distributor 20 has a positive terminal 22 and a negative terminal 26 on the input side. Furthermore, the power distributor 20 has a positive terminal 24 on the output side. The power distributor 20 has a switching system 30 with which the load 40 can be switched on and off. The switching system 30 has a controller 28. The controller 28 can be a higher-level controller. The electrical load 40 has a positive terminal 42 and a negative terminal 44.

[0032] The negative terminal 14 of the power supply 10, the negative terminal 26 of the power distributor 20, and the negative terminal 44 of the load 40 are each connected to earth / ground 50. As a result, the power supply 10, the power distributor 20, and the load 40 have the same reference potential, in this case, for example, ground / earth 50.

[0033] The power supply 10 is connected via its positive terminal 12 to the input-side positive terminal 22 of the power distributor 20. The power distributor 20 is connected on the output side via its output-side positive terminal 24 to the electrical load 40. Even if only one load 40 is shown as an example, several electrical loads 40 can be connected to the power distributor 20, for example via further Figure 1positive output terminals of the power distributor 20 (not shown). The switching system 30 is designed to switch the electrical load 40 on and off. In the case of multiple electrical loads, the system is designed accordingly to switch several electrical loads on and off. One or more such switching systems can be provided for this purpose. If switching off is not possible, the switching system 30 sends a corresponding error message to the controller 28. In particular, the power distribution system can be a power distribution system with high safety (and / or reliability) requirements. In these systems, it is all the more important to be able to verify the functionality of the switches used (for switching the load 40 on and off).

[0034] Figure 2 shows an exemplary design of a power distributor 20 from Figure 1. The power distributor 20 has a positive terminal 22 on the input side. Furthermore, the power distributor 20 has a positive terminal 24 on the output side. Furthermore, the power distributor has a controller 28. The negative terminal of the power distributor Figure 1 For simplicity, Figure 2 not shown. In Figure 2 is an exemplary embodiment of the switching system 30 from Figure 1 shown. According to this example, the switching system 30 comprises a phase generator 32, a first semiconductor switch 34a, a second semiconductor switch 34b, and a comparator 38. The first semiconductor switch 34a and the second semiconductor switch 34b serve to switch the electrical load 40 on and off. In particular, the switch-off functionality should be monitored for its reliability. The first semiconductor switch 34a and the second semiconductor switch 34b are connected in parallel.

[0035] The phase generator 32 controls the first semiconductor switch 34a and the second semiconductor switch 34b, e.g., each with the aid of a generated control signal. A first detection component can detect a profile of an electrical variable of the first semiconductor switch 34a, which is controlled by a first control signal. A second detection component can detect a profile of an electrical variable of the second semiconductor switch 34b, which is controlled by a second control signal. The electrical variable can be, for example, an electrical current or an electrical voltage. The first and / or the second detection component can, as shown by way of example in Figure 2 intended to be part of the comparator 38, ie according to Figure 2The comparator 38 may include the first and / or second detection components. Alternatively, the first and / or second detection components may be configured and arranged as separate devices from the comparator 38.

[0036] The comparator 38, as an example of a determination unit, can determine an output signal based on the profile of the electrical variable of the first semiconductor switch 34a and the profile of the electrical variable of the second semiconductor switch 34b. The output signal can allow / enable detection of an error in the switching of the first semiconductor switch 34a and / or the second semiconductor switch 34b. In other words, the detected output signals of the first semiconductor switch 34a and the second semiconductor switch 34b can be compared and evaluated in the comparator 38. The comparator 38 generates a comparison signal as an output signal from the output signals of the first and second semiconductor switches.From this comparison signal, it can be deduced whether the first semiconductor switch 34a and / or the second semiconductor switch 34b actually switches as intended or not, in particular whether it switches off as intended or whether it can be switched off. If an error is detected during switching, in particular during switching off, the controller 28 is informed of this, for example. The controller 28, as a higher-level entity, can, for example, take appropriate measures, such as switching off the electrical load 40 itself, disconnecting it from the power distributor 20, or transferring it to a safe state.

[0037] Figure 3shows a specific embodiment, more precisely a possible circuit as a hardware implementation, of the switching system 30. The switching system 30 has a phase generator 32. The phase generator 32 is configured to generate a first drive signal V_phase1 and a second drive signal V_phase2. The first drive signal V_phase1 is input to a first gate driver 62a. The second drive signal V_phase2 is input to a second gate driver 62b. The first gate driver 62a is connected to the gate terminal of the first semiconductor switch 34a, which in the example from Figure 3 is designed as a first MOSFET 34a and is therefore referred to below as the first MOSFET 34a. The second gate driver 62b is connected to the gate terminal of the second semiconductor switch 34b, which in the example from Figure 3as a MOSFET 34b and is accordingly referred to as the second MOSFET 34b. The source terminal of the first MOSFET 34a is connected via a variable resistor, which is the load 40 from Figure 1 in the circuit Figure 3 illustrated and accordingly also designated by reference numeral 40, is connected to ground / earth. The source terminal of the second MOSFET 34b is connected to ground / earth via the variable resistor. The drain terminal of the first MOSFET 34a is connected to a first current measuring resistor 64a. The first MOSFET 34a and the first current measuring resistor 64a are connected in series. The drain terminal of the second MOSFET 34b is connected to a second current measuring resistor 64b. The second MOSFET 34b and the second current measuring resistor 64b are connected in series. A current I1 is generated via a grounded voltage source 10. The voltage source 10 is Figure 3designated by the reference number 10, since they are the power supply 10 from Figure 1 can correspond.

[0038] The first measuring amplifier 66a and the second measuring amplifier 66b from Figure 3 can be considered as a specific realization of the first acquisition component or the second acquisition component (e.g. from Figure 2). The first measuring amplifier 66a is designed to detect an electrical quantity at the first current measuring resistor 64a. For example, the first measuring amplifier 66a can be designed to detect a voltage applied to the first current measuring resistor 64a. Additionally or alternatively, the first measuring amplifier 66a can be designed to detect an electrical current flowing through the first current measuring resistor 64a. The second measuring amplifier 66b is designed to detect an electrical quantity at the second current measuring resistor 64b. For example, the second measuring amplifier 66b can be designed to detect a voltage applied to the second current measuring resistor 64b. Additionally or alternatively, the second measuring amplifier 66b can be designed to detect an electrical current flowing through the second current measuring resistor 64b.

[0039] The first and second measuring amplifiers 66a, 66b input their detected / measured values ​​to an averager 68. Furthermore, the electrical quantity profile measured by the first measuring amplifier 66a is input to a positive (non-inverting) input of a first comparator 70a, hereinafter referred to as operational amplifier 70a. Furthermore, the electrical quantity profile measured by the second measuring amplifier 66b is input to a positive (non-inverting) input of a second comparator 70b, hereinafter referred to as operational amplifier 70b. Both the negative (inverting) input of the first operational amplifier 70a and the negative (inverting) input of the second operational amplifier 70b are fed by the averager 68.

[0040] In the Figure 3In the example shown, the operational amplifiers 70a, 70b are designed as non-inverting operational amplifiers (non-inverting comparators). In such a non-inverting operational amplifier, the reference voltage, in the case of Figure 3 i.e., the mean value, is connected to the inverting input of the operational amplifier. The input signal, here the respective curve of the electrical quantity of the semiconductor switches 34a, 34b from the measuring amplifiers 66a, 66b, is connected to the non-inverting input of the operational amplifier. With a non-inverting operational amplifier, a digital 0 (a LOW level) is output if the input voltage is less than the reference voltage. If, however, the input voltage is equal to or greater than the reference voltage, a digital 1 (a HIGH level) is output. Alternatively, it would be possible to use inverting operational amplifiers in Figure 3 to be provided.

[0041] The output of the first operational amplifier 70a is connected to a first XOR gate 72a. As a result, the first XOR gate 72a receives the output signal V_comp1 of the first operational amplifier 70a as its first input. The output of the second operational amplifier 70b is connected to a second XOR gate 72b. As a result, the second XOR gate 72b receives the output signal V_comp2 of the second operational amplifier 70b as its first input. The first XOR gate 72a receives the first control signal V_phase1 as its second input. The second XOR gate 72b receives the second control signal V_phase2 as its second input. The first XOR gate 72a therefore performs an XOR operation between the output of the first operational amplifier 70a (signal V_comp1) and the first control signal V_phase1. The second XOR gate therefore performs an XOR operation of the output of the second operational amplifier 70b (signal V_comp2) and the second control signal V_phase2.

[0042] The outputs of the first XOR gate 72a (signal V_out1) and the second XOR gate 72b (signal V_out2) are input to an OR gate 74. The output of the OR gate 74 is therefore a superposition of the outputs of the first and second XOR gates 72a, 72b.

[0043] Problems or errors in the switching of the first MOSFET 34a and / or the second MOSFET 34b can be derived from the output signal of the OR gate (signal V_out3).

[0044] Error detection can be improved by connecting a time delay element 76 behind the OR gate 74. This can be achieved by excluding so-called spikes (spikes can be understood as short peaks, i.e., peaks with a duration below a predetermined time threshold) using the time delay element 76. The time delay element 76 ensures that only those abnormalities are recognized as errors whose duration lies above a predetermined time threshold. The signal output from the time delay element 76 can therefore be referred to as the error signal V_error. In other words, the time delay element 76 can be referred to as a switch-on delay, which ensures that only error signals over a certain length are evaluated as valid, i.e., as actual / valid error signals.

[0045] With reference to Figure 3 the comparator can be Figure 2For example, it can be implemented by the measuring amplifiers 66a, 66b, the averager 68, the operational amplifiers 70a, 70b, the XOR gates 72a, 72b and the OR gate 74 from Figure 3 Alternative implementations are possible in which one or more of the aforementioned components are omitted, replaced and / or additional components are added. Figure 3 is therefore only an exemplary hardware implementation of the switching system from Figure 2 to watch.

[0046] The functionality of the design from Figure 3 will now be explained using exemplary signal curves from Figure 4a and 4b described in more detail. In the Figure 4a and 4bThe signal curves are shown over time. The ordinate represents the respective electrical quantity, e.g., current or voltage, and the abscissa represents time. The abscissa is divided into several regions (more precisely, nine regions), each of which is referred to herein as time windows Z1 to Z9.

[0047] Both MOSFETs 34a, 34b are designed as normally-off n-channel MOSFETs in the example. Therefore, MOSFETs 34a, 34b are in a closed state and conduct current when the voltage between gate and source exceeds a threshold value. The threshold value is below the values ​​shown in the example. Figure 4a and 4b 5V assumed as maximum values ​​of the control signals V_phase1, V_phase2.

[0048] As with the exemplary signal curves in the Figure 4a and 4bAs can be seen, both control signals V_phase1, V_phase2 begin in the first time window Z1 with a value of approximately 5V. This corresponds to a high level, also referred to as HIGH (digital 1). Due to the HIGH levels of the control signals V_phase1, V_phase2, a voltage is present between the gate and source of the first MOSFET 34a and between the gate and source of the second MOSFET 34b that exceeds the threshold value of the MOSFETs 34a, 34b. Both MOSFETs 34a, 34b are therefore in a closed state.

[0049] In the exemplary design from Figure 3the total resistance of the first current measuring resistor 64a and the first MOSFET 34a corresponds at least almost exactly to the total resistance of the second current measuring resistor 64b and the second MOSFET 34b. If both MOSFETs 34a, 34b are closed, the current I1 is therefore divided at least almost equally between the parallel connection of the two MOSFETs 34a, 34b. Therefore, at least almost 1.5 flows through both branches of the circuit. A first measuring amplifier 66a can, for example, directly measure the current through the first current measuring resistor 64a. A second measuring amplifier 66b can, for example, directly measure the current through the second current measuring resistor 64b. Alternatively, the first measuring amplifier 66a can measure the voltage drop across the first current measuring resistor 64a. Furthermore, the second measuring amplifier 66b can measure the voltage drop across the second current measuring resistor 64b.Regardless of the measuring method, the first measuring amplifier 66a and the second measuring amplifier 66b determine an electrical quantity that is at least almost the same when both the first MOSFET 34a and the second MOSFET 34b are closed.

[0050] After a certain time, the first control signal V_phase1 is set to a voltage of approximately 0V for a time period Vlow1 in the first time window Z1. This corresponds to a low level, also referred to as a LOW level (digital 0). In this case, only a very low voltage, if any, remains between the gate and source of the first MOSFET 34a, which voltage is below the threshold value of the first MOSFET 34a. The MOSFET 34a therefore transitions to an open state. During the same time period Vlow1 of the first time window Z1, the second control signal V_phase2 remains at a HIGH level. The second MOSFET 34b therefore remains closed.Since the first MOSFET 34a is open in the first time period Vlow1 of the first time window Z1 and the second MOSFET 34b is closed in the first time period Vlow1 of the first time window Z1, the current I1 flows at least almost entirely via the branch of the parallel connection of the two MOSFETs in which the second MOSFET 34b is located. The first measuring amplifier 64a therefore determines a value of at least almost 0 as an electrical quantity. At the same time, the second measuring amplifier 64b determines a value that at least almost corresponds to the current I1 or to the multiplication of current I1 and current measuring resistor 64b. This corresponds to twice the mean value. The first measuring amplifier 64a determines a value of at least almost 0 as an electrical quantity in the same time period Vlow1.

[0051] The second control signal is switched to a low level, LOW level (digital 0), for a time period Vlow2 in a second time window Z2. In this case, only a very low voltage, if any, is present between the gate and source of the second MOSFET 34b, which voltage is below the threshold value of the second MOSFET 34b. The MOSFET 34b therefore transitions to an open state. During the same time period Vlow2 of the second time window Z2, the first control signal V_phase1 is at a HIGH level. The first MOSFET 34a is therefore closed. Since the first MOSFET 34a is closed during the time period Vlow2 of the second time window Z2 and the second MOSFET 34b is open during the time period Vlow2 of the second time window Z2, the current I1 flows at least almost entirely via the branch of the parallel connection of the two MOSFETs in which the first MOSFET 34a is located.The first measuring amplifier 64a therefore determines a value as an electrical quantity that is at least nearly equal to the current I1 or the multiplication of current I1 and the current measuring resistor 64a. This corresponds to twice the mean value. The second measuring amplifier 64b determines a value of at least nearly 0 as an electrical quantity in the same time period Vlow2.

[0052] If the first MOSFET 34a and the second MOSFET 34b are each in a closed state, the two measuring amplifiers 66a, 66b, as described, determine a value for the measured electrical quantity that is at least almost equal. The averager 68 calculates the average from the measured quantities. In the case of equally large values, the average of the electrical quantity corresponds at least almost to the measured value itself. Therefore, the operational amplifier 70a detects no difference between the quantity V_cs1 measured by the first measuring amplifier 66a and the average value V_avg from the averager 68 and accordingly outputs a HIGH level (a 1). Furthermore, the operational amplifier 70b detects no difference between the quantity V_cs2 measured by the second measuring amplifier 66b and the average value V_avg from the averager 68 and accordingly outputs a HIGH level (a 1).

[0053] If the first MOSFET 34a is in an open state and the second MOSFET 34b is in a closed state (see, for example, the time period Vlow1 in the first time window Z1 and the third time window Z3), the first measuring amplifier 66a determines a minimum value of 0 and the second measuring amplifier 66b determines the maximum value. The averager 68 calculates the average value from the measured variables. Therefore, the first operational amplifier 70a determines that the value of the electrical output variable V_cs1 of the first measuring amplifier 66a is below the average value and accordingly outputs a LOW level (digital 0). Furthermore, the operational amplifier 70b determines that the value of the electrical output variable V_cs2 of the second measuring amplifier 66b is not below the average value from the averager 68 and accordingly outputs a HIGH level (a 1) (see signal V_comp1).

[0054] If the first MOSFET 34a is in a closed state and the second MOSFET 34b is in an open state (see, for example, the time period Vlow2 in the second time window Z2 and the fourth time window Z4), the first measuring amplifier 66a determines a maximum value and the second measuring amplifier 66b a minimum value of 0. The averager 68 calculates the average value from the measured variables. Therefore, the operational amplifier 70a determines that the value of the electrical output variable V_cs1 of the first measuring amplifier 66a is not below the average value and accordingly outputs a HIGH level (digital 1). Furthermore, the operational amplifier 70b determines that the value of the electrical output variable V_cs2 of the second measuring amplifier 66b is below the average value from the averager 68 and accordingly outputs a LOW level (digital 0) (see signal V_comp2).

[0055] When the first MOSFET 34a is open, a double peak caused by propagation delays and / or switching delays results as the output variable V_out1 of the first XOR gate 72a at approximately the time level of the LOW level of the first control signal V_phase1, i.e., approximately at the time period Vlow1 in the first time window Z1 and in the third time window Z3. When the second MOSFET 34b is open, a double peak results as the output variable V_out2 of the second XOR gate 72b at approximately the time level of the LOW level of the second control signal V_phase2, i.e., approximately at the time period Vlow2 in the second time window Z2 and in the fourth time window Z4 (and likewise in the sixth time window Z6 and eighth time window Z8). The outputs of the first XOR gate 72a and the second XOR gate 72b are input to an OR gate 74. The output of the OR gate 74 is therefore a superposition of the outputs of the first XOR gate 72a and the second XOR gate 72b.The output signal V_out3 of the OR gate 74 therefore shows a double peak in the first time window Z1 to the fourth time window Z4 (and also in the sixth time window Z6 and eighth time window Z8), which indicates the opening of the first and second MOSFETs 34a, 34b, respectively.

[0056] Assuming, for example, that in the fifth time window Z5, seventh time window Z7, and ninth time window Z9, the first MOSFET 34a does not open correctly, even though the first control signal V_phase1 assumes a LOW level in the time period Vlow1, the MOSFET 34a remains in the closed state in the fifth time window Z5, seventh time window Z7, and ninth time window Z9. As explained, in this case, the current I1 is distributed at least almost equally between the parallel connection of the MOSFETs 34a, 34b. Each of the MOSFETs 34a, 34b and thus each current measuring resistor 64a, 64b is therefore flowed through by a current with a value of at least nearly I1 / 2. The measuring amplifiers 66a, 66b therefore determine a value that is at least almost the same. Both operational amplifiers 70a, 70b therefore detect no difference between the measured values ​​of the measuring amplifiers 66a, 66b and the mean value.Both operational amplifiers 70a, 70b therefore output a HIGH level for the signals V_comp1, V_comp2 in the fifth time window Z5, the seventh time window Z7, and the ninth time window Z9, even during the time period Vlow1. The XOR operation of the output of the first operational amplifier 72a with the first control signal V_phase1 therefore results in a (single) HIGH level approximately during the time period Vlow1 of the fifth time window Z5 (V_out1), not a double peak. The XOR operation of the output of the second operational amplifier 72b with the second control signal V_phase2 results in a LOW level (V_out2). The OR operation of the outputs of both XOR gates 72a, 72b therefore leads to a (single) peak in the fifth time window Z5, seventh time window Z7 and ninth time window Z9 (at least approximately at the level of the time period Vlow1 in the fifth time window Z5, seventh time window Z7 and ninth time window Z9).This single peak (instead of a double peak with a smaller width of each peak caused by propagation delays and / or switching delays) in the output signal of the OR gate 74 (V_out3) therefore indicates an error.

[0057] Error detection can be improved by inserting a time delay behind the OR gate 74, which is sometimes referred to below as time delay element 76. The time delay ensures that only those peaks are detected as errors whose duration exceeds a predetermined time threshold. The duration of the double peaks in the first time window Z1 to the fourth time window Z4 (and also in the sixth time window Z6 and eighth time window Z8) is each below the time threshold. Therefore, the output of the time delay element 76 outputs a LOW level (see signal V_error). The duration of the peaks in the fifth time window Z5, seventh time window Z7, and ninth time window Z9, however, are above the time threshold. The time delay element 76 therefore outputs a HIGH level in the fifth time window Z5, seventh time window Z7, and ninth time window Z9 for a specific duration (see signal V_error).

[0058] According to a specific implementation of the time delay, the time delay element 76 can be designed as a switch-on delay or can effect a switch-on delay. In this case, the time delay element 76 can, for example, effect a time-delayed switch-on or switch-on with a time delay. The time delay can be at least equal to or greater than the magnitude (in time terms) of one of the pulses of the double pulses of the signals Vout1, Vout2, Vout3. As a result, the respective pulses of these double pulses are suppressed or masked out, and only the longer pulses (i.e., the pulses with a width greater than the time delay or greater than the width of each peak of the double peak) are output, each shortened by the magnitude of the time delay in the error signal V_error. This is shown in Fig. 4bcan be seen, in which a valid error signal V_error is shown. In the V_error signal, the rising edge of an error pulse is offset or shortened by the amount of the switch-on delay compared to the rising edge of a long peak, for example in the Vout3 signal (i.e. shortened by at least the width of one pulse of a double pulse / double peak). The falling edge of the pulse of the error signal V_error, on the other hand, falls at the same time as the corresponding pulse in the Vout3 signal, since it is only a switch-on delay and not a switch-off delay. This affects all time slots with errors, i.e. Z5, Z7 and Z9. The pulses of each double pulse, on the other hand, are suppressed by the switch-on delay. After all, these are not actual / valid error pulses.

[0059] As a result, the output signal V_error of the time delay element 76 only shows a peak when there is an error in the switching of one of the MOSFETs 64a, 64b. Propagation delays, however, are suppressed. The output of the time delay 76 can therefore be referred to as the error signal V_error. A detection circuit can automatically detect the peaks in the error signal V_error. Based on the peaks and the control signals, the detection circuit can immediately determine which of the two MOSFETs 34a, 34b has not switched correctly. Therefore, not only can the error be detected promptly, but the affected component can also be replaced or another response to correct the error can be implemented promptly.

[0060] The Figure 3 , 4a and 4b can be summarized as follows. In the Figure 3In the circuit shown, two power semiconductors (MOSFETs) 34a, 34b are connected in parallel, each with a current measuring resistor (shunt) 64a, 64b. A logic circuit alternately switches both power semiconductors 34a, 34b on and off. In the ideal (fault-free) state, at least one power semiconductor 34a, 34b is always on. The current through each of the two parallel paths is measured via the two shunts 64a, 64b using a separate current measuring amplifier 66a, 66b. When both MOSFETs 34a, 34b are on (closed), approximately the same current is measured via both measuring amplifiers 66a, 66b (half the load current I1 in each case). As soon as one of the two MOSFETs 34a, 34b switches off, the full load current I1 flows through one of the two paths, while the other path no longer carries any current. However, the mean value of the two currents remains the same.Two comparators (comparators / operational amplifiers) 70a, 70b compare the output signal V_cs1, V_cs2 of the two current measuring amplifiers 66a, 66b with the mean value and convert them into digital signals by comparators 70a, 70b. The signal waveform of comparators 70a, 70b thus roughly corresponds to the signal sequence V_phase1, V_phase2, with which the respective MOSFET 34a, 34b is controlled. By comparing the respective control signal V_phase1, V_phase2 of MOSFETs 34a, 34b with the output signal V_comp1, V_comp2 of the respective comparator 70a, 70b using an exclusive-OR operation (XOR operation), it can now be detected whether the respective MOSFET 34a, 34b is actually turning off. The two XOR-linked signals V_out1, V_out2 of the two MOSFETs 34a, 34b are then combined by an OR operation to form a signal V_out3 and filtered by a switch-on delay 76.The on-delay 76 is advantageous for preventing faulty diagnoses triggered by signal propagation times and / or switching delays. The output signal V_error is a pulse sequence that approximately corresponds (albeit abbreviated) to the drive pulses of the defective MOSFET 34a, 34b. The output signal V_error of the on-delay 76 can now be read and processed by a higher-level controller (not shown, but see controller 28 in ). Figure 2 ). Alternatively, the pulse sequence can be converted into a static value using a storage element (not shown).

[0061] Even if the description of the embodiments from the Figures 2 to 4breference was made to detect whether the first 34a and / or second semiconductor switch 34b is correctly transferred from a closed to an open state, it can accordingly be detected from the signal curves whether the first 34a and / or second semiconductor switch 34b is correctly transferred from an open to a closed state.

[0062] The detection of a non-switching semiconductor switch of the first and / or second semiconductor switch 34a, 34b enables the use of simple and cost-effective components and it is possible to dispense with a series connection of an additional semiconductor switch for redundancy purposes.

[0063] Even if the description of the embodiments from the Figures 2 to 4bWhile reference is always made only to a first semiconductor switch 34a and a second semiconductor switch 34b, these exemplary embodiments and the invention in general are not limited to exactly two semiconductor switches connected in parallel. Likewise, three or more semiconductor switches can be provided. In summary, therefore, at least two semiconductor switches can be present, and at least one non-switching semiconductor switch can be identified from these at least two semiconductor switches connected in parallel.

[0064] An advantage of the parallel connection of at least a third semiconductor switch to the first 34a and second semiconductor switch 34b will now be explained with respect to the Figures 3 to 4b described without showing the at least one third semiconductor switch in the figures.

[0065] As described, in the first time window Z1, the first semiconductor switch 34a is opened if the first control signal V_phase1 assumes a LOW level in the time period Vlow1. After the time period Vlow1 has elapsed, the first control signal V_phase1 again assumes a HIGH level. In this case, the first semiconductor switch 34a would close again. However, if the first semiconductor switch 34a is defective, the first semiconductor switch 34a remains open, i.e., it no longer closes, even though the first control signal V_phase1 has again assumed a HIGH level. As described, in the second time window Z2, the second semiconductor switch 34b will open during the time period Vlow2, since the second control signal assumes a LOW level during the time period Vlow2.Consequently, during the time period Vlow2, both the first semiconductor switch 34a (because it no longer closes, although it should actually be closed) and the second semiconductor switch 34b are open (due to the LOW level of the second control signal V_phase2). Thus, the load switches off (briefly) during the time period Vlow2 in the time windows Z2, Z4, Z6, Z8.

[0066] However, if at least a third semiconductor switch is connected in parallel, this can – if correctly connected – enable a type of emergency operation. This is because the at least one third semiconductor switch will be in a closed state during the Vlow2 time period with the help of at least a third control signal, which assumes a HIGH level during the Vlow2 time period. Consequently, the load is not disconnected from the system and the power supply and is therefore not switched off.

Claims

1. A system for identifying a non-switching semiconductor switch, wherein the system has: a first detection component, which is configured to detect a profile of an electrical variable of a first semiconductor switch (34a), controlled by means of a first control signal; a second detection component, which is configured to detect a profile of an electrical variable of a second semiconductor switch (34b), controlled by means of a second control signal and connected in parallel with the first semiconductor switch (34a); a determination unit, which is configured, based on the profile of the electrical variable of the first semiconductor switch (34a) and the profile of the electrical variable of the second semiconductor switch (34b) to determine an output signal, which allows an identification of a non-switching semiconductor switch of the first semiconductor switch (34a) and / or of the second semiconductor switch (34b), characterised in that the determination unit has: a first comparison component, which is configured to determine a first comparison profile by comparing the profile of the electrical variable of the first semiconductor switch (34a) with a profile of an average of the profile of the electrical variable of the first semiconductor switch (34a) and the profile of the electrical variable of the second semiconductor switch (34b); and a second comparison component, which is configured to determine a second comparison profile by comparing the profile of the electrical variable of the second semiconductor switch (34b) with the profile of the average of the profile of the electrical variable of the first semiconductor switch (34a) and the profile of the electrical variable of the second semiconductor switch (34b).

2. The system according to claim 1, wherein the first detection component has a first measuring amplifier (66a) or is configured as a first measuring amplifier (66a), wherein the first measuring amplifier (66a) is configured, for example, to determine as the profile of the electrical variable of the first semiconductor switch (34a) a profile of an electric current through a first current sense resistor (64a), connected in series with the first semiconductor switch (34a); and / or the second detection component has a second measuring amplifier (66b) or is configured as a second measuring amplifier (66b), wherein the second measuring amplifier (66b) is configured, for example, to determine as the profile of the electrical variable of the second semiconductor switch (34b) a profile of an electric current through a second current sense resistor (64b), connected in series with the second semiconductor switch (34b).

3. The system according to claim 1 or 2, wherein the output signal, determined by the determination unit, allows a fault in the switching of the first semiconductor switch (34a) and / or of the second semiconductor switch (34b) from a closed state into an open state to be identified.

4. The system according to any one of claims 1 to 3, wherein the system further has an identification component, which is configured to identify the fault in the switching of the first semiconductor switch (34a) and / or of the second semiconductor switch (34b) on the basis of the output signal.

5. The system according to any one of claims 1 to 4, wherein the system further has a delay element, which is configured to determine a fault signal by combining the output signal with a switch-on delay.

6. The system according to any one of claims 1 to 5, wherein the first comparison component has a comparator (70a) or is configured as a comparator (70a); and / or the second comparison component has a comparator (70b) or is configured as a comparator (70b).

7. The system according to any one of claims 1 to 6, wherein the determination unit has: a first logic component, which is configured to determine a first logic signal by combining the first comparison profile with the first control signal; a second logic component, which is configured to determine a second logic signal by combining the second comparison profile with the second control signal; a third logic component, which is configured to determine the output signal by combining the first logic signal with the second logic signal.

8. The system according to claim 7, wherein the first logic component is configured as an XOR gate (72a); and / or the second logic component is configured as an XOR gate (72b); and / or the third logic component is configured as an OR gate (74).

9. The system according to any one of claims 1 to 8, wherein the first semiconductor switch (34a) and / or the second semiconductor switch (34b) is / are configured as a power semiconductor; and / or wherein the system has: the first semiconductor switch (34a); and / or the second semiconductor switch (34b), connected in parallel with the first semiconductor switch (34a); and / or at least a third semiconductor switch, connected in parallel with the first and second semiconductor switches.

10. A method for identifying a non-switching semiconductor switch, wherein the method comprises: detecting a profile of an electrical variable of a first semiconductor switch (34a), controlled by means of a first control signal; detecting a profile of an electrical variable of a second semiconductor switch (34b), controlled by means of a second control signal and connected in parallel with the first semiconductor switch (34a); determining an output signal on the basis of the profile of the electrical variable of the first semiconductor switch (34a) and the profile of the electrical variable of the second semiconductor switch (34b), wherein the output signal allows the identification of a non-switching semiconductor switch of the first semiconductor switch (34a) and / or of the second semiconductor switch (34b), characterised in that the determining an output signal comprises: determining a first comparison profile by comparing the profile of the electrical variable of the first semiconductor switch (34a) with a profile of an average of the profile of the electrical variable of the first semiconductor switch (34a) and the profile of the electrical variable of the second semiconductor switch (34b); and determining a second comparison profile by comparing the profile of the electrical variable of the second semiconductor switch (34b) with the profile of the average of the profile of the electrical variable of the first semiconductor switch (34a) and the profile of the electrical variable of the second semiconductor switch (34b).