BUILDING ELEMENT WITH INTEGRATED BLOCKING LAYER FIELD EFFECTIVE TRANSISTOR AND METHOD FOR MANUFACTURING IT

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor manufacturing technology, and more particularly to a method for manufacturing a device comprising a power vertical double diffused metal-oxide-semiconductor field-effect transistor, VDMOS, in a VDMOS region, integrated with a junction field effect transistor, JFET, in a JFET region.BACKGROUND

[0002] Integrating a high-voltage junction field effect transistor (JFET) on high-voltage process platform is an advanced development and concept in the recent field of smart power integrated circuit, which can greatly improve the on-state performance of vertical power devices, and significantly reduce the chip area, thereby meeting the mainstream trend for manufacturing the smart power device nowadays.

[0003] The conventional structure of high-voltage integrated JFET can be achieved by a simpler process, but it cannot be applied in the smart power integrated field on a large scale due to the unstable pinch-off voltage thereof.

[0004] As to a conventional Vertical Double-diffused MOSFET (VDMOS) integrated JFET, the current flows through the JFET from the bottom drain terminal and flows out of source 2 when the VDMOS is in turn-on stage. When a gradually increased voltage Vg2 is applied to the source 2, and in the same time, the same voltage Vg 1 is applied to the gate; when the Vg2 > the pinch-off voltage Voff, the depletion layer of the JFET blocks the current, that is, a pinch-off phenomenon occurs. At this time, Vg1 > Vth (Vth is the threshold voltage of VDMOS), VDMOS is turned on, and a turn-on process is completed. Then the JFET absorbs an abrupt current of the VDMOS on the Miller platform, which makes the startup more gradual, and the current can be approximately linearly transformed. Therefore, the JFET has a significant effect for the stability of the device during the startup process. The power devices have an advantage of integrating parasitic JFET on process platforms thereof.

[0005] The most important characteristics of the integrated parasitic JFET are the stability of the overall breakdown voltage and of the pinch-off voltage. The most ideal is that the breakdown voltage of the device remains the same after being integrated, and the breakdown point is preferably maintained at the breakdown point of the power VDMOS. The joint of the conventional integrated structure VDMOS and JFET only uses the substrate for isolation, and only the lateral distance of the substrate epitaxy can be extended to ensure the margin when depleted, which may increase the area of the entire die. Meanwhile, since the epitaxial layer specifications have deviation, the breakdown point may transfer if a slight change occurs in the process, and the breakdown point may transfer from the cell region of the body to the JFET region or the joint, which greatly reduces the stability of the breakdown and results in a phenomenon of breakdown voltage creep. The conventional structure generally uses a self-aligned P-type implanted substrate as a P-type pinch-off substrate. Since the P-type substrate of the cell region of the VDMOS has a very shallow depth of the longitudinal junction (generally only from 3 microns to 5 microns), the longitudinal channel of the JFET is very short, the length thereof cannot be adjusted, and then the pinch-off voltage is very unstable. It can be seen that the pinch-off voltage Voff may increase from 11 V up to 20 V when the drain voltage changes from 50 V to 100 V by simulation. However, it needs a stable Voff in practical applications, therefore the conventional structure is difficult to meet the actual requirement.

[0006] The document US2011180858A1 discloses a semiconductor device. The semiconductor comprises a substrate, a VDMOS, a JFET, a first electrode, a second electrode, a third electrode and a fourth electrode. The VDMOS is formed in the substrate. The JFET is formed in the substrate. Wherein the first electrode, the second electrode and a third electrode are connected to the VDMOS and used as a first gate electrode, a first drain electrode and a first source electrode of the VDMOS respectively. The second electrode, the third electrode and the fourth electrode are connected to the JFET and used as a second drain electrode, a second gate electrode and a second drain electrode of the JFET respectively.

[0007] The document US4454523 discloses a high voltage field effect transistor includes a source region in a first major surface of a semiconductor body and a drain region in a second major surface of the semiconductor body. A first gate region is formed in the first major surface and is surrounded by the source regions. A second gate region surrounds the source region and includes a buried region extending into the semiconductor body between the source and drain regions. The buried gate structure can be fabricated by epitaxial grown over diffused regions in a semiconductor substrate, or alternatively ion implantation can be employed to form the buried gate regions.SUMMARY

[0008] According to various embodiments of the present disclosure, it is necessary to provide a method for manufacturing a device comprising a power vertical double diffused metal-oxide-semiconductor field-effect transistor, VDMOS, in a VDMOS region, integrated with a junction field effect transistor, JFET, in a JFET region to solve the problem that the pinch-off voltage of the conventional JFET is unstable.

[0009] According to the invention, there is provided a method for manufacturing a device comprising a power vertical double diffused metal-oxide-semiconductor field-effect transistor, VDMOS, in a VDMOS region, integrated with a junction field effect transistor, JFET, in a JFET region wherein the device comprises a drain, and a first conduction type region disposed on a front surface of the drain, while a part of the drain is located in the JFET region and the other part of the drain is located in the VDMOS region, and a part of the first conduction type region is located in the JFET region and the other part of the first conduction type region is located in the VDMOS region, the method comprising: providing a substrate of the first conduction type serving as said drain, wherein the first conduction type region is formed on the substrate; forming a second conduction type buried layer in the first conduction type region of the JFET region; while the first conduction type is opposite to the second conduction type; implanting ions of the second conduction type into the first conduction type region and forming a first well of the JFET region in the first conduction type region by driving-in; growing a field oxide layer and a gate oxide layer on a surface of the first conduction type region in turn, and forming a polysilicon layer on the surface of the first conduction type region; implanting the ions of the second conduction type into the first conduction type region and forming a second well of the JFET region and a second well of the VDMOS region, by driving-in; implanting ions of the first conduction type, to form a JFET source at the JFET region and form a VDMOS source at the VDMOS region; and forming a photoresist mask and etching contact holes while the photoresist mask is present, depositing a metal layer filling the contact holes, to form a metal electrode of the JFET source, a JFET metal gate and a metal contact of the VDMOS source respectively; wherein after the step of implanting the ions of the second conduction type into the first conduction type region and forming a second well of the JFET region and a second well of the VDMOS region, by driving-in, and prior to the step of implanting ions of the first conduction type, the method further comprises: forming an implanting barrier layer and implanting the ions of the second conduction type through the implanting barrier layer into the second well of the JFET region and into the second well of the VDMOS region to form unclamped inductive switching (UIS) regions, wherein the implanting energy of the UIS regions is greater than the implanting energy of the ions of the first conduction type.

[0010] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and description below. Other features, objects, and advantages of the present disclosure will be apparent from the description, drawings and claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To illustrate the technical solutions according to the embodiments of the present disclosure or in the prior art more clearly, the accompanying drawings for describing the embodiments or the prior art are introduced briefly in the following. Apparently, the accompanying drawings in the following description are only some embodiments of the present disclosure, and persons of ordinary skill in the art can derive other drawings from the accompanying drawings without creative efforts. FIG. 1 is a schematic view of a cross-sectional structure of a device integrated with JFET according to an example of a device helpful for understanding the invention; FIG. 2 is a flowchart of a method for manufacturing a device integrated with JFET in an embodiment; and FIG. 3a to FIG. 3d are cross-sectional schematic views of the manufacturing method described in FIG. 2 in the process of manufacturing the device. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0012] For the convenience of understanding the present disclosure, a more comprehensive description of the present disclosure will be made according to the relevant drawings below. One or more preferred embodiments of the disclosure are given in drawings. However, the present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the disclosure more thorough and comprehensive.

[0013] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used in the specification of the present application are only for the purpose of describing specific embodiments, and not to limit the present application. The term "and / or" used herein includes any and all combinations of one or more relevant listed items.

[0014] It should be understood that when an element is referred to as being "disposed" or "provided" on another element, it can be directly on the other element or intervening elements may be present. When an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element or intervening elements may be present. The terms "vertical", "horizontal", "up", "down", "left", "right", and the like, as used herein are for illustrative purposes only.

[0015] The semiconductor field of terms used herein are common technical terms used by those persons skilled in the art, for example, as to a P type impurity and an N type impurity, in order to distinguish doping concentration, the P+ type is simply represented as the P type with heavy doping concentration, the P type is represented as the P type with normal doping concentration, and the P- type is represented as the P type with mild doping concentration, the N+ type is simply represented as the N type with heavy doping concentration, the N type is represented as the N type with normal doping concentration, and the N- type is represented as the N type with mild doping concentration.

[0016] FIG. 1 is a schematic view of cross-sectional structure of a device comprising a VDMOS integrated with a JFET according to an example of a device helpful for understanding the invention. In the example, the N type is defined as a first conduction type, the P type is defined as a second conduction type. As shown in FIG. 1, the device is divided into a JFET region and a VDMOS region according to the structure thereof, the drain 201 of the N type on the back surface of the device (that is, a surface facing downward in FIG. 1) is partly used for forming the JFET region, and is partly used for forming the VDMOS region. Similarly, the N type region (including a first N type region 202 and a second N type region 204) on the front surface of drain 201 (that is, a surface facing upward in FIG. 1) is partly used for forming the JFET region, and is partly used for forming the VDMOS region. In the present example, the drain 201 is an N+ drain and the N type region is an N- epitaxial layer. In order to facilitate to form the P type buried layer 203, the N type region forms the first N type region 202 and the second N type region 204 respectively by twice epitaxial processes, it should be understood that in other examples, the N type region may also be a single-layer structure provided that the required P type buried layer 203 is formed. The variation of a thickness and concentration of the epitaxial layer may change the pinch-off voltage; the concentration is smaller, the epitaxial thickness is thinner (considering the backward expansion as well as the depth of P well, the total epitaxial thickness of the first N type region 202 and the second N type region 204 is generally greater than 4 microns (µm), and the thickness is typically between 4 microns and 7 microns), and the pinch-off effect is better.

[0017] In the present example, the JEFT region includes: A first well 205, which is a P- well and is formed in the N type region; A second well 207, which is a high-voltage P well and is formed in the N type region, and an ion concentration of the second well 207 is higher than an ion concentration of the first well 205. The second well 207 forms a conduction channel as an N type contact of the device. A JFET source 212, the N+ JFET source 212 serves as the source contact of the JFET; A metal electrode of the JFET source, which is formed on the JFET source 212, which is in contact with the JFET source 212; The P type buried layer 203, which is formed under the JFET source 212 and the second well 207.

[0018] The above mentioned device integrated with JFET applies the lateral channel formed by the P type buried layer 203 and the second well 207, so that the channel concentration is more uniform, and a longer lateral channel is designed by layout, and the pinch-off voltage thereof may be more stable.

[0019] The example as shown in FIG. 1, a boundary between the JEFT region and the VDMOS region also forms one first well 205, as an isolation well configured to isolate the JEFT region from the VDMOS region. The P- first well 205 is used to assist depletion isolation. The flow-through path of the current can be completely blocked by the deeper P- well isolation, which prevents electric leakage between JFET and VDMOS. In addition, the lower N- epitaxial layer (that is, the first N type region 202) can be assisted to participate in depletion when the device is biased reversely and can withstand the voltage, and the breakdown voltage of the local area can be increased to serve for solidifying the breakdown point. At the same time, the first well 205 serves as the depletion structure of the terminal in the junction terminal extension technology, and can effectively shorten the chip area of the high-voltage VDMOS. In addition, since the junction process of the junction terminal extension exists, the junction depth of the first well 205 greatly exceeds the junction depth of the P type substrate of the VDMOS in the conventional art, thereby resulting in a longer longitudinal current channel. Compared with the conventional structure, the stability of the pinch-off voltage of the device is significantly improved, and the pinch-off voltage is also significantly reduced.

[0020] The example as shown in FIG. 1, The JFET region further includes a JFET metal gate 213 and a JFET gate ohmic contact 214. The JFET metal gate 213 is formed on the JFET gate ohmic contact 214 and is in contact with the JFET gate ohmic contact 214. Each of the JFET gate ohmic contacts 214 is formed in the first well 205 and the second well 207 of the JFET region respectively, and the each of JFET gate ohmic contacts 214 is equipotentially connected with each other via the JFET metal gate 213.

[0021] In one example, the P type buried layer 203 is at least in contact with one first well 205. In the example as shown in FIG. 1, there is one P type buried layer 203 on each of two sides under the second well 207, and the two P type buried layers 203 are in contact with the one first well 205 respectively. The first well 205 formed by the deep well diffusion is connected to the P type buried layer 203, and the potential of the P type buried layer 203 can be led out, thereby preventing the P-type buried layer 203 from floating, so that the pinch-off voltage thereof can be more stable as the drain voltage changes.

[0022] In the example as shown in FIG. 1, the JFET source 212 is formed between the second well 207 and the first well 205 (one first well 205 is adjacent to the second well 207).

[0023] In the example as shown in FIG. 1, the VDMOS region includes a gate 206, a second well 207, an N+ VDMOS source 209 disposed in the second well 207, and an Unclamped Inductive Switching (UIS) region 208 of the P++ type disposed under the VDMOS source 209. The ion concentration of the UIS region 208 is higher than the ion concentration of the second well 207. In the example as shown in FIG. 1, The JFET region is also formed with the UIS region 208. Specifically, the UIS region 208 is disposed under the JFET gate ohmic contact 214 in the second well 207, and in the present example, is in the second well 207. In the other examples, the UIS region 208 may also be outside the second well 207 and be in the first well 205. The UIS region 208 can reduce the base resistance of the parasitic NPN transistor and increase the avalanche tolerance of the device.

[0024] In the example as shown in FIG. 1, there is one second well 207 formed on each of the two sides under the gate 206. The VDMOS source 209 is formed in the two second wells 207, and the VDMOS source 209 is divided into two blocks in each of the two second wells 207. The device further includes a P+ type ohmic contact region 210 formed between the two blocks of the VDMOS source 209.

[0025] FIG. 2 is a flowchart of a method for manufacturing a device comprising a VDMOS integrated with a JFET in an embodiment. The following method for manufacturing the device comprising a VDMOS integrated with JFET will be introduced, in which the first conduction type is an N type, and the second conduction type is a P type.

[0026] At step S510, a substrate of the first conduction type is provided, and a first conduction type region is formed on the substrate.

[0027] In the present embodiment, an N type region is formed on the N+ substrate by epitaxy, and the substrate will serve as the drain 201 of the device subsequently.

[0028] At step S520, a second conduction type buried layer is formed in the first conduction type region of the JFET region.

[0029] In the present embodiment, the first conduction type region includes a first epitaxial layer (that is, the first N type layer 202) and a second epitaxial layer (that is, the second N type layer 204). The Step S520 is to photolithograph the first epitaxial layer, implant P type ions, and form the P type buried layer 203 by driving-in. FIG. 3a is a cross-sectional schematic view of the device after the P type buried layer 203 is formed. The second epitaxial layer is formed on the surface of the first epitaxial layer after the P-type buried layer 203 is formed. The P type buried layer 203 is at least in contact with the one first well 205.

[0030] At step S530, ions of the second conduction type are implanted and a first well is formed in the first conduction type region by driving-in.

[0031] In the present embodiment, The P-type ions are implanted into the N type region and the first well 205 is formed in the N type region by driving-in.

[0032] At step S540, a field oxide layer and a gate oxide layer are grown, and a polysilicon layer is formed.

[0033] A thick field oxide layer is grown on the surface of the N type region and then the gate oxide layer is grown, and the polysilicon layer 604 is formed on the surface of the N type region.

[0034] At step S550, ions of the second conduction type are implanted into the first conduction type region and a plurality of second wells are formed by driving-in.

[0035] In the present embodiment, ions of the P type are implanted into the N type region by serving the field oxide layer and the polysilicon layer 604 as a mask, and the plurality of the second wells 207 are formed by driving-in. FIG. 3b is a cross-sectional schematic view of the device after the step S550 is completed.

[0036] Referring to FIG. 3c, prior to performing a step S560, a step of implanting ions of the P type into the second well 207 is further included, to form the UIS regions 208 in the second wells 207 of the JFET region and the VDMOS region. In order to prevent adversely affecting the channel region by implanting ions of the P type into the second well 207, a step of forming the implanting barrier layer is further included prior to the step of implanting ions of the P type to form the UIS regions 208. The implanting barrier layer is formed by re-forming one oxide layer. Since the oxide layer at the implanting window for implanting ions of the P type to form the UIS regions 208 is thin, the implanted ions of the P type by high-energy can pass through the oxide layer to form the UIS regions 208. The oxide layer at other positions is formed on the structures such as the field oxide layer and the polysilicon layer 604, so that the thickness of the entire implanting barrier layer is thick, and the ions of the P type are difficult to pass through the implanting barrier layer and to enter the N type region.

[0037] At step S560, ions of the first conduction type are implanted, to form a JFET source at the JFET region, and form a power device source at the VDMOS region.

[0038] Referring FIG. 3d, in the present embodiment, the ions of the N type ion are implanted with the photoresist as a mask by using a photolithography process. The JFET source is formed in the second well 207 of the JFET region, and a VDMOS source 209 is formed in the second well 207 of the VDMOS region. The VDMOS source 209 is formed in each second well 207 on both sides of the gate, and is divided into two blocks in each second well 207, leaving a position for the ohmic contact region 210 formed in the subsequent step in the middle.

[0039] In the present embodiment, after the step S560 is completed, a step of forming the gate ohmic contact 214 and the ohmic contact region 210 in the first well 205 and the second well 207 is further included. Specifically, the JFET gate ohmic contact 214 is formed in the first well 205 and the second well 207 of the JFET region, and the ohmic contact region 210 is formed in the second well 207 of the VDMOS region.

[0040] At step S570, a contact hole is photolithographed and etched, the metal layer is deposited, and the metal layer is filled into the contact hole, to form a metal electrode of the JFET source, a JFET metal gate and a metal contact of the power device source respectively.

[0041] The metal filled into the contact hole is in contact with the JFET gate ohmic contact 214 to form the JFET metal gate 213, and is in contact with the JFET source 212 to form the metal electrode of the JFET source. After depositing the metal layer, a passivation layer is formed on the surface of the device, and the cross-section of the completed device is shown in FIG. 1.

[0042] Combining with the above mentioned advantages, the above mentioned device integrated with JFET improves the stability of the pinch-off voltage, solidifies the breakdown point, strengthens the UIS capability, is completely matched with the process, and realizes adjustability of the pinch-off voltage on the basis of the conventional technology.

[0043] In one of the embodiments, the step S520 includes: the step of forming the first well (205) of the JFET region in the first conduction type region by driving-in comprises: forming an isolation well at a boundary between the JFET region and the VDMOS region, as isolation of the JFET region and the VDMOS region.

[0044] In one embodiment, an implantation concentration of the first well 205 of the step S530 is between 1.5E13 cm -2< and 2.2E13 cm -2< , and the well depth of the first well 205 is between 8.5 microns and 13.5 microns.

[0045] The above described embodiments are merely illustrative of several embodiments of the present disclosure, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the present disclosure. It should be noted that several variations and modifications may be made by those persons skilled in the art.

Claims

1. A method for manufacturing a device comprising a power vertical double diffused metal-oxide-semiconductor field-effect transistor, VDMOS, in a VDMOS region, integrated with a junction field effect transistor, JFET, in a JFET region wherein the device comprises a drain (201), and a first conduction type region disposed on a front surface of the drain (201), while a part of the drain (201) is located in the JFET region and the other part of the drain (201) is located in the VDMOS region, and a part of the first conduction type region is located in the JFET region and the other part of the first conduction type region is located in the VDMOS region, the method comprising: providing a substrate of the first conduction type serving as said drain (201), wherein the first conduction type region is formed on the substrate; forming a second conduction type buried layer (203) in the first conduction type region of the JFET region; while the first conduction type is opposite to the second conduction type; implanting ions of the second conduction type into the first conduction type region and forming a first well (205) of the JFET region in the first conduction type region by driving-in; growing a field oxide layer and a gate oxide layer on a surface of the first conduction type region in turn, and forming a polysilicon layer on the surface of the first conduction type region; implanting the ions of the second conduction type into the first conduction type region and forming a second well (207) of the JFET region and a second well (207) of the VDMOS region, by driving-in; implanting ions of the first conduction type, to form a JFET source (212) at the JFET region and form a VDMOS source (212) at the VDMOS region; and forming a photoresist mask and etching contact holes while the photoresist mask is present, depositing a metal layer filling the contact holes, to form a metal electrode of the JFET source (212), a JFET metal gate (213) and a metal contact of the VDMOS source respectively; wherein after the step of implanting the ions of the second conduction type into the first conduction type region and forming a second well (207) of the JFET region and a second (207) well of the VDMOS region, by driving-in, and prior to the step of implanting ions of the first conduction type, the method further comprises: forming an implanting barrier layer and implanting the ions of the second conduction type through the implanting barrier layer into the second well (207) of the JFET region and into the second well (207) of the VDMOS region to form unclamped inductive switching, UIS, regions (208), wherein the implanting energy of the UIS regions is greater than the implanting energy of the ions of the first conduction type.

2. The method of claim 1, wherein the step of forming the first well (205) of the JFET region in the first conduction type region by driving-in comprises: forming an isolation well at a boundary between the JFET region and the VDMOS region, as isolation of the JFET region and the VDMOS region.

3. The method of claim 1, wherein the first conduction type region comprises a first epitaxial layer and a second epitaxial layer; the step of forming the second conduction type buried layer (203) in the first conduction type region of the JFET region comprising: forming a further photoresist mask on the first epitaxial layer, implanting the ions of the second conduction type into the first epitaxial layer while the further photoresist mask is present, and forming the second conduction type buried layer (203) by driving-in; prior to the step of implanting the ions of the second conduction type into the first conduction type region and forming the first well (205) in the first conduction type region by driving-in, further comprising a step of forming the second epitaxial layer on a surface of the first epitaxial layer; the second conduction type buried layer (203) being at least in contact with the first well (205) of the JFET region.

4. The method of claim 1, wherein after the step of forming the JFET source (212) at the JFET region and forming the VDMOS source at the VDMOS region, and prior to the step of forming the photoresist mask and etching the contact hole, the method further comprises a step of implanting the ions of the second conduction type, to form JFET gate ohmic contacts (214) in the first well (205) and the second well (207) of the JFET region, and to form an ohmic contact region (210) in the second well (207) of the VDMOS region.

5. The method of claim 1, wherein the first conduction type is an N type, and the second conduction type is a P type.