IMPROVED MANUFACTURING METHOD OF AN INTEGRATED CIRCUIT COMPLETING AN NMOS AND A PMOS TRANSISTOR

Description

[0001] The invention relates to the manufacture of Silicon-on-insulator transistors, and in particular the manufacture of Silicon-on-insulator transistors exhibiting improved charge mobility properties in their channels.

[0002] In order to increase the mobility in the channel of pMOS transistors and to limit the threshold voltage offset compared to a cointegrated nMOS transistor, it is known to deposit a layer of SiGe by epitaxy on a Silicon layer, then to carry out thermal oxidation and annealing, so as to achieve condensation concentrating the Germanium in the Silicon layer.

[0003] Furthermore, to improve channel mobility in nMOS transistors, a process called STRASS is known. This process involves depositing SiGe onto a silicon layer, relaxing the SiGe, and amorphizing its lower portion and the silicon layer. Next, the SiGe layer is recrystallized from its top, and the silicon layer is also recrystallized to create a voltage constraint. After the SiGe layer is removed, the silicon layer remains under voltage constraint.

[0004] The implementation of these manufacturing processes theoretically allows for the production of combinations of nMOS and pMOS transistors with suitable properties. However, implementing such processes requires a very large number of industrial steps and numerous photolithography steps. Consequently, the current cost of such a manufacturing process is too high to allow for this combination of transistors.

[0005] The invention aims to resolve one or more of these drawbacks. The invention thus relates to a method for manufacturing an integrated circuit, as defined in the attached claims.

[0006] The invention also relates to variants of the dependent claims. Those skilled in the art will understand that each of the features of the description or the dependent claims can be combined independently with the features of an independent claim, without thereby constituting an intermediate generalization.

[0007] Other features and advantages of the invention will become clear from the description given below, by way of example and not limitation, with reference to the accompanying drawings, in which: [ Fig. 1 ] And [ Fig. 2 ] are respectively cross-sectional and top views of an FDSOI substrate (designating a completely depleted Silicon-on-Insulator) intended to form an nMOS transistor and a pMOS transistor; Fig. 3 ], [ Fig. 4 ], [ Fig. 5 ], [ Fig. 6 ], [ Fig. 7 ], [ Fig. 8 ], [ Fig. 9 ], [ Fig. 10 ], [ Fig. 11 ], [ Fig. 12 ], [ Fig. 13 ] are cross-sectional views of said nMOS and pMOS transistors at different stages of their manufacturing process according to a first embodiment which is not covered by the text of the claims [ Fig.14 ] is a diagram illustrating the steps of the manufacturing process according to the first embodiment; [ Fig. 15 ], [ Fig. 16 ], [ Fig. 17 ], [ Fig. 18 ], [ Fig. 19 ], [ Fig. 20 ], [ Fig. 21 ], [ Fig. 22 ], [ Fig. 23 ], [ Fig. 24 ], [ Fig. 25 ], [ Fig. 26 ], [ Fig. 27 ] And [ Fig. 28 ] are cross-sectional views of said nMOS and pMOS transistors at different stages of their manufacturing process according to a second embodiment, covered by the text of the claims; [ Fig. 29 ], [ Fig. 30 ], [ Fig. 31 ], [ Fig. 32 ], [ Fig. 33 ], [ Fig. 34 ], [ Fig. 35 ], [ Fig. 36 ], [ Fig. 37 ], [ Fig. 38 ], [ Fig. 39 ], [ Fig. 40 ] And [ Fig. 41 ] are cross-sectional views of said nMOS and pMOS transistors at different stages of their manufacturing process according to a third embodiment, which is not covered by the text of the claims; Fig. 42 ], [ Fig. 43 ], [ Fig. 44 ], [ Fig. 45 ], [ Fig. 46 ], [ Fig. 47 ], [ Fig. 48 ], [ Fig. 49 ], [ Fig. 50 ], [ Fig. 51 ], [ Fig. 52 ] And [ Fig. 53 ] are cross-sectional views of said nMOS and pMOS transistors at different stages of their manufacturing process according to a fourth method of

[0008] There figure 1 is a cross-sectional view of an example of structure 1 including an FDSOI 10 substrate configured to form nMOS and pMOS transistors according to a process of the invention. figure 2 is a top view of the same substrate 10.

[0009] To obtain this configuration, a substrate 10 is provided with a layer of Silicon 13, for example, unintentionally doped Silicon. The Silicon 13 layer typically has a thickness between 5 and 20 nm, for example, 6 nm. The Silicon 13 layer is formed on a buried insulating layer 12, for example, SiO2, typically with a thickness between 15 and 40 nm, for example, 25 nm. The buried insulating layer 12 is formed on a substrate 11, typically unintentionally doped Silicon.

[0010] A masking step (not shown) was first performed on the entire surface of the Silicon 13 layer, followed by a lithography step (not shown) to form a hard mask 14 on the Silicon 13 layer, and finally an etching step (not shown) was performed according to the previously formed mask 14. This made it possible to expose apertures 51 and 52 and associated areas 151 and 152 of the Silicon 13 layer at the bottom of the apertures 51 and 52. A strip of hard mask 140 is interposed between areas 151 and 152. Area 151 is interposed between a strip 141 of hard mask and the strip 140. Area 152 is interposed between a strip 142 of hard mask and the strip 140. The apertures 51 and 52, for example, have a width of at least 60 nm. The areas 151 and 152 thus made accessible constitute formation areas for an nMOS transistor and a pMOS transistor respectively.

[0011] A manufacturing process not covered by the text of the claims may be implemented from step 300, starting from the configuration illustrated in figures 1 And 2 .

[0012] At step 301, a first deposit 17 of SiGe alloy is formed in the opening 51 on zone 151, as illustrated in the figure 3 Simultaneously, a second SiGe alloy deposit 18 is formed in the aperture 52 on the zone 152. Deposits 17 and 18 are typically formed by epitaxial growth with lateral facets. The lateral faces of deposits 17 and 18 are thus inclined. Processes for growing SiGe by epitaxial growth with facets are known to those skilled in the art. Deposits 17 and 18 typically have a thickness between 5 nm and 30 nm. Deposits 17 and 18 include, for example, a germanium concentration (by atom) between 15 and 35%. Epitaxial growth deposition is for example carried out with SiGe containing 30% Germanium, at a temperature of 630°C for example, using H2 as carrier gas and Germane (GeH4) and Dichlorosilane (DCS, SiH2Cl2) as precursors (or silane SiH4).

[0013] In step 302, the first deposit 17 is covered with a layer 21 of hard mask on the element 17, forming a protective layer, as illustrated in the figure 4 Layer 21 is typically made of SiO2. This layer 21 has, for example, a thickness between 15nm and 40nm.

[0014] In step 303, an advantageously anisotropic etching step is implemented on the second deposit 18 and layer 13. The etching is stopped on layer 12, to obtain the configuration illustrated in the figure 5 This etching process creates grooves 61 and 62, which delineate layer 13 into an element 137 and zones 132 and 133. In this example, a single groove encircles element 137. Layer 12 then forms the bottom of grooves 61 and 62. The superposition of the second deposit 18 and the Si element 137 forms a stack. The grooves 61 and 62, on either side of this stack, typically have a width between 1 and 10 nm. In this example, the etching of grooves 61 and 62 is easily achieved due to the facets formed during the formation of the second deposit 18. The second deposit 18 thus has a decreasing thickness as one approaches the hard mask 14. The thickness of the deposit 18 can, for example, be practically zero at its interface with the hard mask 14. Etching near the hard mask 14 thus makes it easy to reach layer 12 around the second deposit 18.

[0015] In step 304, ion implantation is performed, which amorphizes the stack in depth. Starting from the second deposit 18, the amorphization results in the formation of a layer 181 of amorphous SiGe. Starting from element 137, the amorphization results in the formation of an element 138 of amorphous Silicon. On the surface of the second deposit 18, a layer 182 formed from a non-amorphized SiGe crystal seed is preserved. The crystalline surface of element 137 is also preserved on the amorphous element 138. This yields the configuration illustrated in the figure 6 The presence of grooves 61 and 62 on either side of layer 182 allows layer 182 to avoid lateral stress and to adopt a relaxed stress state in a plane parallel to layer 12.

[0016] In step 305, annealing is performed to recrystallize layer 181 and element 138. Annealing is carried out, for example, at a temperature of 600°C to 700°C, advantageously maintained for 30 seconds to 5 minutes (depending on the thickness of the SiGe / Si layer stack). The annealing operation results in the configuration illustrated in the figure 7 , in which a relaxed SiGe layer 183 has reformed above a Si element 139. The Si element 139 then takes the lattice parameter of the relaxed SiGe layer 183 and thus becomes strained in tension in a plane parallel to the layer 12.

[0017] In step 306, the layer 183 of relaxed SiGe is removed by etching, resulting in the configuration illustrated in the figure 8 . Silicon element 139 maintains a tensile stress in a plane parallel to layer 12.

[0018] In step 307, a hard mask layer 22 is formed on element 139, as illustrated figure 9 Layer 22 forms a protective layer. Element 139 is then protected during subsequent etching steps. The second protective layer 22 is typically made of SiN. This layer 22 has, for example, a thickness of between 30 and 50 nm. The thickness of the layer 22 formed is sufficient to extend beyond the top of layer 21.

[0019] In step 308, an advantageously anisotropic etching step is implemented on the protective layer 21 and the first deposit 17. This forms a SiGe element 171 accessible through the opening 51. The configuration illustrated in the figure 10 .

[0020] In step 309, thermal oxidation annealing of the element SiGe 171 is performed. This annealing causes the Germanium from element 171 to diffuse into the Silicon layer 13, resulting in the formation of the following elements in layer 13: a 172 SiGe element, formed by Germanium enrichment of layer 13; residual Si zones 130 and 131. Zones 130 and 131 are arranged vertically above bands 140 and 141 of the hard mask layer.

[0021] The upper surface of element 172 is covered with a layer 173 of SiO2, obtained by thermal oxidation of element 171. The resulting configuration is illustrated in the figure 11 The SiGe element 172 retains the lattice parameters of the original Silicon 13 layer in the plane. Diffusion of Germanium into the Silicon 13 layer leads to the creation of a biaxial compressive stress in a plane parallel to the insulating layer 12 within the formed element 172. The boundary between element 172 and zones 130 and 131 is positioned approximately vertically above the lateral faces of bands 140 and 141, respectively. The superposition of the SiGe element 172 and the SiO2 layer 173 forms a stack.

[0022] In step 310, the SiO2 layer 173, the protective layer 22, and the bands 140, 141, and 142 are removed, as illustrated in the figure 12 This provides access to the SiGe element 172 on the one hand and to the element 139 on the other.

[0023] In step 311, elements 130, 131, and 132 are removed to form grooves by engraving. The grooves are then filled with insulating material to form elements 1320, 1321, and 1322. This creates deep insulation trenches, generally referred to as STI (for Shallow Trench Insulation), as illustrated in the figure 13 This creates an isolation between a pMOS transistor formation zone and an nMOS transistor formation zone.

[0024] Thus, at the end of the steps of a manufacturing process according to a first embodiment, we have: of a 172 element in compression-stressed SiGe for the formation of the pMOS transistor channel in one zone; of a 139 element in tension-stressed Silicon for the formation of the nMOS transistor channel in the other zone.

[0025] Other areas of the structure may exhibit an unconstrained silicon layer for the formation of other transistors.

[0026] Elements 172 and 139 are obtained from the same initial SiGe deposit by epitaxy, with a reduced number of masking and photolithography steps.

[0027] There figure 14 is a diagram illustrating the steps of the manufacturing process according to the first embodiment, as detailed previously.

[0028] There figure 15 is a cross-sectional view of an example of structure 1 at one stage of a manufacturing process, according to the claimed invention On fournit initially an FDSOI 10 substrate configured to form nMOS and pMOS transistors according to the figures 1 And 2 previously described.

[0029] A uniform dielectric layer 23 was deposited on the upper surface of the structure 1. The layer 23 is, for example, made of SiO2, which allows for perfect control of its thickness.

[0030] Next, layer 23 is etched, advantageously using an anisotropic plasma-type process in fluorocarbon chemistry, as illustrated in the figure 16 This made it possible to expose openings 51 and 52 and associated zones 151 and 152 of the Silicon 13 layer at the bottom of openings 51 and 52.

[0031] A hard mask strip 140 is interposed between zones 151 and 152. A spacer 231, left over from the etching of layer 23 and attached to strip 140, is interposed between strip 140 and zone 151. A spacer 234, left over from the etching of layer 23 and attached to strip 140, is interposed between strip 140 and zone 152.

[0032] Area 151 is interposed between a hard mask strip 141 and strip 140. A spacer 232, remnant of the etching of layer 23 and attached to strip 141, is interposed between strip 141 and area 151.

[0033] Zone 152 is interposed between a hard mask strip 142 and strip 140. A spacer 233, remnant of the etching of layer 23 and attached to strip 142, is interposed between strip 142 and zone 152.

[0034] For example, the openings 51 and 52 have a width of at least 40nm. The areas 151 and 152 thus made accessible constitute formation zones for an nMOS transistor and a pMOS transistor respectively.

[0035] A first deposit 31 of SiGe alloy is then formed in the opening 51 on zone 151, as illustrated in the figure 17 Simultaneously, a second SiGe alloy deposit 32 is formed in the aperture 52 on the zone 152. Deposits 31 and 32 are typically formed by epitaxial growth. Epitaxial growth processes for SiGe are known to those skilled in the art. Deposits 31 and 32 typically have a thickness between 5 nm and 30 nm. Deposits 31 and 32 include, for example, a germanium concentration (by atom count) between 15 and 35%. Epitaxial growth deposition is, for example, carried out with SiGe containing 30% germanium, at a temperature of 630°C, using H₂ as the carrier gas and germane (GeH₄) and dichlorosilane (DCS, SiH₂Cl₂) as precursors (or silane SiH₄).

[0036] As illustrated in the figure 18 The second deposit 32 is then covered with a layer 24 of hard mask. Layer 24 forms a protective layer. Here, layer 24 is combined with spacers 233 and 234, as layers 23 and 24 are made of the same material. The second deposit 32 is thus protected during subsequent etching steps by this protective layer. Simultaneously, a layer of hard mask 241 is also deposited on the strip 141. Layers 24 and 241 are typically made of SiO₂. These layers 24 and 241 have a thickness, for example, between 10 and 40 nm.

[0037] The first SiGe 31 deposit is then annealed by thermal oxidation. This annealing causes the Germanium from the first deposit 31 to the Silicon layer 13, resulting in the formation of the following elements in said layer 13: a SiGe element 34, formed by Ge enrichment of layer 13; residual Si zones 131 and 134. Zone 131 is located vertically along band 141 of the hard mask layer. Zone 134 extends from the vertical line of band 140.

[0038] The upper surface of element 34 is covered with a layer 33 of SiO2, obtained by thermal oxidation of the first deposit 31 and bonding with spacers 231 and 232. The resulting configuration is illustrated in the figure 19 The SiGe element 34 retains the crystalline parameters of the original Silicon 13 layer. The condensation of Germanium in the Silicon 13 layer leads to the creation of a biaxial compressive stress in a plane parallel to the insulating layer 12 within the formed element 34. The boundary between element 34 and zones 131 and 134 is positioned approximately vertically above the lateral faces of bands 141 and 140, respectively. The superposition of element 34 and layer 33 forms a stack.

[0039] As illustrated in the figure 20 Next, a full-plate layer 25 is deposited. Layer 25 is typically made of SOC-type carbon or a silicon-enriched hard mask with an anti-reflective hard mask.

[0040] The previously formed layer 25 then undergoes mechanochemical etching or polishing, stopping at the hard mask layers 24 and 241, as illustrated in the figure 21 . This forms element 251, a remnant of the etching of layer 25. Element 251 forms a protective layer and thus protects layer 33 of SiO 2 and element 34 of SiGe from subsequent etching steps.

[0041] The hard mask layers 24 and 241 are then removed by selective etching, thus freeing access to the second deposit 32 previously formed. This provides temporary access to the second deposit 32. This etching is then continued to form grooves 610 and 620, which separate the second deposit 32 from strip 140 and strip 142, respectively. Layer 134 then forms the bottom of grooves 610 and 620. The resulting configuration is illustrated in the figure 22 .

[0042] Next, an advantageously anisotropic etching step is implemented on layer 134, around the second deposit 32, stopped at layer 12, to obtain the illustrated configuration. figure 23 This etching allows the formation of grooves 61 and 62, extending from grooves 610 and 620. Grooves 61 and 62 separate an element 137 from zones 132 and 130. In this example, a single groove encircles element 137. Layer 12 then forms the bottom of grooves 61 and 62. The superposition of the second deposit 32 and element 137 forms a stack called the second stack. Grooves 61 and 62 typically have a width between 1 and 10 nm. In this example, the etching of grooves 61 and 62 is easily carried out due to the prior creation of grooves 610 and 620. Grooves 610 and 620 form a good starting point for easily reaching layer 12 around the second deposit 32.

[0043] An ion implantation process is then carried out, which amorphizes the stacking of deposit 32 and element 137 at depth. Starting from deposit 32, the amorphization results in the formation of a 322 layer of amorphous SiGe. Starting from element 137, the amorphization results in the formation of an element 138 of amorphous silicon. At the surface of deposit 32, a 321 layer formed from a non-amorphized SiGe crystal seed is preserved. This yields the configuration illustrated in the figure 24 The presence of grooves 61 and 62 on either side of layer 321 allows said layer 321 to avoid lateral stress and to adopt a relaxed stress state in a plane parallel to layer 12.

[0044] The protective layer 251 is then removed. Simultaneously, a recrystallization anneal is also performed to recrystallize layers 322 and 138. The annealing is carried out, for example, at a temperature of 600°C to 700°C, advantageously maintained for 30 seconds to 5 minutes depending on the thickness of the SiGe / Si stack. The annealing operation results in the configuration illustrated in the figure 25 in which a 323 layer of relaxed SiGe has formed above a 139 element of crystalline Si. The 139 element of Si then takes on the lattice parameter of the 323 layer of relaxed SiGe and thus becomes strained in a plane parallel to the 12 layer.

[0045] The next step involves removing layer 323 of relaxed SiGe by etching, resulting in the configuration illustrated in the figure 26 . Silicon element 139 maintains a tensile stress in a plane parallel to layer 12.

[0046] As illustrated in the figure 27 , we then proceed to remove the SiO 2 layer 33 and the bands 140, 141 and 142. This provides access to the Si 139 element on the one hand and to the SiGe element 34 on the other.

[0047] Finally, elements 130, 131, and 132 are removed to create grooves by engraving. These grooves are then filled with insulating material to form elements 1320, 1321, and 1322. This creates deep insulation trenches, generally referred to as STI (for Shallow Trench Insulation), as illustrated in the figure 28 This creates an isolation between a first zone of pMOS transistor formation and a second zone of nMOS transistor formation.

[0048] Thus, at the end of the steps of a manufacturing process according to a second embodiment, we have: of a 34 element in compression-stressed SiGe for the formation of the pMOS transistor channel in the first zone; of a 139 element in tension-stressed Silicon for the formation of the nMOS transistor channel in the second zone.

[0049] by epitaxy, with a reduced number of masking and photolithography steps.

[0050] Other areas of the structure may exhibit an unconstrained silicon layer for the formation of other transistors.

[0051] There figure 29 is a cross-sectional view of an example of structure 1 in a one-step manufacturing process, according to a third embodiment which is not covered by the text of the claims. An FDSOI 10 substrate configured to form nMOS and pMOS transistors is initially provided in accordance with the figures 1 And 2 previously described.

[0052] A first deposit 41 of SiGe alloy was formed in the opening 51 on zone 151, as illustrated in the figure 29 A second SiGe alloy deposit 42 was simultaneously formed in aperture 52 on zone 152. Deposits 41 and 42 are typically formed by epitaxial growth. Epitaxial growth processes for SiGe are known to those skilled in the art. Deposits 41 and 42 typically have a thickness between 5 nm and 30 nm. Deposits 41 and 42 include, for example, a germanium concentration (by atom count) between 15 and 35%. Epitaxial growth deposition is, for example, carried out with SiGe containing 30% germanium, at a temperature of 630°C, using H₂ as the carrier gas and germane (GeH₄) and dichlorosilane (DCS, SiH₂Cl₂) as precursors (or silane SiH₄).

[0053] As illustrated in the figure 30 The second deposit 42 is then covered with a layer 26 of hard mask, forming a protective layer. This second deposit 42 is thus protected during subsequent etching steps. Simultaneously, a layer of hard mask 261 is also deposited on the strip 141. Layers 26 and 261 are typically made of SiO₂. These layers 26 and 261 have, for example, a thickness between 10 and 40 nm.

[0054] The first SiGe 41 deposit is then annealed by thermal oxidation. This annealing causes the Germanium from the first deposit 41 to diffuse into the Silicon layer 13, resulting in the formation of the following elements in said layer 13: a SiGe element 44, formed by Ge enrichment of layer 13; residual Si zones 131 and 134. Zone 131 is located vertically along band 141 of the hard mask layer. Zone 134 extends from the vertical line of band 140.

[0055] The upper surface of element 44 is covered with a layer 43 of SiO2, obtained by thermal oxidation of the first deposit 41. The resulting configuration is illustrated in the figure 31 The SiGe element 44 retains the lattice parameters of the original Silicon 13 layer in its plane. The condensation of Germanium in the Silicon 13 layer leads to the creation of a biaxial compressive stress in a plane parallel to the insulating layer 12 within the formed element 44. The boundary between element 44 and zones 131 and 134 is positioned approximately vertically above the lateral faces of strips 141 and 140, respectively. The superposition of element 44 and layer 43 forms a stack.

[0056] As illustrated in the figure 32 Next, a full-plate layer 27 is deposited. Layer 27 is typically made of SOC-type carbon or a silicon-enriched hard mask with an anti-reflective hard mask.

[0057] The previously formed layer 27 then undergoes mechanochemical etching or polishing, stopping at the hard mask layers 26 and 261, as illustrated in the figure 33 . Element 271 is thus formed from layer 27. Element 271 thus forms a protective layer, which protects the first stack from subsequent etching steps.

[0058] The hard mask layers 26 and 261 are then removed by selective etching, thus freeing access to the second deposit 42 previously formed, as illustrated in the figure 34 .

[0059] Next, an inclined implantation process is implemented, for example, using species C (Carbon) or O (Oxygen) in at least two different inclined directions. The implantation can advantageously be carried out in four inclined directions, contained within two perpendicular planes. The inclination allows for a shading effect due to the greater height of bands 140 and 142 relative to the deposit 42. Following this operation, the configuration illustrated in the... is obtained. figure 35 A high concentration of implanted ions is thus present in zone 71 on the surface of band 142. A high concentration of implanted ions is also present in zone 72 on the surface of the second deposit 42 and in zone 73 on the surface. Finally, a high concentration of implanted ions is present in zone 74 on the surface of band 141, as well as on the surface and lateral faces of element 271.

[0060] Next, an advantageously anisotropic etching step is implemented on the second deposit 42 and layer 13. The etching is stopped at layer 12, to obtain the configuration illustrated in the figure 36 This etching process forms an element 421, a remnant of the second deposit 42. This etching also forms grooves 61 and 62, which delimit layer 13 into an element 137 and zones 130 and 132. In this example, a single groove encircles element 137. Layer 12 then forms the bottom of grooves 61 and 62. The superposition of elements 142 and 137 forms a stack. Grooves 61 and 62 typically have a width between 1 and 10 nm. In this example, the etching of grooves 61 and 62 is easily achieved due to the initial absence of a surface implant on the second deposit 42 at the junction of said second deposit 42 and bands 140 on one side and 142 on the other.

[0061] An ionic implantation process then amorphizes element 421 in depth, resulting in the formation of an amorphous SiGe 4212 layer. This ionic implantation also amorphizes element 137, leading to the formation of an amorphous Silicon 138 element. On the surface of element 421, a 4211 layer formed from a non-amorphized SiGe crystal seed is preserved. This results in the configuration illustrated in the... figure 37 The presence of grooves 61 and 62 on either side of layer 4211 allows said layer 4211 to avoid lateral stress and to adopt a relaxed stress state in a plane parallel to layer 12.

[0062] The first protective layer 271 is then removed. Simultaneously, annealing is also carried out to recrystallize layer 4212 and element 138. Annealing is performed, for example, at a temperature of 600°C to 700°C, advantageously maintained for 30 seconds to 5 minutes depending on the thickness of the SiGe / Si stack. The annealing operation results in the configuration illustrated in the figure 38 in which a 4213 layer of relaxed SiGe has reformed above a 139 element of crystalline Si. The 139 element of Si then takes on the lattice parameter of the 4213 layer of relaxed SiGe and thus becomes strained in tension in a plane parallel to the 12 layer.

[0063] The next step involves removing the 4213 layer of SiGe relaxed by etching, which yields the configuration illustrated in the figure 39 . Silicon element 139 maintains a tensile stress in a plane parallel to layer 12.

[0064] As illustrated in the figure 40 , we then proceed to remove the 43 layer of SiO 2 and the bands 140, 141 and 142. This provides access to the SiGe 44 element on the one hand and to the Si 139 element on the other.

[0065] Finally, elements 130, 131, and 132 are removed to create grooves by engraving. These grooves are then filled with insulating material to form elements 1320, 1321, and 1322. This creates deep insulation trenches, generally referred to as STI (for Shallow Trench Insulation), as illustrated in the figure 41 This creates an isolation between a first zone of pMOS transistor formation and a second zone of nMOS transistor formation.

[0066] Thus, at the end of the steps of a manufacturing process according to a third embodiment, we have: of a 44 element in compression-stressed SiGe for the formation of the pMOS transistor channel in the first zone; of a 139 element in tension-stressed Silicon for the formation of the nMOS transistor channel in the second zone.

[0067] Other areas of the structure may exhibit an unconstrained silicon layer for the formation of other transistors.

[0068] Elements 44 and 139 are obtained from the same initial SiGe deposit by epitaxy, with a reduced number of masking and photolithography steps.

[0069] There figure 42 is a cross-sectional view of an example of structure 1 in a one-step manufacturing process, according to a fourth embodiment. An FDSOI 10 substrate configured to form nMOS and pMOS transistors is initially provided in accordance with the figures 1 And 2previously described. In this embodiment, the order of masking of the formation regions of the nMOS and pMOS transistors is reversed compared to the first to third embodiments.

[0070] A first deposit 17 of SiGe alloy was formed in opening 51 on zone 151, as illustrated in the figure 42 A second SiGe alloy deposit 18 was simultaneously formed in aperture 52 on zone 152. Deposits 17 and 18 are typically formed by epitaxial growth with lateral facets. The lateral faces of deposits 17 and 18 are thus inclined. Processes for growing SiGe by epitaxial growth with facets are known to those skilled in the art. Deposits 17 and 18 typically have a thickness between 5 nm and 30 nm. Deposits 17 and 18 include, for example, a germanium concentration (by atomic number) between 15 and 35%. Epitaxial growth deposition is for example carried out with SiGe containing 30% Germanium, at a temperature of 630°C for example, using H2 as carrier gas and Germane (GeH4) and Dichlorosilane (DCS, SiH2Cl2) as precursors (or silane SiH4).

[0071] As illustrated in the figure 43 The second deposit 18 is then covered with a hard mask layer 26. Layer 26 forms a protective layer. The second deposit 18 is thus protected during subsequent etching steps. Simultaneously, the strip 141 is also covered with a hard mask layer 261. Layers 26 and 261 are typically made of SiO₂. These layers 26 and 261 have, for example, a thickness between 10 and 40 nm.

[0072] Simultaneously, a partial etching of the first deposit 17 is carried out, resulting in the formation of an element 171, whose thickness is advantageously between 5 and 15nm.

[0073] Next, the SiGe 171 element undergoes thermal oxidation annealing. This annealing causes the Germanium from element 171 to diffuse into the Silicon 13 layer, resulting in the formation of the following elements in said layer 13: a 172 SiGe element, formed by Ge enrichment of layer 13; residual Si zones 131 and 134. Zone 131 is located vertically above band 141 of the hard mask layer. Zone 134 extends to partir from the vertical of band 140.

[0074] The upper surface of element 172 is covered with a layer 173 of SiO2, obtained by thermal oxidation of element 171. The resulting configuration is illustrated in the figure 44 The superposition of element 172 and layer 173 forms a stack. The SiGe element 172 retains the crystalline parameters of the original Silicon 13 layer. The condensation of Germanium in the Silicon 13 layer leads to the creation of a biaxial compressive stress in a plane parallel to the insulator layer 12 within the formed element 172. The boundary between element 172 and zones 131 and 134 is positioned approximately vertically above the lateral faces of bands 141 and 140, respectively.

[0075] As illustrated in the figure 45 Next, a full-plate layer 27 is deposited. Layer 27 is typically made of SOC-type carbon or a silicon-enriched hard mask with an anti-reflective hard mask.

[0076] The previously formed layer 27 then undergoes chemical etching or polishing, stopping at the hard mask layers 26 and 261, as illustrated in the figure 46 . This forms element 271, remnant of layer 27. Element 271 forms a protective layer, which thus protects layer 173 of SiO 2 and element 172 of SiGe from subsequent etching steps.

[0077] The second protective layer 26 and the hard mask layer 261 are then removed by etching, thus freeing access to the second deposit 18 previously formed, as illustrated in the figure 47 .

[0078] An advantageously anisotropic etching step is then implemented on the second deposit 18 and layer 13. The etching is stopped on layer 12, to obtain the configuration illustrated in the figure 48 This etching process creates grooves 61 and 62, which delineate layer 13 into an element 137 and zones 130 and 132. In this example, a single groove encircles element 137. Layer 12 then forms the bottom of grooves 61 and 62. The superposition of the second deposit 18 and element 137 forms a stack. Grooves 61 and 62 typically have a width between 1 and 10 nm. In this example, the etching of grooves 61 and 62 is easily achieved due to the facets formed during the formation of the second deposit 18. The second deposit 18 thus has a very thin profile near the hard mask 14. Etching near the hard mask 14 therefore makes it easy to reach layer 12 around the second deposit 18.

[0079] Next, ion implantation is performed, which amorphizes the second stack in depth. The amorphization of the second deposit 18 results in the formation of a layer 181 of amorphous SiGe. The amorphization of element 137 results in the formation of an element 138 of amorphous Silicon. On the surface of the second deposit 18, a layer 182 formed from a non-amorphized SiGe crystal seed is preserved. This yields the configuration illustrated in the figure 49 The presence of grooves 61 and 62 on either side of layer 182 allows said layer 182 to avoid lateral stress and to adopt a relaxed stress state in a plane parallel to layer 12.

[0080] Annealing is then performed to recrystallize layer 181 and element 138. Annealing is carried out, for example, at a temperature of 600°C to 700°C, advantageously maintained for 30 seconds to 5 minutes depending on the thickness of the SiGe / Si stack. The annealing process results in the configuration illustrated in the figure 50 in which a relaxed SiGe layer 183 has reformed above a crystalline Si element 139. The Si element 139 then takes on the lattice parameter of the relaxed SiGe layer 183 and thus becomes strained in a plane parallel to the layer 12.

[0081] The layer 183 of relaxed SiGe is then removed by etching, stopping at element 139, which allows us to obtain the configuration illustrated in the figure 51 . Silicon element 139 maintains a tensile stress in a plane parallel to layer 12.

[0082] Next, the SiO2 layer 173 and bands 140, 141 and 142 are removed, as illustrated in the figure 52 This provides access to the SiGe 172 element on the one hand and to the Si 139 element on the other.

[0083] Finally, elements 130, 131, and 132 are removed to form grooves by engraving. The grooves are then filled with insulating material to form elements 1320, 1321, and 1322. This creates deep insulation trenches, generally referred to as STI (for Shallow Trench Insulation in English), as illustrated in the figure 53 This creates an isolation between a first zone of pMOS transistor formation and a second zone of nMOS transistor formation.

[0084] Thus, at the end of the steps of a manufacturing process according to a fourth embodiment, we have: of a 172 element in compression-stressed SiGe for the formation of the pMOS transistor channel in the first zone; of a 139 element in tension-stressed Silicon for the formation of the nMOS transistor channel in the second zone.

[0085] Other areas of the structure may exhibit an unconstrained silicon layer for the formation of other transistors.

[0086] Elements 139 and 172 are obtained from the same initial SiGe deposit by epitaxy, with a reduced number of masking and photolithography steps.

Claims

1. Process for fabricating an integrated circuit (1) comprising an nMOS transistor and a pMOS transistor, comprising the steps of: - providing a substrate (11) comprising a silicon layer (13) placed on a layer of insulator (12), a layer of hard mask (14) placed on the silicon layer, and first and second apertures (51, 52) encircled by the hard mask and giving access to first and second regions (151, 152) of the silicon layer (13), respectively; - carrying out conformal deposition of insulator (23) on the first and second regions (151, 152) and on the hard mask (14); - anisotropically etching the conformal deposit of insulator (23) so as to uncover one portion of the first and second regions (151, 152) and so as to preserve a spacer (231, 232, 233, 234) against sidewalls of the hard mask (14) encircling the first and second apertures (51, 52); - simultaneously forming first and second deposits (31, 32) of SiGe alloy by epitaxy on the first and second regions of the silicon layer in order to form a first stack of the silicon layer and of the first deposit on the one hand, and a second stack of the silicon layer and of the second deposit on the other hand, respectively; - covering the second deposit (32) with a protective layer (24) and maintaining an access to the first deposit (31); then - enriching the first region (151) in germanium by diffusion from the first deposit (31); - depositing a protective layer (251) on the first stack; - removing the protective layer (24) from the second deposit (32); - carrying out an etch up to the layer of insulator (12), in order to form trenches (61, 62) between the hard mask (14) and two opposite edges of the second stack, this etching step comprising an etch of said spacers and an etch of the periphery of the second region; then - forming a tensilely strained silicon layer (139) in the second region via an amorphization of the second region and of the bottom portion of the second deposit and preservation of a crystallized top portion (321) in the second deposit; then - removing the protective layer 251 from the first stack; - crystallizing the second deposit and the second region in order to tensilely strain the second region.

2. Fabricating process according to Claim 1, wherein said enrichment of the first region in germanium comprises a step of condensing germanium into the first region.

3. Fabricating process according to Claim 2, wherein said enrichment comprises a step of thermally oxidizing and annealing the second deposit.

4. Fabricating process according to any one of the preceding claims, wherein the crystallization of the second deposit and of the second region in order to tensilely strain the second region is followed by a step of removing the second deposit.

5. Fabricating process according to any one of the preceding claims, wherein said etching step forms a trench between a portion of the hard mask separating the first and second apertures and an edge of the second stack.

6. Fabricating process according to any one of the preceding claims, wherein said first and second deposits are formed so as to have a height smaller than that of the hard mask, the process comprising steps of inclined implantation of carbon or of oxygen into said second deposit in at least two different implantation directions, so as to form a median region of the second deposit, in which region the concentration of implanted ions is higher than the concentration of implanted ions on the periphery of this second deposit, said step of etching up to the layer of insulator comprising an etch of the periphery of the stack of the second region and of the second deposit.

7. Fabricating process according to any one of the preceding claims, comprising a step of forming a deep trench isolation between the first and second apertures subsequently to the steps of crystallizing the second deposit and the second region in order to tensilely strain the second region.

8. Fabricating process according to any one of the preceding claims, comprising a step of forming an nMOS transistor the channel of which includes said second tensilely strained region, and comprising a step of forming a pMOS transistor the channel of which includes said first region enriched in germanium.

9. Fabricating process according to any one of the preceding claims, wherein said first and second deposits have a germanium concentration comprised between 15 and 35%.