METHOD FOR SYNCHRONIZING ANALOGUE DATA AT THE OUTPUT OF A MULTIPLE OF DIGITAL / ANALOGUE CONVERTERS

Description

[0001] The present invention relates to a method for synchronizing analog data output from a plurality of digital-to-analog converters onto the same active edge of a common reference clock. It also relates to a device for synchronizing analog data output from a plurality of digital-to-analog converters onto the active edge of a common reference clock for implementing the method of the invention.

[0002] For certain applications, such as matrix antennas or MIMO antennas (Multiple-Input, Multiple-Output antennas), using several digital / analog converters and incoming digital data via serial link, it is necessary to synchronize the converters with each other.

[0003] To achieve this, a synchronization signal supplied to the converters initially synchronizes their internal clocks. Given the high sampling frequency of the converters (from 1 to several gigahertz), the synchronization signal must be very fast, i.e., a few picoseconds, and occur within a time window much shorter than a clock cycle of the converters' clocks.

[0004] Then, in a second step, the data arriving at the input of the converters must be aligned with each other. However, the propagation delays of signals on the traces of a circuit board are on the order of 6 ps / mm. Therefore, in order for all the digital data supplied to the input of the converters to arrive simultaneously at all the converters, the length of the trace carrying this data must be adjusted. For some applications, the physical distance between the components makes this trace length alignment difficult, or even impossible.

[0005] To overcome this problem, various solutions exist to synchronize converters regardless of track lengths up to the different converters.

[0006] One solution involves sending a phase-synchronizing pulse to all converters, its distribution designed to obtain the appropriate propagation delay for each converter, so that the active clock edges, on which the converters' frequency dividers will be initialized, coincide. That is, pairwise, the active edges will all be separated by a number of periods of the reference clock that is a multiple of N: 0, N, 2N, ... Everything is determined by the design of the distribution paths of the reference clock and the synchronizing signal on each converter. This requires a precise evaluation of the propagation delays on each converter.This first solution is quite simple to implement when the working frequencies are low, but when they are above 100 MHz, it becomes increasingly difficult to evaluate propagation delays and to respect time constraints.

[0007] Other solutions modify the sampling clock, which has the effect of degrading the signal of this clock through jitter problems and therefore degrading the performance of the converters.

[0008] Some solutions use subdivisions of the sampling frequency and a master / slave system between the converters and the electronic circuit controlling the synchronization signal to achieve converter synchronization. However, these solutions limit the system's temperature tolerance and complicate clock management within the system.

[0009] EP3375092A1 discloses a device for synchronizing analog data output from one of the plurality of digital / analog converters on an active edge of one of the common reference clocks.

[0010] The invention aims to remedy the aforementioned drawbacks of the prior art, more particularly it aims to offer a solution enabling the synchronization of analog data at the output of digital / analog converters on the same active edge of the clock common to all converters, the synchronization being carried out internally by the converters.

[0011] An object of the invention is therefore a method for synchronizing analog data output from a plurality of digital / analog converters, comprising at least one conversion core, on an active edge of a common reference clock, characterized in that the method comprises the following steps: a) Provide an external synchronization signal, issued by a control unit, to at least one converter of the plurality of converters, and provide a clock signal from the common reference clock to the plurality of converters; b) Generate within each converter of the plurality of converters an internal synchronization signal from the external synchronization signal, such that all internal synchronization signals are aligned on an active edge of the common reference clock; c) Generate, by at least one electronic circuit internal to each converter of the plurality of converters, a start signal representing the beginning of the sending of digital data by the control unit, on each core of the plurality of converters and count a number of clock cycles between the generation of the start signal and the generation of the internal synchronization signal for each of the cores of the plurality of converters;d) Apply a delay Ri, to each core i of the plurality of converters, equal to the difference between the highest number counted in step c) and the number counted in step c) for core i, i being an integer between 1 and the number of cores in the plurality of converters. ;

[0012] According to specific embodiments of such a process: Internal synchronization signals can be generated in step b) by resampling the external synchronization signal. The converters of the plurality of converters can form a serial transmission chain for the external synchronization signal, step a) also comprising: the initialization in each converter of the plurality of converters of a synchronization circuit having at least one polarity parameter defining as the polarity of a reference clock edge, for signal detection at the input of the converters' synchronization circuit, the polarity of the active edge of the reference clock or the inverse polarity; and step b) also includes: the detection of a synchronization signal at the input of the synchronization circuits of each converter, on a reference clock edge, which has the polarity defined by the value of the polarity parameter of the synchronization circuit; and the alignment on the next active edge of the detected signal to provide an internal synchronization signal aligned on an active edge of reference clock at the output of the synchronization circuit of the converter.

[0013] Another object of the invention is a device for synchronizing analog data output from a plurality of digital-to-analog converters on an active edge of a common reference clock for implementing such a method, comprising: a plurality of digital-to-analog converters comprising: N conversion cores and N memories, each converter comprising at least one digital input, at least one analog output, at least one of the N memories, at least one of the N conversion cores and a synchronization circuit connected to the digital input, the synchronization circuits of the converters being connected to each other in cascade, the memories of the converters each being connected to a conversion core of the converter and the synchronization circuit of the converters being configured to generate an internal synchronization signal and such that the generated internal synchronization signals are aligned to an active edge of a common clock, and N being an integer greater than or equal to 1; and a control unit configured to send a signal from the common reference clock, the external synchronization signal and digital data to each converter;characterized in that each converter also includes a data decoding circuit, including a counter, for each conversion core included in the converter, the data decoding circuits being placed at the output of the synchronization circuit and at the input of the memories and configured to generate the start signals, representative of the start of the sending of digital data on a conversion core and each counter being configured to count the number of clock cycles between the generation of the start signal and the generation of the internal synchronization signal of the conversion core, and in that the i-th memory is configured to apply the delay Ri to the i-th conversion core, i being an integer between 1 and N.;

[0014] According to particular embodiments of such a device: The control unit may include at least one programmable logic circuit configured to send the external synchronization signal.

[0015] The control unit may include at least one programmable logic circuit configured to send digital data.

[0016] The control unit can also be configured to receive the number of clock ticks counted by the N counters, to determine the delays Ri and to provide the N memories with a value of the delay Ri to be applied to the i-th conversion core.

[0017] The N memories can be shift registers.

[0018] The plurality of converters can include N converters, each converter comprising a single conversion core out of the N conversion cores.

[0019] Other features, details and advantages of the invention will become apparent from the description provided with reference to the accompanying figures given by way of example, which represent, respectively: [ Fig.1 ], a diagram of the steps of the process according to the invention; [ Fig.2 ], a device for implementing the process according to the invention; and [ Fig. 3 ], an example of a multi-core digital / analog converter enabling the implementation of the process according to the invention.

[0020] [ Fig. 1 Figure 1 represents a diagram of the steps of the process according to the invention. The first step, step a), consists of providing at least one converter of a plurality of digital-to-analog converters with an external synchronization signal SYNC_ext. The external synchronization signal SYNC_ext is emitted by a control unit CU controlling the plurality of converters.

[0021] The second step, step b), consists of generating an internal synchronization signal SYNC_int within each converter. These internal synchronization signals SYNC_int are synchronized with each other on an active edge of a common reference clock Clk.

[0022] The alignment of the internal synchronization signals SYNC_int can be performed outside the converters using delay lines, dedicated to the external synchronization signal SYNC_ext, between the control unit (CU) and the converters. In this case, all converters receive the external synchronization signal SYNC_ext directly and simultaneously via the delay lines, and therefore the internal synchronization signals SYNC_int generated by the converters are synchronized to the same clock edge. The internal synchronization signal SYNC_int is thus generated directly within each converter from the external synchronization signal SYNC_ext.

[0023] This alignment can also be performed, preferably, within the converters using the method described in French patent no. 1560739. This method consists of configuring the plurality of converters in a serial chain and replacing the phase distribution of the SYNC_ext synchronization signal across all converters with the transmission of this external SYNC_ext synchronization signal from one converter to another, reaching all converters in the chain in succession. In other words, only the first converter directly receives the external SYNC_ext synchronization signal, then it generates an internal SYNC_int synchronization signal which it transmits to the next converter, which in turn generates an internal synchronization signal which it transmits to the next converter, and so on, until the last converter in the chain is reached.In this case, the internal synchronization signal SYNC_int is generated indirectly, within each converter, from the external synchronization signal SYNC_ext, by step-by-step transmission.

[0024] This is achieved in combination with a parameterization of each converter in the chain which reflects the propagation delays of the SYNC_ext synchronization signal in this chain of converters and by which an internal synchronization signal SYNC_int is transmitted at the output of each converter which is resynchronized for the next converter.

[0025] In this method, the converters form a serial transmission chain for a synchronization signal; that is, each converter includes a synchronization circuit connected in series with the other synchronization circuits of the converters in the plurality of converters. Furthermore, step a) of the method also includes initializing the synchronization circuit (CS, CS1, CS2, CSI) in each converter of the plurality of converters. This circuit must have at least one polarity parameter defining the polarity of a reference clock edge, for the input signal detection of the converters' synchronization circuit, as either the polarity of the active edge of the reference clock or the inverse polarity.

[0026] Step b) also includes the detection of a synchronization signal (SYNC_ext, SYNC_int1, SYNC_int2) arriving at the input of the synchronization circuits of each converter and coming from the synchronization circuit of the preceding converter in the transmission chain (or from the control unit for the first converter in the chain), on a reference clock edge, which has the polarity defined by the value of the polarity parameter of the synchronization circuit.

[0027] Then, step b) includes aligning to the next active edge of the detected signal to provide an internal synchronization signal (SYNC_int1, SYNC_int2, SYNC_intl) aligned to an active edge of reference clock output of the converter synchronization circuit.

[0028] In each converter, the parameter setting also allows you to choose the correct reference clock edge which retrieves the signal that resets the sampling clock generator, allowing the sampling clocks of all converters to be synchronized in phase.

[0029] Then, the third step of the process according to the invention, step c), consists of generating a START signal representing the beginning of the transmission of digital data, by the control unit, to each core of the plurality of converters. This START signal is an internal signal for each converter, emitted for each conversion core, indicating to all the converter cores that the next data received by the core is the first useful data, and therefore the first useful data to be converted. The start signal(s) are generated by the converter's decoding block, which includes one or more decoding circuits (Dec) depending on the number of conversion cores. This is described in more detail with reference to the figures 2 And 3 .

[0030] This START signal is generated upon the arrival of the very first useful data. In other words, as soon as the converter receives the first data from the serial link sent by the control unit, it generates the START signal.

[0031] Then, in step c), the number of clock cycles between the generation of the START signal and the generation of the internal synchronization signal SYNC_int is counted for all conversion cores. This can be done using a Cpt counter present in each converter and for each conversion core within the converters.

[0032] Then, in the last step, step d), a delay Ri is applied to each core i of the plurality of converters, equal to the difference between the highest number counted in step c) and the number counted in step c) for core i, i being an integer between 1 and the number of cores in the plurality of converters.

[0033] For example, consider three converters, each with a single conversion core. The first converter has 13 clock cycles between receiving the START signal and its internal synchronization signal SYNC_int, the second converter has 17 clock cycles, and the third converter has 14 clock cycles. Since the highest count is 17, we will apply a delay R1 to the first converter equal to 17 - 13, or a delay of 4 clock cycles. For the second converter, its delay R2 will be 0, as it serves as the reference, and finally, for the third converter, we will apply a delay R3 equal to 17 - 14, or a delay of 3 clock cycles.

[0034] If the converters include several conversion cores, the same principle is applied. The number of clock cycles between the reception of the START signal and the internal synchronization signal SYNC_int is counted for each core of all converters, then a delay is applied to each core equal to the difference between the highest number counted for all cores and all converters and the number counted for the core in question.

[0035] Applying a delay to each core allows all cores to be synchronized to the slowest conversion core, thus obtaining, at the output of the conversion cores, converted and synchronized data on the same active edge of the common reference clock.

[0036] [ Fig. 2 ] presents an example of a synchronization device enabling the process according to the invention to be implemented, and applying the method of French patent no. 1560739 for step b) of the process.

[0037] The device comprises a control unit (CU) and a plurality of digital-to-analog converters (DAC1, DAC2, DACI). The control unit (CU) provides at least one DAC1 converter from the plurality of DAC1, DAC2, DACI converters with an external synchronization signal (SYNC_ext). It also provides a clock signal from the common reference clock (Clk) and the digital data (Data_num1, Data_num2, Data_numl) transmitted serially to the plurality of DAC1, DAC2, DACI converters.

[0038] As shown in the figure, the reception of external synchronization signals SYNC_ext by DAC1 and internal SYNC_int1 by DAC2 and SYNC_int2 by DACI, allowing the generation of internal synchronization signals SYNC_int1, SYNC_int2 and SYNC_int1 according to the method of French patent no. 1560739, or of digital data Data_num1, Data_num2, Data_numl on the converters is not synchronized on the same active edge of the Clk clock.

[0039] Each converter DAC1, DAC2, DACI includes, in this example, a synchronization circuit CS, a data decoding circuit Dec including a counter Cpt, a memory M and a conversion core C.

[0040] The CS synchronization circuits of the DAC1, DAC2, and DACI converters form a serial transmission chain. Thus, the synchronization circuit of the first converter, DAC1, is connected to the control unit, and its output is connected to the input of the synchronization circuit of the second converter, DAC2. The output of the CS circuit of the second converter, DAC2, is connected to the input of the CS circuit of the third converter, DACI.

[0041] The CS synchronization circuit will generate the internal synchronization signal SYNC_int1, SYNC_int2, SYNC_intl within each converter DAC1, DAC2, DACI so that all the SYNC_int1, SYNC_int2, SYNC_intl signals of the converters are aligned on an active edge of the common clock Clk, which corresponds to the execution of step b) of the method according to the invention.

[0042] The data decoding circuit receives the internal synchronization signal SYNC_int1 for DAC1, SYNC_int2 for DAC2, and SYNC_intl for DACI from the converter's synchronization circuit (CS), as well as the digital data sent by the control unit (CS): Data_num1 for DAC1, Data_num2 for DAC2, and Data_numl for DACI. Upon receiving the digital data, this data decoding circuit generates a START signal (START1 in DAC1, START2 in DAC2, and STARTI in DACI), representing the converter's receipt of the first digital data.

[0043] The device shown in this figure allows the application of the method described in French patent no. 1560739. Therefore, only the CS synchronization circuit of the DAC1 converter receives the external synchronization signal SYNC_ext emitted by the control unit (CU). The CS synchronization circuit of DAC1 then generates an internal synchronization signal SYNC_int1, which is transmitted to the decoding circuit (Dec) of DAC1 and to the CS synchronization circuit of DAC2. The CS synchronization circuit of DAC2 then generates an internal synchronization signal SYNC_int2, which is transmitted to the decoding circuit (Dec) of DAC2 and to the CS synchronization circuit of the DACI converter. The CS synchronization circuit of the last DACI converter generates an internal synchronization signal SYNC_intl, which is transmitted only to the decoding circuit (Dec) of the last DACI converter.

[0044] The Cpt counter in the Dec decoding circuits is configured to count the number of clock cycles between the generation of the START signal and the generation of the internal synchronization signal SYNC_int by the Dec decoding circuit. Therefore, the Cpt counter of DAC1 counts the number of clock cycles between the START1 signal and the SYNC_int1 synchronization signal, the Cpt counter of DAC2 counts the number of clock cycles between the START2 signal and the SYNC_int2 synchronization signal, and the Cpt counter of DACI counts the number of clock cycles between the START1 signal and the SYNC_int1 synchronization signal.

[0045] Memory M is configured to apply a delay Ri to the transmission of data to be converted between the data decoding circuit Dec and the conversion core C. This delay Ri is the one described in step d) with reference to the figure 1 . It is therefore equal to the difference between the number of clock cycles counted by all the highest counters and the number of clock cycles counted for the converter including this memory.

[0046] To calculate this delay, the counter Cpt can send the number of clock cycles counted to the control unit UC, which analyzes all the received counts to determine which converter (specifically the conversion core) is the slowest—that is, the conversion core providing the analog data last among all the cores in the plurality of converters. Then, the control unit UC then controls the delays Ri: R1, R2, RI applied by the different memories M.

[0047] Finally, the conversion core C is configured to perform the conversion of the digital data Data_num1, Data_num2, Data_numl into analog data Data_ana1, Data_ana2, Data_anal retrieved from the output of the converter DAC1, DAC2, DACI. All the analog data Data_ana1, Data_ana2, Data_anal output from the conversion cores C are then aligned to the same active edge of the clock Clk.

[0048] [ Fig.3 ] presents another example of a device for implementing the process according to the invention, and more particularly an example of a DAC converter having several conversion cores C1 and C2.

[0049] In the case of a converter with two conversion cores C1 and C2, the DAC includes a synchronization circuit CS, two data decoding circuits Dec1 and Dec2, therefore two counters Cpt1 and Cpt2, and two memories M1 and M2. The synchronization circuit CS receives an external synchronization signal SYNC_ext from the control unit UC, then generates an internal synchronization signal SYNC_int which is transmitted to the two data decoding circuits Dec1 and Dec2.

[0050] The decoding circuits Dec1 and Dec2 are each connected to the same synchronization circuit CS, but are each connected to a memory and a core (M1 and C1 for the Cpt1 circuit and M2 and C2 for the Cpt2 circuit).

[0051] The CS synchronization circuit can also receive a synchronization signal from another converter, if the DAC belongs to a plurality of converters, as described in the figure 2 .

[0052] Then each of the data decoding circuits Dec1 and Dec2 receives digital data Data_num1 for Dec1 and Data_num2 for Dec2 from the control unit UC and therefore each generates a START1 and START2 signal representing the arrival of the first data to be converted on the conversion core C1 and C2.

[0053] The Cpt1 counter of the Dec1 decoding circuit then counts the number of clock strokes between the generation of the START1 signal and that of the SYNC_int signal, while the Cpt2 counter of the Dec2 decoding circuit counts the number of clock strokes between the generation of the START2 signal and that of the SYNC_int signal.

[0054] The control unit (CU) receives the clock cycle counts from the two counters Cpt1 and Cpt2 and can then determine which of the converter's C1 and C2 cores is the slowest, and more generally, which of all the converter cores distributed across the converters is the slowest. The slowest core will then be the reference for calculating the delay to be applied to the other converter cores.

[0055] Next, the M1 and M2 memories are configured to apply a delay R1 and R2 and thus synchronize the arrival of the data to be converted on each core to the slower core.

[0056] The control unit (CU) can be implemented using a programmable logic device (FPGA). It is designed to control all the DAC1, DAC2, and DACI converters and their C1 and C2 conversion cores, using a master / slave communication scheme via a peripheral interface bus such as the SPI (Serial Peripheral Interface), a widely used synchronous serial data bus. The SPI bus enables data exchange between the control unit (UC) and the DAC1, DAC2, and DACI converters and their C1 and C2 cores, specifically the data to be converted.

[0057] The control unit (CU) can also include one or more FPGA-type programmable logic devices. In the case of multiple devices, one FPGA can be dedicated to sending digital data to the converters, while a second FPGA can be dedicated to sending the external synchronization signal SYNC_ext. It is also possible to have dedicated FPGAs for sending digital data, with one dedicated to a single converter.

[0058] The M memories present in the DAC converters, DAC1, DAC2, DACI can be shift registers whose register length is equal to the difference between the highest number of clock strokes counted among all the converter cores and the number counted for the core connected to that register.

Claims

1. A method for synchronising analogue data (Data_anal, Data_ana2, Data_anal) at an output of a plurality of digital / analogue converters (DAC, DAC1, DAC2, DACI), comprising at least one conversion core (C, C1, C2), on an active edge of a common reference clock (Clk), wherein the method comprises the following steps: a) Supplying an external synchronisation signal (SYNC_ext), emitted by a control unit (UC), to at least one converter of the plurality of converters, and supplying a clock signal of the common reference clock to the plurality of converters; b) Generating, within each converter of the plurality of converters, an internal synchronisation signal (SYNC_int, SYNC_int1, SYNC_int2, SYNC_intl) based on the external synchronisation signal, such that all the internal synchronisation signals are aligned on an active edge of the common reference clock; c) Generating, by means of at least one electronic circuit internal to each converter of the plurality of converters, a start signal (START1, START2, STARTI) which represents the start of the sending of digital data (Data_numl, Data_num2, Data_numl) by the control unit, on each core of the plurality of converters, and counting a number of clock strokes between the generation of the start signal and the generation of the internal synchronisation signal for each of the cores of the plurality of converters; and d) Applying a delay Ri (RI, R2, RI) to each core i of the plurality of converters, equal to the difference between the highest number counted in step c) and the number counted in step c) for the core i, i being an integer between 1 and the number of cores of the plurality of converters.

2. The method for synchronising analogue data according to claim 1, wherein the internal synchronisation signals are generated in step b) by resampling the external synchronisation signal.

3. The method for synchronising analogue data according to one of the preceding claims, wherein the converters of the plurality of converters form a serial transmission chain for the external synchronisation signal, and step a) also comprises: - initialising, in each converter of the plurality of converters, a synchronisation circuit (CS, CS1, CS2, CSI) including at least one polarity parameter defining, as polarity of a reference clock edge, for detecting signals at the input of the synchronisation circuit of the converters, the polarity of the reference clock active edge or the opposite polarity; and step b) also comprises: - detecting a synchronisation signal (SYNC_ext, SYNC_int1, SYNC_int2) at the input of the synchronisation circuits of each converter, on a reference clock edge, which has the polarity defined by the value of the polarity parameter of the synchronisation circuit; and - aligning, on the following active edge, the detected signal in order to supply an internal synchronisation signal (SYNC_int1, SYNC_int2, SYNC_intl) aligned on a reference clock active edge at an output of the synchronisation circuit of the converter.

4. A device for synchronising analogue data at an output of the plurality of digital / analogue converters on an active edge of the common reference clock (Clk) for performing the method according to the preceding claim, the device comprising: - the plurality of digital / analogue converters (DAC, DAC1, DAC2, DACI) comprising: - N conversion cores (C, C1, C2) and - N memories (M, M1, M2), each converter comprising at least one digital input, at least one analogue output, at least one of the N memories, at least one of the N conversion cores and a synchronisation circuit (CS, CS1, CS2, CSI) connected to the digital input, the synchronisation circuits of the converters being connected to one another in a cascade, the memories of the converters each being connected to a conversion core of the converter and the synchronisation circuit of the converters being configured so as to generate an internal synchronisation signal (SYNC_int, SYNC_int1, SYNC_int2, SYNC_intl) and so that the internal synchronisation signals generated are aligned on an active edge of a common clock, and N being an integer greater than or equal to 1; and - the control unit (UC) configured so as to send a signal from the common reference clock (Clk), the external synchronisation signal (SYNC_ext) and digital data (Data_num1, Data_num2, Data_numl) to each converter; characterised in that each converter also comprises a data decoding circuit (Dec1, Dec2, Dec), comprising a counter (Cpt, Cpt1, Cpt2), for each conversion core included in the converter, the data decoding circuits being placed at an output of the synchronisation circuit and at an input of the memories and configured so as to generate the start signals (START1, START2, STARTI) which represent a start of the sending of digital data on a conversion core and each counter being configured so as to count a number of clock strokes between the generation of the start signal and the generation of the internal synchronisation signal of the conversion core, and in that the ith memory is configured so as to apply the delay Ri (R1, R2, RI) to the ith conversion core, i being an integer between 1 and N.

5. The device for synchronising analogue data according to the preceding claim, wherein the control unit comprises at least one programmable logic circuit configured to send the external synchronisation signal.

6. The device for synchronising analogue data according to one of claims 4 or 5, wherein the control unit comprises at least one programmable logic circuit configured to send the digital data.

7. The device for synchronising analogue data according to one of claims 4 to 6, wherein the control unit is also configured to receive the number of clock strokes counted by the N counters, to determine the delays Ri and to supply, to the N memories, a delay value Ri to be applied to the ith conversion core.

8. The device for synchronising analogue data according to one of claims 4 to 7, wherein the N memories are shift registers.

9. The device for synchronising analogue data according to one of claims 4 to 8, wherein the plurality of converters comprises N converters, each converter comprising a single conversion core from the N conversion cores.

10. The method according to claim 1, wherein the external synchronisation signal (SYNC_ext) is supplied to each converter of the plurality of converters via a respective delay line between the control unit (UC) and each converter.

11. The method according to claim 1, wherein: the external synchronisation signal (SYNC_ext) is supplied to a first converter of the plurality of converters, wherein each converter of the plurality of converters comprises a synchronisation circuit, and wherein the synchronisation circuits of the plurality of converters form a serial transmission chain for the external synchronisation signal; and the generation of the internal synchronisation signal comprises : generating, in the first converter, the internal synchronisation signal (SYNC_intl) from the external synchronisation signal received at an input of the synchronisation circuit of the first converter; and generating, in each remaining converter of the plurality of converters, the internal synchronisation signal (SYNC_int2, SYNC_intl) from the internal synchronisation signal transmitted by a preceding converter in the serial transmission chain and arriving at an input of the synchronisation circuit of the converter.