ELECTRONIC VOLTAGE DIVISION SWITCHING IN FDSOI TECHNOLOGY

Description

[0001] The present invention relates to a voltage divider circuit comprising transistors on thin insulating film (or FDSOI type, or "Fully Depleted Silicon On Insulator" in English), and which can be used in different circuits, for example a clock generation circuit including a ring oscillator.

[0002] Ring oscillators consist of an odd number of inverters forming a loop. At the output of each inverter, a naturally oscillating signal is obtained. Their oscillation frequency is based on the switching time of the inverters, it is therefore directly related to the number of inverters in the loop. The more inverters there are, the more the oscillation frequency decreases. The switching time of an inverter depends on various parameters, including their supply voltage, their temperature, and this switching time can vary from one inverter to another due to technological dispersions. The oscillation frequency is therefore highly dependent on these parameters and can be difficult to control and stabilize.

[0003] In order to solve this problem, the prior art includes ring oscillators comprising a circuit for generating a current / voltage supply comprising a differential amplifier AO and a reference resistor R ref , as shown in figure 1A .

[0004] The operating principle of this type of oscillator is to control the intrinsic resistance (coming from inverters I1, I2 and I3 which can be likened to switching capacitors) of the inverter chain I1, I2, I3 relative to the reference resistance R ref . The reference resistance R ref is fixed. The intrinsic resistance is then equal to the reference resistance R ref , because the potentials V ro and V res are identical and the currents ires, i ro flowing in the two branches B res and B ro are identical.

[0005] This type of oscillator oscillates at a frequency f depending on the intrinsic resistance, therefore on the reference resistance R ref , on an equivalent capacitance C representing the switching of the inverters I1, I2 and I3 and on a parameter n representing the number of inverters in the loop, such that f = 1 / (nx C x R ref ).

[0006] However, for low-power oscillators, it is necessary to use a high-value reference resistor R ref (around 10 to 100 MΩ), because the potentials V res and V ro at the input of the AO amplifier are a few hundred millivolts and the currents are as low as possible for consumption reasons. The resistor R ref is therefore bulky and expensive in terms of silicon surface area. For example, for a voltage V ro = V res = 500 mV and a current i of 100 nA, it will be necessary to use a resistor R ref of 5 MΩ. The resistor R ref will therefore be bulky and will represent, in practice, almost 80% of the silicon surface area of ​​the oscillator.

[0007] This architecture requires a compromise between the oscillation frequency, the power consumption and the silicon area of ​​the reference resistor R ref in a low power application (about 10 to 50 nW).

[0008] Furthermore, a disadvantage of the oscillator circuit shown in figure 1 is that it is difficult in practice to make it insensitive to temperature variations. If the value of the reference resistor varies according to the temperature then the frequency of the oscillator will also vary. Thus, the use of such an oscillator requires the use of resistors that are little or not sensitive to temperature if we do not want to cause variations in the oscillation frequency. This limits the possibilities for producing resistors and can lead to additional surface cost to produce such resistors insensitive to temperature variations. In addition, it is rarely possible to have a temperature-compensated resistor, especially in FDSOI technologies.

[0009] More generally, this problem of silicon surface area footprint also arises in all applications using a reference resistor, for example for reference current or reference voltage generators or more generally for all analog voltage / current conversion schemes implemented in current generators, analog-to-digital converters or oscillators.

[0010] There figure 1B represents an example of a circuit for generating a reference current. The reference voltage V ref used in such a circuit is generally provided by a "bandgap" circuit delivering a "high" voltage (typically 1.2V). If we also want to have lower power consumption, it is necessary that the current flowing in the resistor is as low as possible. Thus, as for the oscillator, it is necessary that the resistor has a high value. It should also be noted that this type of circuit also requires the use of a resistor insensitive to temperature variations if we want to obtain a generated reference current that is invariant in temperature. US 2016 / 352339 A1 discloses a PTAT current source for biasing a ring oscillator, in which a bias adjustment circuit adjusts the voltage of the gate on the rear face of at least one transistor of the PTAT current source.

[0011] The invention aims to remedy the aforementioned drawbacks of the prior art, by proposing an electronic voltage divider circuit produced using FDSOI (thin insulating film transistor) technology.

[0012] According to the invention, this aim is achieved through clever use of the rear gate biases of FDSOI type transistors of a circuit usually used to produce a current source.

[0013] An object of the invention is therefore an electronic voltage divider circuit, in accordance with independent claim 1 in the appendix, comprising at least two insulating thin-film transistors FDSOI of a first type connected to a first supply potential and arranged in a current mirror structure and two thin-film transistors FDSOI of a second type and an electrical load of non-zero impedance, the transistors each having a main gate on the front face and an adjustment gate on the rear face, a drain of a first transistor of the second type being connected to the drain of a first transistor of the first type, a drain of a second transistor of the second type being connected to the drain of a second transistor of the first type, the drain of the first transistor of the second type being connected to the gate on the front face of this same transistor, the gates on the front face of the first and second transistors of the second type being connected to each other,the source of the first transistor of the second type being connected to a second supply potential and said non-zero impedance load being placed between the source of the second transistor of the second type and said second supply potential, characterized in that the rear-face gates of the first and second transistors of the second type are connected to an external circuit applying a non-zero input voltage between these two rear-face gates, such that the rear-face gate of the first transistor of the second type is brought to a potential (V BBN1 ) lower than that (V BBN2 ) of the rear-face gate of the second transistor of the second type if these two transistors are of the nMOS type, and that the rear-face gate of the first transistor of the second type is brought to a potential (V BBP 1 ) higher than that (V BBP2 ) of the rear-face gate of the second transistor of the second type if these two transistors are of the pMOS type,whereby the voltage across the terminals of said load constitutes an output voltage equal to a fraction of the input voltage.

[0014] Another object of the invention is an electronic system comprising such an electronic circuit and comprising a third transistor of the first type whose source is connected to the first supply potential, the gate being connected to the gates of the first and second transistors of the first type, and the drain being connected to a node connected to a load circuit.

[0015] Particular embodiments of the electronic voltage divider circuit and the electronic system constitute the subject matter of the dependent claims.

[0016] Other characteristics, details and advantages of the invention will emerge from reading the description given with reference to the appended figures given by way of example and which represent, respectively: [ Fig.1A ], already described, a ring oscillator comprising an inverter loop according to the prior art; [ Fig.1B ], already described, a current source comprising a resistor and a circuit for controlling the voltage across the resistor according to the prior art; [ Fig. 2 ], a FDSOI type transistor according to the prior art; [ Fig.3 ], an electronic circuit generating a reference voltage according to a first embodiment of the invention; [ Fig. 4] et [Fig. 5 ], the ratio between two potentials as a function of temperature for two types of transistors of the circuit according to the first embodiment of the invention; [ Fig. 6 ], an electronic circuit according to a second embodiment of the invention; [ Fig. 7 ], a ring oscillator according to a first embodiment of the invention; [ Fig. 8 ], the oscillation frequency as a function of the temperature of the oscillator according to the first embodiment of the invention determined by simulation; [ Fig. 9 ], a ring oscillator according to a second embodiment of the invention; [ Fig. 10 ], a current generator produced from a circuit according to the invention; and [ Fig. 11a ] And [ Fig. 11b ], simulation results obtained for the current generator of the figure 10 .

[0017] [ Fig. 2 ] represents the internal structure of an FDSOI transistor (transistor made on a thin insulating film). The FDSOI transistor comprises a layer of a p-type silicon substrate Sub, a buried layer of an insulating material Iso, also called BOX, separated from the substrate Sub by a ground plane PM. The insulating layer Iso is topped by an active layer of silicon Act in which are placed a source S, a channel C and a drain D. The ground plane PM (or NWELL or PWELL box depending on its doping) improves the electrostatic control of the transistor by limiting the penetration of the electric fields generated by the drain D and the source S under the channel C. The channel C is covered with a layer of gate oxide OxG. The gate oxide OxG is topped by a metal gate G. The FDSOI transistor has a front-side gate Gtop and a rear-side gate Gback .The front-panel gate G top is the main gate used to select the transistor's operating mode (off, on). The rear-panel gate G back is a control gate; the voltage applied to this rear gate allows the transistor's operating characteristics, including its threshold voltage, to be varied.

[0018] Generally speaking, it is possible to vary the threshold voltage V th of FDSOI transistors by varying the n or p doping of the PM well, the gate connection metal and the well voltage relative to the source voltage applied to the transistor. To provide different types of transistor (different threshold voltage V th ), the manufacturing process relies on the gate connection metal and the well doping (n or p). A low V th transistor, called an LVT transistor (Low Threshold Voltage), will have a rather low V th voltage (around 400 to 450 mV) and a high V th transistor, called an RVT transistor (Regular Threshold Voltage) will have a rather higher V th voltage (around 500 to 550 mV).

[0019] In the use of transistors, the dynamic modification of the threshold voltage V th of the transistors occurs by modifying the voltage difference between the well and the source, which advantageously makes it possible to obtain lower threshold voltages V th with LVT transistors (classically used to accelerate its speed) and to obtain higher threshold voltages V th with RVT transistors (classically used to control and limit static leaks). Indeed, a PM ground plane of the same type as the source S and the drain D makes it possible to obtain an FDSOI transistor having a low threshold voltage value V th , while a PM ground plane of a different type from the source S and the drain D makes it possible to obtain an FDSOI transistor having a high threshold voltage value V th .

[0020] An FDSOI nMOS LVT transistor therefore has an n-doped D drain and S source and an n-doped PM ground plane (i.e., an n-doped NWELL well), while an nMOS RVT transistor has an n-doped D drain and S source and a p-doped PM ground plane (i.e., a p-doped PWELL well).

[0021] An FDSOI pMOS LVT transistor has a p-doped D drain and S source and a p-doped PM ground plane (i.e., a p-doped PWELL well), while an FDSOI pMOS RVT transistor has a p-doped D drain and S source and an n-doped PM ground plane (i.e., an n-doped NWELL well).

[0022] A detailed description of the different possibilities for producing transistors with higher or lower threshold voltage ranges is provided in the applicant's patent EP2415079.

[0023] [ Fig.3 ] represents an electronic voltage divider circuit according to a first embodiment of the invention. Two pMOS type FDSOI transistors TP1 and TP2 are connected together so as to form a current mirror. The source of transistor TP1 and the source of transistor TP2 are connected to the same supply potential V DD , the front face gate G top of transistor TP1 is connected to the front face gate of transistor TP2 and the front face gate of transistor TP2 is connected to the drain of transistor TP2.

[0024] We consider that the transistors TP1 and TP2 are identical, so their W / L ratios are identical, with W the channel width and L the length of the gate on the front face G top of each of the transistors. The current mirror forms two branches B1 and B2 in which the same electric current i flows.

[0025] This current mirror is connected to a pair of nMOS type FDSOI transistors TN1 and TN2. The drain of transistor TP1 is connected to the drain of transistor TN1 and the drain of transistor TP2 is connected to the drain of transistor TN2. The source of nMOS transistor TN1 is connected to an electrical ground.

[0026] A resistor R is placed between the source of transistor TN2 and electrical ground. The drain of transistor TN1 is connected to the front-facing gate G to p of transistor TN1 and the two front-facing gates G top of transistors TN1 and TN2 are connected to each other.

[0027] The rear-face gates G back of the four FDSOI transistors TN1, TN2, TP1 and TP2 are biased by an "external" CPGA circuit. More specifically, the rear gates G back of the transistors TN1 and TN2 are respectively biased to potentials V BBN1 and V BBN2 while the rear gates G back of the other transistors TP1 and TP2 are maintained at a constant potential, equal in this example to the ground potential. As will be understood from the explanations below, for the circuit to be functional (for a current to flow in the branches) the potentials V BBN2 and V BBN1 must be different, in practice significantly different, and must be such that V BBN2 > V BBN1 .

[0028] We note VR the potential of the source of the transistor TN2 (corresponding to the voltage across the resistor R), and this potential VR is worth ix R, i being the current flowing in the two branches B1 and B2.

[0029] We also note the capability of a transistor β = (W / L) x µ x C ox , with (W / L) the ratio between the width W and the length L of the transistor channel, µ the mobility of the charge carriers and C ox the gate oxide capacitance of the transistor.

[0030] We can write for transistor TN1 that the current i is equal to: i = β TN 1 J D 0 exp V GTN 1 − V ThTN 1 nV T e − V STN 1 V T − e V DTN 1 V T

[0031] With β TN1 the capability of transistor TN1, J D0 a constant representing the saturation threshold of the transistors, n the slope factor, V GTN1 the gate potential on the front panel G top of transistor TN1, V ThTN1 the threshold voltage of transistor TN1, VT the thermal voltage of the transistors, V STN1 the source potential of transistor TN1 and V DTN1 the drain potential of transistor TN1.

[0032] We can also write for transistor TN2 that the current i is equal to: i = β TN 2 J D 0 exp V GTN 2 − V ThTN 2 nV T e − V STN 2 V T − e V DTN 2 V T

[0033] With β TN2 the capability of the TN2 transistor, V GTN2 the gate potential on the front panel Gtop of the TN2 transistor, V ThTN2 the threshold voltage of the TN2 transistor, V STN2 the source potential of the TN2 transistor and V DTN2 the drain potential of the TN2 transistor.

[0034] We can expand equation (1) to obtain: i = β TN 1 J D 0 exp V GTN 1 − V ThTN 1 nV T 1 − e V STN 1 V T − V DTN 1 V T e − V STN 1 V T

[0035] However, the terms e V STN 1 V T − V DTN 1 V T And e V STN 2 V T − V DTN 2 V T are almost identical between transistor TN1 and transistor TN2 with a cascode assembly (described below), and very close without a cascode assembly. We can therefore combine equations (2) and (3) to obtain the following development: β TN 1 J D 0 exp V GTN 1 − V ThTN 1 nV T e − V STN 1 V T = β TN 2 J D 0 exp V GTN 2 − V ThTN 2 nV T e − V STN 2 V T

[0036] Since the source of transistor TN1 is connected to electrical ground, the potential V STN1 of the source of transistor TN1 is zero. In addition, the potential V STN2 of the source of transistor TN2 is equal to VR . Equation (4) becomes: β TN 1 exp V GTN 1 − V ThTN 1 nV T = β TN 2 exp V GTN 2 − V ThTN 2 nV T e − V R V T β TN 1 β TN 2 = exp − V GTN 1 − V ThTN 1 nV T exp V GTN 2 − V ThTN 2 nV T e − V R V T ln β TN 1 β TN 2 = − V GTN 1 − V ThTN 1 nV T + V GTN 2 − V ThTN 2 nV T − V R V T ln β TN 1 β TN 2 = V GTN 2 − V GTN 1 + V ThTN 1 − V ThTN 1 − nV R nV T V R = V T ln β TN 2 β TN 1 + V GTN 2 − V GTN 1 n + V ThTN 1 − V ThTN 2 n

[0037] The gates of transistors TN1 and TN2 being connected together, their potential difference (V GTN2 - V GTN1 ) is zero. We note the difference between the threshold voltages of the two transistors TN1 and TN2 ΔV th with Δ V th = V ThTN 2 - V ThTN 1 . Equation (9) therefore becomes: V R = V T ln β TN 2 β TN 1 − Δ V th n

[0038] However, according to Alyssa Bonnoit's thesis, "Reducing power using body biasing in microprocessors with dynamic voltage / frequency scaling", Jean-Philippe Noël's thesis, "Optimization of FDSOI devices for power consumption and speed management: application to memory and logic functions", and Andreia Cathelin's presentation "Analog / RF design techniques in 28 nm FDSOI technology" from 2017 at the SOI Industry Consortium, we can write that Δ V th = α ( V BBN 1 _fixe - V BBN 2 + V R ), with α a real number.

[0039] Equation (10) therefore becomes: V R = V T ln β TN 2 β TN 1 − α − V BBN 2 + V R + V BBN 1 n V R n + α n = V T ln β TN 2 β TN 1 − αV BBN 1 n + α V BBN 2 n V R = V T n n + α ln β TN 2 β TN 1 + α V BBN 2 − V BBN 1 n + α

[0040] It can be seen from equation (13) that the potential VR is related to the potential difference V BBN2 - V BBN1 by a linear relationship in the second term of the equation.

[0041] The term V T n n + α ln β TN 2 β TN 1 is null before the term α V BBN 2 − V BBN 1 n + α if the W / L ratios of transistors TN1 and TN2 are identical. Equation (13) then becomes: V R = α V BBN 2 − V BBN 1 n + α

[0042] This equation 14 clearly shows that the proposed circuit can indeed produce a voltage divider, the division factor being equal to α n + α .

[0043] Generically, we see that equation (13) is composed of two terms A+B, with A and B defined as follows: A = V T n n + α ln β TN 2 β TN 1 B = α V BBN 2 − V BBN 1 n + α

[0044] By choosing different TN1 and TN2 transistors (thus having different W / L ratios), it is possible to introduce temperature compensation, as explained below. However, even if the W / L ratios of TN1 and TN2 transistors are chosen to be different, in practice slightly different (for example by 10% or even 20% at most, the percentage being understood in relation to the largest W / L value), the first term A will often be lower than the term B if the potentials V BBN2 and V BBN1 are significantly different. Note that the term A can be positive or negative depending on whether the TN2 transistor is respectively larger or smaller than the TN1 transistor.

[0045] For comparison, in the case where the circuit of the figure 3 would be used as in the prior art to form a current source, with identical back gate potentials for V BBN2 and V BBN1 , there would be a ratio of 1 to 8 between the sizes of the transistors TN1 and TN2 to have a sufficient voltage across the resistor. The term B would then be equal to 0 and the voltage VR would be obtained solely thanks to the term A, using very significantly different geometries for TN1 and TN2 so that the term A is not too small. On the contrary, in a voltage divider circuit according to the present invention, the term B will be given greater priority thanks to the input voltage resulting in different potentials V BBN2 and V BBN1 . The term A is introduced only in the case where it is desired to compensate for temperature variations of the resistor.For example, for the same voltage VR across the resistor, we have a ratio of 11 / 12 (understand: transistors TN1 and TN2 have 11 and 12 elementary fingers respectively) with the circuit of the . figure 3 , with an input voltage of 2V (difference between the potentials V BBN2 and V BBN1 ).

[0046] Furthermore, in the case where one of the potentials V BBN1 or V BBN2 is equal to the standard potential Vss defining the electrical mass, we can simplify equation (14), and consider that the term αV BBN 2 ou 1 n + α is almost zero.

[0047] This aforementioned development is applied in the case of weak inversion mode operation of transistors TN1 and TN2, in other words in the case of transistors TN1 and TN2 in conduction below the threshold.

[0048] The proposed circuit therefore makes it possible to lower the voltage VR across the resistor R compared to the input voltage equal to V BBN2 - V BBN1, while maintaining a low current value i in the two branches B1 and B2 and a resistance value R making it possible to minimize the size in terms of silicon surface.

[0049] The same reasoning can be carried out for TN1 and TN2 transistors in strong inversion operation with V DS > V GS - VT , (and V GS > VT ) where V DS is the voltage between the drain and the source of a transistor, V GS the voltage between the front gate and the source of the same transistor and VT is the thermal voltage of the transistor. The current in transistors TN1 and TN2 is written: i = β 2 V GS − V th 2 1 + λV DS

[0050] With β the transistor capability, V GS the voltage between the gate and the source of the transistor, V th the threshold voltage of the transistor, V DS the voltage between the drain and the source of the transistor and λ the modulation coefficient of the channel length.

[0051] The current i is identical in the two transistors TN1 and TN2 due to the current mirror structure, so we can write: β TN 1 ( V GTN 1 - V STN1 - V ThTN 1 ) 2< (1 + λ DSTN 1) = β TN 2 ( V GTN 2 - V STN2 - V ThTN 2 ) 2< (1 + λ DSTN 2)

[0052] For the same reasons as before, we can neglect the two terms (1 + λV DSTN 2) and (1 + λV DSTN 1) and obtain: V R = 1 α + 1 T T 0 2 I μ 0 C ox W 1 L 1 1 − 1 K + α α + 1 V BBN 2 − V BBN 1 −

[0053] As before, equation (17) can be written in the form VR = A+B with A = 1 α + 1 T T 0 2 I μ 0 C ox W 1 L 1 1 − 1 K B = α α + 1 V BBN 2 − V BBN 1 −

[0054] The ratio between the potential VR and the difference V BBN2 - V BBN1_ is therefore substantially constant, whatever the operating regime of the transistors TN1 and TN2 because n is close to 1 in FDSOI technology (around 1.2 to 1.6). This can be generalized by inverting the structure as described more precisely with reference to the figure 6 .

[0055] According to a possible embodiment, the transistor TN2 has a front-panel gate width G top greater than that of the transistor TN1 (or more precisely W2 / L2 > W1 / L1), which makes it possible to obtain a "proportional to absolute temperature" (PTAT) effect on the current i flowing in the resistor R because of the voltage values ​​between the gate and the source of the transistors which increase with the temperature. This is explained by the fact that V GS1 - V GS2 = VR , so if the voltages V GS increase, then VR also increases and therefore the current i too. This makes it possible to compensate for a positive temperature coefficient of the resistor R which causes an "inversely proportional to absolute temperature" (CPTAT) effect on the current i. The two CPTAT and PTAT effects therefore compensate each other and the ratio between VR and V BBN2 -V BBN1_fixe remains stable in temperature.This is also explained by the fact that the coefficient A in formula (14) or (17) is a function of VT and is positive. VT increasing with temperature, the variation of A and therefore of VR will be positive if . β TN 2 > β TN 1 so if transistor TN2 is bigger than transistor TN1.

[0056] In the less frequent case where the resistor used has a negative temperature coefficient causing a PTAT effect on the current i, it is possible to compensate for this PTAT effect by a CPTAT effect by inversely unbalancing the geometric ratios of the transistors TN2 and TN1, by taking W2 / L2 < W1 / L1. This is also explained by the fact that the coefficient A will be negative in this case. VT increasing with temperature, the variation of A and therefore of VR will be negative if β TN 2 < β TN 1, so if transistor TN2 is smaller than transistor TN1.

[0057] The circuit represented in figure 3 can be achieved using LVT or RVT transistors. The choice of the type of LVT or RVT transistors for the TN1 and TN2 transistors depends on the intended application and the technological manufacturing possibilities of the FDSOI transistors, in particular for the production of Nwell / Pwell wells placed under the thin oxide layer and the production of deep isolation wells making it possible to separate a Pwell well from the “massive” substrate, generally of the P type. As is well known to those skilled in the art, in the case where the Nwell or Pwell well is biased at a voltage different from the substrate, and possibly from the “Deep Nwell” well, it is necessary to ensure that the diodes present between well / substrate or well / Deep Nwell are not conductive.

[0058] The voltage divider circuit can be used with input potentials, on V BBN1 and V BBN2 , which are each fixed or variable.

[0059] The 2 input potentials, and therefore the input voltage, will be fixed if the voltage divider is for example used to generate the equivalent of a “low” reference voltage VR from a “high” reference voltage for example provided by a circuit conventionally called by the English acronym “bandgap”, such a low reference voltage being able among other things to be used in a reference current source circuit as described below in relation to the figure 10 .

[0060] The input voltage may be variable, for example by varying at least one of the two potentials. In the example of an oscillator circuit described below, one of the potentials, V BBN1 , is fixed and the other potential, V BBN2 , can vary within a given range of values. In the case where the divider circuit is, for example, connected to a sensor providing a differential signal, the two potentials could be caused to fluctuate.

[0061] Whatever the intended application of such a voltage divider circuit, the choice of LVT or RVT transistors will be mainly guided by the simplicity of implementation of the circuit. If at least one of the potentials is negative, it will be easier to use nMOS RVT transistors to be able to negatively bias the PWELL and isolate it from the substrate to ground, by a DeepNWELL well. Conversely, if the potentials are rather positive, or very slightly negative (greater than -0.6V) it will be possible to use LVT transistors because it is possible to bias the Nwell well to these values ​​without making the Nwell / Psubstrate diode conductive.

[0062] According to a possible embodiment, the transistors TN1, TN2, TP1 and TP2 are transistors comprising several “fingers”, for example identical fingers; the transistor TN1 comprises X “fingers” and the transistor TN2 comprises X + K “fingers” with X and K two integers, or vice versa if it is desired that the transistor TN2 be smaller than the transistor TN1.

[0063] The advantage of using FDSOI transistors is to be able to access a wide range of values ​​in bias potential V BBN2 or V BBN1 of the back gate Gback of the FDSOI transistor TN2 or TN1 (or both possibly) and thus to also have a wide range of values ​​in threshold voltage V th of the transistor TN2 and / or TN1, as shown in the presentation by Andreia Cathelin "Analog / RF design techniques in 28 nm FDSOI technology" from 2017 made during the SOI Industry Consortium. This results in a low α factor (equation (11)) and therefore makes it possible to more strongly reduce the potential VR (or voltage across the resistor) compared to the input voltage V BBN2 - V BBN1 , and thus to more advantageously limit the size of the resistor R on the silicon surface when one wishes to use a low value bias current to limit consumption.

[0064] [ Fig. 4 ] presents results of simulations carried out with the circuit of the figure 3 in which the transistors TN1 and TN2 are of the same size and of the LVT GO1 type, that is to say that their insulation thickness on the rear face allows them to support a voltage of approximately 1 V on the front gate G back of the transistor, and the resistor R has no temperature coefficient. The potential V BBN1 is in this example equal to that of the ground, therefore zero. The ratio V BBN 2 V R ∼ n + α α is represented on the ordinate and the temperature of the circuit (therefore of all the transistors of the figure 3 ) is represented on the abscissa. We note that for a temperature varying between -45 °C and 150 °C, the ratio V BBN 2 V R ∼ n + α α varies between 6.36 and 6.5. We can therefore consider that this ratio is not very sensitive to the circuit temperature. The ratio V BBN 2 V R ∼ n + α α varies much more in temperature if we carry out these simulations with a resistor R having a temperature coefficient. This is why the transistors TN1 and TN2 advantageously have different W / L ratios to compensate for the temperature variation.

[0065] The circuit proposed in figure 3 therefore allows a voltage divider circuit to be created, considering that V BBN2 -V BBN1 is the input voltage and the voltage across the load (equal, in this case, to VR) is the output voltage, obtained by dividing V BBN2 by a factor n + α α > 1 little sensitive to temperature, and therefore to produce a circuit for generating a reference voltage including a space-saving reference resistor.

[0066] [ Fig. 5 ] presents results of simulations carried out with the circuit of the figure 3 in which the TN1 and TN2 transistors are still the same size but of the LVT GO2 type. They therefore have an insulator thickness twice as large (GO2 type transistors), which allows them to withstand a greater bias voltage on their front gate. The ratio V BBN 2 V R ∼ n + α α is represented on the ordinate and the temperature of the circuit of the figure 3 is represented on the abscissa. We note that for a temperature varying between -45 °C and 150 °C, the ratio V BBN 2 V R ∼ n + α α varies between 13.02 and 13.12. We can therefore consider that this ratio is not very sensitive to the temperature of the circuit, and as previously that the circuit proposed in figure 3 allows the creation of a voltage divider circuit that is not very sensitive to temperature and can adapt the division factor V BBN 2 V R ∼ n + α α thanks to the thickness of the thin oxide layer, BOX oxide and silicon film, and thus have a reference resistance that takes up little space in terms of silicon surface.

[0067] [ Fig. 6 ] represents a second embodiment. Two nMOS type FDSOI transistors TN1 and TN2 are connected together so as to form a current mirror. This current mirror is connected to a pair of pMOS type FDSOI transistors TP1 and TP2. The source of the pMOS transistor TP1 is connected to the potential V DD , and the drains of the two transistors TP1 and TP2 are connected respectively to the drains of the nMOS transistors TN1 and TN2. The sources of the nMOS transistors TN1 and TN2 are connected to an electrical ground. A resistor R is placed between the source of the transistor TP2 and the potential V DD . The gate on the front face of the transistor TN2 is connected to the source of the transistor TN2 and the two gates on the front face of the transistors TN1 and TN2 are connected together. The front-facing gate of transistor TP1 is connected to the source of transistor TP1 and the gates of transistors TP1 and TP2 are connected to each other.We consider that transistors TN1 and TN2 are identical, so their W / L ratios are identical. The current i flowing in the two branches B1 and B2 formed by the current mirror is identical.

[0068] The rear gates of the four FDSOI transistors TN1, TN2, TP1 and TP2 are biased by an external circuit not shown, analogous to the CPGA circuit of the figure 3 . More specifically, the rear gates of transistors TP1 and TP2 are respectively biased to potentials V BBP1 and V BBP2 while the rear gates of the other transistors TN1, TN2 are maintained at a constant potential, equal to ground in this example. As will be understood from reading the explanations below, for the circuit to be functional (for a current to flow in the branches) the potentials VBBP2 and VBBP1 must be different, in practice significantly different, and must be such that V BBP2 < V BBP1 .

[0069] We note VR the potential between the source of transistor TP2 and the resistor R. The voltage across the terminals of the resistor R, equal to V DD -VR is worth ix R where i is the current flowing in the two branches B1 and B2.

[0070] We can apply the same reasoning as that carried out for the circuits in the previous figures, namely that the current i arriving at the source of transistor TP1 can be written: i ∼ β TP 1 J D 0 exp V GTP 1 − V ThTP 1 nV T e − V STP 1 V T

[0071] And the current i arriving at the source of transistor TP2 can be written: i ∼ β TP 2 J D 0 exp V GTP 2 − V ThTP 2 nV T e − V STP 2 V T

[0072] By combining equations (23) and (24) and based on the aforementioned thesis by Jean-Philippe Noël, we obtain a linear relationship linking the potentials VR and V BBP2: Vdd − V R = V T n n + α ln β TP 2 β TP 1 + α V BBP 1 − V BBP 2 n + α

[0073] In order, as before, to have a voltage across the resistor R (equal to V DD -VR ), it is necessary, in this complementary case where the input voltage is applied between the rear gates of the pMOS, that V BBP2 is lower than V BBP1 and we obtain a voltage divider circuit. This thus makes it possible to reduce the value of the resistor R while having a low current value i and a high input voltage V BBP1 - V BBP2.

[0074] As before, equation (25) can be written in the form A+B with: A = V T n n + α ln β TP 2 β TP 1 B = α V BBP 1 − V BBP 2 n + α

[0075] It is then possible to compensate for any variation in resistance as a function of temperature by proceeding as described previously, thanks to the presence of the term A in the formula giving the voltage V DD -VR .

[0076] Furthermore, without repeating all the developments, in saturated mode, we obtain an equation (26) equivalent to equation (17) again with two terms A and B as previously. V dd − V R = α α + 1 V BBP 1 − V BBP 2 _

[0077] The circuits presented allow the construction of a voltage divider with a low reference resistance and a low current i. These circuits can have different applications. A first application, described with reference to figures 7 à 9 , is a circuit for generating a clock signal using a ring oscillator.

[0078] [ Fig. 7 ] represents an example of such a clock generation circuit comprising a circuit delivering a voltage and a current to a ring oscillator. The oscillator comprises three inverters I1, I2, and I3 connected together to form a loop. More generally, the oscillator may comprise 2N+1 inverters, with N a natural number greater than 1.

[0079] By using the electronic circuits presented in the previous figures as a reference voltage / current generator for supplying the inverters, it is possible to have a voltage V RO across the reference resistor of a few tens of millivolts and a low current i while having low reference resistor values ​​R ref. In fact, thanks to the voltage divider produced by the invention, it is possible to lower the voltage VR circulating in the reference resistor R ref and thus reduce its value.

[0080] The circuit includes the same components as those of the circuit of the figure 3 and further comprises a transistor TP5 connected to the transistors TP1 and TP2 so as to form a current mirror thus comprising three branches B1, B2 and B3 in which the same current i flows. Thus, the sources of the three transistors TP1, TP2 and TP5 are connected to the same potential V DD , their front face gates are connected to each other.

[0081] The gate on the rear face of transistor TN2 is connected to a "power supply" node with a variable potential V RO which is the power supply potential of inverters I1, I2 and I3. This power supply node is connected to branch B3 of the current mirror, the inverters being therefore powered by the current i flowing in branch B3. Branch B3 and the three inverters therefore play the role of the CPGA circuit of the figure 4

[0082] In this embodiment, the reference voltage circuit comprises transistors TN3, TN4, TP3, TP4 and TP6 configured in cascode assembly with the already present transistors TN1, TN2, TP1, TP2 and TP5. As is known to those skilled in the art, this assembly makes it possible to ensure quasi-equality of the VDS voltages of the transistors of each current mirror. Thus, with reference to the aforementioned equations giving the value of the current i, it is possible to eliminate the components linked to the VDS voltages and to have an “ideal” voltage divider. Thus, the pMOS transistors TP3, TP4, TP6, and nMOS transistors TN3, TN4 are placed respectively in series with the pMOS transistors TP1, TP2, TP5 and the nMOS transistors TN1 and TN2. The power supply node (potential V R0 ) is thus connected to the drain of the pMOS transistor TP6.

[0083] The rear-facing gates of the transistor assembly, except for transistor TN2, are maintained at a constant potential equal in this example to ground.

[0084] The source of transistor TP3 is connected to the drain of transistor TP1, the source of transistor TP4 is connected to the drain of transistor TP2, and the source of transistor TP6 is connected to the drain of transistor TP5. The front gates of transistors TP3 and TP4 are connected to each other. The front gates of transistors TP5 and TP6 are connected to each other. The front gates of transistors TP3 and TP4 are connected to the front gates of transistors TP1 and TP2. The front gate of transistor TP4 is connected to the drain of transistor TP4, and the front gates of transistors TP5 and TP6 are connected to the drain of transistor TP4.

[0085] The drain of transistor TN3 is connected to the drain of TP3 and the drain of TN4 is connected to the drain of TP4. The front gates of transistors TN3 and TN4 are connected to each other. The drain of TN3 is connected to the front gate of transistor TN3. The source of transistor TN3 is connected to the drain of transistor TN1 and the source of transistor TN4 is connected to the drain of transistor TN2.

[0086] The rear-facing gates of all transistors, except transistor TN2, are held at an equal constant potential in this example. The oscillation frequency f of this oscillator can be written as a function of the equivalent resistance of the ring oscillator, the oscillator constituting a "load" supplied by branch B3; f=1 / (n*C*R equi ). The current flowing through the reference resistor R ref is equal to that flowing through the equivalent resistance of the ring oscillator R equi , so i =VR / R ref =V R0 / R equi . Furthermore, as described previously, V R0 =KBB*V Ref , with KBB>0. Thus, VR / R ref = KBB*V Rref / R equi , and R equi =KBB*R ref . The clock generation circuit shown implements a feedback loop of the value of the equivalent resistance R equi to the value of the reference resistor multiplied by this factor KBB.A significant advantage of this clock generation circuit using a voltage divider according to the present invention over the clock generation circuit shown in . figure 1 is that it requires a reference resistor of lower value than the desired equivalent resistance of the ring oscillator. Thus, since the KBB ratio can be large, easily between 5 and 10, one can use a resistor 5 to 10 times smaller and consequently a current and therefore a consumption 5 to 10 times smaller than that of the prior art circuit.

[0087] [ Fig. 8 ] presents the oscillation frequency f of the ring oscillator of the circuit of the figure 7 as a function of the temperature determined by simulations. We note that the frequency f is not very sensitive to the temperature of the circuit, because it varies between 9.04 MHz and 10.06 MHz for a temperature varying between -50 °C and 150 °C. This is explained by the fact that the resistance R ref decreases with the temperature but by having transistors TN1 and TN2 such that W2 / L2 > W1 / L1, we obtain a stability of the ratio between V RO and VR and therefore a stability of the oscillation frequency f over a wide temperature range.

[0088] [ Fig. 9 ] represents a ring oscillator-based clock generation circuit according to another embodiment of the invention, complementary to that represented in figure 7 The oscillator consists of three inverters I1, I2, and I3 connected together to form a loop. More generally, the oscillator can consist of 2N+1 inverters, with N a natural number greater than 1.

[0089] As before, a voltage divider circuit with a current mirror is used to supply inverters I1, I2 and I3.

[0090] Thus, the oscillator comprises three nMOS transistors TN1, TN2 and TN5 connected together to form a current mirror comprising three branches B1, B2 and B3 in which the same current i flows. Thus, the sources of the three transistors TN1, TN2 and TN5 are connected to the same potential, which is here, an electrical ground. Their gates on the front face are connected together.

[0091] There are also two pMOS transistors TP1 and TP2 and a resistor R ref placed between a supply voltage V DD and the source of transistor TP2. The front-facing gates of transistors TP1 and TP2 are connected together. The front-facing gate of transistor TP1 is connected to the drain of TP1.

[0092] The reference voltage circuit also includes transistors configured in cascode assembly, namely nMOS transistors TN3, TN4 and TN6 and pMOS transistors TP3 and TP4.

[0093] The source of transistor TN3 is connected to the drain of transistor TN1, the source of transistor TN4 is connected to the drain of transistor TN2 and the source of transistor TN6 is connected to the drain of transistor TN5. The front-panel gates of transistors TN1, TN2, TN3, TN4, TN5 and TN6 are connected to each other and are connected to the drain of transistor TN4.

[0094] The drain of transistor TP3 is connected to the drain of TN3 and the drain of TN4 is connected to the drain of TP4. The front gates of TP3 and TP4 are connected to each other and connected to the front gate of transistor TP3. The source of TP3 is connected to the drain of TP1 and the source of TP4 is connected to the drain of TP2.

[0095] Branch B3 is connected to a low supply terminal of the ring oscillator. In other words, the oscillator inverters are placed between a "high" supply voltage V DD and a low supply voltage, corresponding in this circuit to a supply node with a potential V R0 . This supply node is connected to branch B3, more precisely to the drain of transistor TN6, and is also connected to the back gate of transistor TP2. Branch B3 and the three inverters therefore play the role of the CPGA circuit of the figure 4 .

[0096] The rear-panel gates of all transistors, except transistor TP2, are also held at a fixed potential, for example equal to ground.

[0097] [ Fig. 10 ] presents a second application of the circuits according to the invention, namely a current generator. The generated current i ref is in this example equal to the current i from the three branches B1, B2 and B3 of the current mirror formed by the three identical pMOS transistors TP1, TP2 and TP3. The current i ref is then equal to VR / R ref . It can advantageously be substantially insensitive as explained previously. As well known to those skilled in the art, it is possible to obtain a current i ref that is a multiple of the current flowing in branches B1 / B2 by providing different transistor sizes between transistor TP3 on the one hand and transistors TP1 / TP2 on the other. If it is desired to have a fixed generated current, it is possible, for example, to use a reference voltage that is very stable in temperature in particular, for example delivered by a bandgap circuit, to bias the rear gate of transistor TN2 or TN1.The other rear gates of the other transistors, and in particular that of the other transistor TN1 or TN2 of the nMOS mirror, are biased to another potential value, advantageously ground or V DD . The choice of bias voltage is in particular a function, as explained above, of the type of LVT or RVT transistors used to make the circuit.

[0098] The generator thus formed can generate low current values ​​i ref while having a reference resistance R ref of low value, therefore taking up little space. Indeed, if we compare the current generator to that of the prior art illustrated in figure 1bis, using the same reference voltage, we can use a resistance 5 to 10 times lower than that of the circuit of the prior art, thanks to the voltage division between the reference voltage and the voltage present at the terminals of the resistance.

[0099] [ Fig. 11a ] And [ Fig. 11b ] present simulation results obtained for the current generator of the figure 10 .

[0100] More specifically, the figure 11a represents the current i ref generated as a function of temperature. This varies between 220.8 nA and 221.2 nA for a temperature between - 40 °C and 150 °C. This current generator is therefore very stable over temperature.

[0101] There figure 11b represents the generated current i ref as a function of the potential V BBN2 of polarization of the rear gate of the transistor TN2. We note that these two quantities are proportional, which confirms the fact that the ratio between VR and V BBN2 is constant whatever the value of V BBN2 . Therefore, whether the transistors are in weak or strong inversion operation, this ratio remains stable.

[0102] In general, an electronic system can be produced comprising an electronic circuit according to the invention.

[0103] Furthermore, the term external circuit has been used to designate an electronic circuit consisting of components other than those present in the two branches B1 and B2 and necessary for the production of an electronic voltage divider circuit according to the present invention. It will nevertheless be noted that all the “external” circuits described above are in practice intended to be preferably produced on the same integrated circuit.

Claims

1. An electronic voltage divider circuit comprising at least two FDSOI transistors on insulating thin film (TP1, TP2) of a first type connected to a first supply potential and arranged in a current mirror structure and two FDSOI transistors on thin film (TN1, TN2) of a second type and an electrical load of non-zero impedance (R), the transistors each having a front-face main gate (Gtop) and a back-face control gate (Gback), a drain of a first transistor (TN1) of the second type being connected to the drain of a first transistor (TP1) of the first type, a drain of a second transistor (TN2) of the second type being connected to the drain of a second transistor (TP2) of the first type, the drain of the first transistor of the second type being connected to the front-face gate of this same transistor, the front-face gates of the first and second transistors of the second type being connected to one another, the source of the first transistor of the second type being connected to a second supply potential and said load of non-zero impedance being placed between the source of the second transistor of the second type and said second supply potential, the drain of the second transistor (TP2) of the first type being connected to a front-face gate of the first and second transistors (TP1, TP2) of the first type, wherein the back-face gates of the first and second transistors of the second type (TN2) are connected to an external circuit (CPGA) applying a non-zero input voltage between these two back-face gates, such that the back-face gate of the first transistor of the second type is brought to a potential (VBBN1) lower than that (VBBN2) of the back-face gate of the second transistor of the second type if these two transistors are of nMOS type, and that the back-face gate of the first transistor of the second type is brought to a potential (VBBP1) greater than that (VBBP2) of the back-face gate of the second transistor of the second type if these two transistors are of pMOS type; whereby the voltage across the terminals of said load (VR) is an output voltage equal to the sum of a first component A and a second component B; the first component A being dependent on the difference between the geometric ratios of gate width to gate length of said transistors; the second component B being proportional to said non-zero input voltage with a proportionality factor strictly less than 1; the second component B being preponderant with respect to the first component A.

2. The electronic circuit according to claim 1, wherein the transistors of the first type are pMOS transistors and the transistors of the second type are nMOS transistors, and wherein the potential (VBBN2) applied to the back-face gate of the second transistor of the second type is greater than the potential (VBBN1) applied to the back-face gate of the first transistor of the second type.

3. The electronic circuit according to claim 1, wherein the transistors of the first type are nMOS transistors and the transistors of the second type are pMOS transistors, and wherein the potential (VBBN2) applied to the back-face gate of the second transistor of the second type is less than the potential (VBBN1) applied to the back-face gate of the first transistor of the second type.

4. The electronic circuit according to one of the preceding claims, wherein the transistors of the second type are transistors with a low threshold value LVT.

5. The electronic circuit according to one of claims 1 to 3, wherein the transistors of the second type are transistors with a standard threshold value RVT.

6. The electronic circuit according to one of claims 1 to 5, wherein the transistors of the second type are identical.

7. The electronic circuit according to one of claims 1 to 5, wherein the transistors of the second type are different, their geometrical ratios of gate width to gate length being different by at most 20%.

8. The electronic circuit according to one of claims 1 to 7, wherein the input voltage between the two back-face gates of the first (TN1) and second (TN2) transistors of the second type is sufficiently high for the second component B to be greater, by at least a factor of 10, than the first component A.

9. The electronic system comprising an electronic circuit according to one of the preceding claims, wherein the external circuit (CPGA) comprises a third transistor (TP6) of the first type, whose source is connected to the first supply potential, whose gate is connected to the gates of the first and second transistors of the first type, and whose drain is connected to a node connected to a load circuit.

10. The current source type electronic system according to claim 9, wherein the external circuit (CPGA) generates a stable reference voltage, for example supplied by a bandgap circuit; said stable reference voltage is applied as input voltage between the back-face gates of the first and second transistors of the second type.

11. The electronic system comprising an electronic circuit according to claim 9, wherein the external circuit (CPGA) further comprises a circuit for generating an oscillating clock signal, comprising a plurality of inverters connected to one another so as to form a loop, an output of one inverter being connected to an input of another inverter and wherein said node is connected on the one hand to a voltage / current supply terminal of said plurality of inverters, and on the other hand to the back-face gate of the second transistor of the second type.

12. The electronic circuit according to one of claims 1 to 7, further comprising at least one cascode pair of transistors of the first type placed between the current mirror and the transistors of the second type.

13. The electronic circuit according to one of claims 1 to 7, further comprising at least one cascode pair of transistors of the second type placed between the transistors of the first type and the transistors of the second type.