Operating point stabilization of VCO-ADC using switched capacitor frequency-to-current conversion

Abstract

The invention relates to operating point stabilization of VCO-ADC using switched capacitor frequency to current conversion. A circuit includes a micro-electro-mechanical system (MEMS) microphone configured to generate a voltage signal at an output terminal of the MEMS microphone in response to a sound signal; a voltage controlled oscillator (VCO) coupled to an output terminal of the MEMS microphone and configured to output a frequency modulated signal at an output terminal of the VCO, the frequency modulated signal having a frequency proportional to the voltage signal; a frequency-to-digital (FTD) converter coupled to an output terminal of the VCO and configured to convert the frequency modulated signal to a frequency proportional digital output signal; a frequency voltage (FTV) conversion circuit coupled to an output terminal of the VCO and configured to generate a bias voltage at the output terminal of the FTV conversion circuit according to a frequency modulation signal; and a resistor coupled between the output terminal of the MEMS microphone and the output terminal of the FTV conversion circuit.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to circuits, and in particular embodiments, to voltage controlled oscillator based analog-to-digital converters (VCO-ADCs). BACKGROUND

[0002] Microelectromechanical systems (MEMS) microphones are widely used in electronic devices due to their small form factor and low cost. Traditionally, the analog output of the microphone is converted to a digital output signal by a voltage coding based system, such as a sigma-delta analog-to-digital converter (ΣΔ-ADC), which uses an analog-to-digital converter (ADC) to convert the output voltage of the microphone to a digital output signal.

[0003] Voltage controlled oscillator based ADCs (VCO-ADCs) are a promising alternative to traditional voltage coding based systems and are well suited for low cost digital microphone (e.g., MEMS microphone) applications. The principle of operation is to convert an analog input voltage signal to a variable frequency digital signal. A frequency-to-digital (FTD) converter of the VCO-ADC then converts the variable frequency digital signal to a multi-bit digital output signal at a sampling frequency determined by a system sampling clock signal. While VCO-ADCs have advantages over conventional voltage coding based systems, there remain challenges to using VCO-ADCs, for example, in MEMS microphone systems. SUMMARY

[0004] According to an embodiment, a circuit includes: a micro-electro-mechanical system (MEMS) microphone configured to generate a differential output signal in response to a sound signal, the differential output signal including a first voltage signal at a first output terminal of the MEMS microphone and a second voltage signal at a second output terminal of the MEMS microphone; a first voltage-controlled oscillator (VCO) coupled to the first output terminal of the MEMS microphone, wherein the first VCO is configured to output a first frequency modulated signal at an output terminal of the first VCO, the first frequency modulated signal having a first frequency proportional to the first voltage signal; a second VCO coupled to the second output terminal of the MEMS microphone, wherein the second VCO is configured to output a second frequency modulated signal at an output terminal of the second VCO, the second frequency modulated signal having a second frequency proportional to the second voltage signal; a common mode feedback (CMFB) circuit coupled to the output terminal of the first VCO and the output terminal of the second VCO, wherein the CMFB circuit is configured to generate a bias voltage at an output terminal of the CMFB circuit based on the first frequency modulated signal and the second frequency modulated signal, wherein the bias voltage is proportional to a quiescent frequency of the first VCO, wherein the quiescent frequency of the first VCO is the first frequency of the first frequency modulated signal when no sound signal is transmitted to the MEMS microphone; a first resistor coupled between the first output terminal of the MEMS microphone and the output terminal of the CMFB circuit; and a second resistor coupled between the second output terminal of the MEMS microphone and the output terminal of the CMFB circuit.

[0005] According to an embodiment, a circuit includes: a micro-electro-mechanical system (MEMS) microphone configured to generate a first voltage signal at a first output terminal of the MEMS microphone in response to a sound signal; a first voltage-controlled oscillator (VCO) coupled to the first output terminal of the MEMS microphone, wherein the first VCO is configured to output a first frequency modulated signal at an output terminal of the first VCO, the first frequency modulated signal having a first frequency proportional to the first voltage signal; a first frequency-to-digital (FTD) converter coupled to the output terminal of the first VCO, wherein the first FTD converter is configured to convert the first frequency modulated signal to a first digital output signal proportional to the first frequency; a first frequency-to-voltage (FTV) conversion circuit coupled to the output terminal of the first VCO, wherein the first FTV conversion circuit is configured to generate a first bias voltage from the first frequency modulated signal, and configured to output the first bias voltage at an output terminal of the first FTV conversion circuit; and a first resistor coupled between the first output terminal of the MEMS microphone and the output terminal of the first FTV conversion circuit.

[0006] According to an embodiment, a method of operating a microelectromechanical system (MEMS) microphone system includes generating, by a MEMS microphone, a differential output signal in response to a sound signal, wherein the differential output signal includes a first voltage signal at a first output terminal of the MEMS microphone and a second voltage signal at a second output terminal of the MEMS microphone; generating, by a first voltage controlled oscillator (VCO) coupled to the first output terminal of the MEMS microphone, a first frequency modulated signal, the first frequency modulated signal having a first frequency proportional to the first voltage signal; generating, by a second VCO coupled to the second output terminal of the MEMS microphone, a second frequency modulated signal, the second frequency modulated signal having a second frequency proportional to the second voltage signal; generating, by a common mode feedback (CMFB) circuit coupled to the first VCO and the second VCO, a bias voltage based on the first frequency modulated signal and the second frequency modulated signal, wherein the bias voltage is proportional to a quiescent frequency of the first VCO, wherein the quiescent frequency of the first VCO is the first frequency of the first frequency modulated signal when no sound signal is transmitted to the MEMS microphone; and setting a bias voltage of the MEMS microphone by transmitting the bias voltage to a first terminal of a first resistor and a first terminal of a second resistor, wherein a second terminal of the first resistor and a second terminal of the second resistor are coupled to the first output terminal of the MEMS microphone and the second output terminal of the MEMS microphone, respectively. BRIEF DESCRIPTION OF DRAWINGS

[0007] For a more complete understanding of the present application, and for further features and advantages thereof, reference is made to the following description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 A microelectromechanical system (MEMS) microphone system in an embodiment is illustrated, which includes a capacitive MEMS microphone and a voltage controlled oscillator based analog-to-digital converter (VCO-ADC);

[0009] Figure 2A A frequency-to-digital (FTD) converter in an embodiment is illustrated;

[0010] Figure 2B An output of the FTD converter in Figure 2A

[0011] Figure 3 A block diagram of a MEMS microphone system in an embodiment is illustrated, which includes a VCO-ADC with a common mode feedback (CMFB) circuit;

[0012] Figure 4 A circuit diagram of the CMFB circuit in Figure 3

[0013] Figure 5 ​​FIGURE 1 illustrates a frequency dependent resistor (FDR) in an embodiment;

[0014] Figure 6A and Figure 6B Pictured Figure 4 An alternative embodiment of the CMFB circuit 450 in;

[0015] Figure 7 A block diagram of a MEMS microphone system in an embodiment is shown, the MEMS microphone system including a VCO-ADC with a frequency-to-voltage (FTV) conversion circuit;

[0016] Figure 8 The embodiment of the invention is shown in FIG. Figure 7 Circuit diagram of the FTV conversion circuit in;

[0017] Figure 9 FIG2 illustrates a block diagram of a MEMS microphone system in an embodiment, which includes a VCO-ADC with an FTV conversion circuit; and

[0018] Figure 10 A flow chart of a method of operating a MEMS microphone system in an embodiment is illustrated. DETAILED DESCRIPTION

[0019] The manufacture and use of the examples disclosed herein are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The specific examples discussed are merely illustrative of specific ways to manufacture and use the present invention and do not limit the scope of the invention. Throughout the discussion herein, unless otherwise indicated, identical or similar reference numerals in different figures represent identical or similar components. For simplicity, the details of components having identical or similar reference numerals will not be described again.

[0020] The present invention will be described with reference to examples in a specific context, and in particular, a MEMS microphone system including a capacitive MEMS microphone and a VCO-ADC readout circuit.

[0021] Figure 1 The system diagram of the MEMS microphone system 100 in an embodiment is shown, which includes a capacitive MEMS microphone and a voltage-controlled oscillator-based analog-to-digital converter (VCO-ADC). Note that for simplicity, not all features of the MEMS microphone system 100 are shown.

[0022] like Figure 1 As shown, the MEMS microphone system 100 includes a capacitive MEMS microphone 103, which is configured to generate an output voltage V in response to a sound signal. g .exist Figure 1In the example of the capacitive MEMS microphone 103 is or includes a capacitor, where a diaphragm of the capacitor vibrates in response to an acoustic pressure to generate an output voltage V g . A high voltage bias (e.g., a +12V voltage) is supplied to the capacitive MEMS microphone 103 to bias the capacitive MEMS microphone 103. The high voltage bias can be provided by a voltage source 101 (e.g., a charge pump circuit) coupled between the capacitive MEMS microphone 103 and a reference voltage node 123 configured to be coupled to a reference voltage, such as electrical ground. An output terminal of the capacitive MEMS microphone 103 is coupled to a node 104. A high ohmic resistor 105 (e.g., having a resistance in the order of a giga ohm) is coupled between the node 104 and a node 106. In the illustrated embodiment, a bias voltage V bias is provided at the node 106 to set an operating point (e.g., a rest frequency) of the MEMS microphone system 100. As an example, the bias voltage V bias at the node 106 can be provided by a biasing circuit 107 of the VCO-ADC, which is designed to generate an appropriate bias voltage V bias for the capacitive MEMS microphone 103. Examples of the biasing circuit are discussed below.

[0023] In Figure 1 , an input stage circuit 109 is coupled between the node 104 and an input terminal of a voltage controlled oscillator (VCO) 113. In Figure 1 , the input stage circuit 109 is a source follower circuit including a transistor. A gate terminal of the transistor is coupled to the node 104. A drain terminal of the transistor is coupled to a supply voltage node 111 configured to receive a supply voltage (e.g., +3V, +5V, etc.) for the MEMS microphone system 100. A source terminal of the transistor is coupled to the input terminal of the VCO 113. In some embodiments, the input stage circuit 109 (e.g., the source follower circuit) provides a buffer voltage to the VCO 113 having a voltage value proportional to the output voltage V g of the capacitive MEMS microphone 103.

[0024] The VCO 113 is configured to generate an output signal f vco . A frequency of the output signal f vco is modulated (e.g., controlled) by the output voltage V g of the capacitive MEMS microphone 103. In some embodiments, the frequency of the output signal f vco generated by the VCO 113 is proportional to the output voltage V g , and thus, the output signal f vco of the VCO 113 is also referred to as a frequency modulated signal fvco In an example embodiment, VCO 113 is a ring oscillator, although any other suitable type of VCO may be used as VCO 113. Voltage controlled oscillators, such as ring oscillators, are known and used in the art, and therefore are not discussed in detail here.

[0025] Still refer to Figure 1 The output terminal 114 of the VCO 113 is coupled to the input terminal of a frequency to digital (FTD) converter 115. The clock input terminal of the FTD converter 115 (also referred to as an F2D converter) is coupled to the system sampling clock f generated by the system clock source 121. clk The system clock source 121 may include an oscillator, a phase-locked loop (PLL), a combination thereof, etc., and is configured to generate a highly accurate digital clock signal (e.g., f clk ).

[0026] The FTD converter 115 is configured to convert the frequency modulated signal f vco In some embodiments, the FTD converter 115 is configured to convert the FTD signal into a digital output signal y[n] (eg, a multi-bit digital signal). vco and the system sampling clock signal f clk Generate digital signals (see e.g. Figure 2B 230), and is configured to sample the clock signal f by using the system clk The digital signal is sampled to generate a digital output signal y[n]. Figure 2A and Figure 2B The details of the FTD converter 115 are discussed.

[0027] In some embodiments, Figure 1 Some or all of the components within the area bounded by dashed line 150 in FIG. 1 are integrated into a semiconductor die, such as an application-specific integrated circuit (ASIC) or a portion of an ASIC. Input stage circuit 109, VCO 113, FTD converter 115, and system clock source 121 may be collectively referred to as a VCO-ADC or a VCO-ADC readout circuit. In some embodiments, system clock source 121 is omitted from the VCO-ADC, and the system sampling clock f clk The clock source outside the VCO-ADC is provided to the VCO-ADC.

[0028] Note that in Figure 1 In the example, the capacitive MEMS microphone 103 is shown to generate a single-ended output signal V gsingle-ended microphone so as to easily illustrate the working principle of the VCO-ADC. The capacitive MEMS microphone 103 can be a differential microphone that generates a differential output comprising a pair of output voltages V g_p and V g_n In this case, the VCO-ADC can comprise two parallel circuit branches of circuitry for processing the output voltages V g_p and V g_n , where each of the two parallel branches comprises a VCO 113 and an FTD converter 115. Examples of MEMS microphone systems with differential microphones are discussed below.

[0029] During operation of the MEMS microphone system 100, when no sound is applied to the capacitive MEMS microphone 103, the VCO 113 oscillates at a quiescent frequency determined by a bias voltage V bias The bias voltage V bias sets the operating point of the VCO 113 through the high-ohmic resistor 105. Ensuring a stable quiescent frequency is important for MEMS microphone systems for various reasons. First, if an oscillator (e.g., 113) runs faster than desired, the drift of the quiescent frequency from the nominal value can significantly increase the power consumption in the analog domain. Second, the drift of the quiescent frequency can change the gain and offset of the output signal (e.g., y[n]) upon digital reconstruction. Furthermore, the quiescent frequency is a key parameter in determining the signal quantization noise ratio (SQNR) of the VCO-ADC. Moreover, in differential VCO-ADC designs, the residual frequency mismatch between the branches of the VCO-ADC also affects the digital reconstruction.

[0030] Unfortunately, process-voltage-temperature (PVT) variations strongly affect the quiescent frequency of the VCO-ADC. PVT variations refer to variations in process, voltage, and temperature. PVT variations can affect the electrical response of circuits and devices. PVT variations can also affect the timing, power, and noise characteristics of circuits. As such, for conventional VCO-ADCs, a calibration procedure is performed to reduce the impact of PVT variations. However, the calibration methods for conventional VCO-ADCs can require relatively complex hardware and software designs, and can need to be performed periodically, and can be labor-intensive, thus increasing the cost and power consumption of the VCO-ADC. The present disclosure discloses various embodiments of VCO-ADCs with feedback loops for automatically compensating for PVT variations, thus achieving a stable quiescent frequency without the need for calibration.

[0031] Figure 2A A frequency-to-digital (FTD) converter 200 in an embodiment is illustrated. The FTD converter 200 can be used as the FTD converter 115 in Figure 1 or the FTD converters (e.g., 315A, 315B) discussed below. Note that,Figure 1 The VCO 113 is also shown in Figure 2A to illustrate the connection of the FTD converter 200, it is to be understood that the VCO 113 is not part of the FTD converter 200.

[0032] In the example of Figure 2A the FTD converter 200 comprises a counter 201 and a register 203. An input terminal of the counter 201 is coupled to the VCO 113 to receive the frequency modulated signal f vco . A reset terminal of the counter 201 is coupled to the system sampling clock signal f clk . The counter 201 is configured to count the number of periods (also referred to as oscillator periods) of the frequency modulated signal f vco between adjacent active edges (e.g. rising edges or falling edges) of the system sampling clock signal f clk .

[0033] The output of the counter 201, which is a multi-bit digital signal, is sent to the register 203. A clock terminal of the register 203 is coupled to the system sampling clock signal f clk . The register 203 is configured to latch the multi-bit digital signal at the output of the counter 201 at active edges of the system sampling clock signal f clk . In other words, the multi-bit digital signal at the output of the counter 201 is sampled at active edges of the system sampling clock signal f clk and the sampled values are output as the digital output signal y[n] of the FTD converter 200.

[0034] Figure 2B Fig. 3 illustrates the output of the FTD converter in an embodiment. In Figure 2A the signal 210 in the top sub-plot illustrates the output of the VCO 113, which is the frequency modulated signal f vco . The signal 220 in the middle sub-plot illustrates the output of the system clock source 121, which is the system sampling clock signal f clk . The signal 230 illustrates the output of the counter 201 in the FTD converter 200. As Figure 2B illustrated, the counter output is reset to zero at active edges (e.g. rising edges) of the system sampling clock signal f clk and then increases as the counter 201 counts the periods in the frequency modulated signal f vco . At the next active edge, the output signal of the counter 201 is latched into the register 203 and the counter 201 is again reset to zero. Figure 2B

[0035] Figure 3 ​FIG. 1 shows a block diagram of a MEMS microphone system 300 including a VCO-ADC with a common mode feedback (CMFB) circuit 317 in an embodiment. Figure 3 In the embodiment, the MEMS microphone system 300 includes a capacitive MEMS microphone 303, which outputs a voltage signal V at a first output terminal and a second output terminal of the capacitive MEMS microphone 303, respectively. g_p and V g_n Therefore, the MEMS microphone system 300 can also be called a differential MEMS microphone system. Figure 3 In the example of FIG, a capacitive MEMS microphone 303 has two capacitors 301A and 301B for generating a differential output signal. in_p and V in_n are supplied to capacitors 301A and 301B, respectively. Of course, this is merely a non-limiting example. In other embodiments, the capacitive MEMS microphone 303 may include only one capacitor, wherein both membranes of the capacitor vibrate (e.g., in opposite directions) to generate a differential output signal. In addition to the examples discussed above, other suitable types of MEMS microphones may also be used to generate the differential voltage signal V g_p and V g_n These and other variations are fully intended to be included within the scope of this disclosure.

[0036] like Figure 3 As shown in the figure, the MEMS microphone system 300 includes two parallel circuit branches, for example, for processing the voltage signal V g_p The upper branch is used to process the voltage signal V g_n The upper branch includes the input stage 309A, the VCO 313A, the FTD converter 315A, and the high-ohmic resistor 305A. The lower branch includes the input stage 309B, the VCO 313B, the FTD converter 315B, and the high-ohmic resistor 305B. In some embodiments, the voltage signal V g_p Modulate the VCO 313A to generate a frequency modulated signal f vco_p , where the frequency modulation signal f vco_p The frequency and voltage signal V g_p The frequency modulated signal f is then converted by the FTD converter 315A to vco_p Converted into digital output signal y p [n]. Similarly, the voltage signal V g_n Modulate VCO313B to generate a frequency modulation signal f vco_n , where the frequency modulation signal f vco_n The frequency and voltage signal V g_n Then, the FTD converter 315B converts the frequency modulated signal fvco_n Converted into digital output signal y n [n] In some embodiments, the digital output signal y p [n] and y n The difference between [n] (e.g. y p [n]-y n [n]) is used as the output of the MEMS microphone system 300. The input stages 309A and 309B, the VCOs 313A and 313B, the FTD converters 315A and 315B, and the high-ohmic resistors 305A and 305B are connected to the MEMS microphone system 300. Figure 1 The input stage circuit 109, VCO 113, FTD converter 115 and high-ohmic resistor 105 in FIG. 1 are the same or similar, so their details are not repeated.

[0037] It is worth noting that the MEMS microphone system 300 includes a CMFB circuit 317. The input terminal of the CMFB circuit 317 is coupled to the output terminals of the VCOs 313A and 313B. The CMFB circuit 317 modulates the VCO frequency based on the signal f vco_p and f vco_n Generates common-mode output voltage V bias .

[0038] In some embodiments, the common-mode output voltage V bias With the frequency modulated signal f vco_p and f vco_n In the illustrated embodiment, the upper and lower branch circuits in the MEMS microphone system 300 are identical (e.g., by implementing the same circuit twice in hardware), and therefore, the quiescent frequency of VCO 313A is the same as the quiescent frequency of VCO 313B. Due to the differential output of the capacitive MEMS microphone 303, and given Figure 3 The configuration of the MEMS microphone system 300 shown is such that the frequency dependent resistors (FDRs) 404A and 404B of the MEMS microphone system 300 (see FIG. Figure 4 ) at the differential cancellation, the frequency modulated signal f vco_p and f vco_n The sum of the frequencies of is equal to twice the quiescent frequency of VCO 313A (or 313B), the details of which will be discussed below. Figure 3 In the embodiment shown, the common-mode output voltage V bias Proportional to the quiescent frequency of VCO 313A (or 313B).

[0039] Common mode output voltage V biasis used as a common bias voltage for the input stage of the MEMS microphone system 300 and is applied to the input stages 309A and 309B via high ohmic resistors 305A and 305B, respectively. bias Feedback to the input stage thus forms a feedback loop that ensures a stable static frequency value against PVT variations through closed-loop feedback control. The upper branch circuit, lower branch circuit, and CMFB circuit 317 may be collectively referred to as a VCO-ADC of the MEMS microphone system 300 .

[0040] Figure 4 FIG. 4 shows a circuit diagram of a CMFB circuit 450 in an embodiment. The CMFB circuit 450 can be used as Figure 3 CMFB circuit 317 in. Figure 4 As shown, the CMFB circuit 450 includes a common mode detector 400, an error amplifier 410, and a reference generator 420. The common mode detector 400 uses frequency dependent resistors (FDRs) 404A and 404B to generate a current output i FDR , and the error amplifier 410 outputs the current i FDR Converted to bias voltage to drive high ohmic resistors 305A and 305B (see Figure 3 ) and biases the VCO-ADC input stage. Reference generator 420 automatically compensates for PVT variations, enabling the bias voltage generated by error amplifier 410 to achieve a stable static frequency for VCOs 313A and 313B through closed-loop feedback control. Details are discussed below.

[0041] exist Figure 3 , the common mode detector 400 includes a diode-connected transistor 401 coupled between a power supply voltage node 402 and a node 406. The power supply voltage node 402 is configured to be provided with a power supply voltage V DD (e.g., +3V, +5V, etc.) Frequency dependent resistors (FDRs) 404A and 404B are coupled in parallel between node 406 and a reference voltage node 408 (e.g., for connection to electrical ground). The control terminal f of FDR 404A is p is configured to couple to Figure 4 The output terminal 314A of the VCO 313A receives the frequency modulated signal f vco_p . The control terminal f of FDR 404B n is configured to couple to Figure 4 The output terminal 314B of the VCO 313B receives the frequency modulated signal f vco_n Capacitor 409 is coupled between node 406 and reference voltage node 408. Figure 5In the example, FDRs 404A and 404B have the same structure, and the resistance of FDR 404A (or 404B) is proportional to the frequency modulation signal f vco_p (or f vco_n ) is inversely proportional to the frequency.

[0042] like Figure 5 As shown, FDR 404A includes a transistor 403 and a transistor 405 coupled in series between a node 406 and a reference voltage node 408, wherein transistor 403 is a P-type transistor and transistor 405 is an N-type transistor. The gate terminal of transistor 403 and the gate terminal of transistor 405 are coupled to the control terminal f of FDR 404A. p The FDR 404B has the same structure as the FDR 404A, and the gate terminals of the transistors 403 and 405 of the FDR 404B are coupled to the control terminal f of the FDR 404B. n The working principle of FDR is as follows Figure 4 shown.

[0043] Figure 5 On the left hand side is shown a diagram with Figure 5 The FDRs (e.g., 404A, 404B, 404C) in the FIG404 have the same structure. Figure 4 The middle portion of FIG illustrates an equivalent circuit of FDR 404 when a logic low voltage and a logic high voltage are applied to the control terminal of FDR 404, respectively. Note that the control signal applied to the control terminal of FDR 404 switches between a logic high value and a logic low value at a certain switching frequency. FDR 404 functions as a switched capacitor circuit, whose output resistance is inversely proportional to the input frequency (e.g., the switching frequency of the control signal). Figure 4 The right-hand side of illustrates the FDR 404 as an equivalent resistor having a resistance R determined by the switching frequency at its control terminal, where the resistance R is given by:

[0044]

[0045] where f is the switching frequency (e.g., the frequency of the frequency modulated signal applied at the control terminal), and C FDR is the capacitance of capacitor 407.

[0046] Come back for reference Figure 3 , the common mode detector 400 is implemented by placing FDRs 404A and 404B of equal size in parallel and connecting them to each branch of the VCO-ADC (e.g., upper branch circuit or lower branch circuit). g_p and V g_nThe differential characteristic of the VCO 313A is obtained by applying a differential signal caused by a sound signal to the VCO-ADC. vco_p Frequency f p It can be expressed as f p =f0+Δf, and the output signal f of VCO 313B vco_n Frequency f n It can be expressed as f n =f0-Δf, where f0 is the stationary frequency and Δf is the change in output frequency due to the differential output signal. The equivalent resistance of the parallel-connected FDRs 404A and 404B follows directly from equation (1) and is given by:

[0047]

[0048] As shown in equation (2), when a sound signal is applied to the VCO-ADC, the equivalent resistance of the parallel-connected FDRs 404A and 404B does not change and is inversely proportional to twice the stationary frequency f0. Therefore, a feedback loop can be formed to control the value of the stationary frequency f0 with respect to the reference provided by the reference generator 420. By placing the diode-connected transistor 401 of the current mirror (formed by the diode-connected transistor 401 and the transistor 411 in the error amplifier 410) on the FDR power supply, a current output i proportional to the stationary frequency f0 is obtained. FDR (For example, FDR =V FDRs / R FDRs ). Capacitor 409 is placed in parallel with FDRs 404A and 404B to reduce the current output i caused by the switching of the FDRs. FDR Ripples in the.

[0049] Still refer to Figure 4 The error amplifier 410 includes an output terminal 415 (also referred to as the output terminal V out ) between the transistor 411. The output terminal 415 corresponds to Figure 4 The output terminal 318 of the CMFB circuit 317 in FIG. 4 is connected to the gate terminal of the diode-connected transistor 401 of the common mode detector 400. The diode-connected transistor 401 and the transistor 411 form a current mirror so that the output current i of the common mode detector 400 is FDR The output current i is mirrored into the error amplifier 410 and flows through the load path terminal (eg, source / drain terminal) of the transistor 411. The output current i is converted by the load impedance 413. FDR Converted to the bias voltage V at the output terminal 415 bias ,exist Figure 3In the example, the load impedance 413 is realized as a reference bias voltage V bias_ref Biased transistor 413. Transistor 413 is coupled between output terminal 415 and reference voltage node 408. In some embodiments, the voltage drop across load impedance 413 (which is equal to the bias voltage V at output terminal 415) bias ) is calculated as the output current i FDR Multiply by the drain-source resistance R of transistor 413 RS .

[0050] Reference generator 420 mirrors the design of common-mode detector 400 and error amplifier 410 and eliminates PVT variations of CMFB circuit 450. In some embodiments, components of reference generator 420 are formed to have the same dimensions (e.g., physical dimensions) as corresponding components of common-mode detector 400 and error amplifier 410, and have the same nominal values ​​(e.g., capacitance values) and / or electrical characteristics. By using reference generator 420, all PVT variations are eliminated simultaneously, thereby eliminating the need for calibration of CMFB circuit 450.

[0051] like Figure 6A As shown, reference generator 420 includes a diode-connected transistor 421 connected between supply voltage node 402 and node 426. FDR 404C is coupled between node 426 and reference voltage node 408, wherein FDR 404C has the same structure as FDRs 404A and 404B. Note that the control terminal f of FDR 404C is ref The control terminal f of the FDR 404C is configured to receive a reference frequency signal. ref Corresponding to Figure 6B In some embodiments, the control terminal f ref The applied reference frequency signal is generated by a reference clock source and is a highly accurate clock signal. The frequency of the reference frequency signal has a fixed relationship with the stationary frequency f0 (e.g., proportional to the stationary frequency). Capacitor 429, corresponding to capacitor 409 in common mode detector 400, is coupled between node 426 and reference voltage node 408. Reference generator 420 also includes transistor 431 and transistor 433 coupled in series between power supply voltage node 402 and reference voltage node 408. The gate terminal of transistor 431 is coupled to the gate terminal of diode-connected transistor 421, and the drain terminal of transistor 433 and the gate terminal of transistor 433 are coupled to the gate terminal of transistor 413 of error amplifier 410. In some embodiments, at control terminal f of FDR 404C, the gate terminal of transistor 431 is coupled to the gate terminal of transistor 413 of error amplifier 410. ref The reference frequency signal applied at the control terminal f ref The output current i is proportional to the frequency of the reference frequency signal applied atref , the output current i ref is mirrored into the load path terminal (eg, source / drain terminal) of transistor 431 and converted to a reference bias voltage V bias_ref . Reference bias voltage V bias_ref For properly biasing transistor 413 and generating a bias voltage V at output terminal 415 of CMFB circuit 450 bias .

[0052] The performance of the disclosed VCO-ADC with the CMFB circuit 450 has been simulated and shows that, without the need for calibration, the quiescent frequency is within ±0.8% of the nominal value for all process variations over the temperature range between -20°C and 80°C.

[0053] Figure 4 and Figure 6A Pictured Figure 6B An optional embodiment of the CMFB circuit 450 in. Figure 4 and Figure 4 The CMFB circuit in is similar to the CMFB circuit 450, but with the Figure 6A Reference generator 420 in . In addition, Figure 6B The error amplifier 410 in Figure 6A The transimpedance amplifier 410A and Figure 6B The transimpedance amplifier 410B in FIG. Figure 4 and Figure 6A The common mode detector 400 in Figure 6B The same as in , so no details are shown.

[0054] Figure 7 CMFB circuit 450A is illustrated in which the load impedance of transimpedance amplifier 410A is implemented as resistor 417. Resistor 417 may be implemented as a programmable resistor having an electrical fuse, wherein the resistance of the programmable resistor is programmed (eg, selected) by programming the electrical fuse of the programmable resistor. Figure 3 The CMFB circuit 450B is shown in which the load impedance of the transimpedance amplifier 410B is realized as having a voltage V applied at its gate terminal. bias_M1 By eliminating the reference generator 420, the CMFB circuits 450A and 450B are simpler, less expensive to manufacture, and consume less power. However, without the reference generator 420, the output terminal V out The bias voltage V generated at biasIt may be affected by PVT variations and thus, calibration may be required to compensate for PVT variations. In some embodiments, the calibration process may be accomplished by programming the electrical fuses after manufacturing the semiconductor chip including the CMFB circuit (eg, 450A or 450B).

[0055] Figure 3 FIG. 3 is a block diagram of a MEMS microphone system 300A including a VCO-ADC with a frequency-to-voltage (FTV) conversion circuit 319 in an embodiment. The MEMS microphone system 300A is similar to Figure 8 The MEMS microphone system 300 has a single-ended output signal V g As a result, the MEMS microphone system 300A includes a circuit branch instead of Figure 3 Specifically, the MEMS microphone system 300A includes an input stage 309A, a VCO 313A, and an FTD converter 315A. It is worth noting that the frequency-to-voltage (FTV) conversion circuit 319A is coupled to the output terminal of the VCO 313A and is configured to modulate the frequency of the signal f according to the frequency of the signal f. vco The bias voltage V is generated at the output terminal 320A of the FTV conversion circuit 319A. bais . Bias voltage V bias The reference frequency is fed back to the input stage 309A through the high ohmic resistor 305A. Thus, the MEMS microphone system 300A achieves a stable static frequency through closed-loop control with feedback. Figure 8 ) eliminates the effects of PVT variations, and the MEMS microphone system 300A does not require a calibration process. In some embodiments, the input stage 309, VCO 313A, FTD converter 315, and high ohmic resistor 305A are connected to Figure 8 The input stage 309, VCO 313A, FTD converter 315, high ohm resistor 305A, and FTV conversion circuit 319A may be collectively referred to as the VCO-ADC circuit of the MEMS microphone system 300A. Figure 7 An embodiment of the FTV conversion circuit 319A is discussed.

[0056] Figure 8 The circuit diagram of the FTV conversion circuit 550 in the embodiment is shown. The FTV conversion circuit 550 can be used as Figure 4 In the FTV conversion circuit 319A. Figure 4 In the example of FIG. 5 , the FTV conversion circuit 319A includes a frequency-to-voltage (FTV) converter 500, an error amplifier 510, and a reference generator 520. The FTV converter 500 is similar toFigure 8 The common mode detector 400 in the Figure 4 FDR 404B in the FTV converter 500. in The FTV converter 500 is configured to generate a frequency modulated signal f vco The frequency is proportional to the output current i FDR .

[0057] exist Figure 7 In the example, the error amplifier 510 and the reference generator 520 are respectively Figure 7 The error amplifier 410 and the reference generator 420 in the reference generator 520 are the same. The control terminal f of the FDR 404C in the reference generator 520 is ref The control terminal f of the FDR 404C is configured to receive a reference frequency signal, wherein the frequency of the reference frequency signal has a fixed relationship with the stationary frequency f0 (eg, is proportional to the stationary frequency f0). ref Corresponding to Figure 4 Input terminal 321 in.

[0058] In some embodiments, the transistor 411 of the error amplifier 510 forms a current mirror with the diode-connected transistor 401 of the FTV converter 500 and outputs a current i FDR is converted into a bias voltage V by the load impedance 413 (e.g., a transistor). bias , and the bias voltage V bias It is outputted at the output terminal 415 of the FTV conversion circuit 550. The output terminal 415 corresponds to Figure 6A The reference generator 520 reflects the design of the FTV converter 500 and the error amplifier 510 and is used to eliminate the effects of PVT variations. The working principle of the FTV converter circuit 550 is similar to that of the reference generator 520. Figure 6B 4. After reading this disclosure, a person skilled in the art should be able to easily apply the teachings of the CMFB circuit 450 to the FTV conversion circuit 550 and understand how the FTV conversion circuit 550 works. Therefore, further details about how the FTV conversion circuit 550 works will not be discussed here.

[0059] Variations and modifications to the FTV conversion circuit 550 are possible and are fully intended to be included within the scope of the present disclosure. For example, an alternative embodiment of the FTV conversion circuit may include the FTV converter 500, but in Figure 6A (or Figure 6B ) removes the reference generator 520 and replaces the error amplifier 510 with the transimpedance amplifier 410A (or 410B). In other words,Figure 8 The common mode detector 400 in (or Figure 9 ) can be replaced with the FTV converter 500 in to form an alternative embodiment of the FTV conversion circuit. Figure 7

[0060] Figure 9 A block diagram of a MEMS microphone system 300B including a VCO-ADC with an FTV conversion circuit in an embodiment is illustrated. The MEMS microphone system 300B is similar to the MEMS microphone system 300A in Figure 7 but has a capacitive MEMS microphone 303 that outputs differential output signals V g_p and V g_n . As a result, the MEMS microphone system 300B includes two parallel circuit branches for processing the output signals V g_p and V g_n . For example, the upper circuit branch of the MEMS microphone system 300B includes an input stage 309A, a VCO 313A, an FTD converter 315A, an FTV conversion circuit 319A, and a high-ohmic resistor 305A. The lower circuit branch of the MEMS microphone system 300B includes an input stage 309B, a VCO 313B, an FTD converter 315B, an FTV conversion circuit 319B, and a high-ohmic resistor 305B. The upper branch generates a bias voltage V bias_p that is fed back to the input stage 309A and forms a closed-loop control for stabilizing the rest frequency of the VCO 313A. Similarly, the lower branch generates a bias voltage V bias_n that is fed back to the input stage 309B and forms a closed-loop control for stabilizing the rest frequency of the VCO 313B. In the embodiment shown in Figure 7 , the upper and lower circuit branches are Figure 9 replicas of the circuit branch in Figure 10 . In other words, Figure 10 the circuit branch in can be implemented as twice the upper and lower circuit branches of the circuit in The principle of operation of the MEMS microphone system 300B can be the same or similar to the principle of operation of the MEMS microphone system 300A, and therefore the details are not repeated here.

[0061] Figure 10 A flowchart of a method 1000 of operating a MEMS microphone system in an embodiment is illustrated. It should be understood that the embodiment method shown Figure 10 is merely an example of many possible embodiment methods. Those of ordinary skill in the art will recognize many changes, substitutions, and modifications. For example, various steps shown in ​ may be added, removed, replaced, rearranged, or repeated.

[0062] Reference is made to ​At block 1010, the MEMS microphone generates a differential output signal in response to the sound signal, where the differential output signal includes a first voltage signal at a first output terminal of the MEMS microphone and a second voltage signal at a second output terminal of the MEMS microphone. At block 1020, a first voltage controlled oscillator (VCO) coupled to the first output terminal of the MEMS microphone generates a first frequency modulation signal having a first frequency proportional to the first voltage signal. At block 1030, a second VCO coupled to the second output terminal of the MEMS microphone generates a second frequency modulation signal having a second frequency proportional to the second voltage signal. At block 1040, a common mode feedback (CMFB) circuit coupled to the first VCO and the second VCO generates a bias voltage based on the first frequency modulation signal and the second frequency modulation signal, where the bias voltage is proportional to a quiescent frequency of the first VCO, where the quiescent frequency of the first VCO is the first frequency of the first frequency modulation signal when no sound signal is transmitted to the MEMS microphone. At block 1050, a bias voltage of the MEMS microphone is set by transmitting the bias voltage to a first terminal of a first resistor and a first terminal of a second resistor, where a second terminal of the first resistor and a second terminal of the second resistor are coupled to the first output terminal of the MEMS microphone and the second output terminal of the MEMS microphone, respectively.

[0063] Embodiments can achieve the following advantages as described below. Various embodiments of the VCO-ADC circuit can be used to form a differential MEMS microphone system or a single-ended MEMS microphone system. By using closed-loop feedback control and a reference generator, the effects of PVT variations are eliminated and the quiescent frequency is automatically controlled at the target frequency. The disclosed MEMS microphone system does not require calibration, which reduces production cost and improves system performance.

[0064] Embodiments of the application are summarized here. Other instances can also be appreciated from the entirety of the specification and claims submitted herewith.

[0065] Example 1. In an embodiment, a circuit comprises: a microelectromechanical system (MEMS) microphone configured to generate a differential output signal in response to a sound signal, the differential output signal comprising a first voltage signal at a first output terminal of the MEMS microphone and a second voltage signal at a second output terminal of the MEMS microphone; a first voltage controlled oscillator (VCO) coupled to the first output terminal of the MEMS microphone, wherein the first VCO is configured to output a first frequency modulated signal at an output terminal of the first VCO, the first frequency modulated signal having a first frequency proportional to the first voltage signal; a second VCO coupled to the second output terminal of the MEMS microphone, wherein the second VCO is configured to output a second frequency modulated signal at an output terminal of the second VCO, the second frequency modulated signal having a second frequency proportional to the second voltage signal; a common mode feedback (CMFB) circuit coupled to the output terminal of the first VCO and the output terminal of the second VCO, wherein the CMFB circuit is configured to generate a bias voltage at an output terminal of the CMFB circuit based on the first frequency modulated signal and the second frequency modulated signal, wherein the bias voltage is proportional to a quiescent frequency of the first VCO, wherein the quiescent frequency of the first VCO is the first frequency of the first frequency modulated signal when no sound signal is sent to the MEMS microphone; a first resistor coupled between the first output terminal of the MEMS microphone and the output terminal of the CMFB circuit; and a second resistor coupled between the second output terminal of the MEMS microphone and the output terminal of the CMFB circuit.

[0066] Example 2. The circuit of example 1, wherein the quiescent frequency of the first VCO is the same as a quiescent frequency of the second VCO, wherein the quiescent frequency of the second VCO is the second frequency of the second frequency modulated signal when no sound signal is sent to the MEMS microphone.

[0067] Example 3. The circuit of example 1, wherein the CMFB circuit comprises a common mode detector, wherein the common mode detector comprises: a first diode-connected transistor coupled between a supply voltage node and a first node; a first frequency dependent resistor (FDR) coupled between the first node and a reference voltage node, wherein a control terminal of the first FDR is coupled to the output terminal of the first VCO, wherein a resistance of the first FDR is inversely proportional to the first frequency of the first frequency modulated signal; a second FDR coupled in parallel with the first FDR between the first node and the reference voltage node, wherein a control terminal of the second FDR is coupled to the output terminal of the second VCO, wherein a resistance of the second FDR is inversely proportional to the second frequency of the second frequency modulated signal; and a first capacitor coupled between the first node and the reference voltage node.

[0068] Example 4. The circuit of example 3, wherein the first FDR comprises: a first transistor and a second transistor coupled in series between the first node and a reference voltage node, wherein one of the first transistor and the second transistor is an N-type transistor and the other of the first transistor and the second transistor is a P-type transistor, wherein a gate terminal of the first transistor and a gate terminal of the second transistor are coupled to a control terminal of the first FDR; and a second capacitor coupled between a drain terminal of the second transistor and a source terminal of the second transistor, wherein the second FDR has the same structure as the first FDR.

[0069] Example 5. The circuit of example 4, wherein the CMFB circuit further comprises an error amplifier, wherein the error amplifier comprises: a third transistor coupled between the supply voltage node and an output terminal of the CMFB circuit, wherein a gate terminal of the third transistor is coupled to a gate terminal of the first diode-connected transistor of the common-mode detector; and a fourth transistor coupled between the output terminal of the CMFB circuit and the reference voltage node.

[0070] Example 6. The circuit of example 5, wherein the CMFB circuit further comprises a reference generator, wherein the reference generator comprises: a second diode-connected transistor coupled between the supply voltage node and a second node; a third FDR coupled between the second node and the reference voltage node, wherein the third FDR has the same structure as the first FDR, wherein a control terminal of the third FDR is configured to receive a reference frequency signal; a third capacitor coupled between the second node and the reference voltage node; and a fifth transistor and a sixth transistor coupled in series between the supply voltage node and the reference voltage node, wherein a gate terminal of the fifth transistor is coupled to a gate terminal of the second diode-connected transistor, wherein a drain terminal of the sixth transistor and a gate terminal of the sixth transistor are coupled to a gate terminal of the fourth transistor.

[0071] Example 7. The circuit of example 1, further comprising: a first frequency-to-digital (FTD) converter coupled to the output terminal of the first VCO, wherein the first FTD converter is configured to convert the first frequency modulated signal to a first digital output signal proportional to the first frequency; and a second FTD converter coupled to the output terminal of the second VCO, wherein the second FTD converter is configured to convert the second frequency modulated signal to a second digital output signal proportional to the second frequency.

[0072] Example 8. In an embodiment, a circuit comprises: a microelectromechanical system (MEMS) microphone configured to generate a first voltage signal at a first output terminal of the MEMS microphone in response to a sound signal; a first voltage controlled oscillator (VCO) coupled to the first output terminal of the MEMS microphone, wherein the first VCO is configured to output a first frequency modulated signal at an output terminal of the first VCO, the first frequency modulated signal having a first frequency proportional to the first voltage signal; a first frequency to digital (FTD) converter coupled to the output terminal of the first VCO, wherein the first FTD converter is configured to convert the first frequency modulated signal to a first digital output signal proportional to the first frequency; a first frequency to voltage (FTV) conversion circuit coupled to the output terminal of the first VCO, wherein the first FTV conversion circuit is configured to generate a first bias voltage from the first frequency modulated signal, and configured to output the first bias voltage at an output terminal of the first FTV conversion circuit; and a first resistor coupled between the first output terminal of the MEMS microphone and the output terminal of the first FTV conversion circuit.

[0073] Example 9. The circuit of example 8, wherein the first bias voltage sets a rest frequency of the first VCO.

[0074] Example 10. The circuit of example 8, wherein the first FTV conversion circuit comprises a first FTV converter, wherein the first FTV converter comprises: a diode-connected transistor coupled between a supply voltage node and a first node; a frequency dependent resistor (FDR) coupled between the first node and a reference voltage node, wherein a control terminal of the FDR is coupled to the output terminal of the first VCO, wherein a resistance of the FDR is inversely proportional to a frequency of a control signal applied at the control terminal of the FDR; and a first capacitor coupled between the first node and the reference voltage node.

[0075] Example 11. The circuit of example 10, wherein the FDR comprises: a first transistor and a second transistor coupled in series between the first node and the reference voltage node, wherein one of the first transistor and the second transistor is an N-type transistor and the other of the first transistor and the second transistor is a P-type transistor, wherein a gate terminal of the first transistor and a gate terminal of the second transistor are coupled to the control terminal of the FDR; and a second capacitor coupled between a drain terminal of the second transistor and a source terminal of the second transistor.

[0076] Example 12. The circuit of example 11, wherein the first FTV conversion circuit further comprises a first error amplifier, wherein the first error amplifier comprises: a third transistor coupled between the supply voltage node and an output terminal of the first FTV conversion circuit, wherein a gate terminal of the third transistor is coupled to the gate terminal of the diode-connected transistor of the first FTV converter; and a fourth transistor coupled between the output terminal of the first FTV conversion circuit and the reference voltage node.

[0077] Example 13. The circuit of example 12, wherein the first FTV conversion circuit further comprises a first reference generator, wherein the first reference generator comprises: a second FTV converter coupled between the supply voltage node and the reference voltage node, wherein the second FTV converter has the same structure as the first FTV converter, wherein a control terminal of the FDR of the second FTV converter is configured to receive the reference frequency signal; and a fifth transistor and a sixth transistor coupled in series between the supply voltage node and the reference voltage node, wherein a gate terminal of the fifth transistor is coupled to the gate terminal of the diode-connected transistor of the second FTV converter, wherein a drain terminal of the sixth transistor and a gate terminal of the sixth transistor are coupled to the gate terminal of the fourth transistor.

[0078] Example 14. The circuit of example 11, wherein the first FTV conversion circuit further comprises a transimpedance amplifier, wherein the transimpedance amplifier comprises: a third transistor coupled between the supply voltage node and an output terminal of the first FTV conversion circuit, wherein a gate terminal of the third transistor is coupled to the gate terminal of the diode-connected transistor of the first FTV converter; and a second resistor or a fourth transistor coupled between the output terminal of the first FTV conversion circuit and the reference voltage node.

[0079] Example 15. The circuit of example 13, wherein the MEMS microphone is configured to generate a differential output signal comprising a first voltage signal at a first output terminal of the MEMS microphone and a second voltage signal at a second output terminal of the MEMS microphone, wherein the circuit further comprises: a second VCO coupled to the second output terminal of the MEMS microphone, wherein the second VCO is configured to output a second frequency modulated signal at an output terminal of the second VCO, the second frequency modulated signal having a second frequency proportional to the second voltage signal; a second FTD converter coupled to the output terminal of the second VCO, wherein the second FTD converter is configured to convert the second frequency modulated signal to a second digital output signal proportional to the second frequency; a second FTV conversion circuit coupled to the output terminal of the second VCO, wherein the second FTV conversion circuit is configured to generate a second bias voltage from the second frequency modulated signal, and configured to output the second bias voltage at an output terminal of the second FTV conversion circuit; and a second resistor coupled between the second output terminal of the MEMS microphone and the output terminal of the second FTV conversion circuit.

[0080] Example 16. The circuit of example 15, wherein the first VCO and the second VCO have the same structure, wherein the first FTD converter and the second FTD converter have the same structure, wherein the first FTV conversion circuit and the second FTV conversion circuit have the same structure.

[0081] Example 17. In an embodiment, a method of operating a microelectromechanical system (MEMS) microphone system includes: generating, by a MEMS microphone, a differential output signal in response to a sound signal, wherein the differential output signal includes a first voltage signal at a first output terminal of the MEMS microphone and a second voltage signal at a second output terminal of the MEMS microphone; generating, by a first voltage controlled oscillator (VCO) coupled to the first output terminal of the MEMS microphone, a first frequency modulated signal, the first frequency modulated signal having a first frequency proportional to the first voltage signal; generating, by a second VCO coupled to the second output terminal of the MEMS microphone, a second frequency modulated signal, the second frequency modulated signal having a second frequency proportional to the second voltage signal; generating, by a common mode feedback (CMFB) circuit coupled to the first VCO and the second VCO, a bias voltage based on the first frequency modulated signal and the second frequency modulated signal, wherein the bias voltage is proportional to a quiescent frequency of the first VCO, wherein the quiescent frequency of the first VCO is the first frequency of the first frequency modulated signal when no sound signal is transmitted to the MEMS microphone; and setting a bias voltage of the MEMS microphone by transmitting the bias voltage to a first terminal of a first resistor and a first terminal of a second resistor, wherein a second terminal of the first resistor and a second terminal of the second resistor are coupled to the first output terminal of the MEMS microphone and the second output terminal of the MEMS microphone, respectively.

[0082] Example 18. The method of example 17, further comprising: converting, using a first frequency to digital (FTD) converter coupled to the first VCO, the first frequency modulated signal to a first digital output signal proportional to the first frequency; and converting, using a second FTD converter coupled to the second VCO, the second frequency modulated signal to a second digital output signal proportional to the second frequency.

[0083] Example 19. The method of example 17, wherein generating the bias voltage includes: generating, by a common mode detector of the CMFB circuit, a current signal based on the first frequency modulated signal and the second frequency modulated signal, wherein the current signal is proportional to the quiescent frequency of the first VCO, wherein the CMFB circuit includes a first frequency dependent resistor (FDR) and a second FDR coupled in parallel, wherein a first resistance of the first FDR and a second resistance of the second FDR are inversely proportional to the first frequency and the second frequency, respectively, wherein a first control terminal of the first FDR and a second control terminal of the second FDR are configured to receive the first frequency modulated signal and the second frequency modulated signal, respectively; generating, by an error amplifier of the CMFB circuit, a mirror current of the current signal; and converting, by the error amplifier, the mirror current to the bias voltage by causing the mirror current to flow through a bias transistor.

[0084] Example 20. The method of example 19, wherein generating the bias voltage further comprises: providing a reference frequency signal to a reference generator of the CMFB circuit, wherein the reference generator is configured to generate a reference bias voltage proportional to a frequency of the reference frequency signal; and sending the reference bias voltage to the gate of the bias transistor.

[0085] While the application has been described with reference to illustrative examples, the description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative examples, as well as other examples, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or examples.

Claims

1. A circuit comprising: a microelectromechanical system (MEMS) microphone configured to generate a differential output signal in response to a sound signal, the differential output signal comprising a first voltage signal at a first output terminal of the MEMS microphone and a second voltage signal at a second output terminal of the MEMS microphone; a first voltage controlled oscillator (VCO) coupled to the first output terminal of the MEMS microphone, wherein the first VCO is configured to output a first frequency modulated signal at an output terminal of the first VCO, the first frequency modulated signal having a first frequency proportional to the first voltage signal; a second VCO coupled to the second output terminal of the MEMS microphone, wherein the second VCO is configured to output a second frequency modulated signal at an output terminal of the second VCO, the second frequency modulated signal having a second frequency proportional to the second voltage signal; a common mode feedback (CMFB) circuit coupled to the output terminal of the first VCO and the output terminal of the second VCO, wherein the CMFB circuit is configured to generate a bias voltage at an output terminal of the CMFB circuit based on the first frequency modulated signal and the second frequency modulated signal, wherein the bias voltage is proportional to a quiescent frequency of the first VCO, wherein the quiescent frequency of the first VCO is the first frequency of the first frequency modulated signal when no sound signal is transmitted to the MEMS microphone; a first resistor coupled between the first output terminal of the MEMS microphone and the output terminal of the CMFB circuit; and a second resistor coupled between the second output terminal of the MEMS microphone and the output terminal of the CMFB circuit.

2. The circuit of claim 1, wherein the quiescent frequency of the first VCO is the same as a quiescent frequency of the second VCO, wherein the quiescent frequency of the second VCO is the second frequency of the second frequency modulated signal when no sound signal is transmitted to the MEMS microphone.

3. The circuit of claim 1, wherein the CMFB circuit comprises a common mode detector, wherein the common mode detector comprises: a first diode-connected transistor coupled between a supply voltage node and a first node; a first frequency dependent resistor (FDR) coupled between the first node and a reference voltage node, wherein a control terminal of the first FDR is coupled to the output terminal of the first VCO, wherein a resistance of the first FDR is inversely proportional to the first frequency of the first frequency modulated signal; a second FDR coupled in parallel with the first FDR between the first node and the reference voltage node, wherein a control terminal of the second FDR is coupled to the output terminal of the second VCO, wherein a resistance of the second FDR is inversely proportional to the second frequency of the second frequency modulated signal; and a first capacitor coupled between the first node and the reference voltage node. ​ ​ 4. The circuit of claim 3, wherein the first FDR comprises: a first transistor and a second transistor coupled in series between the first node and the reference voltage node, wherein one of the first transistor and the second transistor is an N-type transistor and the other of the first transistor and the second transistor is a P-type transistor, wherein a gate terminal of the first transistor and a gate terminal of the second transistor are coupled to the control terminal of the first FDR; and a second capacitor coupled between a drain terminal of the second transistor and a source terminal of the second transistor, wherein the second FDR has the same structure as the first FDR.

5. The circuit of claim 4, wherein the CMFB circuit further comprises an error amplifier, wherein the error amplifier comprises: a third transistor coupled between the supply voltage node and the output terminal of the CMFB circuit, wherein a gate terminal of the third transistor is coupled to a gate terminal of the first diode-connected transistor of the common mode detector; and a fourth transistor coupled between the output terminal of the CMFB circuit and the reference voltage node.

6. The circuit of claim 5, wherein the CMFB circuit further comprises a reference generator, wherein the reference generator comprises: a second diode-connected transistor coupled between the supply voltage node and a second node; a third FDR coupled between the second node and the reference voltage node, wherein the third FDR has the same structure as the first FDR, wherein a control terminal of the third FDR is configured to receive a reference frequency signal; a third capacitor coupled between the second node and the reference voltage node; and a fifth transistor and a sixth transistor coupled in series between the supply voltage node and the reference voltage node, wherein a gate terminal of the fifth transistor is coupled to a gate terminal of the second diode-connected transistor, wherein a drain terminal of the sixth transistor and a gate terminal of the sixth transistor are coupled to a gate terminal of the fourth transistor.

7. The circuit of claim 1, further comprising: a first frequency-to-digital (FTD) converter coupled to the output terminal of the first VCO, wherein the first FTD converter is configured to convert the first frequency modulated signal to a first digital output signal proportional to the first frequency; and a second FTD converter coupled to an output terminal of the second VCO, wherein the second FTD converter is configured to convert the second frequency modulated signal to a second digital output signal proportional to the second frequency.

8. A circuit comprising: a microelectromechanical system (MEMS) microphone configured to generate a first voltage signal at a first output terminal of the MEMS microphone in response to a sound signal; a first voltage-controlled oscillator VCO coupled to the first output terminal of the MEMS microphone, wherein the first VCO is configured to output a first frequency modulated signal at an output terminal of the first VCO, the first frequency modulated signal having a first frequency proportional to the first voltage signal; a first frequency-to-digital FTD converter coupled to the output terminal of the first VCO, wherein the first FTD converter is configured to convert the first frequency modulated signal to a first digital output signal proportional to the first frequency; a first frequency-to-voltage FTV conversion circuit coupled to the output terminal of the first VCO, wherein the first FTV conversion circuit is configured to generate a first bias voltage from the first frequency modulated signal, and configured to output the first bias voltage at an output terminal of the first FTV conversion circuit; and a first resistor coupled between the first output terminal of the MEMS microphone and the output terminal of the first FTV conversion circuit.

9. The circuit of claim 8, wherein the first bias voltage sets a quiescent frequency of the first VCO.

10. The circuit of claim 8, wherein the first FTV conversion circuit comprises a first FTV converter, wherein the first FTV converter comprises: a diode-connected transistor coupled between a supply voltage node and a first node; a frequency-dependent resistor FDR coupled between the first node and a reference voltage node, wherein a control terminal of the FDR is coupled to the output terminal of the first VCO, wherein a resistance of the FDR is inversely proportional to a frequency of a control signal applied at the control terminal of the FDR; and a first capacitor coupled between the first node and the reference voltage node.

11. The circuit of claim 10, wherein the FDR comprises: a first transistor and a second transistor coupled in series between the first node and the reference voltage node, wherein one of the first transistor and the second transistor is an N-type transistor and the other of the first transistor and the second transistor is a P-type transistor, wherein a gate terminal of the first transistor and a gate terminal of the second transistor are coupled to the control terminal of the FDR; and a second capacitor coupled between a drain terminal of the second transistor and a source terminal of the second transistor.

12. The circuit of claim 11, wherein the first FTV conversion circuit further comprises a first error amplifier, wherein the first error amplifier comprises: a third transistor coupled between the supply voltage node and the output terminal of the first FTV conversion circuit, wherein a gate terminal of the third transistor is coupled to a gate terminal of the diode-connected transistor of the first FTV converter; and a fourth transistor coupled between the output terminal of the first FTV conversion circuit and the reference voltage node. ​ ​ ​ ​ 13. The circuit of claim 12, wherein, The first FTV conversion circuit further includes a first reference generator, wherein the first reference generator includes: a second FTV converter coupled between the supply voltage node and the reference voltage node, wherein the second FTV converter has a same structure as the first FTV converter, wherein a control terminal of a FDR of the second FTV converter is configured to receive a reference frequency signal; and a fifth transistor and a sixth transistor coupled in series between the supply voltage node and the reference voltage node, wherein a gate terminal of the fifth transistor is coupled to a gate terminal of a diode-connected transistor of the second FTV converter, wherein a drain terminal of the sixth transistor and a gate terminal of the sixth transistor are coupled to a gate terminal of the fourth transistor.

14. The circuit of claim 11, wherein the first FTV conversion circuit further includes a transimpedance amplifier, wherein the transimpedance amplifier includes: a third transistor coupled between the supply voltage node and the output terminal of the first FTV conversion circuit, wherein a gate terminal of the third transistor is coupled to a gate terminal of the diode-connected transistor of the first FTV converter; and a second resistor or a fourth transistor coupled between the output terminal of the first FTV conversion circuit and the reference voltage node.

15. The circuit of claim 13, wherein the MEMS microphone is configured to generate a differential output signal including the first voltage signal at the first output terminal of the MEMS microphone and a second voltage signal at a second output terminal of the MEMS microphone, wherein the circuit further includes: a second VCO coupled to the second output terminal of the MEMS microphone, wherein the second VCO is configured to output a second frequency modulated signal at an output terminal of the second VCO, the second frequency modulated signal having a second frequency proportional to the second voltage signal; a second FTD converter coupled to the output terminal of the second VCO, wherein the second FTD converter is configured to convert the second frequency modulated signal to a second digital output signal proportional to the second frequency; a second FTV conversion circuit coupled to the output terminal of the second VCO, wherein the second FTV conversion circuit is configured to generate a second bias voltage from the second frequency modulated signal, and configured to output the second bias voltage at an output terminal of the second FTV conversion circuit; and a second resistor coupled between the second output terminal of the MEMS microphone and the output terminal of the second FTV conversion circuit.

16. The circuit of claim 15, wherein the first VCO and the second VCO have a same structure, wherein the first FTD converter and the second FTD converter have a same structure, wherein the first FTV conversion circuit and the second FTV conversion circuit have a same structure.

17. A method of operating a microelectromechanical system (MEMS) microphone system, the method comprising: generating, by a MEMS microphone, a differential output signal in response to a sound signal, wherein the differential output signal comprises a first voltage signal at a first output terminal of the MEMS microphone and a second voltage signal at a second output terminal of the MEMS microphone; generating, by a first voltage controlled oscillator (VCO) coupled to the first output terminal of the MEMS microphone, a first frequency modulated signal having a first frequency proportional to the first voltage signal; generating, by a second VCO coupled to the second output terminal of the MEMS microphone, a second frequency modulated signal having a second frequency proportional to the second voltage signal; generating, by a common mode feedback (CMFB) circuit coupled to the first VCO and the second VCO, a bias voltage based on the first frequency modulated signal and the second frequency modulated signal, wherein the bias voltage is proportional to a rest frequency of the first VCO, wherein the rest frequency of the first VCO is the first frequency of the first frequency modulated signal when no sound signal is transmitted to the MEMS microphone; and setting a bias voltage of the MEMS microphone by transmitting the bias voltage to a first terminal of a first resistor and a first terminal of a second resistor, wherein a second terminal of the first resistor and a second terminal of the second resistor are coupled to the first output terminal of the MEMS microphone and the second output terminal of the MEMS microphone, respectively.

18. The method of claim 17, further comprising: converting, using a first frequency to digital (FTD) converter coupled to the first VCO, the first frequency modulated signal to a first digital output signal proportional to the first frequency; and converting, using a second FTD converter coupled to the second VCO, the second frequency modulated signal to a second digital output signal proportional to the second frequency.

19. The method of claim 17, wherein generating the bias voltage comprises: generating, by a common mode detector of the CMFB circuit, a current signal based on the first frequency modulated signal and the second frequency modulated signal, wherein the current signal is proportional to the rest frequency of the first VCO, wherein the CMFB circuit comprises a first frequency dependent resistor (FDR) and a second FDR coupled in parallel, wherein a first resistance of the first FDR and a second resistance of the second FDR are inversely proportional to the first frequency and the second frequency, respectively, wherein a first control terminal of the first FDR and a second control terminal of the second FDR are configured to receive the first frequency modulated signal and the second frequency modulated signal, respectively; generating, by an error amplifier of the CMFB circuit, a mirror current of the current signal; and converting, by the error amplifier, the mirror current to the bias voltage by flowing the mirror current through a bias transistor.

20. The method of claim 19, wherein generating the bias voltage further comprises: providing a reference frequency signal to a reference generator of the CMFB circuit, wherein the reference generator is configured to generate a reference bias voltage proportional to a frequency of the reference frequency signal; and sending the reference bias voltage to a gate of the bias transistor.

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