ERROR DETECTION

Description

Domaine technique

[0001] This description relates, in general, to electronic systems and circuits, and, more particularly, to electronic systems and circuits comprising memories. This description relates, even more particularly, to the reading and writing of data in these memories, and, more precisely, to the detection of errors during readings or writings of data. Technique antérieure

[0002] Data management during the operation of a system or electronic circuit generally requires the use of one or more memories. Operating data is, for example, written to and / or read from these memories before or after being used.

[0003] Document EP2095234 A1 discloses a system for storing data in a main memory comprising a unit adapted to generate an ECC code from data to be stored.

[0004] Document EP3489830 A1 discloses a memory device implementing the integrity of stored data by using error detection codes and separate storage areas for data and their associated error codes.

[0005] Many errors, or faults, can be encountered during the reading and / or writing of data in a memory. For example, a read error can consist of reading data at an incorrect address. A write error can consist of writing data at an incorrect address. These errors can be accidental or intentional. For example, a deliberate error can be produced by a fault injection process, for example implemented by an attacker, with the aim of modifying the operation of the electronic system.

[0006] It would be desirable to be able to improve, at least in part, certain aspects of the methods for reading and / or writing data in memory, and more particularly, certain aspects of the methods for detecting errors in reading and / or writing data in memory. Résumé de l'invention

[0007] There is a need for more reliable methods of reading and / or writing data into memories.

[0008] There is a need for more efficient methods for detecting read and / or write errors.

[0009] There is a need for methods for detecting read and / or write errors adapted to detect errors in which data is written to an incorrect address.

[0010] One embodiment overcomes all or part of the drawbacks of known methods for writing data to memory.

[0011] One embodiment overcomes all or part of the drawbacks of known methods for reading data from memory.

[0012] One embodiment overcomes all or part of the drawbacks of known methods for detecting memory reading and / or writing errors.

[0013] One embodiment provides a method for writing data into memory, in which: a binary word, representative of said data and of an error correction or detection code, is split into at least a first and a second part; and said first part is written to a logical address in a first memory circuit; and said second part is written to said logical address in a second memory circuit adapted to store as many binary words as said first memory circuit, said error correction or detection code being dependent on said data and said address.

[0014] According to one embodiment, said first and second parts are of the same size.

[0015] According to one embodiment, the binary word is a concatenation of said data and said error correcting or detecting code.

[0016] According to one embodiment, said data and said address are provided by a single first processor.

[0017] According to one embodiment, said data and said address are provided by at least a second processor and a third processor.

[0018] According to one embodiment, said data provided by the second processor is compared to said data provided by the third processor, and said address provided by the second processor is compared to said address provided by the third processor.

[0019] According to one embodiment, the second processor provides said address to one of said at least two memory circuits, and the third processor provides said address to another of said at least two memory circuits.

[0020] According to one embodiment, the second processor provides said address to said at least two memory circuits.

[0021] According to one embodiment, said first and second memory circuits are of the same size.

[0022] According to one embodiment, internal control signals of said at least two memory circuits are compared.

[0023] Another embodiment provides a method of reading data written according to the method described above.

[0024] According to one embodiment, said binary word is formed by concatenating said first and second parts read in said first and second memory circuits.

[0025] According to one embodiment, the data is obtained by removing the error correcting or detecting code from the binary word.

[0026] Another embodiment provides a method for detecting an error in data written by the method described above, in which the error correcting or detecting code is recalculated from the data read by the method described above.

[0027] According to one embodiment, the error correcting or detecting code is verified.

[0028] Another embodiment provides a method for detecting a write error of data in memory in which: at least two parts of the same size of a binary word representative of said data are stored at the same address in at least two identical memory circuits; and internal control signals of the two memory circuits are compared.

[0029] According to one embodiment, the internal signals comprise a word signal.

[0030] According to one embodiment, the internal signals comprise a signal for selecting one of the memory circuits.

[0031] According to one embodiment, the internal signals include a write enable signal.

[0032] According to one embodiment, the internal signals include a column selection / number signal.

[0033] According to one embodiment, the internal signals include a line selection / number signal.

[0034] According to one embodiment, the binary word is obtained from said data and an error correcting or detecting code, said error correcting or detecting code being representative of said data and said address.

[0035] According to one embodiment, the binary word is obtained by concatenation of said data and the error correcting or detecting code.

[0036] According to one embodiment, the error correcting or detecting code is representative of said data and said address.

[0037] According to one embodiment, the error correcting or detecting code is obtained by a signature method. Brève description des dessins

[0038] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: there figure 1 represents, schematically and in the form of blocks, a part of an architecture of an embodiment of an electronic system; the figure 2 represents, schematically and in the form of blocks, another part of the architecture of the system of the figure 1 ; there figure 3 represents, schematically and in block form, a part of an architecture of another embodiment of an electronic system; figure 4 represents, schematically and in the form of blocks, another part of the architecture of the system of the figure 3 ; there figure 5 represents, schematically and in block form, a part of an architecture of another embodiment of an electronic system; figure 6 represents, schematically and in the form of blocks, another part of the architecture of the system of the figure 5 ; there figure 7 represents, schematically and in block form, a part of an architecture of another embodiment of an electronic system; figure 8 represents, schematically and in the form of blocks, another part of the architecture of the system of the figure 7 ; there figure 9 represents, schematically and in the form of blocks, a part of an architecture of a memory circuit; and the figure 10 represents, schematically and in block form, part of the architecture of another embodiment of an electronic system. Description des modes de réalisation

[0039] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0040] For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been represented and are detailed.

[0041] Unless otherwise specified, when two elements are connected together, this means directly connected without intermediate elements other than conductors, and when two elements are connected or coupled together, this means that these two elements can be connected or be connected or coupled through one or more other elements.

[0042] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0043] In the remainder of the description, the formation of several secondary binary words from bits of the initial binary word is called splitting, cutting, or division of an initial binary word into several parts. More precisely, each secondary binary word is composed in such a way that the concatenation of all the secondary binary words, in a specific order, gives the initial binary word.

[0044] Furthermore, in the remainder of the description, a logical address is an address generated by a processor and intended for a memory circuit. This address is decoded by an address decoder circuit associated with the memory circuit and which provides a physical address in terms of coordinates (row-column) in the memory plane.

[0045] There figure 1 represents, schematically and in the form of blocks, a part 10 of an architecture of an embodiment of an electronic system 1. The part 10 is adapted to writing data into the memory of the electronic system 1.

[0046] Part 10 includes: a processor 101 (CPU); a circuit 102 (EDC GEN) for generating an error correction or detection code; a circuit 103 (EDC ADD) for forming a binary word; a circuit 104 (SPLIT) for dividing a binary word; two memory circuits 105 (MEM1) and 106 (MEM2); and an address decoder circuit 107 (ADD DEC).

[0047] The processor 101 is a processor adapted to request the writing of data in the memories 105 and 106. The processor 101 provides, as output, a data item Data1 to be written and a logical address AddL1. The address AddL1 is the logical address to which the data item Data1 must be written in memory. For example, the logical address AddL1 is a binary word whose high-order bits indicate the row of the memory circuit to which the binary word must be written, and the low-order bits indicate the column of the memory circuit to which the binary word must be written.

[0048] The circuit 102 for generating an error correcting or detecting code is a circuit adapted to calculate an error detecting code EDC1 (EDC), or an error correcting code (ECC), representative of the data Data1 and the logical address AddL1. Thus, the circuit 102 receives, as input, the data Data1 and the logical address AddL1, and provides, as output, the error correcting or detecting code EDC1. For example, the EDC1 code is obtained using a signature algorithm.

[0049] The circuit 103 for forming a binary word is a circuit adapted to form a binary word Code1 representative of the data Data1 and the code EDC1. The circuit 103 receives, as input, the data Data1 and the code EDC1, and provides, as output, the binary word Code1. For example, the data Data1 and the code EDC1 are concatenated by the circuit 103 to form the binary word Code1. The order in which the data Data1 and the code EDC1 are concatenated to form the binary word Code1 is not important.

[0050] The binary word division circuit 104 is a circuit adapted to split the binary word Code1 into several binary words. The circuit 104 receives, as input, the binary word Code1, and provides, as output, in this example, two binary words Code1A and Code1B. In other words, the concatenation of the binary words Code1A and Code1B, in a specific order, gives the binary word Code1. The binary words Code1A and Code1B are, for example, of different sizes. As a variant, the binary words Code1A and Code1B are of the same size, that is to say that they each comprise half of the bits of the binary word Code1.

[0051] The address decoder circuit 107 is a circuit adapted to provide physical addresses readable by memory circuits from a logical address. The circuit 107 receives, as input, the logical address AddL1, and provides, as output, two physical addresses Add1A and Add1B. The circuit 107 makes it possible, more particularly, to define, from the logical address AddL1 provided by the processor 101, the two physical addresses Add1A and Add1B at which the binary words Code1A and Code1B will be written in the memory circuits 105 and 106. For example, the addresses Add1A and Add1B are identical.

[0052] The memory circuits 105 and 106 are adapted to store the binary words Code1A and Code1B respectively at the addresses Add1A and Add1B. Thus, the memory 105 receives, as input, the binary word Code1A and the address Add1A, and the memory 106 receives, as input, the binary word Code1B and the address Add1B. The memory circuits 105 and 106 are adapted to store the same number of binary words. The memory circuits 105 and 106 are, for example, volatile memories. For example, the memory circuits 105 and 106 are of the same size.

[0053] Alternatively, part 10 could comprise more than two memory circuits identical in structure and size. In this case, circuit 104 would be adapted to provide as many binary words as there are memory circuits included in part 10. In other words, circuit 104 is adapted to divide the binary word Code1 into as many parts as there are memory circuits included in part 10. In addition, circuit 107 is adapted to provide as many physical addresses from the logical address AddL1 as there are memory circuits included in part 10.

[0054] A method of writing the data Data1 into memory implementing part 10 of the system 1 is as follows. When the processor 101 wants to store the data Data1 in memory, it generates the address AddL1 at which it wishes to store it. The processor 101 then provides the data Data1 and the logical address AddL1 to the circuit 102 so that the latter generates the code EDC1. In parallel, the address AddL1 is converted into two physical addresses Add1A and Add1B by the circuit 107. The data Data1 and the code EDC1 are then used, by the circuit 103, to provide the binary word Code1. The binary word Code1 is then divided into two parts, the two binary words Code1A and Code1B, by the circuit 104. The binary words Code1A and Code1B are stored, respectively, in the memory circuit 105 and in the memory circuit 106 at the addresses Add1A and Add1B. Thus, the data Data1 is stored in the memory circuits 105 and 106, in the form of the binary words Code1A and Code1B.

[0055] There figure 2 represents, schematically and in the form of blocks, another part 11 of the architecture of the embodiment of the electronic system 1, part 10 of which is described in relation to the figure 1 . Part 11 is suitable for reading data from memories of the electronic system 1. More particularly, Part 11 is, in figure 2 , suitable for reading the data Data1 written in memory at the address AddL1 as described in relation to the figure 1 .

[0056] Part 11 includes: a processor 111 (CPU); a circuit 112 (EDC CHECK) for verifying a correcting or error-detecting code; a circuit 113 (EDC REMOVAL) for recovering data; a circuit 114 (MERGE) for concatenating binary words; the two identical memory circuits 105 (MEM1) and 106 (MEM2); and the circuit 107 (ADD DEC) address decoder.

[0057] The processor 111 is a processor adapted to request the reading of data in the memories 105 and 106. The processor 111 provides, as output, an address, for example the logical address AddL1 described in relation to the figure 1 , and receives, as input, a data item corresponding to the address, that is to say the data item Data1 described in relation to the figure 1 . The processor 111 is, for example, the same processor as the processor 101 described in connection with the figure 1 , but, alternatively, the processor 111 may be a separate processor from the processor 101 described in connection with the figure 1 .

[0058] The circuit 112 for verifying an error correcting or detecting code is a circuit adapted to verify the EDC1 code associated with the data Data1. The circuit 112 receives, as input, the binary word Code1 and the logical address AddL1, and provides, as output, an error signal ErrEDC1. To verify the EDC1 code, the circuit 112 finds, from the binary word Code1, the data Data1 and the EDC1 code. Then, the circuit 112 calculates a new error detecting or correcting code from the data Data1 and the address AddL1 provided by the processor 111. The new code is then compared to the EDC1 code. If they are equal, then there is no error. If they are not, then there is an error. Any error is indicated by means of the signal ErrEDC1. The circuit 102 described in relation to the figure 1 is, for example, part of circuit 112, but, alternatively, circuits 102 and 112 may be separate circuits.

[0059] The data recovery circuit 113 is a circuit adapted to recover the data Data1 from the binary word Code1. The circuit 113 receives, as input, the binary word Code1, and provides, as output, the data Data1. For example, when the binary word Code1 is a concatenation of the data Data1 and the code EDC1, the circuit 113 is adapted to truncate the code EDC1 from the binary word Code1, and, thus, to retain only the data Data1. The circuit 113 and the circuit 103 described in relation to the figure 1 may, for example, be part of the same circuit, or may, alternatively, be two separate circuits.

[0060] The binary word concatenation circuit 114 is a circuit adapted to recover the binary word Code1 from the two binary words Code1A and Code1B. Thus, the circuit 114 receives, as input, the binary words Code1A and Code1B, and provides, as output, the binary word Code1. The circuit 114 is particularly adapted to concatenate the binary words Code1A and Code1B in the correct order to recover the initial binary word Code1. The circuit 114 and the circuit 104 described in relation to the figure 1 may, for example, be part of the same circuit, or may, alternatively, be two separate circuits.

[0061] Alternatively, parts 10 and 11 could comprise more than two memory circuits. In this case, circuit 114 is adapted to receive, as input, as many binary words as there are memory circuits included in parts 10 and 11. In other words, circuit 114 is adapted to reform the binary word Code1 from as many binary words as there are memory circuits included in parts 10 and 11. In addition, circuit 107 is, in this case, adapted to provide as many physical addresses as necessary.

[0062] A method for reading the data Data1 implementing part 11 of the system 1 is as follows. The processor 111 provides the circuit 107 with the address AddL1 at which it wants to read a data item, in this case the data item Data1. The circuit 107 provides the memories 105 and 106 with the physical addresses Add1A and Add1B from the logical address AddL1. At the address Add1A of the memory circuit 105 is stored the binary word Code1A, and at the address Add1B of the memory circuit 106 is stored the binary word Code1B. The memory circuits 105 and 106 provide the circuit 114 with the two binary words Code1A and Code1B to reform the binary word Code1. Circuit 113 is responsible for extracting the data Data1 from the binary word Code1 and transmitting it to the processor 111. Circuit 112, for its part, checks whether there is no error, by verifying the code EDC1.

[0063] An advantage of this embodiment is that, during the reading process, the circuit 112 makes it possible to detect an addressing error of the data item Data1. Indeed, the code EDC1 being representative of the data item Data1 and of the logical address AddL1 to which the data item was written, the comparison of the code EDC1 with a code generated from the logical address AddL1 provided by the processor 111 can make it possible to detect a difference in logical addresses.

[0064] There figure 3 represents, schematically and in the form of blocks, a part 20 of an architecture of an embodiment of an electronic system 2. The part 20 is adapted to writing data into the memory of the electronic system 2.

[0065] Part 20 includes: two processors 201 (CPU1) and 202 (CPU2); a circuit 203 (EDC Gen) for generating a correcting or error-detecting code; a circuit 204 (EDC ADD) for forming a binary word; a circuit 205 (SPLIT) for dividing a binary word; two memory circuits 206 (MEM1) and 207 (MEM2); two address decoder circuits 209A (ADD DEC 1) and 209B (ADD DEC 2); and a comparison circuit 208 (COMP).

[0066] The processors 201 and 202 are processors identical in structure and adapted to provide the same data and commands. The processors 201 and 202 are, more particularly, processors adapted to request the writing of data in the memories 206 and 207. Each processor 201, 202 provides, as output, a data item Data2 and a logical address AddL2. The address AddL2 is the logical address to which the data item Data2 must be written. The use of the two processors 201 and 202 in parallel allows, among other things, the detection of errors by redundancy checks.

[0067] The circuit 203 for generating a correcting or error-detecting code is a circuit identical to the circuit 102 described in relation to the figure 1 . The circuit 203 receives, as input, the data Data2 coming from the processor 201, and the logical address AddL2 coming from the processor 201. The circuit 203 provides, as output, a correcting code or error detector EDC2.

[0068] The circuit 204 for forming a binary word is a circuit identical to the circuit 103 described in relation to the figure 1 The circuit 204 receives, as input, the code EDC2 and the data Data2 coming from the processor 201, and provides, as output, a binary word Code2.

[0069] The circuit 205 for dividing a binary word is a circuit identical to the circuit 104 described in relation to the figure 1 . Circuit 205 receives, as input, the binary word Code2, and provides, as output, two binary words Code2A and Code2B corresponding to two parts of the binary word Code2.

[0070] Circuits 209A and 209B are circuits similar to circuit 107 described in connection with the figure 1 . The circuit 209A receives, as input, the logical address AddL2 coming from the processor 201, and provides, as output, a physical address Add2A. The circuit 209B receives, as input, the logical address AddL2 coming from the processor 202, and provides, as output, a physical address Add2B.

[0071] The memory circuits 206 and 207 are adapted to store the binary words Code2A and Code2B respectively at the addresses Add2A and Add2B. The memory circuits 206 and 207 are memory circuits adapted to store the same number of binary words. The memory circuit 206 receives, as input, the binary word Code2A, and the address Add2A coming from the circuit 209A. The memory circuit 207 receives, as input, the binary word Code2B, and the address Add2B coming from the circuit 209B. The memory circuits 206 and 207 are, for example, volatile memories. For example, the memory circuits 206 and 207 are of the same size.

[0072] Alternatively, part 20 could comprise more than two memory circuits identical in structure and size. In this case, circuit 205 is adapted to provide as many binary words of the same size as there are memory circuits included in part 20. In other words, circuit 205 is adapted to divide the binary word Code2 into as many binary words as there are memory circuits included in part 20. In addition, circuits 209A and 209B are adapted, in this case, to provide as many physical addresses from the logical address AddL2 as there are memory circuits included in part 20.

[0073] The comparison circuit 208 is a circuit adapted to compare the data Data2 provided by the processors 201 and 202, and the logical addresses AddL2 provided by the processors 201 and 202. If the data Data2 transmitted by the two processors 201 and 202, or the addresses AddL2 transmitted by the two processors 201 and 202, are not the same then an error is detected. The circuit 208 receives, as input, the data Data2 transmitted by the two processors 201 and 202, and the addresses AddL2 transmitted by the two processors 201 and 202, and provides, as output, an error signal ErrComp20. Any error detected by the circuit 208 is transmitted via the error signal ErrComp20.

[0074] A method for writing the data Data2 to memory using part 20 of the system 2 is as follows. When the processors 201 and 202 want to store the data Data2 in memory, they generate the logical address AddL2 at which they wish to store it. The processor 201 then provides the data Data2 and the logical address AddL2 to the circuit 203 so that the latter generates the code EDC2. In parallel, the logical address AddL2 is converted into two physical addresses Add2A and Add2B respectively by the circuits 209A and 209B. The code EDC2 is therefore representative of the data Data2 and the address AddL2 provided by the processor 201. The data Data2 and the code EDC2 are then used by the circuit 204 to provide the binary word Code2. The binary word Code2 is then divided into the two binary words Code2A and Code2B, by the circuit 205.The binary words Code2A and Code2B are stored, respectively, at the address Add2A in the memory circuit 206 and at the address Add2B in the memory circuit 207.

[0075] There figure 4 represents, schematically and in the form of blocks, another part 21 of the architecture of the embodiment of the electronic system 2, part 20 of which is described in relation to the figure 3 . Part 21 is adapted for reading data from memories of the electronic system 2. More particularly, part 21 is, in figure 4 , suitable for reading the data Data2 written in memory at the logical address AddL2 as described in relation to the figure 3 .

[0076] Part 21 includes: two processors 211 (CPU1) and 212 (CPU2); a circuit 213 (EDC CHECK) for verifying a correcting or error-detecting code; a circuit 214 (EDC REMOVAL) for recovering data; a circuit 215 (MERGE) for concatenating binary words; and the two identical memory circuits 206 (MEM1) and 207 (MEM2); the two address decoder circuits 209A (ADD DEC 1) and 209B (ADD DEC 2); and a comparator circuit 218 (COMP).

[0077] The processors 211 and 212 are processors identical to the processor 111. The processors 211 and 212 each provide, as output, the logical address AddL2 at which they wish to read a data item, and each receive in return the data item Data2. The processors 211 and 212 are, for example, the same processors as the processors 201 and 202 described in relation to the figure 3 , but, alternatively, processors 211 and 212 may be separate processors from processors 201 and 202.

[0078] The circuit 213 for verifying a correcting or error-detecting code is a circuit identical to the circuit 112 described in relation to the figure 2 . The circuit 213 receives, as input, the logical address AddL2 transmitted by the processor 211 and the binary word Code2, and provides, as output, an error signal ErrEDC2. The circuit 213 and the circuit 203, described in relation to the figure 3 , may, for example, be part of the same circuit, or may, alternatively, be two separate circuits.

[0079] The circuit 214 for recovering data is a circuit identical to the circuit 113 described in relation to the figure 2 . Circuit 214 receives, as input, the binary word Code2, and provides, as output, the data Data2.

[0080] The binary word concatenation circuit 215 is a circuit identical to the circuit 114 described in relation to the figure 2 . Circuit 215 receives, as input, the two binary words Code2A and Code2B, and provides, as output, the binary word Code2. Circuit 215 and circuit 205, described in relation to the figure 3 , may, for example, be part of the same circuit, or, alternatively, may be separate circuits.

[0081] Circuits 209A and 209B convert the logical address AddL2 into, respectively, the physical addresses Add2A and Add2B. Circuit 209A receives, as input, the logical address AddL2 from the processor 211, and provides, as output, the physical address Add2A. Circuit 209B receives, as input, the logical address AddL2 from the processor 212, and provides, as output, the physical address Add2B.

[0082] Memory circuits 206 and 207 store binary words Code2A and Code2B, respectively, at addresses Add2A and Add2B. Memory circuit 206 receives address Add2A from circuit 209A, and memory circuit 207 receives address Add2B from circuit 209B.

[0083] Alternatively, parts 20 and 21 could comprise more than two memory circuits. In this case, circuit 215 is adapted to receive, as input, as many binary words as there are memory circuits included in parts 20 and 21. In other words, circuit 215 is adapted to reform the binary word Code2 from as many binary words as there are memory circuits included in parts 20 and 21. In addition, circuits 209A and 209B are adapted to provide as many physical addresses from the logical address AddL2 as there are memory circuits present in parts 20 and 21.

[0084] The comparator circuit 218 is a circuit adapted to compare the logical addresses AddL2 transmitted by the processors 211 and 212. The comparator circuit 218 receives, as input, the address AddL2 provided by the processor 211 and the address AddL2 provided by the processor 212, and provides, as output, an error signal ErrComp21. If the logical addresses transmitted by the processors 211 and 212 are not identical then an error is detected, and is transmitted via the error signal ErrComp21. The circuit 218 and the circuit 208 described in relation to the figure 3 may, for example, be part of the same circuit, but, alternatively, circuits 208 and 218 may be separate circuits.

[0085] A method for reading the data Data2 implementing part 21 of the system 2 is as follows. The processors 211 and 212 provide the circuits 209A and 209B with the address AddL2 at which they want to read a data item, in this case the data item Data2. The circuits 209A and 209B provide the physical addresses Add2A and Add2B to the memory circuits 206 and 207. The comparison circuit 218 checks whether the processors 211 and 212 transmit the same logical address AddL2. At the address Add2A of the memory circuit 206 is stored the binary word Code2A, and at the address Add2B of the memory circuit 207 is stored the binary word Code2B. The memory circuits 206 and 207 provide the circuit 215 with the two binary words Code2A and Code2B to reform the binary word Code2. Circuit 214 is responsible for retrieving the data Data2 and transmitting it to processors 211 and 212. Circuit 213, for its part, checks whether there are any errors.

[0086] An advantage of this embodiment is that, during the reading process, the circuit 213 makes it possible to detect an addressing error of the data Data2. Indeed, the code EDC2 being representative of the data Data2 and of the logical address to which the data was written, the comparison of the code EDC2 with a code generated from the logical address AddL2 provided by the processor 211 can make it possible to detect a difference in logical addresses.

[0087] Another advantage of this embodiment is that the use of two processors 201 and 202, and 211 and 212, in parallel makes it possible to detect errors issued during the read command or the write command. These errors are detected by the circuits 208 and 218.

[0088] There figure 5 represents, schematically and in the form of blocks, a part 30 of an architecture of an embodiment of an electronic system 3. The part 30 is adapted to writing data into the memory of the electronic system 3.

[0089] Electronic system 3 is similar to electronic system 2, parts 20 and 21 of which are described in relation to the figures 3 et 4 . Elements common to systems 2 and 3 will not be described again below.

[0090] Part 30 includes the same circuits as Part 20 of System 2. Thus, Part 30 includes: two processors 201 (CPU1) and 202 (CPU2); a circuit 203 (EDC Gen) for generating a correcting or error-detecting code; a circuit 204 (EDC ADD) for forming a binary word; a circuit 205 (SPLIT) for dividing a binary word; two identical memory circuits 206 (MEM1) and 207 (MEM2); an address decoder circuit 309 (ADD DEC); and a comparison circuit 208 (COMP).

[0091] The difference between part 20 of system 2 and part 30 of system 3 is that, in part 30, the logical address AddL2 is transmitted by the processor 201 to the circuit 309 which is identical to the circuit 107 described in relation to the figure 1 . Circuit 309 outputs the two physical addresses Add2A and Add2B. The two memory circuits 206 and 207 receive, respectively, the physical addresses Add2A and Add2B from circuit 309. In part 20, each memory circuit receives the physical address Add2A or Add2B from a different decoder circuit. In this embodiment, processor 202 only provides the logical address AddL2 to comparator circuit 208.

[0092] There figure 6 represents, schematically and in the form of blocks, another part 31 of the architecture of the embodiment of the electronic system 3, part 30 of which is described in relation to the figure 5 . The electronic system 3 is a preferred embodiment. The part 31 is adapted for reading data in memories of the electronic system 3. More particularly, the part 31 is, in figure 6 , suitable for reading the data Data2 written in memory at the address AddL2 as described in relation to the figure 3 .

[0093] Electronic system 3 is similar to electronic system 2, parts 20 and 21 of which are described in relation to the figures 3 et 4 . The elements common to systems 2 and 3 will not be described again below.

[0094] Part 31 includes some of the circuits of Part 21 of System 2. Thus, Part 31 includes: two processors 211 (CPU1) and 212 (CPU2); circuit 213 (EDC CHECK) for verifying a correcting or error-detecting code; circuit 214 (EDC REMOVAL) for recovering data; circuit 215 (MERGE) for concatenating binary words; and the two identical memory circuits 206 (MEM1) and 207 (MEM2); address decoder circuit 309 (ADD DEC); and comparator circuit 218 (COMP).

[0095] The difference between part 21 of system 2 and part 31 of system 3 is that in part 31, both memory circuits 206 and 207 receive the addresses Add2A and Add2B from circuit 309. In part 20, each memory circuit receives the address Add2A, Add2B from a different address decoder circuit. In this embodiment, processor 212 only provides the logical address AddL2 to comparator circuit 218.

[0096] An advantage of this embodiment is that, during the reading process, the circuit 213 makes it possible to detect an addressing error of the data Data2. Indeed, the code EDC2 being representative of the data Data2 and of the logical address to which the data was written, the comparison of the code EDC2 with a code generated from the logical address AddL2 provided by the processor 211 makes it possible to detect a difference in logical addresses.

[0097] Another advantage of this embodiment is that the two binary words Code2A and Code2B are written to physical addresses Add2A and Add2B, coming from the same logical address AddL2, in the memory circuits 206 and 207, even if the logical addresses AddL2 transmitted by the processors 201 and 202 are different by mistake.

[0098] There figure 7 represents, schematically and in the form of blocks, a part 40 of an architecture of an embodiment of an electronic system 4. The part 40 is adapted to writing data into the memory of the electronic system 4.

[0099] Part 40 includes: two processors 401 (CPU1) and 402 (CPU2); two circuits 403 (EDC GEN 1) and 404 (EDC GEN 2) for generating a correcting or error-detecting code; two circuits 405 (EDC ADD 1) and 406 (EDC ADD 2) for forming a binary word; circuits 407 (SPLIT 1) and 408 (SPLIT 2) for dividing a binary word; two identical memory circuits 409 (MEM1) and 410 (MEM2); two address decoder circuits 412 (ADD DEC 1) and 413 (ADD DEC2); and a comparison circuit 411 (COMP).

[0100] Processors 401 and 402 are similar to processors 201 and 202 of part 20 of system 2 described in connection with the figure 3 . The processors 401 and 402 are identical in structure and are adapted to provide the same data and commands. The processors 401 and 402 are, more particularly, processors adapted to request the writing of data in the memories 409 and 410. Each processor 401, 402 provides, as output, a data item Data4 to be written to memory and a logical address AddL4. The address AddL4 is the logical address to which the data item Data4 must be written to memory. The use of the two processors 401 and 402 in parallel allows, among other things, the detection of errors by redundancy checks.

[0101] The circuits 403 and 404 for generating a correcting or error-detecting code are circuits identical to the circuits 102 described in relation to the figure 1 . The circuit 403 receives, as input, the data Data4 and the logical address AddL4 both coming from the processor 401, and provides, as output, a code EDC4. The circuit 404 receives, as input, the data Data4 and the logical address AddL4 both coming from the processor 402, and provides, as output, a correcting or error detecting code EDC4.

[0102] The circuits 405 and 406 for forming a binary word are circuits identical to the circuit 103 described in relation to the figure 1 . Circuit 405 receives, as input, the EDC4 code from circuit 403, and provides, as output, the binary word Code4. Circuit 406 receives, as input, the EDC4 code from circuit 404, and provides, as output, the binary word Code4.

[0103] The circuits 407 and 408 for dividing a binary word are circuits adapted to divide the binary word Code4 into several binary words. The circuit 407 receives, as input, the binary word Code4 coming from the circuit 405, and provides, as output, in this example, one of the parts of the binary word Code4, the binary word Code2A. The circuit 408 receives, as input, the binary word Code4 coming from the circuit 406, and provides, as output, in this example, one of the parts of the binary word Code4, the binary word Code2B.

[0104] The address decoder circuits 412 and 413 are circuits identical to the circuit 107 described in relation to the figure 1 . Circuits 412 and 413 convert the logical address AddL4 into, respectively, the physical addresses Add4A and Add4B. Circuit 412 receives, as input, the logical address AddL4 from the processor 401, and provides, as output, the physical address Add4A. Circuit 413 receives, as input, the logical address AddL4 from the processor 402, and provides, as output, the physical address Add4B.

[0105] Memory circuits 409 and 410 are memory circuits identical to memory circuits 105 and 106 described in connection with the figure 1 . The memory circuit 409 receives, as input, the binary word Code4A coming from the circuit 407, and the address Add4A coming from the circuit 412. The memory circuit 410 receives, as input, the binary word Code4B coming from the circuit 408, and the address Add4B coming from the circuit 413. For example, the memory circuits 409 and 410 are the same size.

[0106] Alternatively, part 40 could comprise more than two memory circuits. In this case, part 40 comprises as many circuits for generating a correcting or error detecting code, as many circuits for forming a binary word, and as many circuits for dividing a binary word as there are memory circuits in part 40. In addition, the binary word division circuits are adapted to divide the binary word that they receive as input into as many binary words as the number of memory circuits included in part 40. The address decoder circuits 412 and 413 are adapted to provide as many physical addresses as there are memory circuits included in part 40.

[0107] Comparison circuit 411 is a circuit identical to circuit 208 described in connection with the figure 3 . The circuit 411 receives, as input, the data Data4 transmitted by the processors 401 and 402, and the addresses AddL4 transmitted by the processors 401 and 402. The circuit 411 provides, as output, an error signal ErrComp40.

[0108] A method of writing the data Data4 into memory implementing the part 40 of the system 4 is as follows. When the processors 401 and 402 want to store the data Data4 in memory, they generate the logical address AddL4 at which they wish to store it. The processor 401, respectively 402, then provides the data Data4 and the address AddL4 to the circuit 403, respectively 404, so that it generates the code EDC4. In parallel, the processor 401, respectively 402, provides the address AddL4 to the circuit 412, respectively 413, to obtain the physical address Add4A, respectively Add4B. The EDC4 code is therefore representative of the data Data4 and the logical address AddL4 provided by the processors 401 and 402. The circuit 405 then generates the binary word Code4 from the EDC4 code provided by the circuit 403 and from the data Data4 provided by the processor 401.The circuit 406 then generates the binary word Code4 from the code EDC4 supplied by the circuit 404 and from the data Data4 supplied by the processor 402. The circuits 407 and 408 divide the binary words Code4, received respectively from the circuits 405 and 406, into the binary words Code4A and Code4B. The binary word Code4A is stored in the memory 409 at the address Add4A transmitted by the circuit 412, and the binary word Code4B is stored in the memory 410 at the address Add4B transmitted by the circuit 413.

[0109] There figure 8 represents, schematically and in the form of blocks, another part 42 of the architecture of the embodiment of the electronic system 4, of which part 40 is described in relation to the figure 7 . Part 42 is adapted for reading data from memories of the electronic system 4. More particularly, part 42 is, in figure 8 , adapted to read the data Data4 written to the logical address AddL4 in the memory circuits 409 and 410 as described in relation to the figure 7 .

[0110] Part 42 includes: two processors 421 (CPU1) and 422 (CPU2); circuits 423 (EDC CHECK 1) and 424 (EDC CHECK 2) for verifying a correcting or error-detecting code; circuits 425 (EDC REMOVAL 1) and 426 (EDC REMOVAL 2) for recovering data; circuits 427 (MERGE 1) and 428 (MERGE 2) for concatenating binary words; and the two memory circuits 409 (MEM1) and 410 (MEM2); the two address decoder circuits 412 (ADD DEC 1) and 413 (ADD DEC 2); and a comparator circuit 431 (COMP).

[0111] The two processors 421 and 422 are processors identical to the processors 211 and 212 described in relation to the figure 4 . The processors 421 and 422 each provide, as output, the logical address AddL4 at which they wish to read a data item, and each receive in return the data item Data4. The processors 421 and 422 are, for example, the same processors as the processors 401 and 402, but, alternatively, the processors 421 and 422 may be processors distinct from the processors 401 and 402.

[0112] The circuits 423 and 424 for verifying a correcting or error-detecting code are circuits identical to the circuit 112 described in relation to the figure 2 . The circuit 423 receives as input the logical address AddL4 from the processor 421 and the binary word Code4 from the circuit 427, and provides, as output, an error signal ErrEDC42. The circuit 424 receives as input the address AddL4 from the processor 422 and the binary word Code4 from the circuit 428, and provides, as output, an error signal ErrEDC42. The circuits 403 and 423 may, for example, be part of the same circuit, but may, alternatively, be separate circuits. The circuits 404 and 424 may, for example, be part of the same circuit, but may, alternatively, be separate circuits.

[0113] The circuits 425 and 426 for recovering data are circuits identical to the circuit 113 described in relation to the figure 2 . Circuit 425 receives, as input, the binary word Code4 from circuit 427, and provides, as output, the data Data4. Circuit 426 receives, as input, the binary word Code4 from circuit 428, and provides, as output, the data Data4. Circuits 405 and 425 may, for example, be part of the same circuit, but may, alternatively, be separate circuits. Circuits 406 and 426 may, for example, be part of the same circuit, but may, alternatively, be separate circuits.

[0114] Binary word concatenation circuits 427 and 428 are circuits identical to circuit 114 described in connection with the figure 2 . Circuit 427 receives, as input, the binary words Code4A and Code4B, and provides, as output, the binary word Code4. Circuit 428 receives, as input, the binary words Code4A and Code4B, and provides, as output, the binary word Code4. Circuits 407 and 427 may, for example, be part of the same circuit, but may, alternatively, be separate circuits. Circuits 408 and 428 may, for example, be part of the same circuit, but may, alternatively, be separate circuits.

[0115] Circuits 412 and 413 convert the address AddL4 into, respectively, the physical addresses Add4A and Add4B. Circuit 412 receives, as input, the logical address AddL4, and provides, as output, the physical address Add4A. Circuit 413 receives, as input, the logical address AddL4, and provides, as output, the physical address Add4B.

[0116] Memory circuits 409 and 410 store binary words Code4A and Code4B, respectively, at addresses Add4A and Add4B. Memory circuit 409 receives address Add4A from circuit 412, and memory circuit 410 receives address Add4B from circuit 413.

[0117] Alternatively, parts 40 and 42 could comprise more than two memory circuits. In this case, part 42 comprises as many error-correcting code verification or detection circuits, as many data recovery circuits, and as many binary word concatenation circuits as there are memory circuits in part 41. In addition, the binary word division circuits are, in this case, adapted to divide the binary word they receive into as many binary words as the number of memory circuits included in part 41. In addition, circuits 412 and 413 are adapted to provide as many physical addresses from the logical address AddL4 as there are memory circuits included in part 42.

[0118] The comparator circuit 431 is a circuit adapted to compare, with each other, the addresses AddL4 transmitted by the processors 421 and 422, and the data Data4 transmitted by the circuits 425 and 426. The comparator circuit 431 receives, as input, the address AddL4 provided by the processor 421 and the address AddL4 provided by the processor 422, and the data Data4 transmitted by the circuit 425, and the data Data4 transmitted by the circuit 426. The comparator circuit 431 provides, as output, an error signal Errcomp42. If the addresses transmitted by the processors 421 and 422 are not identical then an error is detected, and is transmitted via the error signal ErrComp42. The circuit 431 and the circuit 411 described in relation to the figure 7 may, for example, be part of the same circuit, but, alternatively, circuits 411 and 431 may be separate circuits.

[0119] A method for reading the data Data4 implementing the part 42 of the system 4 is as follows. The processors 421 and 422 provide the circuits 412 and 413 with the address AddL4 at which they want to read a data item, in this case the data item Data4. The circuits 412 and 413 provide the physical addresses Add4A and Add4B to the memory circuits 409 and 410. The comparison circuit 431 checks whether the processors 421 and 422 transmit the same address AddL4. At the address Add4A of the memory circuit 409 is stored the binary word Code4A, and at the address Add4B of the memory circuit 410 is stored the binary word Code4B. The memory circuits 409 and 410 provide the circuits 427 and 428 with the two binary words Code4A and Code4B to reform the binary word Code4. Circuit 425 is responsible for retrieving the data Data4 from the binary word Code4 transmitted by circuit 427, circuit 426 is responsible for retrieving the data Data4 from the binary word Code4 transmitted by circuit 428.The processor 421 then receives the data Data4 from the circuit 425, and the processor 422 receives the data Data4 from the circuit 426. The comparator circuit 431 verifies the correspondence between the data Data4 supplied to the processors 421 and 422. The circuits 423 and 424 each verify the code EDC4.

[0120] An advantage of this embodiment is that, during the reading process, the circuits 423 and 424 make it possible to detect an addressing error of the data Data4. Indeed, the EDC4 code being representative of the data Data4 and of the logical address to which the data was written, the comparison of the EDC4 code with a code generated from the logical address AddL4 supplied by the processors 421 and 422 makes it possible to detect a difference in addresses.

[0121] Another advantage of this embodiment is that the use of two processors 401 and 402, and 421 and 422, in parallel makes it possible to detect errors issued during the read command or the write command. These errors are detected by the circuits 411 and 431.

[0122] There figure 9 represents, schematically and in block form, a part of a MEM memory circuit. The MEM memory circuit is, for example, the type of memory circuit used by systems 1 to 4 described in relation to the figures 1 à 8 .

[0123] The MEM memory circuit part includes a LOGIC control circuit and a WL line control circuit.

[0124] The LOGIC control circuit is a circuit adapted to process the various commands received from the system of which the MEM memory circuit is a part. The LOGIC circuit receives, as input, an Add address and a Data data to be written. The LOGIC circuit provides, as output, the following signals: a CS signal for selecting the memory circuit MEM; a WEN signal for enabling writing; a COL signal for selecting / numbering columns; and a LIN signal for selecting / numbering rows.

[0125] The Add address is preferably a physical address, i.e. directly interpretable in row and column coordinates in the memory circuit. Alternatively, this address is a logical address provided by the processor and translated by an address decoder circuit associated with the memory circuit, i.e. forming part of the memory circuit.

[0126] The CS signal is used to select the MEM memory circuit during a read or write operation.

[0127] The WEN signal is used to indicate to the MEM memory circuit the nature of the command received, and more specifically, whether a write operation is requested.

[0128] The COL and LIN signals are the signals generated from the Add address received by the LOGIC circuit, and are the signals used to select the memory points (not shown in figure 9 ) of the memory circuit in which we wish to write the data Data.

[0129] The WL line control circuit is a circuit adapted to select the word line corresponding to the Add address received by the memory circuit. The WL circuit receives, as input, the LIN line selection / number signal, and provides, as output, WLN words. In figure 9 , only one WLN word is represented.

[0130] There figure 10 represents, schematically and in the form of blocks, a part 50 of an architecture of an electronic system 5. The part 50 is adapted to the detection of errors when writing data in memories.

[0131] Part 50 of System 5 includes: two memory circuits 51 (MEM3) and 52 (MEM4); and a comparison circuit 53 (COMP).

[0132] The memory circuits 51 and 52 are memory circuits identical in structure and size to the type of memory MEM described in relation to the figure 9 . Thus, the memory circuits 51 and 52 each receive, as input, a physical address Add5. The memory circuit 51 further receives, as input, a binary word Code5A to be stored at the address Add5. The memory circuit 52 further receives, as input, a binary word Code5B to be stored at the address Add5. As described in relation to the figure 9 , each memory circuit 51, respectively 52, provides, at output, the following output signals: a word WLN51, respectively WLN52; a signal CS51, respectively CS52, for selecting the memory circuit 51, respectively the memory circuit 52; a signal WEN51, respectively WEN52, for activating writing; a signal COL51, respectively COL52, for selecting / numbering a column; and a signal LIN51, respectively LIN52, for selecting / numbering a row.

[0133] The binary words Code5A and Code5B are binary words of the same size, both representing data to be written to memory. As an example, the binary words Code5A and Code5B are obtained by dividing the data to be written to memory in two. According to another example, the binary words Code5A and Code5B are obtained in the same way as the binary words Code1A and Code1B described in relation to the figure 1 .

[0134] The comparison circuit 53 is a circuit for comparing the output signals of the two memory circuits 51 and 52 to detect an error during a write operation. The comparison circuit 53 receives, as input, the following signals: the words WLN51 and WLN52; the signals CS51 and CS52; the signals WEN51 and WEN52; the signals COL51 and COL52; and the signals LIN51 and LIN52.

[0135] The comparison circuit 53 provides, at output, a comparison signal CompErr5. The comparison circuit 53 compares, more particularly, each output signal of the memory circuit 51 with the homologous output signal of the memory circuit 52. In other words, the comparison circuit 53 is adapted to: compare the words WLN51 and WLN52; compare the signals CS51 and CS52; compare the signals WEN51 and WEN52; compare the signals COL51 and COL52; and compare the signals LIN51 and LIN52.

[0136] The comparison circuit 53 may be an assembly of EXCLUSIVE OR type logic gates.

[0137] Alternatively, the part 50 could comprise more than two memory circuits. In this case, the comparison circuit 53 is adapted to receive, as input, all the output signals of the memory circuits of the part 50. In addition, each of these memory circuits is adapted to store a binary word representative of the data to be written in memory different from the binary words stored in the other memory circuits.

[0138] A method for detecting read errors implementing part 50 of system 5 is as follows. While writing the binary words Code5A and Code5B in the memory circuits 51 and 52 at the address Add5, the memory circuits 51 and 52 transmit their output signals to the comparison circuit 53. The binary words Code5A and Code5B being binary words, of the same size, stored at an identical address in identical memory circuits, thus, the output signals of the memory circuits 51 and 52 should therefore be identical. The comparison circuit 53 then compares the output signals of the memory circuits 51 and 52, each difference between two signals can mean an error. A possible error is transmitted via the signal CompErr5.

[0139] An advantage of this embodiment is that it allows address errors to be detected during a write operation of data in memory without requiring a read operation of said data.

[0140] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0141] In particular, the embodiments described in connection with the figures 1 et 2 , 3 And 4 , 5 And 6 , And 7 et 8 are all compatible with the embodiment described in relation to the figures 9 et 10 .

[0142] Additionally, the embodiments described in connection with the figures 3 et 4 , 5 And 6 , And 7 et 8include two identical processors, but alternatively, these embodiments could include more than two processors.

[0143] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

1. A method for writing a datum (Data1; Data2; Data4) in memory, in which: - a binary word (Code1; Code2; Code4), representative of said datum (Data1; Data2; Data4) and an error correcting or detecting code (EDC1; EDC2; EDC4), is formed then split into at least a first part and a second part (Code1A, Code1B; Code2A, Code2B; Code4A, Code4B); and - said first part (Code1A; Code2A; Code4A) is written at a logical address (AddL1; AddL2; AddL4) in a first memory circuit (105; 206; 409); and - said second part (Code1B; Code2B; Code4B) is written at said logical address in a second memory circuit (106; 207; 410) configured to store as many binary words as said first memory circuit (105; 206; 409), said error correcting or detecting code (EDC1; EDC2; EDC4) being dependent on said datum (Data1; Data2; Data4) and said address (AddL1; AddL2; AddL4).

2. The method according to claim 1, wherein said first and second parts (Code1A, Code1B; Code2A, Code 2B; Code4A, Code4B) are the same size.

3. The method according to claim 1 or 2, wherein the binary word (Code1; Code2; Code4) is a concatenation of said datum (Data1; Data2; Data4) and said correcting or error detecting code (EDC1; EDC2; EDC4).

4. The method according to any one of claims 1 to 3, wherein said datum (Data1) and said address (AddL1) are supplied by a single first processor (101).

5. The method according to any one of claims 1 to 4, wherein said datum (Data2; Data4) and said address (AddL2; AddL4) are supplied by at least one second processor (201; 401) and a third processor (202; 402).

6. The method according to claim 5, wherein said datum (Data2; Data4) supplied by the second processor (201; 401) is compared to said datum (Data2; Data4) supplied by the third processor (202; 402), and said address (AddL2; Addl4) supplied by the second processor (201; 401) is compared to said address (AddL2; AddL4) supplied by the third processor (202; 402).

7. The method according to claim 5 or 6, wherein the second processor (201; 401) supplies said address (AddL2, Addl4) to one of said at least two memory circuits (206; 409), and the third processor (202; 402) supplies said address (AddL2; AddL4) to another of said at least two memory circuits (207; 410).

8. The method according to claim 5 or 6, wherein the second processor (201) supplies said address (AddL2) to said at least two memory circuits (206, 207).

9. The method according to any one of claims 1 to 8, wherein said first and second memory circuits (105, 106; 206, 207; 409, 410) are the same size.

10. The method according to any one of claims 1 to 9, wherein internal control signals (WL51, CS51, WEN51, COL51, LIN51; WL52, CS52, WEN52, COL52, LIN52) of said at least two memory circuits (51, 52) are compared.

11. A method for reading a datum (Data1; Data2; Data4) written according to the method of claims 1 to 10.

12. The method according to claim 11, wherein said binary word (Code1; Code2; Code4) is formed by concatenating said first and second parts (Code1A, Code1B; Code2A, Code2B; Code4A, Code4B) read in said first and second memory circuits (105, 106; 206, 207; 409, 410).

13. The method according to claim 11 or 12, wherein the datum (Data1; Data2; Data4) is obtained by removing the error correcting or detecting code (EDC1, EDC2, EDC4) from the binary word (Code1; Code2; Code4).

14. A method for detecting an error in a datum written by the method according to any one of claims 1 to 10, wherein the error correcting or detecting code is computed again from the datum read by the method according to any one of claims 11 to 13.

15. The method according to claim 4, wherein the error correcting or detecting code (EDC1; EDC2; EDC4) is verified.