METHOD FOR FABRICING AN ELECTRONIC ASSEMBLY ON THE FRONT SIDE OF A SEMICONDUCTOR WAFER

Description

DOMAINE DE L'INVENTION

[0001] The present invention relates to the field of semiconductors. More specifically, the present invention relates to a method for manufacturing a set of electronic components on a semiconductor wafer allowing the location of all or part of these components on the wafer. ARRIERE PLAN TECHNOLOGIQUE DE L'INVENTION

[0002] In the semiconductor industry, a common method for manufacturing electronic components in large quantities is to produce a set of identical electronic components on a semiconductor wafer. In order to form a stack of layers on the wafer forming the electronic components, photolithography techniques are generally used. The principle of these techniques is well known: a layer of material is deposited over the entire wafer, then a photoresist is deposited on the layer. A photolithographic mask is then applied above the photoresist, in a first field called the exposure field and representing a fraction of the surface of the semiconductor wafer. In the first exposure field, the part not covered by the mask is then exposed to light, locally transforming the photoresist.The sequence of applying the photolithographic mask and exposing it to light is repeated successively on each of the other exposure fields. The transformed resist is then removed, and the layer is locally etched according to the mask pattern, over the entire surface of the semiconductor wafer, before the remaining photoresist is in turn removed. The process is thus repeated for each layer of the stack, using a different photolithographic mask each time.

[0003] Once all the electronic components are formed on the wafer, the wafer is cut around each component to form a chip, which is then individually encapsulated in a package. Typically, chip pick-and-place equipment (also known as pick-and-place) ensures that each chip (component) is matched to the semiconductor wafer from which it originates.

[0004] But in the event of a component failure, it may be desirable to trace the precise location of the electronic component on the board, so as to check the physical parameters of the layers during manufacturing in the corresponding area of ​​the board and to facilitate failure analysis.

[0005] Electronic component traceability can be achieved at the time of assembly, i.e. when the component is encapsulated, with specific marking on the housing. However, this operation, often carried out by a manual operator, results in significant costs and production time. In addition, it is not suitable if the component is not encapsulated in a housing, and is not very suitable for mass production.

[0006] Some assembly lines offer a semi-manual solution, with picking, creation of a correspondence file between the position of the component on the board and the package number, as well as serialization of the package, monitored by the operator. However, all these operations require the intervention of human operators, which can be a source of error.

[0007] Document US8187897 presents a method for manufacturing a set of electronic components on a semiconductor wafer. An individual pattern is affixed to one of the layers of the electronic component, which constitutes a unique identifier of the component making it possible to trace the wafer from which it originates as well as its position on the wafer.

[0008] However, this approach has the disadvantage of a certain complexity of implementation, in particular in that it requires the application of additional photolithographic masks, compared to a conventional process for manufacturing a set of components, to generate a specific pattern for each component. Such an application results in additional cost and production time.

[0009] Document WO2008 / 069212 describes a semiconductor wafer and a method of manufacturing semiconductor devices from this wafer. OBJET DE L'INVENTION

[0010] The present invention relates to an alternative solution to those of the state of the art, and aims to remedy all or part of the aforementioned drawbacks. It relates in particular to a method for manufacturing a set of electronic components on a semiconductor wafer allowing the location of each electronic component on the wafer after its cutting, without requiring an additional photolithographic step during the production of the set of electronic components. BREVE DESCRIPTION DE L'INVENTION

[0011] In order to achieve this aim, the subject of the invention proposes a method for manufacturing a set of electronic components on the front face of a semiconductor wafer having a plurality of field zones, each zone comprising at least one field and each field comprising at least one electronic component, the method comprising a plurality of photolithography steps to form a stack of layers constituting each electronic component, each photolithography step comprising the application of a mask successively on each field in photolithography equipment.

[0012] The manufacturing method according to the invention is remarkable in that one of the masks further comprises an identification pattern, said mask being designated an identification mask, and in that, in the photolithography step associated with the identification mask, at least one photolithographic parameter of the photolithography equipment is different for each field zone, so as to expose the identification pattern differently in each field zone.

[0013] Thus, at the end of the photolithography step associated with the identification mask, an identification mark specific to each field zone is formed because the spatial resolution of the identification pattern from which said mark originates differs between each field zone.

[0014] According to other advantageous and non-limiting characteristics of the invention, taken alone or in any technically feasible combination: the plurality of photolithography steps comprises a step of opening contacts of the electronic components, the identification mask being the mask applied to said step of opening contacts; the photolithographic parameter is chosen from the exposure dose and the focusing; the exposure dose varies between 5 mJ / cm 2< and 1000 mJ / cm 2<; the focusing varies by + / -10 µm; the identification pattern has at least one dimension of the order of a few µm, typically between 1 micron and 20 microns; the electronic components comprise high electron mobility transistors based on III-N materials; at least one field zone comprises a plurality of fields; each field zone comprises a plurality of fields. BREVE DESCRIPTION DES FIGURES

[0015] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which: [ Fig. 1 ] There figure 1 represents a semiconductor plate having a set of electronic components obtained by a manufacturing method according to the invention; [ Fig. 2 ] There figure 2 represents different examples of identification patterns according to the invention; [ Fig. 3 ] There figure 3 represents different identification marks according to the invention obtained from different identification patterns and for different photolithographic parameters.

[0016] The figures are schematic representations which, for the sake of readability, are not necessarily to scale. The same references in the figures may be used for elements of the same nature. The different possibilities (variants and embodiments illustrated and / or detailed in the description to follow) must be understood as not being mutually exclusive and may be combined with each other. DESCRIPTION DETAILLEE DE L'INVENTION

[0017] The invention relates to a method for manufacturing a set of electronic components. An electronic component is understood to mean any component of micrometric to millimetric size, consisting of a stack of layers, capable of using electric currents to transmit, process or store information. Each electronic component may thus consist of or comprise, for example, a resistor, a capacitor, a coil, a transistor, an integrated circuit, any combination or assembly of these elements, or even other elements or assemblies of elements well known to those skilled in the art.

[0018] Preferably, but without this being limiting of the invention, the electronic components may in particular comprise high electron mobility transistors produced on a substrate based on III-N materials.

[0019] More generally, the electronic components 3 are formed on a front face of a semiconductor plate 1 ( figure 1 ). The semiconductor plate 1 is preferably in the form of a circular substrate, with a diameter of between 100 mm and 450 mm, and a thickness of between 100 and 1500 microns. The semiconductor plate 1 may be made of any semiconductor material, for example silicon and more specifically, as stated previously, a superposition of III-N materials.

[0020] Of course, the invention is in no way limited to such shapes, dimensions or composition of the semiconductor plate 1.

[0021] The front face of the semiconductor wafer 1 defines a plane (x,y), the stack of layers forming the electronic components being produced along an axis z normal to this plane (x,y). The production of this stack requires a succession of so-called production steps, namely steps of layer deposition, lithography to define the structuring of said layer, etching to structure the layer, surface treatments, etc.

[0022] As recalled in the introductory part of the present application, during a production lithography or photolithography step, the application of a photolithographic mask and the exposure to light are carried out at the level of a field 2 (also called exposure field 2). A field 2 may comprise a single electronic component or a plurality of electronic components 3, typically between two and several hundred. For the sake of simplification on the figure 1 , 3-components were only represented on four 2-fields, in this case nine 3-components per 2-field.

[0023] As can be seen on the figure 1 , the front face of the semiconductor plate 1 has a plurality of field zones 4 (the example of the figure 1 schematically represents five field zones 41, 42, 43, 44, 45). Each zone 4 comprises at least one field 2, preferably a plurality of fields 2. The number and distribution of the fields in each zone 4 may be identical for all the zones 4, or different from one zone to another. As will be described later, the invention provides the possibility of grouping several fields 2 into field zones 4, so that the fields 2 of the same zone 4 have similar characteristics, while the fields 2 of different zones 4 have different recognizable characteristics.

[0024] Thus, on the schematic example of the figure 1 , the first zone 41 comprises a single field 2, positioned in the center of the semiconductor plate 1. The second zone 42 comprises eight fields 2, the third zone 43 comprises sixteen fields 2, the fourth zone 44 comprises twenty-four fields 2, and the fifth zone 45 comprises twenty fields 2. For the sake of simplification, the components 3 per field 2 have been represented only on two fields of the second zone 42 and on one field of the third 43 and fourth 44 zones.

[0025] The shape and size of the zones 4 can be freely chosen. Preferably, when the semiconductor plate 1 is a circular substrate, the zones 4 can be chosen so as to be concentric, as in the example of the figure 1 . Alternatively, the zones 4 may represent a portion of the semiconductor wafer 1, for example half or a quarter of the wafer. The zones 4 may also be slices of the semiconductor wafer 1 along one or other of the x and y axes, without the invention being in any way limited to such distributions of zones.

[0026] Returning to the manufacturing method according to the invention, such a method comprises a plurality of production photolithography steps to form a stack of layers constituting each electronic component 3. These photolithography steps are interspersed with other well-known steps allowing the formation of the stack, such as heat treatment, deposition, etching, cleaning, doping or polishing steps. The different steps for forming a stack constituting an electronic component are entirely conventional and known to those skilled in the art and will only be briefly mentioned.

[0027] The heat treatment steps are thus carried out in furnaces, typically at temperatures between 400 and 1200°C, in order to produce the silicon oxide or nitride layers, or to carry out a rearrangement of the crystal lattices. The deposition steps can be carried out by various known physical or chemical techniques, such as vapor deposition, sputtering, or epitaxy for example, depending on the type of layers desired and the compatibility, particularly in terms of stack temperature. The deposited layers can be of various types: semi-conductor, insulating or conductive.

[0028] During each photolithography step, the semiconductor wafer 1 is arranged in photolithography equipment (not shown). After a photoresist layer has been deposited, generally over the entire surface of the wafer 1, each photolithography step comprises applying a mask successively to each field 2. When applied to a field 2, the latter is exposed to a low-wavelength light source, generally ultraviolet or X-ray, in order to project the image of the mask into the photoresist layer, forming a structure in the photoresist layer.

[0029] The etching steps can be carried out by means of wet etching or dry etching, in order to reproduce the structure of the photoresist layer in the layer of material located below. The structure can consist for example of an arrangement of interdigitated fingers to form the gate, source and drain electrodes of a transistor, or of an array of openings to form electrically conductive interconnection vias, or of a plurality of contact pads to connect each component 3. In all cases, the structure is here functional, that is to say that its shape and its arrangement are defined to make the electronic component 3 functional.

[0030] Generally speaking, when the electronic component 3 comprises a transistor, the stack obtained comprises an active semiconductor layer, on which a plurality of interconnection layers are superimposed, and finally an upper passivation layer.

[0031] Once all the electronic components 3 have been formed on the plate 1, the latter is cut around each component 3, forming a chip which is then individually encapsulated in a package.

[0032] In the manufacturing method according to the invention, one of the masks used during one of the production photolithography steps comprises, in addition to the so-called functional pattern(s) used to form the functional structures of the stack, an identification pattern. Because it carries this additional pattern, said mask is referred to as an “identification mask” in the present description.

[0033] According to the invention, in the photolithography step associated with the identification mask, at least one photolithographic parameter of the photolithography equipment is different for each field zone 4, so as to expose the identification pattern differently in each field zone 4. To put it another way, in the photolithography step associated with the mask having the identification pattern, this identification mask is applied above each field 2, successively; and when the mask leaves one field zone 4 to enter another, at least one photolithographic parameter of the photolithography equipment is modified. Of course, the variation of the photolithographic parameter is controlled and its value associated with the zone 4 in question.

[0034] In this way, the shape of the identification pattern on the photoresist, and of the identification mark then formed in the layer below, is different from one zone 4 to another. Thus, after cutting an electronic component 3, it is possible to recognize the zone 4 of the wafer 1 from which the component 3 in question originates by analyzing the shape of the identification mark, which is associated with the lithographic parameter that made it possible to form it and therefore with the zone 4 of the semiconductor wafer 1 from which it originates. The manufacturing method according to the invention therefore makes it possible, without carrying out an additional photolithography step (i.e. by carrying out only the production photolithography steps), and in particular without an additional mask to be applied, to identify the location of components 3 by zone 4 of the semiconductor wafer 1, by the simple controlled variation of a photolithographic parameter from one zone 4 to another.

[0035] So, in the example shown in the figure 1 , the components 3 of the two fields of the second zone 42 will have an identical identification mark, but different from the components of the fields of the third zone 43 and the fourth zone 44, themselves different from each other.

[0036] Although the shape and dimensions of the identification pattern can be freely chosen, it is necessary to be able to identify and characterize, for each zone 4, the deformation of the identification mark as a function of the photolithographic parameter.

[0037] Examples of identification patterns are shown on the figure 2 . Thus, the identification pattern can be a rectilinear opening of a given thickness drawn on the mask ( figure 2(a) ), two bars of given thickness and spacing ( figure 2(b) ), a plurality of discs of decreasing diameter aligned in one direction and spaced a fixed or variable distance apart ( figure 2(c) ), a plurality of spacer bars increasing in one direction ( figure 2(d) ). But the invention is obviously not limited to such examples of patterns.

[0038] The characteristics (above-mentioned dimensions and shapes of the patterns) of the identification patterns depend on the type of resin used in the photolithography step associated with the identification mask. To be sensitive to changes in lithographic parameters, the identification patterns advantageously have dimensions of the order of the thickness of the resin.

[0039] The photolithographic parameter that varies from one area to another is a parameter that modifies the exposure of the identification pattern from one area to another. It can notably be chosen from the exposure dose or the focus. The exposure dose corresponds to the light energy received by the resin and the focus corresponds to a sharpness adjustment (focus). Of course, several parameters can vary, simultaneously or alternately, and other parameters modifying the exposure can be considered. In all cases, the value of this (these) parameter(s) will be associated with each area 4 of the semiconductor wafer 1.

[0040] When the photolithographic parameter that varies is the exposure dose, this can typically vary between 5 mJ / cm2 and 1000 mJ / cm2.

[0041] When the photolithographic parameter that varies is the focus, this can typically vary by + / - 10 µm.

[0042] These dose and focus variation ranges are wide enough to consider significant field-to-field variations.

[0043] It follows that the spatial resolution of the identification pattern, from which the identification mark is derived, for the components of each field area will be specific and will differ from one field area to another.

[0044] Examples of identification marks, formed from the identification patterns shown on the figure 2 , are represented on the figure 3 for the three zones 42, 43, 44 (respectively designated by points ii, iii and iv). The photolithographic parameter which varied from one zone to another is here the exposure dose, which decreased from the second 42 to the third zone 43, then from the third 43 to the fourth zone 44.

[0045] Thus, if we start from the reason for identifying the figure 2(a) , we see that the rectilinear opening, perfectly reproduced when the exposure dose is maximum ( figure 3(a)ii ), is not fully reproduced when the exposure dose is intermediate ( figure 3(a)iii ) and is no longer reproduced at all when the exposure dose is minimal ( figure 3(a)iv ).

[0046] The maximum exposure dose may correspond to a nominal value of the exposure dose, this value being reduced for the other zones compared to the nominal value. Of course, this situation is not limiting of the invention, and it is possible for the nominal exposure dose to correspond to the intermediate value, the exposure dose varying above or below this value depending on the zones, or to the minimum value, the exposure dose increasing for the other zones compared to the nominal value.

[0047] According to another example, if we start from the identification pattern of the figure 2(b) , we see that the two bars, perfectly reproduced when the exposure dose is maximum ( figure 3(b)ii ), overlap while allowing two distinct forms to be distinguished when the exposure dose is intermediate ( figure 3(b)iii ), and form only one bar when the exposure dose is minimal ( figure 3(b)iv ).

[0048] Similarly, if we start from the reason for identifying the figure 2(c) , we see that the plurality of discs is perfectly defined, each disc being perfectly distinct, when the exposure dose is maximum ( figure 3(c)ii ), that the different forms partially overlap when the exposure dose is intermediate ( figure 3(c)iii ), and that the discs with the smallest diameters are no longer reproduced when the exposure dose is minimal ( figure 3(c)iv ).

[0049] According to yet another example, if we start from the identification pattern of the figure 2(d), we see that the plurality of bars is perfectly reproduced when the exposure dose is maximum (figure 2(d)ii). When the exposure dose is intermediate, the three bars with the smallest spacing overlap (figure 2(d)iii). Finally, when the exposure dose is minimum, the four bars with the smallest spacing overlap.

[0050] It is thus possible, by recognizing the shape of the identification mark of each of the components, to associate this shape with a given exposure dose, and more generally with a given photolithographic parameter, and therefore to associate this shape with the field zone 4 of the plate 1 from which the component 3 comes.

[0051] Of course, the dimension of the identification pattern must be sufficiently small and the identification pattern must be sufficiently far from the functional patterns of the identification mask so that the identification mark formed by the identification pattern does not affect the integrity of the functional structures of the layer in question and of the lower or upper layers.

[0052] Typically, while the surface dimensions of the functional structures of the active layer of a component in the plane formed by the front face of the semiconductor wafer 1 are of the order of 10 nm 2< to 10 5< µm 2< , or the dimensions of the contacts of the components on the surface of the upper passivation layer are typically of the order of 10 6< µm 2< , the dimensions of the identification pattern may be of the order of 20 µm 2< . The distance on the identification mask between a structural pattern and the identification pattern may typically be chosen to be greater than 1 µm.

[0053] For example, we can mention a contact opening of the order of 500 µm to 2000 µm and identification marks of the order of 5 to 10 µm, resulting from an identification pattern present on the contact opening mask.

[0054] Thus, in order not to affect the most complex and functional layers of the stack, it is preferable that the identification mask is a mask applied to form a layer distant from the active layer. In addition, it is preferable that the layer chosen to receive the identification pattern is detectable on the electronic component after its manufacture. Consequently, the photolithographic step corresponding to the opening of the electrical contacts of the electronic components, generally carried out on the upper passivation layer, is particularly suitable for the implementation of the identification mask. The identification mark is then placed on the upper passivation layer, which has the advantage of being visible during a visual inspection. An observation under an optical microscope of the bare component will then make it possible to identify the original location of the latter on the plate.Of course, other optical methods than simple observation under an optical microscope can be used to analyze identification marks, such as optical analysis using pattern recognition software, for example.

[0055] A manufacturing method according to the invention therefore makes it possible to obtain a semiconductor wafer on the front face of which is arranged a set of electronic components arranged. The semiconductor wafer has a plurality of field zones, each electronic component occupying a field of the front face of the wafer, each zone comprising at least one field, each electronic component consisting of a stack of layers. Each of the components comprises an identification mark derived from an identification pattern. The spatial resolution and therefore the shape of these identification marks differs between each field zone. Thus, this identification mark is different for each zone 4, in order to make it possible, once the cutting of the electronic structure around each electronic component 3 has been carried out, to be able to identify the zone 4 of the wafer 1 from which the electronic component 3 originates.

[0056] Of course, the invention is not limited to the embodiments described and variant embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

1. Method of manufacturing an assembly of electronic components (3) on the front surface of a semiconductor wafer (1) comprising a plurality of field areas (4), each area (4) comprising at least one field (2) and each field (2) comprising at least one electronic component (3), the method comprising a plurality of photolithography steps to form a stack of layers forming each electronic component (3), each photolithography step comprising the application of a mask successively on each field (2) in photolithography equipment, one of the masks comprises an identification pattern, said mask being called identification mask; the manufacturing method being characterized in that, at the photolithography step associated with the identification mask, as least one photolithographic parameter of the photolithography equipment is different for each field area (4), to expose the identification pattern differently in each field area (4).

2. Manufacturing method according to the foregoing claim, wherein the plurality of photolithography steps comprises a step of openings of contacts of the electronic components (3), the identification mask being the mask applied at said contact opening step.

3. Manufacturing method according to one of the foregoing claims, wherein the photolithographic parameter is selected from among the exposure dose and the focusing.

4. Manufacturing method according to the foregoing claim, wherein the exposure dose varies between 5 mJ / cm2 and 1,000 mJ / cm2.

5. Manufacturing method according to one of the two foregoing claims, wherein the focusing varies by + / -10 µm.

6. Manufacturing method according to one of the foregoing claims, wherein the identification pattern has at least one dimension in the order of a few µm, typically in the range from 1 micrometer to 20 micrometers.

7. Manufacturing method according to one of the foregoing claims, wherein the electronic components (3) comprise high electron mobility transistors based on III-N materials.

8. Manufacturing method according to one of the foregoing claims, wherein each field area (4) comprises a plurality of fields (2).