Semiconductor component and method for manufacturing such a semiconductor component

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device according to the preamble of claim 1 and a method of manufacturing such semiconductor device according to claim 3.BACKGROUND OF THE DISCLOSURE

[0002] A package where heat occurs at both sides of the device are known. Such packages are, for example, embedded packages, SRD dual cool packages, source down packages or inverted packages. Those packages are either difficult to manufacture or are not transferring heat efficiently to both sides of the package.

[0003] Accordingly, it is a goal of the present disclosure to provide an improved thermal performance of a semiconductor device. Furthermore the present disclosure will provide a cost effective alternative to using ceramic substrates and bare die. Also power density will improve due to PCB temperature reduction which will allow to place components closer. Relevant prior art in relation to the disclosure are: US 2012 / 061816A1, which discloses a semiconductor package and method of fabricating the same, wherein the package includes an interconnection substrate, a semiconductor chip mounted on the interconnection substrate, a lateral wire bonded on the interconnection substrate and configured to enclose a side surface of the semiconductor chip, as well as a metal layer disposed on the semiconductor chip and electrically connected to the lateral wire.

[0004] US 2004 / 012099A1, which discloses a semiconductor device with a substrate on which a wiring pattern is formed, a semiconductor die mounted on the substrate, a sealed part sealing the semiconductor die on the substrate, and a heat sink for the semiconductor die supported above the substrate by the sealed part, with the heat sink being in electrical contact with the grounding line of semiconductor die.

[0005] JP 2016-103616A, which discloses a packaged board with a plurality of electronic elements mounted thereon disposed in an upper mold, and a tabular member with a conductor with which a protruding conductive member is formed is disposed on an inner bottom face of a cavity of a lower mold, wherein an upper part of the conductive member is exposed from a liquid-state resin that is injected into the cavity.SUMMARY OF THE DISCLOSURE

[0006] According to a first example of the disclosure, a semiconductor device is disclosed in accordance with the characterizing features of claim 1. It consists of a package with a first surface side and a second surface side opposite to the first surface side. The package comprises at least one semiconductor structure and a group of terminals, wherein the group of terminals is connected to the at least one semiconductor structure and mounted and exposed on the first surface side of the package. The package further comprises at least one heat slug mounted and exposed on the second surface side of the package, and at least one feedthrough wire in the package such that the feedthrough wire electrically connects with the at least one heat slug.

[0007] Preferably the semiconductor structure is a transistor.

[0008] The semiconductor structure is a cascode, wherein the cascode comprises a high-electron-mobility transistor and a metal-oxide semiconductor field-effect transistor, wherein a source terminal of the high-electron-mobility transistor is electrically connected to a drain terminal of the metal-oxide semiconductor field-effect transistor, and where a gate terminal of the high-electron-mobility transistor is electrically connected to a source terminal of the metal-oxide semiconductor field-effect transistor.

[0009] The semiconductor structures form a half bridge.

[0010] According to the characterizing part of claim 1, a first terminal is connected to the drain terminal of the high-electron-mobility transistor of a first cascode, a second terminal is electrically connected to the gate terminal of the metal-oxide semiconductor field-effect transistor of the first cascode, a third terminal is electrically connected to the source terminal of the metal-oxide semiconductor field-effect transistor and the gate terminal of the high-electron-mobility transistor of the first cascode and the drain terminal of the high-electron-mobility transistor of a second cascode, a fourth terminal is electrically connected to the gate terminal of the metal-oxide semiconductor field-effect transistor of the second cascode and the fifth terminal is electrically connected to the source terminal of the metal-oxide semiconductor field-effect transistor and the gate terminal of the high-electron-mobility transistor of the second cascode, wherein the third terminal is electrically connected with a first heat slug and the fifth terminal is electrically connected to a second heat slug.

[0011] According to a second example of the disclosure a method of manufacturing the semiconductor device according to the disclosure is proposed, the method comprising steps of: a) preparing a lead frame having a first surface side and a second surface side opposite from the first surface side, the lead frame comprising a group of terminals of the second surface side, b) placing at least one semiconductor structure having a first surface side and a second surface side opposite from the first surface side, with its second surface side on the first surface side of the lead frame, c) placing at least one heat slug on the first surface side of the at least one semiconductor structure, d) down bonding at least one feedthrough wire on at least one terminal on the first surface side of the lead frame, e) molding the lead frame, the at least one semiconductor structure, the at least one heat slug and the at least one feedthrough into a package having a first surface side and a second surface side opposite to the first surface side, f) exposing the at least one feedthrough wire and the at least one the heat slug through removal of a layer of material from the first surface side of the package, g) forming an electrical connection through printing of a copper deposition on the exposed parts of the at least one heat slug and the at least one feedthrough wire, h) plating of the printed copper deposition.

[0012] Preferably the removal step f) is performed by means of the step of polishing.

[0013] Preferably the steps a)-c) involve the step of sintering or the step of soldering.

[0014] Preferably the step b) comprises the sub-steps b1) and b2): b1) placing as the at least one semiconductor structure at least one metal-oxide semiconductor field-effect transistor on the first surface side of the lead frame, and b2) placing as at least one further semiconductor structure at least one high-electron-mobility transistor on the first surface side of the lead frame, such that every high-electron-mobility transistor at least partly overlaps the at least one metal-oxide semiconductor field-effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The disclosure will now be discussed with reference to the drawings, which show in: Figure 1 depicts a lead frame of a semiconductor device. Figure 2 depicts a solder placed on the lead frame of a semiconductor device. Figure 3 depicts first semiconductor structures placed on the lead frame of the semiconductor device. Figure 4 depicts a solder placed on the first semiconductor structures. Figure 5 depicts second semiconductor structures placed on the first semiconductor structures. Figure 6 depicts a solder placed on the second semiconductor structures. Figure 7 depicts a placing heat slugs on the second semiconductor structures. Figure 8 depicts a feedthrough wires connected to terminals of the lead frame. Figure 9 depicts a package comprising lead frame, the first semiconductor structures, the second semiconductor structures, the heat slugs and the feedthrough wires. Figure 10 depicts a cross section of the semiconductor device before exposing the feedthrough wire. Figure 11 depicts a cross section of the semiconductor device after forming an electrical connection through printing of a copper deposition on the exposed parts. Figure 12 depicts the semiconductor device where exposed surfaces of the second semiconductor structures and the feedthrough wires have been connected with the copper deposition. Figure 13 depicts the semiconductor where a surface of the copper deposition has been covered with a metal during plating. DETAILED DESCRIPTION OF THE DISCLOSURE

[0016] For a proper understanding of the disclosure, in the detailed description below corresponding elements or parts of the disclosure will be denoted with identical reference numerals in the drawings. Throughout a whole application reference numerals will refer to: 1lead frame 1afirst surface side of lead frame 1bsecond surface side of lead frame 2solder 3first semiconductor structure 3afirst surface side of first semiconductor structure 3bsecond surface side of first semiconductor structure 4further semiconductor structure 4afirst surface side of second semiconductor structure 4bsecond surface side of second semiconductor structure 5heat slug 6feedthrough wire 7package 7afirst surface side of package 7bsecond surface side of package 8copper deposition 9plated surface 10terminals

[0017] The disclosure is a method of assembling a source down semiconductor package with top and bottom exposed terminals using package polishing, down bonding and Cu printing method to form, HEMT gate to FET source connections.

[0018] The method is applicable in either a standard or a half bridge configuration GaN cascode or a standard product using clip bonding method, where one or two polarities located in either top or bottom of a die such as vertical products. The concept is designed for a standard dual cool package, it can also apply to a standard source down package.

[0019] Source down power packages are becoming famous due to better performance it can contribute which results in low parasitic inductance, lower package resistance and high current.

[0020] Combining a source down package with a top cooled drain (or source / gate) will increase advantage on thermal performance, either by adding heatsink on top of it, or using a water / air cooling system.

[0021] Other known advantages of introducing a source down cool package are a cost effective alternative to using ceramic substrates and bare dies, as in demanding applications such as EPS it allows the use of FR4 PCB's instead of bare die modules. Also it is a potential alternative to bare die modules in BRM systems (10-20 kW) which requires a water cooling system.

[0022] Furthermore it improves a power density, especially in dual redundant systems. Cooling HEMTs or MOSFETs from the top helps to reduce the PCB temperature. Lower PCB temperatures allows components to be placed closer to the MOSFETs

[0023] The figures depict an example of a semiconductor device according to the disclosure. It consists of a package (reference numeral 7) with a first surface side 7a and a second surface side 7b opposite to the first surface side 7a. The first surface side 7a can be the lower or bottom surface side of the package 7, whereas the second surface side 7b can be the upper or top surface side of the package 7. The package 7 further comprises at least one semiconductor structure (indicated with reference numerals 3 and 4), such as a power transistor or a half bridge, and a group of terminals 8 (10). The group of terminals 8 (10) is connected to the at least one semiconductor structure 3, 4 and are mounted and exposed on the first surface side 7a of the package 7.

[0024] In an example shown in figs. 1-13 a cascode formed of two transistors is presented. The package 7 further comprises at least one heat slug 5 mounted and exposed on the second surface side 7b of the package 7. At least one feedthrough wire 6 is positioned in the package 7 such that the feedthrough wire 6 electrically connects with the at least one heat slug 5.

[0025] The semiconductor device, as described hereinbefore, will allow to transfer heat to both sides of a package which will allow heat dissipation more efficient. It is especially important in power devices such as a half bridge.

[0026] The semiconductor structure is a cascode which comprises a high-electron-mobility transistor and a metal-oxide semiconductor field-effect transistor, wherein a source terminal of the high-electron-mobility transistor is electrically connected to a drain terminal of the metal-oxide semiconductor field-effect transistor, and where a gate terminal of the high-electron-mobility transistor is electrically connected to a source terminal of the metal-oxide semiconductor field-effect transistor.

[0027] A first terminal is connected to the drain terminal of the high-electron-mobility transistor of a first cascode. A second terminal is electrically connected to the gate terminal of the metal-oxide semiconductor field-effect transistor of the first cascode. A third terminal is electrically connected to the source terminal of the metal-oxide semiconductor field-effect transistor and the gate terminal of the high-electron-mobility transistor of the first cascode and the drain terminal of the high-electron-mobility transistor of a second cascode. A fourth terminal is electrically connected to the gate terminal of the metal-oxide semiconductor field-effect transistor of the second cascode and the fifth terminal is electrically connected to the source terminal of the metal-oxide semiconductor field-effect transistor and the gate terminal of the high-electron-mobility transistor of the second cascode, wherein the third terminal is electrically connected with a first heat slug and the fifth terminal is electrically connected to a second heat slug.

[0028] Below a method according to the disclosure is presented for manufacturing the semiconductor device as described hereinbefore. In a first step, denoted as step a, a lead frame 1 is prepared as shown in fig. 1. The lead frame 1 has a first surface side 1a and a second surface side 1b opposite from the first surface side 1a. The lead frame 1 comprises a group of terminals 10 on the second surface side 1b. Those terminals 10 will be connected to at least one semiconductor structure 3.

[0029] During a second step, step b, at least one first semiconductor structure 3 each having a first surface side 3a and a second surface side 3b opposite from the first surface side 3a, is placed with its second surface side 3b on the first surface side 1a of the lead frame 1, as it is shown in fig. 3. It should be noted that more first semiconductor structures 3 may be placed, on a lead frame 1 and / or on other semiconductor structures 3, as it is shown in fig. 5. In such a case, step b comprises the sub-steps b1 and b2. During step b1 at least one semiconductor structure 3, preferably being at least one metal-oxide semiconductor field-effect transistor, is placed on the first surface side 1a of the lead frame 1. As a next step, step b2 is performed where at least one further semiconductor structure 4, preferably at least one high-electron-mobility transistor, is placed on the first surface side 1a of the lead frame 1, wherein the at least one further semiconductor structure 4 at least partly overlaps the at least one semiconductor structure 3.

[0030] Next, step c of the method according to the disclosure is performed, wherein at least one heat slug 5 is placed on the first surface side 3a-4a of the at least one semiconductor structure 3, 4. This is shown in fig. 7.

[0031] During a further step, denoted as step d of the method according to the disclosure, at least one feedthrough wire 6 is down bonded on at least one terminal on the second surface side 1b of the lead frame 1, as it is shown in fig. 8. It should be noted that step c of placing at least one heat slug 5 on the first surface side 3a-4a of the at least one semiconductor structure 3, 4 may be performed after step d. Also the at least one feedthrough wire 6 may be in form of a loop, as shown in fig. 8.

[0032] Next, during step e of the method according to the disclosure, a package 7 is made by molding the lead frame 1, the at least one semiconductor structure 3, 4, the at least one heat slug 5 and the at least one feedthrough wire 6 into a package having a first surface side 7a and a second surface side 7b opposite to the first surface side 7a. The package 7 thus obtained is shown in fig. 9.

[0033] During a next step of the method according to the disclosure, denoted as step f, the at least one feedthrough wire 6 and the at least one the heat slug 5 are exposed from the first surface side 7a. This step f is performed by removing a layer of material from the first surface side 7a of the package 7. Preferably it is done by polishing of the first (top) surface side 7a of a package 7.

[0034] During a following step g of the method according to the disclosure, the forming of an electrical connection is performed. This electrical connection is formed by printing a copper deposition 8 on the exposed parts of the at least one heat slug 5 and the at least one feedthrough wire 6. The result of step g is shown in fig. 12.

[0035] The last step, step h, results in plating of the printed copper deposition 8 with a plating material resulting in a plated surface 9 in or on the first surface 7a of the package, as shown in fig. 13.

[0036] In figs. 12 and 13 the package 7 is not shown for a clarity reasons. It should be however noted that the shown structure is enclosed within the package 7 as shown in figs. 9, 10 and 11.

[0037] In a further detailed example of the disclosure, the steps a-c involve the step of sintering or the step of soldering. This is shown in figs. 2, 4, 6.

Claims

1. A semiconductor device consisting of a package (7) with a first surface side (7a) and a second surface side (7b) opposite to the first surface side (7a), the package (7) comprising at least one semiconductor structure (3, 4) and a group of terminals (10), wherein the group of terminals (10) is connected to the at least one semiconductor structure (3, 4) and mounted and exposed on the first surface side (7a) of the package (7), the package (7) further comprising at least one heat slug (5) mounted and exposed on the second surface side (7b) of the package (7), and at least one feedthrough wire (6) in the package (7) such that the feed through wire (6) electrically connects with the at least one heat slug (5), characterised in that the semiconductor structure (3, 4) forms a half bridge and is a cascode comprising a high-electron-mobility transistor and a metal-oxide semiconductor field-effect transistor, wherein a source terminal of the high-electron-mobility transistor is electrically connected to a drain terminal of the metal-oxide semiconductor field-effect transistor, and where a gate terminal of the high-electron-mobility transistor is electrically connected to a source terminal of the metal-oxide semiconductor field-effect transistor, wherein a first terminal is connected to the drain terminal of the high-electron-mobility transistor of a first cascode, a second terminal is electrically connected to the gate terminal of the metal-oxide semiconductor field-effect transistor of the first cascode, a third terminal is electrically connected to the source terminal of the metal-oxide semiconductor field-effect transistor and the gate terminal of the high-electron-mobility transistor of the first cascode and the drain terminal of the high-electron-mobility transistor of a second cascode, a fourth terminal is electrically connected to the gate terminal of the metal-oxide semiconductor field-effect transistor of the second cascode and the fifth terminal is electrically connected to the source terminal of the metal-oxide semiconductor field-effect transistor and the gate terminal of the high-electron-mobility transistor of the second cascode, wherein the third terminal is electrically connected with a first heat slug and the fifth terminal is electrically connected to a second heat slug.

2. The semiconductor device according to claim 1, wherein the semiconductor structure is a transistor.

3. A method of manufacturing the semiconductor device according to claim 1 or 2, the method comprising steps of: a) preparing a lead frame (1) having a first surface side (1a) and a second surface side (1b) opposite from the first surface side (1a), the lead frame (1) comprising a group of terminals (10) on the second surface side (1b), b) placing at least one semiconductor structure (3, 4) having a first surface side (3a, 4a) and a second surface side (3b, 4b) opposite from the first surface side (3a, 4a), with its second surface side (3b, 4b) on the first surface side (1a) of the lead frame (1), c) placing at least one heat slug (5) on the first surface side (3a, 4a) of the at least one semiconductor structure (3, 4), d) down bonding at least one feedthrough wire (6) on at least one terminal (10) on the first surface side (1a) of the lead frame (1), characterised by the steps of e) molding the lead frame (1), the at least one semiconductor structure (3, 4), the at least one heat slug (5) and the at least one feedthrough wire (6) into a package (7) having a first surface side (7a) and a second surface side (7b) opposite to the first surface side (7a), f) exposing the at least one feedthrough wire (6) and the at least one heat slug (5) through removal of a layer of material from the first surface side (7a) of the package (7), g) forming an electrical connection through printing of a copper deposition (8) on the exposed parts of the at least one heat slug (5) and the at least one feedthrough wire (6), h) plating (9) of the printed copper deposition (5).

4. The method according to claim 3, wherein removal step f) Is performed by means of the step of polishing.

5. The method according to claim 3 or 4, wherein steps a)-d) involve the step of sintering or the step of soldering.

6. The method according to any one of claim 3-5, wherein step b) comprises the sub-steps b1) and b2): b1) placing as the at least one semiconductor structure (3) at least one metal-oxide semiconductor field-effect transistor on the first surface side (1a) of the lead frame (1), and b2) placing as at least one further semiconductor structure (4) at least one high-electron-mobility transistor on the first surface side (1a) of the lead frame (1), such that every high-electron-mobility transistor at least partly overlaps the at least one metal-oxide semiconductor field-effect transistor.