HIGH SIGNAL / NOISE RATIO DIGITAL-TO-ANALOGUE CONVERSION DEVICE

Description

TECHNICAL FIELD

[0001] The invention relates to the field of digital-to-analog converters (DACs), and advantageously to that of high-resolution DACs (conversion of digital signals with a number of bits greater than or equal to 16), for which a high signal-to-noise ratio (SNR) is sought. PREVIOUS STATE OF THE ART

[0002] Digital-to-analog signal conversion is a vast field encompassing a multitude of DAC types and technologies. For the realization of high-resolution DACs with a high signal-to-noise ratio (SNR), operating dynamically with sampling frequencies up to approximately 1 MHz, two main technologies are available: ΣΔ-type DACs and R-2R array DACs.

[0003] However, for both of these technologies, the best of these DACs struggle to exceed an SNR above 160 dB / VHz, which may prove insufficient for certain applications, particularly in the field of metrology, especially when the DACs are intended to operate dynamically.

[0004] With a view to static operation of converters, i.e. use where one wishes to generate a parameterizable DC voltage from a digital control word, solutions have been proposed in order to extend the resolution of DACs, i.e. increase the number of bits on which the conversion is carried out.

[0005] For example, to extend the resolution of a DAC, the paper "Using a 16-bit DAC to generate a cost-efficient 18-DAC transfer function," 2016, by Rahul Prakash, describes the possibility of combining four 16-bit DACs to form a total 18-bit DAC. Each DAC is responsible for converting one-quarter of the total conversion range. Thus, to increase the final resolution by 2 bits, this technique requires using four DACs of the same resolution. More generally, to increase the resolution by n bits, it is advisable to combine 2 n< DAC of the same resolution. However, this technique has several drawbacks. managing the "connections" between the different DACs is delicate and becomes prohibitive for resolutions higher than those presented in this document; the number of DACs needed to raise the resolution by a large number of bits is also prohibitive.

[0006] A second technique for extending the resolution of a DAC, mentioned in Maurice Egan's article "The 20-Bit DAC Is the Easiest Part of a 1-ppm-Accurate Precision Voltage Source" (Analog Dialogue 44-04, April 2010), involves using a primary and a secondary DAC paired together. The principle of this technique is as follows: Each quantization step of the main DAC is subdivided by the quantization of the secondary DAC; an attenuator is present at the output of the secondary DAC to ensure that the full-scale voltage of the secondary DAC corresponds to a voltage of 1 LSB (Less Significant Bit) of the main DAC, i.e., to the quantum of the main DAC.

[0007] This technique has the advantage of using only two DACs, regardless of the number of bits to be extended, and allows the accuracy and linearity performance to be maintained, essentially determined by the main DAC.

[0008] Considering a static application of the resulting global DAC—that is, an application where the goal is to generate a configurable DC voltage from a digital control word—the main limitation to the resolution extension achieved by this technique is related to the differential linearity (DNL) defects of the primary DAC. For example, if the primary DAC has a DNL of ±0.25 LSB, subdividing its LSB by a factor of 4 (thus increasing the resolution by 2 bits) will result in a global DNL of ±1 LSB, pushing the DAC to the limit of monotonicity.

[0009] This need for improvement in the RSN of DACs can also be found for DACs with lower resolution (number of bits < 16).

[0010] US patent application 4,410,879 A discloses digital-to-analog converters to increase the resolution of such converters.

[0011] Document Analog Devices: "Evaluation Board User Guide Evaluation Board for a 20-Bit, Serial Input, Voltage Output DAC", concerns an evaluation board for a digital-to-analog converter.

[0012] Maxim document: "Deglitching Techniques for High-Voltage R-2R DACs Deglitching Techniques for High-Voltage R-2R DACs", concerns glitch reduction techniques applied to high-voltage R-2R digital-to-analog converters.

[0013] Egan Maurice's document, "The 20-Bit DAC Is the Easiest Part of a 1-ppm-Accurate Precision Voltage Source", focuses on a high-precision digital-to-analog converter intended for demanding measurement instruments as well as test and characterization systems.

[0014] Document SHAH ANSHUL: "Why Does Voltage Reference Noise Matter?", concerns an analysis of noise affecting reference voltages in a digital-to-analog converter. DESCRIPTION OF THE INVENTION

[0015] One aim of the present invention is to provide a digital-to-analog conversion device whose SNR is better than those of existing conventional DACs, and for example on the order of 180 dB / VHz.

[0016] To this end, the invention proposes a digital-to-analog conversion device, comprising at least: a first digital-to-analog converter (DAC) with an R-2R network; a second DAC with an R-2R network and a resolutionN 2 is less than a resolution N 1 of the first DAC; an attenuator electrically coupled to an output of the second DAC and configured to deliver an output voltage whose amplitude is equal to a quantum q1 of the first CNA, or between 0.9. q1 and 1.1. q1 by considering, for example, a certain tolerance depending on the desired value for the SNR and the resolution value N 1 , when it receives a full-scale voltage input from the second DAC; an adder configured to add an output voltage from the first DAC and the output voltage from the attenuator; a digital driver circuit configured to deliver a data input from the first DAC N 1 most significant bits of a digital signal N bits intended to be converted analogically by the device, and to deliver on a data input of the second DAC ( N - N 1 ) other bits of the digital signal ofN bits, with N 2 ≥ ( N - N 1 ); a voltage reference generation circuit whose output is electrically coupled to an input of a filtering circuit, an output of the filtering circuit being electrically coupled to a voltage reference input of the first DAC.

[0017] In this digital-to-analog converter, the first and second DACs, the attenuator, and the adder together form a conversion system whose quantization noise is significantly lower than the DNL noise of the main DAC. Furthermore, thanks to the filtering performed on the voltage reference applied to the first DAC, whose impact on the overall noise of the conversion device is much greater than that of the voltage reference applied to the second DAC, the only noises limiting the signal-to-noise ratio of the device are the DNL noise, the thermal noise of the R-2R network of the first DAC (which is much greater than that of the R-2R network of the second DAC after the attenuation device), and the glitch noise generated by the first DAC when the digital-to-analog converter operates dynamically.

[0018] Furthermore, this conversion system allows for easy selection of the number of bits that can be converted by the device thanks to the second DAC, which extends the device's resolution compared to the first DAC's resolution. Because of this increased resolution, achieved through the combined operation of the first and second DACs, it is possible to maintain the same signal-to-noise ratio (SNR) performance while using a lower-resolution, less expensive first DAC, provided that its thermal noise and DNL (Dynamic Line Noise) defects are identical relative to its full-scale output voltage.

[0019] The performance achieved in terms of precision and linearity of the device corresponds to that of the first DAC.

[0020] The device is particularly well-suited for converting signals with a very high static or quasi-static component relative to their alternating current components and the desired noise floor. It is therefore well-suited for use in instrumentation and metrology, especially with sensors that rely on a closed-loop system and whose processing is performed digitally.

[0021] The device is used here in a dynamic manner.

[0022] The device is advantageously used to convert a digital signal of at least 16 bits. The number of bits of the digital signals that can be converted by the device is chosen by selecting the resolutions. N 1 And N 2 of the first and second DACs. However, these resolutions can be chosen such that the device is configured to convert digital input signals of less than 16 bits.

[0023] The quantum q total the device is chosen such that the following relationship is verified: q total < DNL cr ê te 2 3 q 1 with q 1 corresponding to the quantum of the first CNA and DNL ridge corresponding to the peak value of the random noise added to each generated sample corresponding to the differential linearity defects of the first DAC.

[0024] The device may also include a glitch suppression circuit comprising, in a first configuration, a data input electrically coupled to an output of the adder, a control input coupled to the digital driver circuit, and an output forming an output of the digital-to-analog converter; or, in a second configuration, the data input electrically coupled to an output of the first DAC, the control input coupled to the digital driver circuit, and the output coupled to one of the adder inputs. Such a circuit makes it possible, in particular, to suppress glitches generated by the first DAC (which generate significantly more noise than that associated with glitches from the second DAC due to the strong attenuation present downstream of the second DAC).Glitches are transient voltages that appear with each change in the converter's output signal value, and their energy depends on the code transition of the input digital signal. Because of this dependence, their impact on the DAC's output voltage noise spectrum is highly dependent on the generated signal, resulting in disturbances in the useful bandwidth of the generated signal. The glitch suppression circuit eliminates these glitches, and therefore the noise associated with them. Such a configuration can be advantageously implemented since the conversion device is designed to operate dynamically.

[0025] The glitch suppression circuit may include an operational amplifier configured as a follower and a sample-and-hold device. One input of this sample-and-hold device serves as the data input for the glitch suppression circuit, and one output of this device is coupled to a non-inverting input of the operational amplifier configured as a follower. The digital driver circuit may be configured to deliver, at a control input of a controlled switch on the sample-and-hold device that serves as the control input for the glitch suppression circuit, a control signal to open or close the controlled switch. The output of the operational amplifier configured as a follower may also serve as the output of the glitch suppression circuit.

[0026] The filtering circuit can be configured to implement low-pass filtering of a voltage reference intended to be applied to its input.

[0027] In this case, according to a first configuration, the filtering circuit may include at least one RC circuit and an operational amplifier mounted as a follower, configured such that an input of the RC circuit is electrically coupled to the output of the voltage reference generation circuit, an output of the RC circuit is coupled to a non-inverting input of the operational amplifier, and an output of the operational amplifier is coupled to the voltage reference input of the first DAC.

[0028] According to a second configuration, the filtering circuit may include at least: an RC circuit and an operational amplifier mounted as a follower, configured such that a non-inverting input of the operational amplifier is electrically coupled to the output of the voltage reference generation circuit, an output of the operational amplifier is coupled to an input of the RC circuit and an output of the RC circuit is coupled to the voltage reference input of the first DAC; a resistive feedback element coupled between the inverting input of the operational amplifier and the voltage reference input of the first DAC; a capacitive feedback element coupled between the inverting input of the operational amplifier and the output of the operational amplifier.

[0029] Advantageously, the first and second CNAs can be such that N 1 ≥ 16 and / or N 2 ≥ 4.

[0030] Advantageously, the resolution N 2 of the second CNA may be such that N 2 > ( N - N 1 ), and the N 2 - ( N - N 1 The most significant bits of the second DAC can be configured to be set to 0, i.e., such that a zero signal is applied to the inputs of the second DAC corresponding to N 2 - ( N - N 1 ) most significant bits of the second DAC.

[0031] The invention also relates to a sensor comprising at least: a sensitive element configured to measure a physical quantity and deliver at output an analog signal representative of the measured physical quantity; an analog-to-digital conversion and processing device receiving at input the analog signal representative of the measured physical quantity; a controller having an input coupled to an output of the analog-to-digital conversion and processing device and an output on which a measurement signal of the physical quantity is intended to be delivered; a digital-to-analog conversion device according to the invention, comprising a data input to be converted coupled to the output of the controller;an electronic feedback chain comprising an input coupled to an output of the digital-to-analog conversion device, and an output coupled to an input of the sensing element which is configured to subtract an output signal from the electronic feedback chain from the physical quantity intended to be measured.

[0032] Advantageously, the sensitive element can be configured to measure a magnetic field.

[0033] In addition, the sensor can be configured to form a fluxgate magnetometer or an optically pumped vector magnetometer. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The present invention will be better understood upon reading the description of exemplary embodiments given by way of illustration only and in no way limiting, with reference to the accompanying drawings in which: there figure 1schematically represents a digital-to-analog conversion device, the subject of the present invention, according to a particular embodiment; figures 2 and 3 schematically represent examples of the implementation of a filtering circuit for a digital-to-analog conversion device, which is the subject of the present invention; figure 4 schematically represents an example of the implementation of a glitch suppression circuit for a digital-to-analog converter device, which is the subject of the present invention; figure 5 represents examples of signals illustrating the operating principle of the glitch suppression circuit shown on the figure 4 ; there figure 6 represents an example of an embodiment of the attenuator and adder of a digital-to-analog conversion device, which is the subject of the present invention; the figures 7 and 8schematically represent examples of sensor implementations, each comprising a digital-to-analog conversion device, which is the subject of the present invention; figure 9 schematically represents a digital-to-analog conversion device, the subject of the present invention, according to one embodiment.

[0035] Identical, similar or equivalent parts of the different figures described below bear the same numerical references in order to facilitate the transition from one figure to another.

[0036] The different parts represented in the figures are not necessarily shown on a uniform scale, in order to make the figures more legible.

[0037] The different possibilities (variants and modes of implementation) should be understood as not being mutually exclusive and can be combined with each other. DETAILED DESCRIPTION OF SPECIFIC METHODS OF IMPLEMENTATION

[0038] An example of the implementation of a 100 digital-to-analog conversion device according to a particular embodiment is schematically represented on the figure 1 and described below.

[0039] Device 100 comprises a first R-2R array DAC 102 and a second R-2R array DAC 104. The first DAC 102 has a resolution N 1 greater than the resolution N 2 of the second CNA 104.

[0040] An output of the second DAC 104 is electrically coupled to an input of an attenuator 106. The attenuator 106 is configured to deliver an output voltage whose amplitude is equal to a quantum q1 of the first CNA 102, or between 0.9.q1 and 1.1.q1, taking into account a certain tolerance depending on the desired value for the RSN and the resolution value N 1 ,when it receives as input the maximum excursion of the second CNA 104 which can range, depending on the operation of the latter, from ten millivolts to a few volts.

[0041] The outputs of attenuator 106 and first DAC 102 are coupled to an adder 108 configured to add the output voltage of first DAC 102 and the output voltage of attenuator 106.

[0042] An output of the adder 108 is coupled to an input of a glitch suppression circuit 110, which allows for the suppression of glitches generated by the first DAC 102. The output voltage of the glitch suppression circuit 110, called "Vout" on the figure 1 , corresponds to the output voltage of device 100.

[0043] Device 100 also includes a digital driver circuit 112 coupled to inputs of the first and second DACs 102, 104 and the glitch suppression circuit 110, allowing coordinated control of the first and second DACs 102, 104 and circuit 110. The digital driver circuit 112 is configured to deliver the following to an input of the first DAC 102: N 1 most significant bits of a digital signal N bits intended to be converted analogically by device 100, and to deliver on an input of the second DAC 104 the ( N - N 1 ) other bits of the digital signal of N bits. The resolution N 2 of the second CNA 104 is such that N 2 ≥ ( N - N 1 ) . As an example, the 112 circuit can be of type FPGA, ASIC, microcontroller, etc.

[0044] Device 100 also includes a filtering circuit 114 interposed between an output of a voltage reference generation circuit 116 and a voltage reference input of the first DAC 102.

[0045] Although not shown on the figure 1 , device 100 also includes a second voltage reference generation circuit coupled to a voltage reference input of the second DAC 104.

[0046] In this device 100, the first and second DACs 102, 104, the attenuator 106 and the adder 108 together form a digital-to-analog conversion system whose resolution N is greater than each of the resolutions N 1 And N 2 of the first and second CNA 102, 104. In this system, the first CNA 102 forms a main CNA whose each quantization step is subdivided by the quantization of the second CNA 104 which forms a secondary CNA.

[0047] Furthermore, in this digital-to-analog conversion system, the quantization noise of the system is lowered well below the noise generated by the differential linearity defects, or DNL noise, of the DACs 102, 104, as explained below.

[0048] In general, quantization noise b. how much The value of a CNA is expressed by the following relationship: b quant = q 12 with q corresponding to the quantum of the CNA.

[0049] The RSN associated with this quantization noise, called SNR amount, is expressed by the following relationship: SNR quant dB = 6.02 N bits + 1.76 with N bits corresponding to the resolution of the CNA.

[0050] With a DAC operating at a frequency Fe, The noise power is spread over the entire Nyquist bandwidth of the DAC, and its SNR is expressed in dB / VHz according to the following relationship: SNR quant dB Hz = 6.02 N bits + 1.76 + 20 log F e 2

[0051] Furthermore, for small signals, and when the DAC is activated with control words (i.e., non-repetitive digital input signals to be converted), the differential linearity defects of the DAC can be likened to the addition of random noise to each generated sample (an error that depends solely on the input digital word) with a peak-to-peak value of ± DNL crest. Its noise level can therefore be estimated at DNL ridge / 3 assuming a Gaussian distribution. Noise from differential linearity defects B DNL and its associated RSB, called SNR DNL, They then express themselves in the following way: b DNL = DNL cr ê te 3 q SNR DNL dB = 20 log 3 DNL cr ê te 2 Nbits − 1 2

[0052] Similar to quantization noise, this noise related to differential linearity defects is also spread over the entire Nyquist bandwidth of the DAC, hence its SNR is expressed in dB / VHz: SNR DNL dB / √ Hz = 20 log 3 DNL cr ê te 2 Nbits − 1 2 + 20 log F e 2

[0053] Since these two noise sources are not correlated, the total noise B DNL The output of a DAC then follows a quadratic summation rule and is expressed by the following relation: b out = b quant 2 + b DNL 2

[0054] The corresponding RSB is then expressed by the relation: SNR OUT = 20 log 2 Nbits − 1 2 b out

[0055] To make the noise quantized b. how much negligible compared to the total output noise end , quantization noise b. how much must be kept well below the DNL b noise. For example, and for the remainder of this discussion, a noise b can be chosen according to equation (9) which limits the increase in total output noise to +0.26 dB end related to quantization noise b. how much : b quant < b DNL / 4

[0056] By combining relations (1), (4) and (9) above, and considering q total as being the quantum of device 100 and q 1 as being the quantum of the first CNA 102, the CNAs 102, 104 can be chosen or designed such that the following relationship is verified: q total < DNL cr ê te 2 3 q 1

[0057] It should be noted that the quantization noise and the DNL noise of the second DAC 104 are, within device 100, much lower than those of the first DAC 102. Thus, the value of the quantum of the second DAC 104 does not appear in equation (10) above.

[0058] In other words, the quantum q total of device 100 is chosen such that relation (10) above is verified, with q 1 corresponding to the quantum of the first CNA 102 and DNL ridge corresponding to the peak value of the random noise added to each generated sample corresponding to the differential linearity defects of the first DAC 102.

[0059] The values ​​of DNL ridgeThe values ​​of the CNA 102, 104, expressed as a fraction of the quantum of these CNA 102, 104, and provided by the manufacturer of the CNA 102, 104 in the corresponding datasheets, depend on the manufacturing quality of the CNA 102, 104 and also on the resolution of the CNA 102, 104: the higher these resolutions, the more difficult it is to obtain values ​​of DNL ridge weak, and vice versa. For example, for a first DAC with a resolution of 102 N 1 equal to 20 bits, the DNL ridge of this CNA can be on the order of 0.3. q 1 The quantum q total of device 100 respecting relation (10) above is then less than approximately q 1 / 12, which is obtained by choosing a second 104 resolution DAC N 2 of at least 4 bits. The resolution value N 2 is chosen to achieve the attenuation factor between the quantums q1 and qtotal, here equal to 12, with N 2 = In12 / ln2 = 3.5, which gives 4 bits when the result is rounded up to the nearest whole number. According to another example, for a first DAC 104 with lower resolution, for example N 1 = 16 bits, the DNL ridge of this first CNA may be lower and for example equal to about 0.1. q 1 The quantum q total of device 100 respecting relation (10) above is then less than approximately q 1 / 35, which is obtained by choosing a second 104 resolution DAC N 2 of at least 6 bits.

[0060] The demonstration above describes how the minimum resolution value is chosen. N 2 of the second DAC 104 to minimize quantization noise in device 100. Advantageously, the resolution value N 2 The second DAC 104 is chosen to be greater than this minimum value, for example, by 4 additional bits compared to this minimum value, which allows it to exhibit the properties of white noise related solely to DNL noise. Indeed, "pure" quantization noise can generate a line spectrum and not white noise. Choose a resolution value N 2 The second CNA 104, exceeding the minimum value indicated above, prevents these lines, where the noise power is concentrated, from exceeding the DNL noise. For example, if the minimum resolution value N 2 is 4 bits, the second 104 DAC can be chosen such that the value of its resolution N 2 or 8 bits.

[0061] In the device 100 described here, in addition to the minimization of quantization noise provided by the system formed by the first and second DACs 102, 104, the attenuator 106 and the adder 108, the increase in the value of the SNR of the device 100 is also obtained through the filtering of the voltage reference delivered by the circuit 116 and intended to be applied to the input of the first DAC 102, this filtering being carried out by the filtering circuit 114.

[0062] Indeed, two main sources of analog noise are present in an R-2R network DAC: the internal noise of the R-2R network; the noise brought by the voltage reference applied to the input of the DAC, which is generally at least 10 times greater than the internal noise of the R-2R network.

[0063] In device 100, the filtering circuit 114 minimizes and makes negligible the noise brought by the voltage reference compared to the internal noise of the R-2R networks of the DACs 102, 104, and therefore the analog noise of device 100 corresponds substantially to this internal noise of the R-2R networks of the DACs 102, 104.

[0064] Indeed, the noise from the R-2R network, called b R-2R , The noise of a DAC essentially corresponds to the thermal noise of the DAC's R-2R network, and therefore depends on the network's equivalent impedance. This R-2R network noise is specific to the DAC's construction and its value b R-2R cannot be reduced. However, its associated RSN is, to some extent, adjustable because it is directly related to the DAC's output voltage excursion, called ΔV out max cc . This RSB, called SNR R-2R, is expressed by the following relationship: SNR R − 2 R dB / √ Hz = 20 log Δ V out max c − c 2 2 b R − 2 R

[0065] The output voltage of a DAC is directly proportional to the reference voltage applied to the DAC's reference input. Therefore, the noise contribution of the voltage reference... Short at full noise end The output voltage of the DAC is all the more important as the value of the DAC output voltage approaches the value of the DAC's full-scale voltage. It is therefore possible to write the following relationship: b out ≡ b Ref Code 2 Nbits with the variable "Code", also called "Data DAC", corresponding to the digital input instruction to be converted by device 100.

[0066] Advantageously, the filtering circuit 114 is configured to implement low-pass filtering. The severity of the filtering (order, cutoff frequency) to be implemented depends on the noise of the chosen voltage reference and the frequency from which the optimized SNR is desired (a value specific to each application).

[0067] A first example of the implementation of the filtering circuit 114 is shown schematically on the figure 2 .

[0068] In this first embodiment, the filter circuit 114 comprises a resistive element 118 and a capacitive element 120 electrically coupled in series to form an RC circuit. An input of the RC circuit, formed by a first electrode of the resistive element 118, is coupled to the output of the voltage reference generation circuit 116, to which a reference voltage Vref is supplied. The filter circuit 114 also includes an operational amplifier 122 configured as a voltage follower. The operational amplifier 122 is advantageously chosen to introduce the least possible noise. The non-inverting input of the operational amplifier 122 is coupled to an output of the RC circuit formed by a second electrode of the resistive element 118, to which one of the electrodes of the capacitive element 120 is electrically coupled.The output of operational amplifier 122, on which the filtered voltage reference "V ref filtered" is delivered, is coupled to the voltage reference input of the first DAC 102.

[0069] The noise of voltage references, even those chosen from the quietest on the market, peaks at around 180nV / √Hz for a 10V voltage. This noise is significantly higher than that of an R-2R network in a DAC, for example, on the order of 7.5nV / VHz. Considering a voltage reference generating 180nV / √Hz noise, with a target of 7.5nV / VHz from 1Hz, the attenuation achieved must be 24 (27.6 dB), and the cutoff frequency for a first-order signal of 0.04 Hz (time constant of 4 seconds), which is achievable with a resistive element of R = 10 kΩ and a capacitive element of C = 400 µF.

[0070] Filtering circuits 114 different from the one described above are possible depending on the applications of the device 100, particularly if these require high specifications for the conversion accuracy of the DC component, in addition to the desired high signal-to-noise ratio (SNR). For example, filtering with a low cutoff frequency to achieve noise attenuation at the desired frequency may require a significant RC couple of values. The leakage current inherent in the capacitive element 120 can cause a slight voltage drop across the resistive element 118 and alter the DC component of the output signal of the device 100. In this case, a circuit with negative feedback can be considered to maintain the accuracy of the DC component of the voltage reference, as shown, for example, in the diagram. figure 3 .

[0071] In the second example of the implementation of the filtering circuit 114 shown on the figure 3The non-inverting input of operational amplifier 122 is coupled to the output of the voltage reference generation circuit 116. The output of operational amplifier 122 is coupled to the input of the RC circuit formed by the resistive element 118 and the capacitive element 120. The output of the RC circuit is coupled to the voltage reference input of the first DAC 102. The filtering circuit 114 also includes a resistive feedback element 124 coupled between the inverting input of operational amplifier 122 and the voltage reference input of the first DAC 102, and a capacitive feedback element 126 coupled between the inverting input of operational amplifier 122 and the output of operational amplifier 122.

[0072] Minimizing the noise of device 100 also advantageously involves using the glitch suppression circuit 110. Advantageously, the glitch suppression circuit 110 can incorporate a sample-and-hold device. An example of such an implementation of the glitch suppression circuit 110 is shown schematically in the diagram. figure 4 In this embodiment, the sample-and-hold device of circuit 110 includes a controlled switch 128, one terminal of which forms a data input to circuit 110 coupled to the output of the adder 108. On the figure 4The signal delivered at the output of the adder 108 is called V out DAC. A control input of this switch 128 is coupled to the digital driver circuit 112, which controls the circuit 110 by sending a control signal to open or close the switch 128, called "Switch Control" on the figure 4 A second terminal of the controlled switch 128 is coupled to an electrode of a capacitive element 130 of the sample-and-hold circuit. The output of the sample-and-hold circuit, formed by the connection between the capacitive element 130 and the controlled switch 128, is coupled to the non-inverting input of an operational amplifier 132 configured as a voltage follower (inverting input coupled to its output). The voltage delivered at the output of the operational amplifier 132 corresponds to the output signal of the circuit 110, that is, the output signal Vout of the device 100.

[0073] Thanks to the glitch suppression circuit 110, all components of the spectrum generated by the glitches of the first DAC 102, including those known as "low frequencies" (and, to a lesser extent, of the second DAC 104) are eliminated.

[0074] The operating principle of the previously described 110 glitch suppression circuit is explained below, in connection with the figure 5In this figure, a glitch appears on the V out_DAC voltage delivered at the output of the adder 108 due to a change in the value of the digital input data "Data DAC" to be converted by device 100 (transition from data "Data n" to data "Data n+1"). A time t1 before this change in the value of "Data DAC", a command to open the controlled switch 128 is sent by circuit 112, and the value of V out_DAC remains stored in the capacitive element 130. At the moment of the setpoint change and for a total time t2, the value of the voltage V out delivered at the output of circuit 110 does not change and remains equal to the value stored in the capacitive element 130, regardless of the presence of the glitch generated following the setpoint change, because the controlled switch 128 is still in the open position.After the duration t2, the glitch having disappeared, the controlled switch 128 is closed and V out takes the new value V out n+1 in a controlled manner.

[0075] For optimal operation of the glitch suppression circuit 110, the durations t1 and t2 can be chosen such that the duration t1 is slightly greater than the opening delay of the controlled switch 128, and the duration t2 is slightly greater than the maximum duration of the glitches generated within the device 100. For example, the switching delays of the analog switches being on the order of 100 ns, the duration t1 can be chosen to be about 200 ns and the duration t2 can be chosen to be about 1 µs (the value of this duration being however dependent on the duration of the glitches generated by the DACs used in the device 100, and in particular the first DAC 102).

[0076] In addition, the operational amplifier 132 is chosen such that it advantageously presents an input noise lower than the noise of the R-2R network of the first DAC 102 in order to contribute as little as possible to the final output noise of the device 100. For example, it is possible to choose an operational amplifier 132 whose input noise is 2.8 nV / VHz for a frequency above 50 Hz, with a maximum bias current of 2 nA (whose maximum effect on the voltage across the capacitor element 130 during the opening of the controlled switch 128 is equivalent to 0.02). q 1 (that is, is negligible).

[0077] In the sample-and-hold circuit 110, the value C of the capacitive element 130 is preferably maximized within the bandwidth limit desired by the digital-to-analog conversion system because: The absorption by the capacitive element 130 of the injection charge Q required to open and close the controlled switch 128, expressed in pC, has the effect of modifying the voltage across the capacitive element 130 by the value ΔU = Q / C. Thus, the larger C is, the less the voltage across its terminals is disturbed; this allows the capacitive element 130 to better retain the value of the "stored" voltage, the capacitor voltage charging or discharging according to the bias current of the operational amplifier 132.

[0078] In the previously described embodiment, the glitch suppression circuit 110 has its data input coupled to the output of the adder 108, and the output of circuit 110 forms the output of device 100. Alternatively, the data input of the glitch suppression circuit 110 may be coupled to the output of the first DAC 102, and the output of circuit 110 may be coupled to one of the inputs of the adder 108. In this case, the output of the adder 108 forms the output of device 100. Such a variant is schematically represented in the diagram. figure 9 .

[0079] There figure 6 described below represents an example of the implementation of attenuator 106 and adder 108.

[0080] In this embodiment, to minimize the use of active components that could potentially degrade noise, the analog attenuation, called "Att," applied to the output voltage of the second DAC 104 is achieved using an injection resistor, with a value of Rinj, forming the attenuator 106. One terminal of the injection resistor 106 is coupled to the output of the second DAC 104. Furthermore, in this embodiment, the adder 108 corresponds to a coupling between the output of the first DAC 102 and a second terminal of the injection resistor 106.

[0081] Considering the internal output resistances of DACs 102 and 104, respectively called RDAC_102 and RDAC_104, the voltage Vout_DAC obtained at the output of adder 108 is expressed by the relation: V out _ DAC = 1 R DAC _ 102 + R DAC _ 104 + R inj V DAC _ 104 R DAC _ 104 + R Inj + V DAC _ 102 R DAC _ 102

[0082] Considering R inj >> R DAC_102 and R DAC-104, equation (13) can be simplified as follows: Vout ≈ V DAC 102 + Att . V DAC _ 104

[0083] With "Att" corresponding to the attenuation coefficient applied by the attenuator 106 to the output voltage of the second DAC 104 and expressed by the following relation: Att ≈ R DAC _ 102 R Inj

[0084] In the device 100 described above, thanks to the reduction of the quantization noise compared to that generated by the differential linearity defects obtained by the digital-to-analog conversion system formed by the first and second DACs 102, 104, the attenuator 106 and the adder 108, the filtering of the voltage reference by the filtering circuit 114 and the elimination of glitches by the glitch suppression circuit 110, the total SNR, called total SNR, attainable by the device 100 is limited only by the two SNRs associated with the two irreducible noise sources, namely the R-2R network and the differential linearity defects, and is expressed by the following relationship: SNR Total = 10 log 1 10 − SNR DNL / 10 + 10 − SNR R − 2 R / 10

[0085] As an example, by choosing a first DAC 102 with a resolution of 20 bits, operated with a maximum output voltage deviation of ±10V (which corresponds to applying a 10V reference voltage to the first DAC 102) and with a sampling frequency Fe of 100 kHz (the frequency allowing correct operation of the glitch suppression circuit 110), a DNL ridge of the order 0.3. q 1 , an R-2R network with an impedance of 3.4 kΩ and a noise of 7.5 nV / VHz, the values ​​of the different SNRs obtained are: SNR R-2R = 182.5 dB / VHz and SNR DNL = 178.4 dB / VHz. The total achievable SNR is then 177dB / √Hz, i.e. a gain of about 15dB compared to the state of the art achievable by a conventional implementation of the best digital-to-analog converters on the market.

[0086] In the previous example, the resolution N 2 The second DAC 104 has a resolution of at least 4 bits to make quantization noise negligible compared to differential linearity noise. Advantageously, it is possible to choose a resolution value N 2 more important, for example equal to 8 bits in the example previously described, the device 100 in this case performing a digital-to-analog conversion of 28 bits in total.

[0087] It is also possible to choose the first and second CNA 102, 104 such that the sum of the resolutions N 1 And N 2 be greater than the number of bits of the digital signal to be converted by the device 100. More specifically, the resolution N 2 of the second CNA 104 may be such that N 2 > ( N - N 1 ), and the N 2 - ( N - N 1The most significant bits of the second 104 DAC can be configured to be set to 0, i.e., such that a zero signal is applied to the inputs of the corresponding second 104 DAC. to N 2 - ( N - N 1 ) most significant bits of the second DAC 104.

[0088] In the previously described example, it is possible to have N 1 = 20 bits and N 2 = 16 bits, although device 100 performs a conversion of only a 28-bit signal. In this case, some of the most significant bits (the 8 most significant bits in the example described here) of the second DAC 104 are left at 0. This allows the second DAC 104 to contribute to the attenuation function performed by attenuator 106, as explained below.

[0089] Indeed, the output voltage V out_DAC obtained by summing the signals delivered by the first and second DACs 102, 104 is expressed as follows: V OUT _ DAC = 2 V REF _ 102 2 N 1 − 1 N H − V REF _ 102 + V REF _ 104 2 N 2 N L 2 N 2 − L − p Att With : V REF_102 corresponding to the value of the reference voltage applied to the input of the first DAC 102; V REF_104 corresponding to the value of the reference voltage applied to the input of the second DAC 104, and which is for example equal to 5 V in the example described above; NH corresponding to a positive binary number between 0 and 2 N1< - 1 and applied as input to the first DAC 102; NL corresponding to a positive binary number between 0 and 2 NL< - 1 and applied as input to the second DAC 104; L corresponding to the number of bits of the second 104 DAC used for the conversion, that is N - N 1 which corresponds to the number of "useful" bits of the bit extension); p corresponding to the number of bits set to 0 on the most significant bits of the word of the second CNA 104, that is N 2 - ( N - N 1 );

[0090] Considering that 2N1< -1 ≈ 2N1< given the high value of N 1 ,Equation (17) can be written as follows: V OUT _ DAC ≈ 2 V REF _ 102 2 L 2 N 1 + L N H − V REF _ 102 + V REF _ 104 2 L + p N L Att

[0091] Considering that the first and second DACs 102, 104, the attenuator 106 and the adder 108 form a single resolution DAC (N 1 +L) bits, the output voltage V OUT_DAC is also expressed by the following equation: V OUT _ DAC = 2 V REF _ 102 2 N 1 + L 2 L N H + N L − V REF _ 102

[0092] Combining equations (18) and (19) leads to the following condition: V REF _ 104 2 L + p Att = 2 V REF _ 102 2 N 1 + L

[0093] The value of the attenuation "Att" to be implemented is then: Att = 2 p 2 V REF _ 102 V REF _ 104 2 N 1

[0094] Thus, with the values ​​of V REF-102 = 10V, V REF_104 = 5V, N 1 = 20 bits, if pIf the value is chosen to be 0 (full-scale voltage of the second DAC 104 equal to the reference voltage injected into it), an extremely severe analog attenuation (corresponding to the attenuation coefficient applied by the attenuator 106) of 262144 would be required, which could prove difficult to implement with the summing architecture used in device 100. On the other hand, by choosing, for example, a second DAC 104 with a resolution of N 2 = 16 bits, of which only the 8 least significant bits will be added to the 20 bits of the first DAC 104, and by setting the 8 most significant bits to 0 (p=8), the second DAC 104 contributes to the attenuation by a factor of 256, and the remaining analog attenuation to be applied is then only 1024, a value that becomes easier to implement. Considering equation (15) described previously, with a first DAC 102 having an output resistance RDAC_102 equal to 3.4 kΩ and a second DAC 104 having an output resistance RDAC-104 equal to 6.2 kΩ, an attenuation factor Att equal to 1024 is obtained by choosing an injection resistance 106 such that Rinj = 3.482 MΩ.

[0095] In the example described above, since the value R inj is much greater than R DAC_102, the bandwidth of device 100 is fixed by the product R DAC_102 x C, with C corresponding to the value of capacitor 130 of the glitch suppression circuit 110. For example, with R DAC_102 = 3.4 kΩ and for a desired bandwidth of 10 kHz, the value C of capacitor 103 can be chosen to be 4.7 nF. By choosing a controlled switch 128 with a low injection load, for example equal to 0.19 pC, the change in voltage across capacitor 130 can be estimated at 40 µV, which is equivalent to twice the value of q1, a disturbance not negligible in itself. However, this disturbance is independent of the digital word applied to the input of device 100 and is constant regardless of the output voltage, unlike the glitches generated by the first DAC 102.The generated interference spectrum is then scaled to the sampling frequency and its multiple harmonics, i.e., outside the bandwidth of the useful signal. A downstream low-pass filter can eliminate these harmonics if necessary, should they prove problematic for the application.

[0096] The device 100 described above is used dynamically. When the device 100 is intended for use at a low operating frequency, the device 100 may not include the glitch suppression circuit 110.

[0097] Device 100 is advantageously used within a sensor based on a closed-loop system and whose processing is performed digitally. An example of such a sensor 1000 is shown schematically on the figure 7 .

[0098] Sensor 1000 includes a sensitive element 1002 that receives as input a physical quantity to be measured and a feedback signal from sensor 1000. The resulting error signal output from sensitive element 1002 is applied to the input of an analog-to-digital conversion and processing circuit 1004. This circuit conditions the error signal for input to the controller 1006. The complexity of this processing varies greatly depending on the nature of the error signal from the sensitive element (application of gains, filtering, demodulation operations, etc.). The controller 1006, typically comprising an integrator, outputs a signal from sensor 1000 that corresponds to a digital measurement of the physical quantity to be measured.This signal is also used to generate the feedback quantity via the digital-to-analog converter 100, followed by the feedback loop 1008, which converts the output voltage of device 100 into a quantity with the same dimensions as the physical quantity to be measured. The output signal of the feedback loop 1008 is applied to the input of the sensing element 1002.

[0099] In such a sensor, where the measurement of the physical quantity is taken from the setpoint of the feedback signal, the quality of the measurement depends directly on the quality of this feedback chain. The digital-to-analog device is therefore a critical element of this type of architecture, since any defect or noise in the device will be reflected in the measured quantity.

[0100] The 1000 sensor, for example, corresponds to a magnetic measurement sensor, such as a helium-4 optically pumped vector magnetometer known as a "zero-field" magnetometer, or a fluxgate magnetometer. figure 8 schematically represents the 1000 sensor in such a configuration.

[0101] As shown in the diagram of the figure 7 , the 1000 sensor shown on the figure 8 includes the sensitive element 1002, which is configured here to measure a magnetic field. The measurement signal delivered at the output of the sensitive element 1002 is applied to the input of circuit 1004, which, in the configuration of the figure 8This device implements probe, signal amplification, analog-to-digital conversion, and processing functions. A digital output signal from circuit 1004 is applied to the input of controller 1006, which here corresponds to a pure integral controller (I controller) or a proportional / integral controller (PI controller). This controller 1006 outputs a signal from sensor 1000, which corresponds to a digital measurement of the magnetic field to be measured. Sensor 1000 also includes a feedback loop comprising device 100, which receives the output signal from sensor 1000 as its input. The analog output signal from device 100 is applied to the input of device 1010, which converts the voltage setpoint into a current. This current is then applied to the input of a coil 1012, which generates the compensating magnetic field applied to the input of the sensing element 1002.

[0102] For the 1000 sensor shown on the figure 7 The DC magnetic field to be measured typically extends over a range of ±70µT for measuring the Earth's magnetic field, while maintaining an extremely low sensor noise level that can reach 50fT / √Hz, all within a measurement bandwidth of a few kilohertz. In this case, the required signal-to-noise ratio (SNR) imposed on the feedback signal (here, the compensating magnetic fields that will impose a zero field within the sensing element 1002 of sensor 1000) is then set at 180dB / √Hz. The digital-to-analog converter 100, as described previously, then proves its worth and allows for a substantial response to the needs of these types of sensors.

[0103] Details of the realization of such a 1000 vector magnetic measurement sensor with helium 4 optical pumping are for example described in the thesis of Matthieu Le Prado, "Design, realization and application of a vector atomic magnetometer", University of Franche-Comté, 2014.

Claims

1. A digital-to-analogue conversion device (100), comprising at least: - a first digital-to-analogue converter, DAC, (102) with R-2R network; - a second DAC (104) with R-2R network and a resolution N2 of which is lower than a resolution N1 of the first DAC (102); - an attenuator (106) electrically coupled to an output of the second DAC (104) and configured to output a voltage whose amplitude is between 0.9xql and 1.1xql, with q1 corresponding to the quantum of the first DAC (102), when it receives as an input a full-scale voltage of the second DAC (104); - an adder (108) configured to add an output voltage of the first DAC (102) and the output voltage of the attenuator (106) ; - a digital drive circuit (112) configured to deliver on a data input of the first DAC (102) N1 most significant bits of a N-bit digital signal intended to be analogueconverted by the device (100), and to deliver on a data input of the second DAC (104) (N - N1) other bits of the N-bit digital signal, with N2 ≥ ( N - N1); - a voltage reference generation circuit (116) an output of which is electrically coupled to an input of a filtering circuit (114), an output of the filtering circuit (114) being electrically coupled to a voltage reference input of the first DAC (102); wherein the quantum qtotal of the device (100) is chosen such that the following relationship is verified: q total < DNL peak 2 3 q 1 with q1 corresponding to the quantum of the first DAC (102) and DNLpeak corresponding to the peak value of the random noise added to each sample generated corresponding to the differential linearity defects of the first DAC (102).

2. The device (100) according to claim 1, further comprising a glitch suppression circuit (110) comprising, in a first configuration, a data input electrically coupled to an output of the adder (108), a control input coupled to the digital drive circuit (112) and an output of which forms an output of the device (100), or, in a second configuration, the data input electrically coupled to an output of the first DAC (102), the control input coupled to the digital drive circuit (112) and the output coupled to one of the inputs of the adder (108).

3. The device (100) according to claim 2, wherein the glitch suppression circuit (110) includes a follower-mounted operational amplifier (132) and a sample-and-hold type device (128, 130) one input of which forms the data input of the glitch suppression circuit (110) and one output of which is coupled to a non-inverting input of the follower-mounted operational amplifier (132), and wherein the digital drive circuit (112) is configured to deliver, on a control input of a controlled switch (128) of the sample-and-hold type device (128, 130) forming the control input of the glitch suppression circuit (110), a control signal for opening or closing the controlled switch (128).

4. The device (100) according to one of the preceding claims, wherein the filtering circuit (114) is configured to implement low-pass filtering on a voltage reference to be applied to its input.

5. The device (100) according to claim 4, wherein the filtering circuit (114) includes at least one R-C circuit (118, 120) and a follower-mounted operational amplifier (122), configured such that an input of the R-C circuit (118, 120) is electrically coupled to the output of the voltage reference generation circuit (116), that an output of the R-C circuit (118, 120) is coupled to a non-inverting input of the operational amplifier (122) and that an output of the operational amplifier (122) is coupled to the voltage reference input of the first DAC (102).

6. The device (100) according to claim 4, wherein the filtering circuit (114) further comprises: - an R-C circuit (118, 120) and a follower-mounted operational amplifier (122), configured such that a non-inverting input of the operational amplifier (122) is electrically coupled to the output of the voltage reference generation circuit (116), that an output of the operational amplifier (122) is coupled to an input of the R-C circuit (118, 120) and that an output of the R-C circuit (118, 120) is coupled to the voltage reference input of the first DAC (102); - a feedback resistive element (124) coupled between the inverting input of the operational amplifier (122) and the voltage reference input of the first DAC (102); - a feedback capacitive element (126) coupled between the inverting input of the operational amplifier (122) and the output of the operational amplifier (122).

7. The device (100) according to one of the preceding claims, wherein N2 ≥ 16 and / or wherein N2 ≥ 4.

8. The device (100) according to one of the preceding claims, wherein N2 > (N - N1), and the N2 - (N - N1) most significant bits of the second DAC are configured to be set to 0.

9. A sensor (1000) comprising at least: - a sensing element (1002) configured to measure a physical quantity and output an analogue signal representative of the physical quantity measured; - an analogue-to-digital conversion and processing device (1004) receiving as an input the analogue signal representative of the physical quantity measured; - a corrector (1006) an input of which is coupled to an output of the analogue-to-digital conversion and processing device (1004) and an output to which a measurement signal of the physical quantity is intended to be delivered; - a digital-to-analogue conversion device (100) according to one of the preceding claims, comprising a data input to be converted, which input is coupled to the output of the corrector (1006); - a reinjection electronic chain (1008, 1010, 1012) comprising an input coupled to an output of the digital-to-analogue conversion device (100), and an output coupled to an input of the sensing element (1002) which is configured to subtract an output signal of the reinjection electronic chain from the physical quantity intended to be measured.

10. The sensor (1000) according to claim 9, wherein the sensing element (1002) is configured to measure a magnetic field.

11. The sensor (1000) according to claim 10, configured to form a fluxgate type magnetometer or an optically pumped vector magnetometer.