Process for fabricating a double semiconductor-on-insulator structure
Patent Information
- Application Number
- EP2023706412
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-01-31
- Filing Date
- 2023-01-30
- Publication Date
- 2024-12-11
AI Technical Summary
The existing methods for manufacturing double semiconductor on insulator (SOI) structures, such as the Smart Cut™ process, face challenges in achieving good bonding quality due to surface roughness and defects, which lead to electrical performance and mechanical strength issues in the final structure.
A method involving a series of surface treatments including rapid thermal annealing, thermal oxidation followed by deoxidation, long-term thermal annealing, and mechanical-chemical polishing is applied to the transferred semiconductor layer to reduce roughness and defectivity, optimizing the surface for improved bonding during the second layer transfer.
This approach significantly reduces the number of holes and irregularities at the bonding interface, minimizing the width of the peripheral crown and enhancing the mechanical and electrical performance of the double SOI structure.
Smart Images
Figure 1.1
Abstract
Description
[0001] METHOD FOR MANUFACTURING A DOUBLE SEMICONDUCTOR-ON-INSULATOR STRUCTURE
[0002] TECHNICAL FIELD
[0003] The invention relates to a method for manufacturing a double semiconductor-on-insulator type structure.
[0004] STATE OF THE ART
[0005] Semiconductor-on-insulator structures are multilayer structures comprising a support substrate which is generally made of a semiconductor material such as silicon, an electrically insulating layer arranged on the support substrate, which is generally an oxide layer such as a silicon oxide layer, and a semiconductor layer arranged on the insulating layer, which is generally a silicon layer. Such structures are called "Semiconductor on Insulator" structures in English, in particular "Silicon on Insulator" (SOI) when the semiconductor material is silicon. The oxide layer is located between the substrate and the semiconductor layer. The oxide layer is then said to be "buried", and is called "BOX" for "Buried Oxide" in English. In the remainder of the text, the term "SOI" will be used to generally designate semiconductor-on-insulator structures.
[0006] In addition to SOI structures comprising a BOX layer and a semiconductor layer arranged on the BOX layer, “double SOI” structures have been produced. The “double SOI” structures comprise a handle substrate, a first oxide layer or lower buried oxide layer arranged on the support substrate, a first semiconductor layer or lower semiconductor layer arranged on the first oxide layer, a second oxide layer or upper buried oxide layer arranged on the first semiconductor layer and a second semiconductor layer or upper semiconductor layer arranged on the second oxide layer.In this double SOI structure, the first oxide layer and the first semiconductor layer constitute the first SOI, arranged in a lower portion of the structure, while the second oxide layer and the second semiconductor layer constitute the second SOI, arranged in an upper portion of the structure.
[0007] A known method for fabricating an SOI structure is the so-called Smart Cut™ method. The Smart Cut™ method comprises implanting atomic species, such as hydrogen (H) and / or helium (He), to create a weakened zone within a donor substrate, bonding the donor substrate to the recipient substrate via an electrically insulating layer and then detaching the donor substrate at the weakened zone so as to transfer a thin layer of the donor substrate to the recipient substrate. The donor substrate and the recipient substrate are preferably in the form of 300 mm diameter wafers of a semiconductor material. The electrically insulating layer can be formed on the donor substrate or the recipient substrate.
[0008] One proposed solution for obtaining a double SOI is to implement two successive Smart Cut™ processes. In the second Smart Cut™ process, the SOI obtained following the first Smart Cut™ process is used as a second recipient substrate onto which a second donor substrate is bonded via a second electrically insulating layer.
[0009] The bonding efficiency during the second Smart Cut™ process is conditioned by the quality of the surface of the first SOI serving as the receiving substrate. In particular, it depends on the roughness and defectivity of said surface after detachment from the first donor substrate along the weakening zone during the first Smart Cut™ process. Indeed, during bonding during the second Smart Cut™ process, defects and other surface irregularities induce the formation of holes between the receiving substrate and the second donor substrate within the final double SOI. Said holes most often impair the electrical performance of the structure and the mechanical strength of the assembly.
[0010] Surface treatments can be implemented to reduce the roughness and defectivity of the surface of the first SOI following detachment from the first donor substrate.
[0011] Commonly used surface treatments include heat treatments such as rapid thermal annealing or furnace annealing. Chemical-mechanical polishing can also be used. Finally, chemical treatments can be applied that sequentially induce oxidation and then deoxidation of the surface of interest.
[0012] However, the application of these techniques does not make it possible to achieve a surface quality sufficient to allow good quality bonding of a second donor substrate on said surface during a new layer transfer step. BRIEF DESCRIPTION OF THE INVENTION
[0013] An aim of the invention is to propose a method for manufacturing a double semiconductor-on-insulator type structure which guarantees good bonding of the donor substrate of the second semiconductor layer to a receiving substrate resulting from a first Smart Cut™ process.
[0014] To this end, the invention proposes a method for manufacturing a double semiconductor-on-insulator type structure comprising the following steps:
[0015] - supply of a first donor substrate and a support substrate,
[0016] - formation of a weakening zone in said first donor substrate so as to delimit a first semiconductor layer to be transferred,
[0017] - bonding the first donor substrate to the support substrate, a first electrically insulating layer being at the interface between the support substrate and the first donor substrate, and detaching the first donor substrate at the weakening zone, so as to obtain a semiconductor-on-insulator type structure comprising, from the rear face to the front face, the support substrate, the first electrically insulating layer and the first transferred semiconductor layer,
[0018] - treatment of the free surface of the first transferred semiconductor layer,
[0019] - supply of a second donor substrate for a second semiconductor layer to be transferred,
[0020] - transfer of said second semiconductor layer onto the front face of the semiconductor-on-insulator type structure, a second electrically insulating layer being at the interface between the first transferred semiconductor layer and the second donor substrate, wherein the treatment of the surface of the first transferred semiconductor layer comprises the following successive steps:
[0021] E1: rapid thermal annealing,
[0022] E2: a sequence including thermal oxidation followed by deoxidation,
[0023] E3: a smoothing heat treatment at a temperature above 1000°C in a non-oxidizing atmosphere,
[0024] E4: chemical-mechanical polishing.
[0025] The free surface of the first semiconductor layer results from the detachment of the first donor substrate along the weakened zone. The treatment process of said surface is optimized to reduce its roughness and defectivity. Said process also makes it possible to reduce the width of the crown on the outer edge of the second receiving substrate. The combined reduction of the defectivity, roughness, width of the crown and irregularity of the crown (a phenomenon known as the "jagged edge" in English) on the outer edge of the plates limits the number of holes formed during the bonding of the donor substrate of the second semiconductor layer.
[0026] According to other optional features of the invention taken alone or in combination when technically possible:
[0027] - step E3 of smoothing heat treatment is a long-term thermal annealing carried out at a temperature between 1050°C and 1250°C for a few minutes to a few hours under an atmosphere of pure or mixed Argon or Hydrogen;
[0028] - heat treatment step E3 is rapid thermal annealing;
[0029] - step E3 of rapid thermal annealing is carried out at a temperature between 1100°C and 1250°C for a few seconds to around a hundred seconds, under an atmosphere comprising pure or mixed Argon or Hydrogen;
[0030] - step E1 of rapid thermal annealing is carried out at a temperature between 1100°C and 1250°C for a few seconds to around a hundred seconds, under an atmosphere comprising pure or mixed Argon or Hydrogen;
[0031] - the thermal oxidation operation of step E2 is carried out at a temperature between 800°C and 1100°C under an atmosphere comprising oxygen or water vapor for a few minutes to a few hours;
[0032] - the deoxidation operation of step E2 is carried out by exposing the surface to be treated to a hydrofluoric acid solution;
[0033] - the support substrate and each donor substrate is in the form of a 300 mm diameter plate;
[0034] - the weakening zone in the first donor substrate is formed by implantation of hydrogen atoms;
[0035] - the transfer of said second semiconductor layer comprises:
[0036] - the formation of a weakening zone in the second donor substrate so as to delimit a second semiconductor layer to be transferred,
[0037] - bonding the second donor substrate to the front face of the semiconductor-on-insulator type structure, a second electrically insulating layer being at the interface between the front face of the semiconductor-on-insulator type structure and the first donor substrate,
[0038] - detaching the second donor substrate at the weakening zone, so as to obtain a double semiconductor-on-insulator type structure comprising, from the rear face to the front face, the support substrate, the first electrically insulating layer, the first transferred semiconductor layer, the second electrically insulating layer and the second transferred semiconductor layer;
[0039] - the weakening zone in the second donor substrate is formed by implantation of hydrogen atoms; - the second electrically insulating layer is formed by oxidation of the front face of the transferred first semiconductor layer, so that, during the transfer of the second semiconductor layer, said first electrically insulating layer is intercalated between the first semiconductor layer and the second semiconductor layer, said additional oxidation step being implemented after the treatment of the free surface of the first semiconductor layer;
[0040] - the second electrically insulating layer is formed by oxidation of a portion of the second donor substrate, so that, upon transfer of the second semiconductor layer, said first electrically insulating layer is also transferred and is intercalated between the first semiconductor layer and said second semiconductor layer;
[0041] - the first electrically insulating layer is formed by oxidation of the front face of the support substrate prior to bonding the first donor substrate to the support substrate so that said first electrically insulating layer is inserted between the support substrate and the first transferred semiconductor layer;
[0042] - the first electrically insulating layer is formed by oxidation of a portion of the first donor substrate prior to bonding said first donor substrate to the support substrate by its oxidized face so that said first electrically insulating layer is inserted between the support substrate and the first transferred semiconductor layer.
[0043] BRIEF DESCRIPTION OF THE FIGURES
[0044] Other characteristics and advantages of the invention will emerge from the detailed description which follows, with reference to the appended drawings, in which:
[0045] - figure 1 represents a sectional view of the intermediate structure of the semiconductor on insulator type obtained following the first layer transfer,
[0046] - figure 2 represents a sectional view of a first layer transfer by a first donor substrate on the front face of the support substrate, the first electrically insulating layer being formed on the surface of the first donor substrate,
[0047] - figure 3 represents a sectional view of a first layer transfer by a first donor substrate on the front face of the support substrate, the first electrically insulating layer being formed on the surface of the support substrate,
[0048] - figure 4 is a diagram representing the sequence of processing steps according to the method of the invention,
[0049] - figure 5 represents the final structure of the double semiconductor on insulator type obtained following the second layer transfer,
[0050] - Figure 6 represents a sectional view of a second transfer of a monocrystalline semiconductor layer by a second donor substrate, the second electrically insulating layer being formed on the second donor substrate, - Figure 7 represents a sectional view of a second transfer of a monocrystalline semiconductor layer by a second donor substrate, the second electrically insulating layer being formed on the structure of Figure 2.
[0051] For readability reasons, the drawings are not necessarily drawn to scale.
[0052] DETAILED DESCRIPTION OF EMBODIMENTS
[0053] A double semiconductor-on-insulator substrate type structure comprises, from the rear face to the front face, a support substrate, a first buried oxide layer corresponding to a first electrically insulating layer, a first monocrystalline semiconductor layer, a second buried oxide layer corresponding to a second electrically insulating layer and a second monocrystalline semiconductor layer.
[0054] The first electrically insulating layer and the first monocrystalline semiconductor layer together form a first semiconductor-on-insulator structure called the lower SOI structure. The second electrically insulating layer and the second monocrystalline semiconductor layer together form a second semiconductor-on-insulator structure called the upper SOI structure.
[0055] The invention relates to a method for preparing a double semiconductor-on-insulator type structure comprising in particular:
[0056] - the preparation of the lower SOI structure by a first transfer of a first monocrystalline semiconductor layer using a SmartCut™ process,
[0057] - an intermediate surface treatment process,
[0058] - preparation of the upper SOI structure by a second transfer of a monocrystalline semiconductor layer.
[0059] The invention relates more particularly to the intermediate surface treatment method implemented following the SmartCut™ method for transferring the first monocrystalline semiconductor layer, the SmartCut™ method and other layer transfer methods being known elsewhere.
[0060] The surface treatment method of the invention has been optimized so as to minimize the roughness and defectivity of a surface formed following the implementation of said first SmartCut™ method so as to improve the quality of the bonding during the second layer transfer. In the following, roughness is understood to mean the maximum peak-to-valley amplitude measured by atomic force microscopy (AFM) on surface profiles between 1x1 pm 2 and 30x30 pm 2 .
[0061] As for defectivity, it is defined as the number of particles deposited on the free surface of the plate, and / or the number of structural defects such as holes or scratches present on the surface of the plate. These defects are of various sizes, for example between 60 nm and several microns. The defects can come from impurities created by the local detachment of the irregular edge of the crown ("jagged edge") or from contamination. Defectivity is measured using equipment using a light scattering technique such as the SP2 equipment from KLA Tencor.
[0062] The method also aims to enlarge the effective bonding area of the second transferred layer so as to reduce the width of the peripheral crown of the second SOI substrate.
[0063] The peripheral region of an SOI substrate where the transfer of the monocrystalline semiconductor layer has not taken place is called a corona. This crown is due to the fact that substrates typically have a peripheral chamfer a few millimeters wide, at which bonding of the donor substrate to the recipient substrate cannot be ensured. During the Smart Cut™ process, the monocrystalline semiconductor layer of the donor substrate is therefore only transferred to the recipient substrate in the central area where bonding has taken place. In some cases, however, isolated areas of the donor substrate may be transferred into the crown. The crown then does not have a perfectly circular shape, but an irregular jagged edge.
[0064] In the case of a double SOI structure, the irregular corona problem therefore occurs twice: during the fabrication of the first SOI substrate and then during the fabrication of the second SOI substrate, and therefore has a significant impact on the useful width of the upper semiconductor layer. Thus, if the width of the corona at the end of the first layer transfer is typically between 0.7 mm and 1.5 mm, the width of the "double corona" at the end of the second layer transfer is between 3 mm and 4 mm.
[0065] The surface treatment method according to the invention is characterized in that it comprises four successive steps, each step being a surface treatment known elsewhere making it possible to act on one or other of the parameters defined below.
[0066] However, each of its steps taken individually does not allow to achieve the expected performances for an efficient bonding, of good quality so that it is free from defects such as holes at the bonding interface and excessively wide crowns, in the context of the fabrication of a double SOI structure.
[0067] In the following, the various steps of the intermediate surface treatment process and their impact on the quality of the treated surface are described in detail. For information purposes, embodiments for the preparation of the lower and upper SOI structures are also described. of the lower SOI structure
[0068] First, the first semiconductor-on-insulator or lower SOI structure is prepared by a first transfer of a single-crystal semiconductor layer. Said structure is shown in Figure 1. Said first transfer is carried out by a Smart Cut™ process which comprises the following steps:
[0069] - providing a first donor substrate of a first monocrystalline semiconductor layer 2b and a support substrate 1,
[0070] - formation of a weakening zone in said first donor substrate so as to delimit the first semiconductor layer 2b to be transferred,
[0071] - bonding the first donor substrate to the support substrate 1, a first electrically insulating layer 2a being at the interface between the support substrate 1 and the first donor substrate, and
[0072] - detachment of the first donor substrate at the level of the weakening zone.
[0073] The support substrate 1 is in the form of a circular plate of a semiconductor material, preferably a plate with a diameter of 300 mm. The support substrate is, for example, a silicon plate. The support substrate is preferably an ultra-flat silicon plate, which has a narrower and steeper chamfer than on conventional plates.
[0074] The width of the wafer edge chamfer can be evaluated using the ZDD148 characteristic, which corresponds to the second derivative of the wafer edge profile at 2 mm from the wafer edge, in other words the inverse of the radius of curvature of this wafer edge. Typically, the ZDD148 of 300 mm diameter silicon wafers is between -20 and -200 nm / mm 2. The ZDD148 measurement is made using WAFERSIGHT equipment from KLA TENCOR. A so-called ultra-flat silicon wafer has a ZDD148 characteristic between 0 and -20nm / mm 2 The use of an ultra-flat silicon plate makes it possible to reduce the width of the peripheral crown.
[0075] The first donor substrate is a single-crystal semiconductor substrate, for example a single-crystal silicon substrate. The first donor substrate is in the form of a plate which is generally the same diameter as the support substrate.
[0076] The embrittlement zone can be created by co-implantation of helium atoms and hydrogen atoms in the first donor substrate of the first semiconductor layer. Helium and hydrogen are implanted with energies between 10 keV and 100 keV and the implanted doses are between 10 15 atoms per cm 2 and 10 17atoms per cm 2 . Alternatively, the weakening zone is preferentially created by implantation of hydrogen atoms. The co-implantation of hydrogen and helium atoms has the advantage of allowing a more straightforward fracture of the donor substrate along the weakening zone, which results in a lower roughness of the transferred semiconductor layer, of the order of 50.10 -10 m RMS or 60. 10 -10 m RMS (either 50 or 60 Â RMS) when measured by AFM 30x30pm 2 , but also by the appearance of the "jagged edge" phenomenon. This phenomenon is all the more important as the transferred semiconductor layer is thick. The implantation of hydrogen atoms alone has the advantage of avoiding the "jagged edge" phenomenon but on the other hand provides greater roughness of the transferred semiconductor layer. The roughness measured by AFM 30x30pm 2 is in this case of the order of 80. 10 -10m RMS (i.e. 80 Å RMS). However, the treatment described below makes it possible to obtain a final surface of the first transferred semiconductor layer sufficiently smooth to allow the formation of the second SOI substrate. Therefore, in view of the advantage presented in terms of limiting the "jagged edge", the implantation of hydrogen atoms alone will be preferred to the co-implantation of hydrogen and helium atoms.
[0077] Detachment along the weakening zone can be triggered by mechanical action, thermal energy input, possibly in combination, or any other suitable means.
[0078] According to an embodiment shown in Figure 2, the first electrically insulating layer 2a is formed on the first donor substrate prior to the formation of the weakening zone within the first donor substrate by implantation of atoms through the first electrically insulating layer 2a. The bonding of the first donor substrate to the support substrate 1 is carried out by the electrically insulating face of said first donor substrate so that said first electrically insulating layer 2a is transferred at the same time as the first semiconductor layer 2b and is intercalated between the support substrate 1 and the transferred first semiconductor layer 2b. The first electrically insulating layer 2a is formed for example by oxidation of the front face of the first donor substrate, so that if the first donor substrate is a silicon substrate, the first electrically insulating layer 2a is a silicon oxide layer.
[0079] According to an alternative embodiment shown in Figure 3, the first electrically insulating layer 2a is formed on the front face of the support substrate 1 prior to bonding the first donor substrate to said support substrate so that said first electrically insulating layer 2a is interposed between the support substrate 1 and the first transferred semiconductor layer 2b. The first electrically insulating layer 2a is formed for example by oxidation of the front face of the support substrate 1, so that if the support substrate 1 is a silicon substrate, the first electrically insulating layer 2a is a silicon oxide layer.
[0080] The front face of the lower SOI structure formed during detachment of the first donor substrate along the weakening zone has a roughness and a defectivity which are linked to the quality of implantation of the atomic species within the first donor substrate during the implementation of the first Smart Cut™ process. As mentioned above, said roughness can be relatively significant, of the order of 50. 10 -10 m RMS at 80.10 -10 m RMS (i.e. from 50 Â RMS to 80Â RMS) depending on the species implanted.
[0081] During the second layer transfer for the preparation of the upper SOI structure, the particle defectivity and surface roughness can lead, at the time of bonding of the second donor substrate, to the formation of holes or defects. For example, a roughness greater than 5. 10 -10 m RMS (i.e. 5Â RMS) generates a hole density of the order of several holes per cm 2 .
[0082] Holes can cause devices manufactured from the SOI substrate containing the holes to malfunction. Furthermore, the holes are distributed unevenly across the substrate. This unevenness of defects leads to high variability in behavior between devices manufactured from the same substrate.
[0083] Thus, devices produced on portions of the substrate comprising a high hole density will not be operational or they will have significant variability in behavior, which is not acceptable for a manufacturer of microelectronic devices, in particular photonic devices. In addition, the plate of the support substrate 1 and the plate of the first donor substrate do not have an edge perpendicular to the surface but have a chamfer or "Edge Roll Off". The bonding of the first donor substrate to the support substrate is therefore not carried out over the entire surface of the substrates up to their edge but only up to the chamfer, so that the transferred part of the donor substrate does not extend over the entire surface of the support substrate. The peripheral crown is delimited on the outer side by the edge of the receiving substrate and on the inner side by the edge of the transferred layer.For a 300 mm plate, the peripheral crown CP typically has a width between 0.7 mm and 1.5 mm relative to the edge of the plate.
[0084] In reality, as mentioned above, the crown often has an irregular shape (the "jagged edge") due to a transitional zone where the bonding has not taken place correctly. The transitional zone represents a potential source of defectivity: parts of said zone can indeed detach and be deposited on the surface of the SOI. During the second layer transfer for the preparation of the upper SOI structure, such a surface condition can also lead to the formation of a significant number of holes or defects and to a width of the double crown much greater than that of the crown resulting from the first layer transfer, of the order of 3 to 4 mm. Such widths are not acceptable, especially for a photonics application which requires the ability to manufacture chips up to 3 mm from the edge of the silicon wafers.
[0085] In the following, the process for achieving the expected performance is described.
[0086] Surface treatment prior to the second layer transfer
[0087] The front face of the first semiconductor layer is formed upon detachment of the first donor substrate along the weakened zone following the Smart Cut™ process. The invention relates to a method for treating said surface. The treatment method according to the invention aims not only to reduce the roughness and defectivity of said surface, but also to reduce the width of the peripheral crown, thereby improving the bonding quality of the second donor substrate.
[0088] The treatment of the free surface of the first semiconductor layer 2b, and / or of the second semiconductor layer according to the invention involves the successive implementation of the following steps shown in the diagram of Figure 4:
[0089] - (E1) rapid thermal annealing,
[0090] - (E2) an oxidation / deoxidation sequence, - (E3) a long-term thermal annealing, known to those skilled in the art under its English name “batch anneal”,
[0091] - (E4) chemical-mechanical polishing.
[0092] Alternatively, the long-term thermal annealing step (E3) can be replaced by a rapid thermal annealing step (E3').
[0093] Rapid thermal annealing means annealing for a period of a few seconds or a few tens of seconds, in a controlled atmosphere. Such annealing is commonly referred to as RTA annealing for Rapid Thermal Annealing. Rapid thermal annealing (RTA) is carried out at a temperature between 1100 °C and 1250 °C for 1 s to 90 s. Rapid thermal annealing (RTA) is carried out in an atmosphere comprising a mixture of argon and hydrogen or in an atmosphere of pure argon.
[0094] Rapid thermal annealing strengthens the bonding interface between the support substrate and the transferred semiconductor layer. It also smooths the surface of the transferred semiconductor layer, causing a reorganization of the atoms present on the surface, and also restores the crystal lattice that may have been disturbed by the implantation. However, it is not sufficient to achieve the level of roughness required to allow the bonding of the second donor substrate and then the transfer of a semiconductor layer from the second donor substrate onto the first SOI.
[0095] The following oxidation / deoxidation step (E2) should be understood as a sequence comprising the succession of the following operations:
[0096] - a thermal oxidation operation (E2a),
[0097] - a chemical deoxidation operation (E2b).
[0098] The oxidation operation (E2a) can for example be carried out by heating the structure to a temperature between 800°C and 1100°C for a few minutes to a few hours in an oxidizing atmosphere, for example water vapor (wet oxidation) or oxygen alone (dry oxidation). During this oxidation, the two faces of the first SOI oxidize. The deoxidation operation (E2b) can for example be carried out by exposing the front face of the structure to a hydrofluoric acid (HF) solution for a few seconds to a few minutes to remove the oxide layer formed on the front face, without removing the oxide layer present on the back face of the structure.
[0099] This oxidation / deoxidation step consumes, by oxidation and then elimination, a surface portion of silicon. The consumption of surface silicon not only makes it possible to adjust the thickness of the semiconductor layer but also to eliminate defects appearing following the layer transfer by Smart Cut™, on the surface of the transferred layer. Long-term thermal annealing, called “batch anneal” in English, corresponds to a thermal annealing lasting from a few minutes to a few hours, generally more than 15 min, advantageously carried out in a controlled atmosphere oven. The use of the oven makes it possible to treat a plurality of substrates at the same time.
[0100] Thermal annealing (E3) is carried out at a temperature between 1,000 and 1250°C for a few minutes to a few hours in an inert atmosphere, for example in an atmosphere of pure or mixed argon or hydrogen.
[0101] Thermal annealing (E3) smooths the surface of the transferred semiconductor layer and therefore reduces its roughness.
[0102] The surface treatment method according to the invention finally comprises a final step (E4) of chemical-mechanical polishing.
[0103] During chemical-mechanical polishing, or CMP, the surface to be polished is modified using a chemical agent, for example a suspension of colloidal silica particles in a liquid base, and the modified surface is removed by mechanical abrasion. The rotation speed and pressure used during step (E4) of CMP are optimized so as to uniformly remove material from the surface of the transferred semiconductor layer or the second electrically insulating layer, without degrading the condition of said surface, in particular without increasing its roughness.
[0104] This chemical-mechanical polishing allows the removal of surface particles. Furthermore, since this polishing is carried out up to the edge of the substrate, it also allows the thickness irregularities of the first SOI to be gradually reduced up to the edge of the wafer at the level of the crown of the first SOI, which allows a second bonding closer to the edge of the wafer. This reduces the width of the crown resulting from the second transfer by Smart Cut ™.
[0105] Alternatively, rapid thermal annealing (E3') is carried out at a temperature between 1100 °C and 1250 <0 for a few seconds to a hundred seconds, for example under an atmosphere comprising argon or hydrogen, alone or in a mixture.
[0106] Preparation of the upper SOI structure Referring to Figure 5, the second semiconductor-on-insulator structure or upper SOI structure is formed on the lower SOI structure by a second transfer of a second monocrystalline semiconductor layer 3b from a second donor substrate, onto the front face of the first semiconductor-on-insulator structure, a second electrically insulating layer 3a being at the interface between the transferred first semiconductor layer and the second donor substrate.
[0107] The second donor substrate is a single-crystal semiconductor substrate, for example a single-crystal silicon substrate. The second donor substrate is in the form of a circular plate generally of the same diameter as the support substrate.
[0108] According to one embodiment, the second layer transfer is carried out according to a second Smart Cut™ process comprising:
[0109] - the formation of a weakening zone in the second donor substrate so as to delimit a second semiconductor layer to be transferred 3b,
[0110] - bonding the second donor substrate to the front face of the semiconductor-on-insulator type structure, a second electrically insulating layer 3a being at the interface between the front face of the semiconductor-on-insulator type structure and the first donor substrate,
[0111] - detachment of the second donor substrate at the weakening zone, so as to obtain a double semiconductor on insulator type structure as shown in Figure 5.
[0112] As with the first donor substrate, the embrittlement zone within the second donor substrate can be created by co-implantation of helium atoms and hydrogen atoms into the second donor substrate of the second semiconductor layer. Alternatively, the embrittlement zone is created by implantation of hydrogen atoms.
[0113] Alternatively to the Smart Cut™ process, the second layer transfer can be achieved by thinning the second donor substrate on its face opposite the face bonded to the second electrically insulating layer until the desired thickness is obtained for the second semiconductor layer 3b.
[0114] According to an embodiment shown in Figure 6, the second electrically insulating layer 3a is formed on the second donor substrate, so that, upon transfer of the second semiconductor layer 3b, said second electrically insulating layer 3a is also transferred and is intercalated between the first semiconductor layer 2b and said second semiconductor layer 3b. The second electrically insulating layer 3a is prepared for example by oxidation of the second donor substrate, so that if the second donor substrate is a silicon substrate, the second electrically insulating layer 3a is a silicon oxide layer.
[0115] In the embodiment where the second layer transfer is carried out according to a second Smart Cut™ process, the second electrically insulating layer 3a is preferentially formed on the second donor substrate prior to the formation of the weakening zone within the second donor substrate by implantation of atoms through the second electrically insulating layer 3a.
[0116] According to an alternative embodiment shown in Figure 7, the second electrically insulating layer 3a is formed on the first semiconductor layer 2b so that, upon transfer of the second semiconductor layer 3b, said second electrically insulating layer 3a is interposed between the first semiconductor layer 2b and the second semiconductor layer 3b. The second electrically insulating layer 3a is for example prepared by oxidation of the front face of the transferred first semiconductor layer 2b, so that if the first donor substrate is a silicon substrate, the second electrically insulating layer 3a is a silicon oxide layer. Said additional step of forming the second electrically insulating layer 3a is implemented after the treatment of the free surface of the first semiconductor layer 2b.Alternatively, steps (E1), (E2) and (E3) of said method are implemented on the free surface of the first transferred semiconductor layer 2b before the step of forming the second electrically insulating layer 3a and step (E4) can be implemented before and after said step of forming the second electrically insulating layer 3a, respectively on the surface of the first transferred semiconductor layer 2b and on the surface of the second electrically insulating layer 3a.
[0117] It is advantageous to carry out one or more cleanings of the free surface of the second electrically insulating layer 3a prior to the second transfer of a second monocrystalline semiconductor layer 3b.
[0118] By way of example, the implementation of the surface treatment method according to the invention, which notably combines thermal smoothing and a CMP step, coupled with the use of an “ultra-flat” support substrate, makes it possible to obtain an SOI structure which has a very low or even zero quantity of holes and a double crown width of less than 3 mm. Optionally, it is also possible to carry out a treatment of the free surface of the second semiconductor layer 3b in order to reduce the defects in this layer and smooth the surface to obtain the properties required for subsequent applications of said layer (manufacture of electronic components, epitaxy, etc.). These treatments are known to those skilled in the art and include, for example, rapid thermal annealing.
Claims
DEMANDS 1. A process for manufacturing a double semiconductor-on-insulator structure comprising the following steps: - provision of a first donor substrate and a support substrate (1), - formation of a weakening zone in said first donor substrate so as to delimit a first semiconductor layer to be transferred (2b), - bonding of the first donor substrate to the support substrate (1), a first electrically insulating layer (2a) being at the interface between the support substrate (1) and the first donor substrate, and detachment of the first donor substrate at the level of the embrittlement zone, so as to obtain a semiconductor-on-insulator type structure comprising, from the back face to the front face, the support substrate (1), the first electrically insulating layer (2a) and the first transferred semiconductor layer (2b), - treatment of the free surface of the first transferred semiconductor layer (2b), - provision of a second donor substrate for a second semiconductor layer to be transferred (3b), - transfer of said second semiconductor layer (3b) onto the front face of the semiconductor-on-insulator type structure, a second electrically insulating layer (3a) being at the interface between the first transferred semiconductor layer (2b) and the second donor substrate, wherein the surface treatment of the first transferred semiconductor layer (2b) comprises the following successive steps: (E1) a rapid thermal annealing, (E2) a sequence including thermal oxidation followed by deoxidation, (E3) a smoothing heat treatment at a temperature above 1000 °C in a non-oxidizing atmosphere, (E4) a mechano-chemical polishing.
2. A process according to claim 1, characterized in that the smoothing heat treatment step (E3) is a long-duration thermal annealing carried out at a temperature between 1050 °C and 1250 °C for a few minutes to a few hours under an atmosphere of pure or mixed Argon or Hydrogen.
3. A process according to claim 1, characterized in that the heat treatment step (E3) is a rapid thermal annealing.
4. A method according to the preceding claim, characterized in that the rapid thermal annealing step (E3) is carried out at a temperature between 1100 °C and 1250 °C for a few seconds to a hundred seconds, under an atmosphere containing pure or mixed Argon or Hydrogen.
5. A process according to any one of claims 1 to 4 characterized in that the step (E1) of rapid thermal annealing is carried out at a temperature between 1100 °C and 1250 °C for a few seconds to a hundred seconds, under an atmosphere comprising Argon or pure or mixed Hydrogen.
6. A process according to any one of claims 1 to 5 characterized in that the thermal oxidation operation of step (E2) is carried out at a temperature between 800 °C and 1100 °C under an atmosphere comprising oxygen or water vapor for a few minutes to a few hours.
7. A process according to any one of claims 1 to 6 characterized in that the deoxidation operation of step (E2) is carried out by exposing the surface to be treated to a hydrofluoric acid solution.
8. A method according to any one of claims 1 to 7 characterized in that the support substrate (1) and each donor substrate is in the form of a plate with a diameter of 300 mm.
9. A method according to any one of claims 1 to 8 characterized in that the embrittlement zone in the first donor substrate is formed by implantation of hydrogen atoms.
10. A method according to any one of claims 1 to 9, characterized in that the transfer of said second semiconductor layer (3b) comprises: - the formation of a weakened zone in the second donor substrate so as to delimit a second semiconductor layer to be transferred (3b), - the bonding of the second donor substrate to the front face of the semiconductor-on-insulator structure, a second electrically insulating layer (3a) being at the interface between the front face of the semiconductor-on-insulator structure and the first donor substrate, - the detachment of the second donor substrate at the level of the embrittlement zone, so as to obtain a double semiconductor-on-insulator type structure comprising, from the back face to the front face, the support substrate (1), the first electrically insulating layer (2a), the first transferred semiconductor layer (2b), the second electrically insulating layer (3a) and the second transferred semiconductor layer (3b). 1 1. Method according to claim 10, characterized in that the embrittlement zone in the second donor substrate is formed by implantation of hydrogen atoms.
12. A method according to any one of claims 1 to 11, characterized in that the second electrically insulating layer (3a) is formed by oxidation of the front face of the first transferred semiconductor layer (2b), so that, during the transfer of the second semiconductor layer (3b), said first electrically insulating layer (3a) is intercalated between the first semiconductor layer (2b) and the second semiconductor layer (3b), said additional oxidation step being carried out after the treatment of the free surface of the first semiconductor layer (2b).
13. A method according to any one of claims 1 to 11, characterized in that the second electrically insulating layer (3a) is formed by oxidation of a part of the second donor substrate, so that, during the transfer of the second semiconducting layer (3b), said first electrically insulating layer (3a) is also transferred and is intercalated between the first semiconducting layer (2b) and said second semiconducting layer (3b).
14. A method according to any one of claims 1 to 13, characterized in that the first electrically insulating layer (2a) is formed by oxidation of the front face of the support substrate (1) prior to the bonding of the first donor substrate to the support substrate so that said first electrically insulating layer (2a) is intercalated between the support substrate (1) and the first transferred semiconducting layer (2a).
15. A method according to any one of claims 1 to 13 characterized in that the first electrically insulating layer (2a) is formed by oxidation of a part of the first donor substrate prior to the bonding of said first donor substrate to the support substrate (1) by its oxidized face so that said first electrically insulating layer (2a) is intercalated between the support substrate (1) and the first transferred semiconducting layer (2b).