Method for manufacturing polycrystalline silicon carbide suitable for manufacturing substrates for integrated circuits, and silicon carbide obtained in this way

Abstract

The invention relates to a method for manufacturing a plate made of polycrystalline SiC, doped by chemical vapour deposition on a graphite surface, wherein a gas mixture is introduced into a heated chamber so as to create a gas phase comprising: - at least one gaseous precursor of silicon and / or carbon; - at least one dopant gas comprising at least one nitrogen atom; and - a carrier gas, the gas mixture decomposing on the graphite surface to form a layer of polycrystalline SiC, and the method being characterised in that the temperature in the reactor is between 1450 K and 1650 K and the total partial pressure of the gaseous precursors is less than 350 mbar. The plate is characterised in that: (i) the texture coefficient C422 thereof is less than 30%, and (ii.a) the texture coefficient C220 thereof is greater than 60%, or (ii.b) the sum of the texture coefficients C111+C222+C511 is greater than 70%.

Description

[0001] METHOD FOR PRODUCING POLYCRYSTALLINE SILICON CARBIDE USABLE FOR PRODUCING INTEGRATED CIRCUIT SUBSTRATES, AND SILICON CARBIDE THUS OBTAINED

[0002] Technical field of the invention

[0003] The invention relates to the field of materials science, and more particularly to the field of materials that can be used to manufacture substrates for integrated circuits, and to methods for producing these materials. It relates more specifically to polycrystalline silicon carbide. This material, like all materials for microelectronic substrates, is implemented in the form of thin wafers (for which those skilled in the art often use the English term "wafer"), typically circular. SiC is particularly suitable for the manufacture of substrates for use in power electronic components. SiC wafers must meet very strict specifications with regard to their flatness, the homogeneity of their properties, and the absence of defects.

[0004] The present invention presents a new type of polycrystalline SiC wafers usable for the manufacture of integrated circuit substrates; these wafers have particular crystallographic characteristics.

[0005] Since integrated circuits are generally deposited on surfaces of a single-crystal semiconductor, in the case of a polycrystalline silicon carbide wafer, the electronically active surface (i.e. the surface on which the integrated circuits are deposited) must be specially prepared by transferring a single-crystal SiC layer. This method of preparation by transferring a single-crystal SiC layer is not part of the present invention.

[0006] The present invention also relates to a new method for manufacturing such a polycrystalline silicon carbide wafer capable of receiving, in a subsequent manufacturing step, the transfer of a layer of monocrystalline SiC. State of the art

[0007] Since the beginning of microelectronics, the vast majority of microelectronic circuits have been manufactured on a single-crystal silicon substrate. For some specific applications, semiconductor silicon is not the ideal substrate, but it is used for lack of a better one. Silicon carbide (abbreviated SiC), on the other hand, is a remarkable semiconductor material. It has a wide band gap, a high breakdown field, high charge carrier mobility at saturation, and high thermal conductivity. This combination of exceptional physical properties gives it excellent voltage resistance, as well as the passage of very high current densities, even at high temperatures. The article "Power Components in SiC - Technology" by D. Tournier, published in 2007 as part D-3120 in the Engineering Techniques collection, provides an introduction to the subject.

[0008] SiC is therefore a material perfectly suited for the manufacture of power components required for the efficient conversion of electrical energy in applications such as electrical power distribution, renewable energies, and electric vehicles. The use of SiC makes it possible to advantageously replace silicon-based transistors such as IGBTs with power components such as MOSFET transistors with voltage resistance in the kilovolt range and much lower switching energy losses. In these power components, voltage resistance and temperature resistance can become limiting factors when designing electronic components and the electronic boards on which these components are installed.The recent development of electric vehicles would greatly benefit from the use of such SiC power components to improve energy efficiency when converting direct current from batteries into alternating current usable by the motor. The cost and availability of these components nevertheless remain obstacles to the adoption of this technology, and for this reason silicon is still widely used as a substrate in specific applications for which SiC would offer technical advantages.

[0009] According to the state of the art, silicon carbide substrates intended to receive the deposition of microelectronic circuits are generally circular wafers. They are manufactured industrially using the PVT (Physical Vapor Transfer) process, which consists of sublimating a SiC powder at high temperature (> 2200°C) and condensing the vapors on a seed to obtain an ingot or "ball" of monocrystalline SiC. Monocrystalline SiC substrates (wafers) are then sliced ​​from this monocrystalline ingot. A layer of crystalline SiC is deposited by epitaxy on one of the faces of this substrate, in order to obtain a crystal with the fewest possible defects. After epitaxy, these wafers will be ready to accommodate the manufacture of electronic components.

[0010] Improvements in the industrial PVT process over the last 30 years have significantly reduced the density of the main crystalline defects in these substrates, such as dislocations and micro-pipes, which had a significant impact on the reliability of SiC components. In addition, it has made it possible to increase the size of the substrates (wafers) up to a diameter of 150 mm as standard, soon to increase to 200 mm. Despite industrial efforts, the PVT process remains complex to master, not very productive and consumes a significant amount of energy because it requires maintaining an oven at very high temperature for around 100 hours.

[0011] Additionally, for power components, a resistor R onThe lowest possible resistivity in on-mode is a determining criterion for improving the energy efficiency of the system by limiting Joule heating during current flow. In these applications, monocrystalline SiC is doped both to enable the fabrication of the component's P / N junctions and to reduce its resistivity in contact with the drain. The addition of nitrogen makes it possible to dope the substrate during crystal growth. As standard, "n" doped wafers have a resistivity of around 20 mOhm.cm. It becomes very difficult to reduce the resistivity below this threshold without degrading the quality of the crystal, because excessive doping creates stresses that promote additional dislocations in the crystal.

[0012] A new technology currently being developed would combine the use of a low-cost SiC substrate (wafer) with improved electrical performance and a thin layer of high-quality monocrystalline SiC in which the microelectronic component would be manufactured. The monocrystalline SiC layer is attached to the substrate by a molecular bonding process as described in WO 01 / 18873 (Commissariat à l'Energie Atomique), which also ensures minimal contact resistance between the substrate and the attached monocrystalline layer. Document EP 3 018696 A1 describes an embodiment of such a process, which results in a monocrystalline SiC layer attached to a polycrystalline SiC substrate (hereinafter referred to as "P-SiC" or "P-SiC Wafer"). These P-SiC substrates must meet strict requirements for electrical resistance, thermal conductivity and flatness.Today, there are prototype "Dummy wafers" on the market, sold by companies such as Ferrotec. These wafers, with a diameter of 150 mm and a thickness of 750 μm as standard, are used to balance a full load of monocrystalline SiC wafers in certain processes to improve their uniformity.

[0013] According to the state of the art, P-SiC wafers are obtained by depositing polycrystalline SiC by CVD on a cylindrical graphite substrate. After machining the SiC layer deposited on the periphery of the cylinder down to the graphite, two SiC discs can be separated from the two faces of the cylinder by air oxidation of the graphite. This is described in patent applications JP 1994 340994 and JP 1997296361.

[0014] However, it quickly became apparent that the resulting wafers exhibited unacceptable deformation (Bow and Warp) for the intended application. The Bow and Warp parameters represent the flatness of a wafer intended for the semiconductor industry and are known to those skilled in the art of semiconductor substrates for microelectronics (only the English words are used for these parameters, which we write here with a capital letter); they will be described in greater detail below and can be measured according to the SEMI MF1390 standard. The processes described in the two Japanese documents cited above find a solution to the problem, thanks to the repetition of several deposition steps of small thicknesses of less than 100 μm. Indeed, for a sufficiently thick deposit, the increase in the grain diameter generates an internal compressive stress. The conical grains repel each other as they grow.This physical mechanism is demonstrated by P. Chaudhari in the publication "Grain growth and Stress relief in thin films", published in Journal of Vacuum Science and Technology 9, 520 (1972), which is a basic document for any specialist in the deposition of layers from a vapor phase. The process described in JP 1994 340994 and JP 1997 296361 makes it possible to obtain thick layers of P-SiC of several hundred microns by limiting the increase in internal compressive stresses and therefore makes it possible to limit their deformations once detached from the graphite.

[0015] Japanese patent JP 3648 112 B2 describes a similar process that alternates the deposition of layers with tensile and compressive stresses, in order to cancel out the stress moment integrated over the entire thickness of the deposit. This mechanical moment is in fact the origin of the deformation observed when the P-SiC disc is removed from its graphite substrate.

[0016] It is important to note, however, that the processes described above are not favorable for achieving low resistivity and good thermal conductivity through the thickness of the wafer due to the multiple interfaces separating the layers in its thickness. Finding a single-layer solution to the problem would be more favorable.

[0017] US Patent 10,934,634 B2 describes the production of a P-SiC wafer with excellent flatness from a single layer of SiC deposited by CVD on a graphite substrate. A sufficiently thick deposit, typically 2 mm, has an upper part where the variation in grain diameter is stabilized. Since the compressive stress no longer changes in this part (as demonstrated in the cited publication by Chaudhari), it is then possible to extract by machining a slice with a thickness of 350 μm which has a near-zero stress gradient like the grain sizes in the thickness and therefore to integrate a near-zero mechanical moment over the thickness. The expected effect is a very low deformation of the wafer.However, the cost and energy expended by such a process is probably unfavorable, since approximately 1.65 mm of the 2 mm CVD-deposited layer must be removed by grinding and polishing to obtain the wafer at the desired thickness of 350 pm with the desired flatness.

[0018] To reduce the manufacturing costs of a doped P-SiC wafer, it would be optimal to grow by CVD at high speed a P-SiC layer of thickness as close as possible to the final thickness with a grain size stabilized very quickly after the start of the layer growth, to avoid any unnecessary extra thickness that would become necessary to reduce or eliminate the grain size gradient.

[0019] At the Transducers & Eurosensors 2007 conference, XA Fu et al. published a paper entitled "Nitrogen doped polycrystalline 3C-SiC films deposited by LPCVD for MEMS applications." In this paper, the authors studied the deposition of SiC for doping gas levels (NH3) varying from 2% to 12% in mole fraction of the silicon precursor (Dichlorosilane). To obtain a resistivity below 20 mohm.cm under these conditions, the dopant level must exceed 5%. A higher dopant level leads to an increase in the residual stress without increasing the stress gradient. In this study, the deposition is carried out at low temperature 900°C and low pressure favoring crystal growth exclusively along the (111) axis, but with an extremely slow deposition rate of 0.6 pm / h. Significant doping does not appear to modify under these conditions the crystalline orientation of the deposited thin layer, measured by X-ray diffraction (XRD) analysis.

[0020] In the 2014 publication by HKE Latha et al in the journal Mater. Res. Express 1 015902, the effects of high doping of 3C-SiC obtained by CVD are studied using methyltrichlorosilane (MTCS) as a silicon and carbon precursor, and NH3 as a doping agent. The deposition conditions are 1040°C at low pressure. The growth rate of the deposit reaches about 5 pm / h, much higher than the previous case, but still very insufficient to produce large thicknesses (several hundred microns) in an economically viable manner. An influence of the doping level on the crystal orientation and grain size is observed under these conditions. A high doping level is accompanied by a coarsening of the grain size and their crystal orientation axis is modified according to X-ray diffraction (XRD) analysis.For certain CVD conditions, particularly at higher temperatures, here 1040°C instead of 900°C as described in the publication by Fu et al. cited above, it seems that a high level of doping can have a very significant influence on the crystalline orientations of SiC deposits by CVD. Thus, the textures and grain sizes obtained can modify the stress distribution in these deposits.

[0021] Patent application WO 2021 / 060515 (Tokai Carbon) proposes a process for obtaining a P-SiC substrate with a thickness between 500 pm and 6 mm, at a high deposition temperature close to 1500°C. The deposition time is between 5 h and 15 h, i.e. deposition rates above 100 pm / h, particularly suitable for industrial production. The doping of the P-SiC is obtained by adding nitrogen to the mixture. To obtain a sufficiently flat substrate, the patent proposes a process that varies the SiC precursor concentration during deposition, in order to reduce the excessively steep grain size gradient in the deposit. This process is proposed for nitrogen mass concentrations between 200 ppm (2.8 x 10 19 atm / cm 3 ) and 1000 ppm (1.38 x 10 2 °atm / cm 3). Beyond 1000 ppm, it is noted that an excessive concentration of nitrogen in P-SiC would generate significant defects in the crystals and an undesired deformation of the substrate. Thus, this state-of-the-art document also shows that a high concentration of nitrogen dopant in the P-SiC material is potentially a limiting factor for obtaining good flatness, but it is desirable for obtaining low electrical resistivity.

[0022] These contradictory trends must be taken into account when attempting to manufacture a P-SiC raw substrate by CVD with low resistivity (e.g. < 10 mOhm.cm) and sufficient flatness to be able to grind a P-SiC wafer by removing as little material as possible. Regarding the flatness of the CVD raw substrate, it must be kept in mind that removing material by grinding from a surface as hard as that of SiC is a time-consuming and expensive process, and in addition, any thickness of material removed by grinding corresponds to material that is lost. Indeed, the manufacturing cost of the P-SiC wafer must be low enough to be used as a substrate combined with a thin layer of polycrystalline SiC in power electronics applications.

[0023] According to the state of the art industrial technology, the nominal thickness of the finished P-SiC wafer is 350 pm for a nominal diameter of 150 mm. A thicker raw product (raw blank) is manufactured from a CVD deposition process on a graphite substrate. For economic reasons, once detached from the graphite, the P-SiC blank must not exceed a thickness of 1 mm; typically 750 pm and preferably 600 pm are targeted, in order to obtain a reasonable CVD deposition time and to reduce the thickness to be removed by grinding and polishing, to a maximum of 650 pm, typically 400 pm, preferably 250 pm respectively.

[0024] The warp of a 350 μm thick wafer with a diameter of six inches must be less than 50 μm after grinding and polishing to comply with microelectronics standards. To achieve this objective, an intermediate blank must first be prepared by grinding from the raw blank detached from the graphite, which will then serve as a starting point to prepare, by fine grinding followed by polishing, the P-SiC wafer onto which a monocrystalline layer of SiC will then be transferred. The difference between the initial thickness of the raw blank and the deformation measured on said raw blank must not be less than the thickness of the intermediate blank. This means that the volume of the ground intermediate (cylindrical) blank must be included in the volume of the raw blank (see Figure 1).

[0025] In the present invention, the inventors sought to optimize the manufacture of a raw SiC substrate having a high N dopant rate typically greater than 5 x 10 19 atoms / cm 3 , preferably greater than 10 2 ° atoms / cm 3 , to typically achieve a material resistivity of less than 15 mOhm.cm and preferably less than 10 mOhm.cm. The thermal conductivity of the material should typically be greater than 200 W / mK, but a value greater than 250 W / m / K is preferred, despite a high N dopant content which can affect the thermal conductivity by generating additional crystal defects harmful to the propagation of phonons. We also seek a substrate which has excellent surface homogeneity of its grain size, and preferably a fine grain.

[0026] Objects of the invention

[0027] It results from the work carried out by the inventors of the present application that a massive plate of polycrystalline SiC (denoted here “P-SiC”) can be obtained by chemical vapor deposition (CVD) operating in a temperature range from approximately 1300 K to approximately 1800 K on a substrate comprising a graphite surface.In this method, which forms the first subject of the present invention, a gas mixture is introduced into a heated enclosure so as to create a gas phase comprising at least one gaseous precursor of silicon and / or carbon, at least one doping gas comprising at least one nitrogen atom, and a carrier gas, said gas mixture decomposing on the surface of said graphite substrate to form a layer of polycrystalline SiC on said graphite surface of said substrate, and said method being characterized in that the temperature in the reactor is between 1450 K and 1650 K and the total partial pressure of said gaseous precursors is less than 350 mbar, and preferably less than 300 mbar. This deposition is carried out on the graphite surface of a substrate comprising a graphite surface; said substrate may be a graphite plate.This substrate, and more particularly this graphite plate, is advantageously circular, so as to allow the direct production of a circular SiC disc.

[0028] According to an advantageous embodiment, said gas phase comprises trichloromethylsilane as a precursor of silicon and carbon, and preferably does not comprise other precursors of silicon and / or carbon. Said doping gas is advantageously selected from the group formed by: NH3, N2H4, N2, H2NCH3.

[0029] This process deposits a layer of polycrystalline silicon carbide (P-SiC) which can then be separated from the graphite surface on which it was formed; this produces a P-SiC disc whose thickness can be reduced by grinding and then polishing both sides.

[0030] Thus, a polycrystalline SiC wafer can be produced, which represents another object of the present invention. This wafer can be a raw blank, which can then undergo rectification steps to become an intermediate blank for the manufacture of a polycrystalline SiC substrate capable of receiving a transfer of a layer of monocrystalline SiC to form a wafer usable for the manufacture of a substrate for the deposition of integrated circuits. Said wafer, said raw blank and said intermediate blank represent other objects of the present invention, as will be explained later. They advantageously have a particular microstructure and crystallographic texture, as will be explained below.

[0031] Said polycrystalline SiC plate has a particular crystallographic texture, which can be obtained for particular doping and conductivity characteristics. Thus, a second subject of the invention is a polycrystalline SiC plate, characterized in that: (i) its texture coefficient C422 is less than 30%, and (ii.a) its texture coefficient C220 is greater than 60% and preferably greater than 80%, or (ii.b) the sum of the texture coefficients Cin+C222 + C5n is greater than 70%; and preferably greater than 80%. Advantageously, its texture coefficient C422 is less than 20%, preferably less than 15%, and preferably less than 10%.

[0032] This polycrystalline SiC plate according to the invention is advantageously doped, preferably with nitrogen. Another example of a doped polycrystalline SiC plate according to the invention is a phosphorus-doped plate.

[0033] Advantageously, the electrical resistivity of this polycrystalline SiC plate is less than 20 mOhm.cm, preferably less than 15 mOhm.cm, and even more preferably less than 10 mOhm.cm, and / or its nitrogen content is greater than 5 x 10 19 atoms / cm 3 , preferably greater than 1 x 1O 20 atoms / cm 3 , and even more preferably greater than 1.5 x 1O 20 atoms / cm 3 . Typically in the field of microelectronic substrates, the doping rate (e.g. nitrogen rate) can be determined by secondary ion mass spectrometry (SIMS).

[0034] A particularly preferred embodiment of this second subject of the invention is a polycrystalline SiC plate, doped with nitrogen with a nitrogen content, measured by secondary ion mass spectroscopy, greater than 5 x 10 19 atoms / cm 3, said plate having an electrical resistivity of less than 15 mOhm.cm and a preferential crystalline orientation, said plate being characterized in that: (i) its texture coefficient C422 is less than 20%, and (ii.a) its texture coefficient C220 is greater than 80%, or (ii.b) the sum of the texture coefficients C111+C222+C511 is greater than 80%.

[0035] Said polycrystalline SiC plate typically has the shape of a circular disc. It is characterized by good flatness, and advantageously has either a diameter between 140 mm and 165 mm or a diameter between 185 mm and 210 mm; these two diameter ranges include the sizes currently customary in the semiconductor industry, namely 6 inches and 8 inches.

[0036] Said polycrystalline SiC plate may be a raw blank resulting from a vapor deposition process. It may also be an intermediate blank for the manufacture of a wafer obtained by grinding such a raw blank. In one embodiment, the polycrystalline SiC plate according to the invention has a thickness of less than 550 μm, preferably less than 500 μm, more preferably less than 450 μm, and even more preferably between 355 μm and 420 μm; this embodiment is particularly suitable for plates with a diameter of between 140 mm and 165 mm.In another embodiment, the polycrystalline SiC plate according to the invention has a thickness of less than 850 μm, preferably less than 800 μm, more preferably less than 750 μm, and even more preferably between 510 μm and 650 μm; this embodiment is particularly suitable for plates with a diameter of between 185 mm and 210 mm.

[0037] In another embodiment, the polycrystalline SiC plate according to the invention has a diameter of between 140 mm and 165 mm, a thickness of between 350 μm and 450 μm and a deformation characterized by a Warp of less than 50 μm, preferably less than 40 μm and even more preferably less than 30 μm. Its thickness is preferably between 350 μm and 400 μm. By way of example, said plate may have a thickness of between 350 μm and 400 μm and a Warp of less than 40 (and preferably less than 30 μm), or its thickness may be between 400 μm and 450 μm and its Warp may then be less than 50 μm (and preferably less than 40 μm).In yet another embodiment, the polycrystalline SiC plate according to the invention has a diameter of between 185 mm and 210 mm, a thickness of between 500 μm and 650 μm and a deformation characterized by a Warp of less than 70 μm, preferably less than 50 μm and even more preferably less than 40 μm. Its thickness is preferably between 500 μm and 600 μm. By way of example, said plate may have a thickness of between 500 μm and 600 μm and a Warp of less than 50 (and preferably less than 40 μm), or its thickness may be between 600 μm and 650 μm and its Warp may then be less than 70 μm (and preferably less than 50 μm).

[0038] Such plates can be manufactured by a CVD process.

[0039] Figures

[0040] Figures 1 to 13 illustrate different aspects of the invention.

[0041] [Fig. 1] schematically shows the measurement of the parameter called “Warp” which expresses a particular aspect of the flatness defect of a semiconductor wafer.

[0042] [Fig. 2] shows an image obtained by backscattered electron scanning electron microscopy of a cross-section of a P-SiC layer obtained by a method according to Example 1.

[0043] [Fig. 3] shows an image obtained by direct mode scanning electron microscopy of a cross-section of a P-SiC layer similar to Example 1.

[0044] [Fig. 4] shows an image obtained by backscattered electron scanning electron microscopy of a cross-section of a P-SiC layer obtained by a method according to Example 2.

[0045] [Fig. 5] shows an image obtained by direct mode scanning electron microscopy of a cross-section of a P-SiC layer similar to Example 2.

[0046] [Fig. 6] shows an image obtained by backscattered electron scanning electron microscopy of a cross-section of a P-SiC layer obtained by a method according to Example 3.

[0047] [Fig. 7] shows an image obtained by direct mode scanning electron microscopy of a cross-section of a P-SiC layer similar to Example 3. [Fig. 8] shows an image obtained by backscattered electron scanning electron microscopy of a cross-section of a P-SiC layer obtained by a method according to Example 4.

[0048] [Fig. 9] shows an image obtained by direct mode scanning electron microscopy of a cross-section of a P-SiC layer similar to Example 4.

[0049] [Fig. 10] shows an image obtained by backscattered electron scanning electron microscopy of a cross-section of a P-SiC layer obtained by a method according to Example 5.

[0050] [Fig. 11] shows an image obtained by direct mode scanning electron microscopy of a cross-section of a P-SiC layer similar to Example 5.

[0051] [Fig. 12] shows schematically and simplified a vertical cross-section through a reactor according to the invention which makes it possible to manufacture a blank for a polycrystalline SiC substrate according to the invention.

[0052] [Fig. 13] shows an image obtained by backscattered electron scanning electron microscopy of a cross-section of a P-SiC layer obtained by a method according to Example 6.

[0053] The following numerical references are used in Figure 12 and in the description:

[0054] I: Reactor according to the invention 2: Enclosure

[0055] 3: Reaction space 4: Heating space

[0056] 5: Exhaust space 6: Heating element

[0057] 7: Graphite susceptor 8: Precursor gas inlet

[0058] 9: Reaction gas outlet 10: Outlet nozzle

[0059] II: Injector 12: Graphite discs (substrates)

[0060] Detailed description

[0061] Those skilled in the art of semiconductor substrates for microelectronics know the different ways to characterize the overall flatness of wafers: these different parameters are known by the terms or acronyms Bow (the distance between the surface and the plane corresponding to the best fit in the center of the unfixed wafer, see standard ASTM F534 “Standard Test Method for Bow of Silicon Wafers” point 3.1.2), Warp (the sum of the maximum positive and negative deviations from the plane corresponding to the best fit for an unfixed wafer, see standard ASTM F 1390 “Standard test Method for Measuring Warp on Silicon Wafers by Automated Non-Contact Scanning”), TTV (Total Thickness Variation, i.e.the difference between the maximum and minimum thickness values ​​for a fixed wafer, see ASTM F657 “Standard Test Method for Measuring Warp and Total Thickness Variation on Silicon Slices and Wafers by a Non-contact Scanning Method”), TIR (Total Indicated Reading, i.e. the sum of the maximum positive and negative deviations from the plane corresponding to the best fit for a fixed wafer), SRAD (Spherical Reference Measurement, expressing a radius of curvature for the sphere corresponding to the best fit); other acronyms express parameters to characterize the local flatness of wafers, in particular: LFPD (Local Focal Plane Deviation, i.e. the maximum distance between the wafer surface and the plane corresponding to the best fit (above or below the surface of the unfixed wafer), for a given area) and LTV (Local Thickness Variation, i.e.the difference between the maximum and minimum values ​​of unfixed wafer thickness, for a given area).

[0062] In the context of the present invention, the flatness of the wafers is characterized by the parameter commonly called "Warp". This parameter refers to the algebraic difference of the deviations of the wafer with respect to a reference plane. Figure 1 schematically illustrates the determination of this parameter from a surface profile by the algebraic difference of the ordinates B and C of the disc placed on a base plane.

[0063] We could also determine a median plane from the surface profile (typically using an algorithm implementing a least squares method) and calculate the Warp from the deviations from the median plane, which gives the same result as long as the median plane is parallel to the base plane. If the median plane is not parallel to the base plane, then the measurement method relative to the base plane increases that relative to the median plane.

[0064] We now describe the method according to the invention which makes it possible to solve the problem posed. The method according to the invention uses the chemical vapor deposition (CVD) technique, implemented in a heated enclosure. The method involves a gas mixture comprising at least one silicon precursor gas (such as a silane or a chlorosilane) and / or at least one carbon precursor gas (such as an alkane or an alkene), and / or at least one silicon and carbon precursor gas (such as methyltrichlorosilane, abbreviated MTCS), and at least one doping gas comprising nitrogen (for example NH3, N2H4, N2). Said doping gas may also be a carbon and / or silicon precursor (for example an amine such as H2NCH3). These gases may be diluted in a carrier gas, which may be a reducing gas such as hydrogen and / or an inert gas such as argon.

[0065] By way of example, a gaseous composition for implementing the method according to the invention may comprise a carbon precursor, a silicon precursor, a doping gas, the carrier gas. Another example is a gaseous composition which comprises a silicon and carbon precursor, a silicon precursor, a carbon precursor, a doping gas, the carrier gas.

[0066] This gas mixture is introduced into a high-temperature reactor where the precursor gases are decomposed and react on the surface to form the 3C-SiC polytype. This material is particularly suitable for combination with a monocrystalline SiC layer, due to its mechanical and thermal resistance properties, its compatibility with thermal expansion and its purity. It can also be doped with nitrogen up to very high levels, typically 1O 20 atoms / cm 3and have a resistivity much lower than 20 Ohm. cm, without degradation of the quality of the substrate which would be detrimental to the manufacture of power components. Finally, it is a material capable of subsequently resisting the high temperature processes that the wafer will have to undergo during the manufacture of the electronic component.

[0067] The temperature of the reactor during CVD deposition of SiC should be between about 1300 K and about 1800 K, and preferably between about 1350 K and about 1700 K, more preferably between about 1400 K and about 1650 K, and even more preferably between about 1450 K and about 1650 K. The total pressure in the reactor advantageously does not exceed 350 mbar, and preferably does not exceed 300 mbar.

[0068] In an advantageous embodiment of the method for manufacturing the P-SiC wafer according to the invention, the deposition is carried out by the CVD route on a graphite surface of a substrate. Very advantageously, said substrate is a fine-grained and purified isostatic graphite substrate, this to avoid any contamination and degassing of impurities during the deposition. For example, to obtain a wafer with a diameter of 150 mm, the deposition is carried out on a disc-shaped graphite cylinder, with a diameter approaching a nominal of 150 mm and a thickness greater than 2 mm to ensure sufficient flatness of the substrate. The reactor may comprise a plurality of these discs, the diameter of which may be identical or different. The two faces of the discs preferably have a flatness < 15 μm, obtained by sufficiently precise machining.The coefficient of thermal expansion of isostatic graphite is carefully chosen to be compatible with the SiC layer during cooling after deposition. A substrate marketed by MERSEN under the designation “grade 2303” can be used.

[0069] The progress of a typical embodiment of the method according to the invention will now be described, and a reactor in which the method according to the invention can be carried out will first be described in relation to Figure 12, by way of example. The method according to the invention takes place in a reactor 1 of a particular type. It comprises a reaction chamber 2, which contains a reaction space 3, a heating space 4 and a reaction gas discharge space 5. Said chamber 2 is designed to be able to reach low pressures down to a minimum of a few tens of millibars by pumping the gases to an effluent treatment device (not shown in the figure). The precursor gases are admitted into the reaction space 3 of the reactor 1 through a plurality of injectors 11 supplied by a gas line 8 called the precursor gas inlet.The reaction gases leave the reaction space 3 towards the discharge space 5, from where they are sucked through an outlet nozzle 10 into the gas line 9 called the reaction gas outlet. The heating space 4 comprises a plurality of heating elements 6, typically solenoids. Graphite cylinders or discs 12, also called substrates here, are loaded into the enclosure 2; for simplicity, Figure 12 does not show the supports which hold said substrates 12 in the reactor 1.

[0070] The deposition chamber 2 is heated by induction of a magnetic field in a graphite susceptor 7 inside which the precursor gases (for example silanes, alkanes and / or methyl-chlorosilanes), the carrier gases (for example hydrogen and / or argon), the doping gas (for example NH3, amines and / or N2) will circulate. The graphite substrates 12 are in thermal equilibrium inside the reaction space 3 heated by the susceptor 7 at a temperature generally between 1300 K and 1700 K (measured by a thermocouple), and more preferably between 1350 K and 1650 K. The gas mixture is introduced by nozzles or injectors 11 allowing a homogeneous distribution of the gas flow in the enclosure 2. In this temperature range, the deposition rates can vary within fairly wide ranges, from pm / h to more than 100 pm / h.The total partial pressure of said gaseous precursors is advantageously less than 350 mbar, and preferably less than 300 mbar.

[0071] To achieve a minimum P-SiC deposition thickness of approximately 600 μm, the gas injection time can vary from a few hours to several tens or even hundreds of hours depending on the conditions chosen. The control parameters indicated above can be adjusted to obtain the product according to the invention, as will be explained in greater detail in relation to the examples. Thus, it is possible to obtain high-quality P-SiC plates at economically satisfactory conditions, allowing them to be used in electronic applications substituting monocrystalline SiC produced by the traditional PVT process.

[0072] When the deposit thickness on the surface of the graphite substrate 12 is reached, the injection of precursor gases into the furnace is stopped and the enclosure is cooled to room temperature to be discharged. The graphite discs 12 coated with a thick layer of SiC deposit are then machined, then oxidized in air typically at 900°C to remove any graphite residue. A raw SiC disc is recovered for each face.

[0073] The deformation of the disc, raw blank, is measured using a white light confocal sensor that scans the surface of the SiC disc that was in contact with the graphite. To perform this measurement, the face of the disc on the CVD deposition side is placed on a support. The difference between the maximum and minimum elevation of the surface scanned by the sensor relative to the support plane of the measuring tool is measured. The graphite-side surface was a flat reference before being detached from the graphite. After detachment from the graphite, this surface becomes warped due to the stress relaxation of the deposited layer. This warped surface can be interpolated by a median plane, using the least squares method. If this median plane is parallel to the support plane, the deformation measurement is equal to the warp. This method of measuring the deformation increases the warp measurement in the general case.

[0074] If the deformation measurement on the raw blank is in accordance with the objective set below, it can be ground to a thickness slightly greater than the nominal 350 pm and to obtain a final warp of less than 50 pm for a standard 6-inch wafer.

[0075] Indeed, it is first necessary to prepare by grinding from the raw blank detached from the graphite an intermediate blank, which will then serve as a starting point to prepare, by fine grinding followed by polishing, the P-SiC wafer onto which a monocrystalline layer of SiC will then be transferred. The difference between the initial thickness of the raw blank and the deformation measured on said raw blank must not be less than the thickness of the intermediate blank. This means that the volume of the ground intermediate (cylindrical) blank must be included in the volume of the raw blank (see figure 1). The grinding step will also aim to eliminate a sufficient thickness on the side of the face in contact with the graphite. This removes the initial growth zone of the crystals, which makes it possible to eliminate the high stresses generated by this evolution of the deposit.

[0076] Over the temperature range 1373 K to 1673 K, the crystal growth orientation of P-SiC was studied by So and Chun in the article "Growth and structure of chemical vapor deposited silicon carbide from methyltrichlorosilane and hydrogen in the temperature range of 1100 to 1400°C" (Journal of Vacuum Science & Technology A 6, 5 (1988)). Figure 4 of this document shows a transition of the texture coefficient for this temperature region from the preferred (111) orientation at low temperature to the (220) orientation at high temperature. The texture coefficient was measured using the method described in the publication by GB Harris (1952) "X. Quantitative measurement of preferred orientation in rolled uranium bars", published in Philosophical Magazine Series 7, 43:336, 113-123.

[0077] The product obtained by the process according to the invention not only has excellent flatness (characterized by a low value of the Warp parameter), low electrical resistance and good thermal conductivity, but also has at its upper surface (i.e. the surface remote from the growth substrate, obtained by removal of material by polishing) a small grain size and good homogeneity of the grain size.

[0078] Examples

[0079] Examples 1 to 6 illustrate certain aspects of the invention, but do not limit its scope. In these examples, diffraction peaks were collected by an X-ray diffractometer of the PANalytical X'Pert PRO MPD type by the 0-20 method over an angle range from 10° to 135° (scale 2 0). Over this range, the ten diffraction peaks shown in Table 1 were taken into account for SiC 3C, classified according to increasing Miller indices (hkl):

[0080] Table 1: Diffraction peaks taken into account

[0081] A texture coefficient Chki (for N=10 peaks) is calculated from the intensity of the peak Ihki proportional to the area under the peak of the sample and the theoretical intensity l0hki of a powder which can be obtained from the theoretical % published by the ICDD (International Centre for Diffraction Data).

[0082] Chkl = (Ihkl / It) hkl) / (1 / NX^ (Ihkl / lo hkl))-

[0083] The texture coefficient in this case varies over a range from 0 to 10. It can also be expressed in %. It allows the average preferential orientation of the crystallites of the deposited layer to be quantified relative to the normal to the surface of the sample.

[0084] In these examples, the carbon source and the silicon source were the same molecule, namely methyl trichlorosilane (abbreviated MTCS). The nitrogen source doping gas was NH3. By modifying the few key parameters of the CVD process (temperature, precursor partial pressure, % of doping gas). It is possible to change the orientation of the deposited layer and its texture. This will have an impact on the intrinsic stress gradient of the deposit, making it possible to obtain a Warp on the raw blank consistent with the objective.

[0085] Example 1: Conical coarse grain texture with preferential orientation (422)

[0086] A 650 pm layer was deposited on a graphite substrate operating at a temperature of 1550 K, a partial pressure of 23 mbar of MTCS and a molar fraction of NH3 of 3%.

[0087] Figure 2 shows the backscattered electron scanning electron microscopy image of a cross-section of the resulting P-SiC layer; the substrate is at the bottom and the black bar corresponds to a length of 100 pm. At the bottom is the texture triangle, on which some facets marked with four different white symbols are indicated for information purposes. Figure 3 shows a similar image obtained by direct mode scanning electron microscopy at a higher magnification; the white bar corresponds to a length of 20 pm. In both micrographs, the substrate is at the bottom.

[0088] The observed orientation is a preferentially oriented texturing (422) with texture coefficients gathered in Table 2:

[0089] Table 2: Texture coefficients of P-SiC according to example 1

[0090] In Figures 2 and 3, a continuous increase in grain diameter over the first 200 microns was observed. This increase in grain size can be evaluated for each ordinate of the reference frame by counting the number of intersections of a horizontal line of constant ordinate with the grain boundaries on the EBSD image.

[0091] The resulting layer contains a nitrogen concentration measured by SIMS of 8 x 10 19 nitrogen atoms per cm 3and an electrical resistivity measured at 16 mohm.cm by the four-point method. The thermal conductivity of the layer is deduced from the result of a thermal diffusivity measurement using the laser flash method. The value of 210 W / m / K was obtained. Despite physical properties consistent with the target, the deformation measured on the raw disc is much higher than the target. On a total of 16 discs produced, the average deformation is 850 pm with a standard deviation of 140 pm. It will not be possible to produce a P-SiC wafer by grinding from a raw disc with a thickness of less than 1000 pm.

[0092] After several deposits under these conditions, the observed texturing is very preferentially oriented (422) with a texture coefficient C422 > 75%.

[0093] Example 2: Fine grain texture oriented (111)

[0094] A 650 pm layer was deposited on a graphite substrate operating at a temperature of 1550 K, a partial pressure of 8 mbar of MTCS and a molar fraction of NH3 of 6%. Figures 4 and 5 are micrographs analogous to Figures 2 and 3 of Example 1 (the white bar in Figure 5 corresponds to a length of 50 pm).

[0095] The observed orientation is a preferentially oriented (111) texturing with texture coefficients gathered in Table 3.

[0096] Table 3: Texture coefficients of P-SiC according to example 2

[0097] Figure 5 shows grains whose size does not increase as the growth of the P-SiC layer progresses; these are grains in the form of thin rods very oriented along the normal to the substrate plane. The grain size can be evaluated for each ordinate of the reference frame by counting the number of intersections of a horizontal line of constant ordinate with the grain boundaries on the EBSD image.

[0098] The deposit obtained contains a nitrogen concentration measured by SI MS of 7 1O 20 nitrogen atoms per cm 3and an electrical resistivity measured at 1.1 mOhm.cm by the 4-point method. The thermal conductivity of the layer is deduced by a thermal diffusivity measurement using the laser flash method. We obtain 52 W / m / K, which is well below the target. The fine-grained structure seems to strongly limit the thermal conductivity. The deformation measured on the raw disc is, however, very good. On a total of 16 discs produced, the average deformation is 190 pm with a standard deviation of 72 pm. This would make it possible to produce P-SiC wafers by grinding from a raw disc with a thickness of less than 1000 pm at a reasonable cost.

[0099] After several deposits under these conditions, the observed orientation is a very preferentially oriented texturing (111) with the sum of texture coefficient Cm +C222 + C51 1 > 80%.

[0100] Example 3: Fine grain texture oriented (220)

[0101] A 650 pm layer was deposited on a graphite substrate operating at a temperature of 1550 K, a partial pressure of 16 mbar of MTCS and a molar fraction of NH3 of 4%.

[0102] Figures 6 and 7 are micrographs analogous to Figures 2 and 3 of Example 1.

[0103] The observed orientation is a preferentially oriented texturing (220) with texture coefficients gathered in Table 4:

[0104] Table 4: Texture coefficients of P-SiC according to example 3

[0105] The resulting deposit contains a nitrogen concentration measured by SIMS of 1.8 x 1O 20 nitrogen atoms per cm 3and an electrical resistivity measured at 5 mohm.cm by the 4-point method. The thermal conductivity of the layer is deduced by a thermal diffusivity measurement using the laser flash method. We obtain 270 W / m / K which is above the target. Despite small grains, the tree-like texture seems to promote good thermal conductivity, despite high doping.

[0106] The deformation measured on the raw disc is also very good. Out of a total of 16 discs produced, the average deformation is 210 pm with a standard deviation of 82 pm. This makes it possible to produce P-SiC wafers by grinding from a raw disc with a thickness of less than 1000 pm at a reasonable cost.

[0107] After several deposits under these conditions, the observed texture is very preferentially oriented (220) with the texture coefficient C220 > 90% and C422 < 10% Example 4: Texture with fine grain predominantly oriented (220) predominantly mixed with large grains oriented (422)

[0108] Figures 8 and 9 are micrographs analogous to Figures 2 and 3 of Example 1.

[0109] An 800 pm layer was deposited on a graphite substrate operating at a temperature of 1600 K, a partial pressure of 16 mbar of MTCS and a molar fraction of NH3 of 4%. A preferentially oriented (220) texturing is observed, presenting large grains preferentially oriented (422) according to the texture coefficients gathered in Table 5:

[0110] Table 5: Texture coefficients of P-SiC according to example 4

[0111] The figure shows two populations of grains of different dimensions. The oriented grains (220) have a diameter between 1 pm and 10 pm. The other predominantly oriented grains (422) have a conical shape whose diameter can increase up to 50 pm. The grain size can be evaluated for each ordinate of the reference frame by counting the number of intersections of a horizontal line of constant ordinate with the grain boundaries on the EBSD image. Here, the growth of the average grain size stabilizes quickly, because the large grains remain a minority in the texture.

[0112] The resulting deposit contains a nitrogen concentration measured by SIMS of 2.2 x 1O 20 nitrogen atoms per cm 3and an electrical resistivity measured at 3.3 mohm.cm by the 4-point method. The thermal conductivity of the layer is deduced by a thermal diffusivity measurement using the laser flash method. We obtain 215 W / m / K which is above the target.

[0113] The deformation measured on the raw disc is also very good. On a total of 16 discs produced, the average deformation is 235 pm with a standard deviation of 90 pm. This makes it possible to produce P-SiC wafers by grinding from a raw disc with a thickness of less than 1000 pm at a reasonable cost. After several depositions under these conditions, the observed texture remains preferentially oriented (220) with the texture coefficient C220 > 60% and C422 < 20%

[0114] Example 5: Texture with mostly coarse grains oriented (422) mostly mixed with a fine texture of small grains oriented (220)

[0115] An 800 pm layer was deposited on a graphite substrate operating at a temperature of 1600 K, a partial pressure of 16 mbar of MTCS and a molar fraction of NH3 of 6%.

[0116] Figures 10 and 11 are micrographs analogous to Figures 2 and 3 of Example 1.

[0117] We observe a preferentially oriented texturing (422) presenting very large grains oriented according to the texture coefficients gathered in table 6:

[0118] Table 6: Texture coefficient of P-SiC according to example 5

[0119] The figure shows very large grains oriented (422) predominantly or (111) in a minority, conical in shape with diameters up to 100 pm. A few small grains (220) smaller than 10 pm are very much in the minority. The figure shows a continuous growth in grain diameter over the first 500 microns. This growth in grain size can be evaluated for each ordinate of the reference frame by counting the number of intersections of a horizontal line of constant ordinate with the grain boundaries on the EBSD image.

[0120] The resulting deposit contains a nitrogen concentration measured by SIMS of 6.8 1O 20 nitrogen atoms per cm 3and an electrical resistivity measured at 0.9 mohm.cm by the 4-point method, well below the targeted upper limit. The thermal conductivity of the layer is also deduced by a thermal diffusivity measurement using the laser flash method. We obtain 130 W / m / K which is below the targeted objective.

[0121] On a total of 16 produced discs, the average deformation is 650 pm with a standard deviation of 178 pm. It will not be possible to produce a P-SiC wafer by grinding from a raw disc with a thickness of less than 1000 pm. After several depositions under these conditions, the observed texture remains preferentially oriented (422) with the texture coefficient C422 > 50% and Cm +0222+0511> 15% and C220 < 10%.

[0122] Example 6: Texture obtained according to example 3 but without the addition of doping gas.

[0123] An 800 pm layer was deposited on a graphite substrate operating under conditions almost identical to those of Example 3, i.e. at a temperature of 1550 K, a partial pressure of 16 mbar of MTCS, but with a molar fraction of NH3 of 0%.

[0124] Figure 13 is a micrograph analogous to Figure 6 of Example 3.

[0125] The observed orientation is a texturing oriented mainly (422) then (111), with a (220) texture almost absent. The texture coefficients are gathered in table 7:

[0126] Table 7: Texture coefficients of P-SiC according to example 6

[0127] The deposit obtained contains a nitrogen concentration below the SIMS detection threshold, well below 10 19 nitrogen atoms per cm 3, and an electrical resistivity of 56 ohm. cm, measured by the 4-point method. The thermal conductivity of the layer is deduced by a thermal diffusivity measurement using the laser flash method. We obtain 130 W / m / K, which is below the target.

[0128] The deformation measured on the raw disc is not in line with expectations. On a total of 16 produced discs, the average deformation is 530 pm with a standard deviation of 110 pm. This will not allow the production by grinding of P-SiC wafers from a raw disc with a thickness of less than 1000 pm at a reasonable cost.

[0129] After several deposits under these conditions, the observed texture is oriented mainly (422) then (111) with the following texture coefficients: C422 > 35% and Ci 11 +C222+C511 > 20% and C220 < 15%.

[0130] Comparison of examples 1 to 6 The main results obtained in relation to the examples presented above are gathered in table 7 below:

[0131] Table 7: Main results of examples 1 to 6 above Examples 2, 3 and 4 show a texture highly oriented along the 2 possible axes (111) and (220) (C220 > 60% or C111+C222+C511 > 80%) and a contribution of the C422 orientation always less than 20%. It consists of a succession of fine grains of elongated shape. The grain stabilizes in diameter at 10 pm maximum for a length that can reach up to 100 pm. Example 6, manufactured under the conditions of example 3 but without the addition of doping gas, has a strong C422 orientation > 20% and a significant deformation that will not allow the production by grinding of a P-SiC wafer from a rough blank with a thickness of less than 1,000 pm.

Claims

Demands 1. A doped polycrystalline SiC plate exhibiting a preferred crystal orientation, said plate being characterized in that: (i) its C422 texture coefficient is less than 30%, and (ii.a) its C220 texture coefficient is greater than 60%, and preferably greater than 80%, or (ii.b) the sum of the texture coefficients C111+C222+C511 is greater than 70%, and preferably greater than 80%.

2. Polycrystalline SiC plate according to claim 1, characterized in that its electrical resistivity is less than 20 mOhm.cm, preferably less than 15 mOhm.cm, and even more preferably less than 10 mOhm.cm.

3. Polycrystalline SiC plate according to any one of claims 1 to 2, characterized in that it is nitrogen-doped with a nitrogen concentration, measured by secondary ion mass spectrometry, greater than 5 x 10 19 atoms / cm 3, preferably greater than 1 x 10 20 atoms / cm 3 , and even more preferably greater than 1.5 x 10 20 atoms / cm 3 .

4. Polycrystalline SiC plate according to any one of claims 1 to 3, characterized in that its texture coefficient C422 is less than 20%, preferably less than 15%, and even more preferably less than 10%.

5. Polycrystalline SiC plate according to any one of claims 1 to 4, nitrogen-doped with a nitrogen content, measured by secondary ion mass spectrometry, greater than 5 x 10 19 atoms / cm 3 said plate having an electrical resistivity of less than 15 mOhm.cm and a preferred crystalline orientation, and said plate being characterized in that: (i) its C422 texture coefficient is less than 20%, and (ii.a) its C220 texture coefficient is greater than 60%, and preferably greater than 80%, or (ii.b) the sum of the texture coefficients C111+C222+C511 is greater than 80%.

6. Polycrystalline SiC plate according to any one of claims 1 to 5, characterized in that it is a rough blank obtained from a vapor phase deposition process.

7. Polycrystalline SiC plate according to any one of claims 1 to 5, characterized in that it is an intermediate blank for the manufacture of a wafer obtained by grinding a rough blank according to claim 6.

8. Polycrystalline SiC plate according to claim 7, characterized in that its thickness is less than 550 pm, preferably less than 500 pm, more preferably less than 450 pm, and even more preferably between 355 pm and 420 pm.

9. Polycrystalline SiC plate according to any one of claims 1 to 8, characterized in that it has a diameter between 140 mm and 165 mm, a thickness between 350 pm and 450 pm and a deformation characterized by a Warp less than 50 pm, preferably less than 40 pm and even more preferably less than 30 pm.

10. Polycrystalline SiC plate according to claim 9, characterized in that it has a thickness between 350 pm and 400 pm.

11. Polycrystalline SiC plate according to any one of claims 1 to 7, characterized in that it has a diameter between 185 mm and 210 mm, a thickness between 500 pm and 650 pm and a deformation characterized by a Warp less than 70 pm, preferably less than 50 pm and even more preferably less than 40 pm.

12. Polycrystalline SiC plate according to claim 11, characterized in that it has a thickness between 500 pm and 600 pm.

13. Polycrystalline SiC plate according to any one of claims 1 to 13, characterized in that it was obtained by a CVD process.

14. A method for manufacturing a polycrystalline SiC plate according to any one of claims 1 to 13 comprising a step of chemical vapor deposition of a layer of polycrystalline SiC onto the graphite surface of a substrate (12) comprising a graphite surface, into which a mixture of gases is introduced in a heated chamber (2) so as to create a gaseous phase comprising: - at least one gaseous precursor of silicon and / or carbon, - at least one doping gas comprising at least one nitrogen atom, - a carrier gas, said gas mixture decomposing on the surface of said graphite substrate (12) to form a layer of polycrystalline SiC on said graphite surface of said substrate, and said process being characterized in that the temperature in said heated chamber (2) is between 1450 K and 1650 K and the total partial pressure of said gaseous precursors is less than 350 mbar, and preferably less than 300 mbar.

15. A process according to claim 14, characterized in that said gaseous phase comprises trichloromethylsilane, and preferably does not comprise other silicon and / or carbon precursors.

16. A method according to any one of claims 14 and 15, characterized in that said dopant gas is selected from the group formed by: NH3, N2H4, N2, H2NCH3.

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