A microelectronic fet device comprising large surface areas of contact between the conduction channel and the source and drain regions
Patent Information
- Application Number
- EP2023844109
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-12-22
- Filing Date
- 2023-12-22
- Publication Date
- 2025-10-29
AI Technical Summary
Conventional microelectronic devices face challenges with high contact resistances at the interfaces between 2D materials and source/drain regions due to small contact surfaces in 'side contact' configurations, and the use of silicon portions creates potential barriers that divert charge transport away from the 2D material.
An FET microelectronic device architecture is developed with large contact surfaces between the conduction channel and source/drain regions, where the semiconductor layer extends between the source/drain regions and dielectric spacers, forming a continuous layer that reduces contact resistances and eliminates the need for silicon portions, allowing for direct coupling without a 'side contact' interface.
This configuration significantly reduces source/drain contact resistances, enhances electric current flow, and prevents damage to the semiconductor layer during source/drain contact production, enabling efficient charge transport and compatibility with various semiconductor materials, including 2D materials.
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Figure 1.1
Abstract
Description
[0001] DESCRIPTION
[0002] TITLE: FET MICROELECTRONIC DEVICE INCLUDING LARGE CONTACT AREAS BETWEEN THE CONDUCTION CHANNEL AND THE SOURCE AND DRAIN REGIONS
[0003] TECHNICAL FIELD
[0004] The invention relates to the field of microelectronic devices applied to advanced CMOS technologies. The invention relates in particular to microelectronic devices of the FET (Field-Effect Transistor) type, in particular of the RFET (Reconfigurable Field-Effect Transistor) type, in particular based on two-dimensional materials, or 2D materials, or semiconductor oxides, as well as the production of such microelectronic devices.
[0005] State of the prior art
[0006] The miniaturization of electronics is constantly increasing, but the industry is now approaching the scaling limit for conventional materials such as silicon. Recently, 2D materials have emerged as promising candidates for use in miniaturized electronic and optoelectronic devices due to their unique properties and the very thin layer thickness of these materials, which can consist of a single layer of atoms or molecules.
[0007] The paper by KP O'Brien et al., "Advancing 2D Monolayer CMOS Through Contact, Channel and Interface Engineering," 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 7.1.1-7.1.4, proposes to realize a MOSFET transistor by integrating a layer of M0S2 to form the conduction channel. This layer is connected to two metallic source and drain regions based on gold, palladium, TiN, tungsten or nickel. The rear gate is formed by a layer of doped silicon positioned on the rear face under a dielectric layer based on SiO?, HfO? or A^Os.
[0008] In order to overcome the constraints related to the deposition of the metallic materials of the source and drain regions on the 2D material, it is possible to form these regions not on the upper face of the 2D material layer, but against the sides of the 2D material layer. This configuration, called "side contact", is however problematic because the contact surface between the 2D material layer and the source and drain regions is small, which generates significant contact resistances at the interfaces between the 2D material layer and the source and drain regions.
[0009] Document US 2022 / 045176 A1 describes several methods for producing gate-last FET transistors, in which silicon portions serve as a support for the deposition of a layer of 2D material. In addition to the disadvantages linked to the fact that the transistors produced have side contact channel / source-drain interfaces, the silicon portions used to deposit the 2D material form a potential barrier at the interface with the 2D material, which is not favorable because part of the charge transport can take place in these silicon portions and not in the 2D material.
[0010] STATEMENT OF THE INVENTION
[0011] An aim of the present invention is to propose a microelectronic device of the FET type, in particular RFET, whose structure is compatible with any type of semiconductor material including 2D materials or other materials of the semiconductor oxide type, and which does not have the disadvantages of a “side contact” configuration.
[0012] For this, the present invention proposes a FET microelectronic device comprising at least:
[0013] - a substrate;
[0014] - a semiconductor layer comprising at least a first zone forming an electrical conduction channel of the FET microelectronic device;
[0015] - several separate electrostatic control grids, spaced from each other and arranged on the first zone of the semiconductor layer;
[0016] - a gate dielectric layer disposed between each of the electrostatic control gates and the first region of the semiconductor layer;
[0017] - dielectric spacers arranged against the sides of each of the electrostatic control grids;
[0018] - source / drain regions electrically coupled to the first area of the semiconductor layer by second areas of the semiconductor layer, the second areas of the semiconductor layer extending between the source / drain regions and the dielectric spacers; and wherein the second areas of the semiconductor layer are not disposed directly against the electrostatic control gate and form, with the first area, a continuous layer.
[0019] One embodiment provides a FET microelectronic device comprising at least:
[0020] - a substrate;
[0021] - a semiconductor layer comprising at least a first zone forming an electrical conduction channel of the FET microelectronic device;
[0022] - several separate electrostatic control grids, spaced from each other and arranged on the first zone of the semiconductor layer;
[0023] - a gate dielectric layer disposed between each of the electrostatic control gates and the first region of the semiconductor layer;
[0024] - dielectric spacers arranged against the sides of each of the electrostatic control grids;
[0025] - source / drain regions electrically coupled to the first area of the semiconductor layer, the source / drain regions comprising or being formed from second areas of the semiconductor layer, the second areas of the semiconductor layer extending between source / drain contacts and the dielectric spacers.
[0026] Typically, the second regions of the semiconductor layer are not arranged directly against the electrostatic control gate. Advantageously, the second regions form, with the first region, a continuous layer.
[0027] The proposed microelectronic device is based on a FET-type architecture that does not include a side contact interface between the channel and the source / drain regions thanks to the second areas of the semiconductor layer providing electrical coupling between the channel formed by the first area of the semiconductor layer and the source / drain regions. These second areas of the semiconductor layer, which extend against at least a portion of the side walls, or flanks, of the source / drain contacts, form a large contact surface with the source / drain contacts, thereby reducing the source / drain contact resistances. Thus, the electrical current flowing in the channel is not reduced due to these contact resistances, which does not reduce the performance of the device.
[0028] Furthermore, with the proposed architecture, the semiconductor layer can be made just before the making of the source / drain contacts or just before the metal deposition of the source / drain contacts. Thus, the semiconductor layer whose first zone is intended to form the conduction channel is not damaged by the steps related to the making of the source / drain contacts. This is particularly advantageous when the semiconductor layer comprises a 2D material.
[0029] Furthermore, the realization of such a device does not require preserving portions of silicon to deposit the semiconductor layer intended to form the channel, thus eliminating the problem of potential barrier at the interface with the material of the semiconductor layer.
[0030] The semiconductor layer may comprise a two-dimensional material or any other semiconductor material deposited by MOCVD (Metal Organic Chemical Vapor Deposition), CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition). In this case, the microelectronic device can be produced with very small dimensions.
[0031] Advantageously, the FET microelectronic device may be such that:
[0032] - each of the source / drain contacts is arranged in a cavity comprising side walls formed at least by the dielectric spacers and by a dielectric insulating material or by one of said dielectric spacers and an insulating spacer of a neighboring microelectronic device;
[0033] - the second areas of the semiconductor layer cover at least part of the walls of the cavities in which the source / drain contacts are arranged. In the above configuration, the source / drain contact surfaces with the semiconductor layer are maximized by using the surface of the cavity walls, and advantageously the entire surface of the cavity walls, to form the contact between the second areas of the semiconductor layer and the source / drain contacts, which makes it possible to have very low contact resistances of the source / drain regions, and therefore a higher current flowing through the conduction channel of the device.
[0034] The microelectronic device comprises several separate electrostatic control gates, spaced apart from each other and arranged on the first area of the active layer. In this configuration, the microelectronic device comprises a “Reconfigurable FET” type architecture.
[0035] The FET microelectronic device may further comprise at least one dielectric portion surrounded by the first region of the semiconductor layer.
[0036] Alternatively, the first region of the semiconductor layer may not surround a dielectric portion.
[0037] Advantageously, the invention can be applied to the production of CMOS components for 5 nm and sub-5nm technology nodes.
[0038] The invention also relates to a method for producing a FET microelectronic device, comprising at least: a) producing at least one portion of temporary material on a substrate, then b) producing, at least on the portion of temporary material, several separate electrostatic control gates spaced apart from each other, and dielectric spacers arranged against flanks of each of the electrostatic control gates, then c) etching the portion of temporary material, then d) producing a semiconductor layer comprising at least a first zone configured to serve as an electrical conduction channel of the FET microelectronic device, arranged under the electrostatic control gates and the dielectric spacers in at least one location formed by the etching of the portion of temporary material, and such that the semiconductor layer extends, without discontinuity, with the first zone,by forming second areas covering at least part of the sides of the dielectric spacers and which are not arranged directly against the electrostatic control gates, then e) producing, on the substrate, source / drain contacts electrically coupled to the first area of the semiconductor layer by the second areas of the semiconductor layer, and such that the second areas of the semiconductor layer extend between the source / drain contacts and the dielectric spacers.,
[0039] The method may further comprise, before implementing step c), a deposition of a dielectric insulating material around the dielectric spacers, then an etching of cavities in the dielectric insulating material such that the cavities comprise at least one side wall formed by one of the dielectric spacers, and in which:
[0040] - step d) is implemented such that the second zones of the semiconductor layer cover at least part of the side walls of the cavities;
[0041] - step e) is implemented such that each of the source / drain contacts is arranged in one of the cavities.
[0042] The method may further comprise a step of depositing a gate dielectric layer implemented:
[0043] - between steps a) and b), on the portion of temporary material, the electrostatic control grids then being produced on the grid dielectric layer, and / or
[0044] - between steps c) and d), under the electrostatic control gates and the dielectric spacers, in at least one location formed by etching the portion of temporary material, the semiconductor layer then being produced by covering the gate dielectric layer.
[0045] The invention also relates to a method for producing a FET microelectronic device, comprising at least: a) producing at least one portion of temporary material on a substrate, then b) producing, at least on the portion of temporary material, several temporary gates that are distinct and spaced apart from each other and dielectric spacers arranged against sides of each of the temporary gates, then c) depositing a dielectric insulating material around the dielectric spacers, then d) etching the temporary gates, and producing several electrostatic control gates in place of the temporary gates, the electrostatic control gates being distinct and spaced apart from each other, then e) etching cavities in the dielectric insulating material such that the cavities comprise at least one side wall formed by one of the dielectric spacers, then f) etching the portion of temporary material,then g) producing a semiconductor layer comprising at least a first zone configured to serve as an electrical conduction channel of the FET microelectronic device, arranged under the electrostatic control gates and the dielectric spacers in at least one location formed by the etching of the portion of temporary material, and such that the semiconductor layer extends, without discontinuity with the first zone, forming second zones covering at least part of the sides of the dielectric spacers and which are not arranged directly against the temporary gates, then h) producing, on the substrate, source / drain contacts each arranged in one of the cavities and electrically coupled to the first zone of the semiconductor layer by the second zones of the semiconductor layer,and such that second regions of the semiconductor layer extend between the source / drain contacts and the dielectric spacers.,
[0046] The method may further comprise a step of depositing a gate dielectric layer implemented:
[0047] - during step e), on the first zone of the semiconductor layer, the electrostatic control gates then being produced on the gate dielectric layer, and / or
[0048] - between steps c) and d), under the temporary gates and the dielectric spacers, in at least one location formed by etching the portion of temporary material, the semiconductor layer then being produced by covering the gate dielectric layer. Throughout the document, the terms "on" and "under" are used without distinction of the orientation in space of the element to which this term relates. For example, in the characteristic "on a face of the first substrate", this face of the first substrate is not necessarily oriented upwards but can correspond to a face oriented in any direction.Furthermore, the arrangement of a first element on a second element should be understood as being able to correspond to the arrangement of the first element directly against the second element, without any intermediate element between the first and second elements, or as being able to correspond to the arrangement of the first element on the second element with one or more intermediate elements arranged between the first and second elements. Throughout the document, the term "layer" can refer to a single layer or a stack of several layers.
[0049] Throughout the document, the expression "electrically couple" is used to designate an electrical connection which may be direct or indirect (i.e. made through one or more intermediate electrical elements).
[0050] BRIEF DESCRIPTION OF THE DRAWINGS
[0051] The present invention will be better understood by reading the description of exemplary embodiments given purely for informational purposes and in no way limiting, with reference to the appended drawings in which:
[0052] - [Fig. 1] to [Fig. 5] schematically represent the steps of a method for producing the microelectronic device, the subject of the present invention, according to a particular embodiment;
[0053] - [Fig. 6] schematically represents a microelectronic device, object of the present invention, according to an alternative embodiment.
[0054] Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the transition from one figure to another.
[0055] The different parts represented in the figures are not necessarily shown on a uniform scale, in order to make the figures more readable. The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with each other.
[0056] Detailed description of specific embodiments
[0057] A method of producing a device 100 of the “Reconfigurable FET” type according to a particular embodiment is described below in connection with figures 1 to 5.
[0058] An etching of a semiconductor layer, corresponding for example to the surface layer of a substrate 102 of the SOI type, is implemented so as to form, on the substrate 102 (on the buried dielectric layer 130 in the example described), a portion of temporary material 160. As a variant, the substrate 102 can be of the bulk type.
[0059] A dielectric layer 112 and several electrostatic control grids 110 are formed on the temporary portion 160 and spaced apart from each other (see FIG. 1). In the example described here, the device 100 comprises two grids: a control grid and a polarity grid.
[0060] The 110 grids produced are distinct and spaced apart from each other.
[0061] The layer 112 comprises, for example, a high-K dielectric material (with high dielectric permittivity) such as HfOz. Alternatively, this layer 112 may comprise SiO2 or AUOs or any other suitable material or combination of materials.
[0062] The control grids 110 are for example produced by depositing one or more conductive materials on the layer 112, for example a first deposit of a thin layer of TiN (thickness for example equal to 3 nm) on which is stacked a layer of tungsten with a thickness for example equal to 200 nm. Alternatively, the grids 110 may comprise one or more materials different from TiN and W, such as for example doped polysilicon or any other metal (Mo, etc.).
[0063] Dielectric spacers 114 are formed against the sides of the gates 110. A material suitable for forming the dielectric spacers 114 corresponds, for example, to SiN, SiCO or SiBCN. The thickness of the layer deposited to form the dielectric spacers 114 is, for example, between 5 nm and 15 nm.
[0064] After the formation of the spacers 114, a dielectric insulating material 128, for example SiO?, is then deposited and then planarized with a stop on the hard mask present on the grids 110 (not visible in the figures). The dielectric insulating material 128 is deposited with a high thickness, then planarization is implemented until reaching the hard mask. The hard mask is then removed for example by wet etching, for example using a diluted H3PO4 solution and used at a temperature of 110°C.
[0065] The structure obtained at this stage of the process is shown in Figure 2.
[0066] Cavities 150 are then etched in the insulating dielectric material 128 (see FIG. 3). These cavities 150 include sidewalls formed by the dielectric spacers 114 and remaining portions of the insulating dielectric material 128. These cavities 150 form locations for forming the source and drain regions of the device 100. The portions of the temporary portion 160 not covered by the gates 110, the gate dielectric layer 112 and the dielectric spacers 114 and located at the bottom of the cavities are etched.
[0067] The remaining part of the temporary portion 160 covered by the gates 110, the gate dielectric layer 112 and the dielectric spacers 114 is etched, then a semiconductor layer 120 is deposited such that a first zone 122 of the semiconductor layer 120 forms a portion of semiconductor material arranged on the substrate 102 and the gates 110 and the gate dielectric layer 112 are arranged on this first zone 122 of the semiconductor layer 120. Furthermore, in the example visible in FIG. 4, a dielectric layer 152 is deposited prior to the semiconductor layer 120.
[0068] Second areas 124 of the semiconductor layer 120 cover the walls of the cavities 150. These second areas 124 form, with the first area 122, a continuous layer 120. These second areas 124 belong to the source and drain regions or form the source and drain regions.
[0069] Advantageously, the semiconductor layer 120 comprises at least one 2D semiconductor material, for example a transition metal dichalcogenide such as M0S2, or WSez, or WS2, or MoTe2. It is also possible that the material of the semiconductor layer 120 corresponds to IGZO, I^Os, IWO, ITO, or an amorphous semiconductor oxide, or any other suitable semiconductor material.
[0070] Contacts 116, 118 respectively of source region and drain region, also called source contact 116 and drain contact 118 are then produced in the cavities 150 by depositing, in the example described, one or more metallic materials in the cavities 150. Before this or these metallic deposits, it is possible to deposit a layer of graphene in the cavities 150, this or these metals then being deposited on the layer of graphene. These source 116 and drain 118 contacts, in FIG. 5, are electrically coupled to the first region 122 of the semiconductor layer 120 via the second regions 124 of the semiconductor layer 120 which extend between the source / drain contacts 116, 118 and the dielectric spacers 114 as well as against the other walls of the source 116 / drain 118 contacts located in the cavities 150.The material of these regions deposited outside the cavities 150 is removed by implementing planarization with stopping on the insulating dielectric material 128.
[0071] Advantageously, the source and drain contacts 116, 118 respectively comprise at least one metallic material such as gold, palladium, TiN, W, Ni, etc. According to an exemplary embodiment, each of the source 116 / drain 118 contacts comprises a layer of TiN on which a portion of tungsten is formed. Different metals can be used to form the contacts 116, 118 in order to promote low contact resistances, such as for example: S, Bi, Sn, Pd, Ru, Cu, Ni, Ti, TiN, W, Au, etc. These materials can also be modified subsequently (to improve their properties), by a doping step for example.
[0072] In the embodiment described above, the semiconductor layer 120 is such that the space previously occupied by the temporary portion 160 is completely filled by the material of the semiconductor layer 120. Alternatively, it is possible that the semiconductor layer 120 does not completely fill the space previously occupied by the temporary portion 160. In this case, after the deposition of the semiconductor layer 120, the remaining space(s) are filled with dielectric material so as to form a dielectric portion surrounded by the first zone 122 of the semiconductor layer 120. To form this dielectric portion, one or more dielectric layers, comprising for example KAI2O3 (or HfC) and / or SiC (or a low-k dielectric, or with low dielectric permittivity), are deposited and then etched isotropically in order to retain only the portion located in the remaining space.
[0073] Alternatively, the device 100 may comprise a different number of grids. Thus, in the example of FIG. 6, the device 100 comprises three grids: two control grids and one polarity grid.
[0074] In the various examples previously described, the second zones 124 of the semiconductor layer 120 cover all the sides and the bottom walls of the source 116 and drain 118 contacts so as to completely cover these contacts, except on an upper end portion opposite the bottom walls. This end portion preferably lies flush with a mouth of the cavities 150. Generally, it is possible for the second zones 124 of the semiconductor layer 120 to extend between the source and drain contacts 116, 118 and the dielectric spacers 114 and / or against walls of the source and drain contacts different from those arranged against the dielectric spacers 114. Furthermore, the walls of the source and drain contacts 116, 118 may be only partially covered by the second zones 124 of the semiconductor layer 120.
[0075] In the exemplary embodiments previously described for the first and second embodiments, the gate dielectric layer 112 and the electrostatic control gates 110 are produced on the portion of temporary material 160 before the deposition of the insulating dielectric material 128 and its planarization (so-called “gate first” approach).
[0076] Alternatively, according to a so-called “gate last” approach, it is possible to produce, instead of the gate dielectric layer 112 and the electrostatic control gates 110 and before the deposition of the insulating dielectric material 128 and its planarization, several temporary gates arranged on temporary dielectric portions themselves arranged on the temporary material portion 160. The temporary dielectric portions comprise for example SiC, and the temporary gates comprise for example polysilicon. These temporary elements are produced by depositing the desired layers of materials, by planarizing the polysilicon layer and by etching these layers according to the desired geometry for these temporary gates (geometry similar to that of the final gates produced subsequently). The dielectric spacers 114 are then produced are the sides of the temporary gates.After the deposition of the insulating dielectric material 128 and its planarization, the temporary gates and the temporary dielectric portions are removed by etching, then the gate dielectric layer 112 and the electrostatic control gates 110 are made in the locations formed by the etching of the temporary gates and the temporary dielectric portions. The device 100 is then completed in a manner similar to the method previously described, by implementing the steps described in connection with FIGS. 3 to 5.
[0077] In the previously described embodiments, the gate dielectric layer 112 is produced just before the electrostatic control gates 110 are produced, whether or not temporary gates have been used. Alternatively, it is possible for the electrostatic control gates 110 to be produced without having previously produced the gate dielectric layer 112. In this case, the gate dielectric layer 112 may be deposited just before the semiconductor layer 120 is deposition, at least against the walls of the location obtained by etching the temporary material portion 160. In this case, the layer 112 covers the various walls on which the material of the semiconductor layer 120 is intended to be deposited, thus homogenizing the surfaces, and therefore the interfaces, against which the semiconductor layer 120 is then deposited.
[0078] According to another variant, it is possible for the layer 112 to be deposited during two different steps: firstly just before the production of the gates 110 as previously described in connection with FIG. 1, then in the spaces formed by the etching of the portions 160 and in the cavities 150, just before the deposition of the semiconductor layer 120. In this case, the parts of the layer 112 located directly above the gate 110 are thicker than the other parts of the layer 112 because these parts combine the thicknesses of material deposited during the two deposition steps.
Claims
CLAIMS 1. FET microelectronic device (100) comprising at least: - a substrate (102); - a semiconductor layer (120) comprising at least a first zone (122) forming an electrical conduction channel of the FET microelectronic device (100); - several separate electrostatic control grids (110), spaced from each other and arranged on the first zone of the semiconductor layer; - a gate dielectric layer (112) disposed between each of the electrostatic control gates (110) and the first region (122) of the semiconductor layer (120); - dielectric spacers (114) arranged against sides of each of the electrostatic control grids (110); - source / drain regions electrically coupled to the first area (122) of the semiconductor layer (120), the source / drain regions comprising or being formed from second areas (124) of the semiconductor layer (120), the second areas (124) of the semiconductor layer (120) extending between source / drain contacts (116, 118) and the dielectric spacers (114); and wherein the second areas (124) of the semiconductor layer (120) are not disposed directly against the electrostatic control gate (110) and form, with the first area (122), a continuous layer.
2. The FET microelectronic device (100) of claim 1, wherein the semiconductor layer (120) comprises a two-dimensional material.
3. FET microelectronic device (100) according to one of the preceding claims, wherein: - each of the source (116) / drain (118) contacts is arranged in a cavity (150) comprising side walls formed at least by the dielectric spacers (114) and by a dielectric insulating material (128) or by one of said dielectric spacers (114) and an insulating spacer of a neighboring microelectronic device; - the second zones (124) of the semiconductor layer (120) cover at least a portion of the walls of the cavities (150) in which the source (116) / drain (118) region contacts are arranged.
4. FET microelectronic device (100) according to one of the preceding claims, further comprising at least one dielectric portion surrounded by the first zone (122) of the semiconductor layer (120).
5. FET microelectronic device (100) according to one of claims 1 to 4, wherein the second zones (124) of the semiconductor layer (120) entirely cover flanks and entirely a bottom wall of each of the source (116) and drain (118) contacts.
6. Method for producing a FET microelectronic device (100), comprising at least: a) producing at least one portion of temporary material (160) on a substrate (102), then b) producing, at least on the portion of temporary material (160), several electrostatic control gates (110) that are distinct and spaced apart from each other, and dielectric spacers (114) arranged against flanks of each of the electrostatic control gates (110), then c) etching the portion of temporary material (160), then d) producing a semiconductor layer (120) comprising at least a first zone (122) configured to serve as an electrical conduction channel of the FET microelectronic device (100), arranged under the electrostatic control gates (110) and the dielectric spacers (114) in at least one location formed by the etching of the portion of temporary material (160), and such that the layer of semiconductor (120) extends,without discontinuity with the first zone (122), by forming second zones (124) covering at least part of the sides of the dielectric spacers (114) and which are not arranged directly against the electrostatic control gates (110), the second zones (124) forming source (116) / drain (118) regions, then e) producing, on the substrate (102), source (116) and drain (118) contacts (116, 118) electrically coupled to the first zone (122) of the semiconductor layer, (120) by the second regions (124) of the semiconductor layer (120), and such that second regions (124) of the semiconductor layer (120) extend between the source (116) / drain (118) contacts and the dielectric spacers (114), and wherein the method further comprises providing a gate dielectric layer disposed between each of the electrostatic control gates and the first region of the semiconductor layer.
7. Method according to claim 6, further comprising, before implementing step c), a deposition of an insulating dielectric material (128) around the dielectric spacers (114), then an etching of cavities (150) in the insulating dielectric material (128) such that the cavities (150) comprise at least one side wall formed by one of the dielectric spacers (114), and in which: - step d) is implemented such that the second zones (124) of the semiconductor layer (120) cover at least part of the side walls of the cavities (150); - step e) is implemented such that each of these source (116) / drain (118) contacts is arranged in one of the cavities (150).
8. Method according to one of claims 6 and 7, further comprising a step of depositing the layer (112) of gate dielectric implemented: - between steps a) and b), on the portion of temporary material (160), the electrostatic control grids (110) then being produced on the layer (112) of grid dielectric, and / or - between steps c) and d), under the electrostatic control gates (110) and the dielectric spacers (114), in at least one location formed by the etching of the portion of temporary material (160), the semiconductor layer (120) then being produced by covering the layer (112) with gate dielectric.
9. Method for producing a FET microelectronic device (100), comprising at least: a) producing at least one portion of temporary material (160) on a substrate (102), then b) producing, at least on the portion of temporary material (160), several separate temporary gates spaced apart from each other and dielectric spacers (114) arranged against flanks of each of the temporary gates, then c) depositing a dielectric insulating material (128) around the dielectric spacers (114), then d) etching the temporary gates, and producing several electrostatic control gates (110) in place of the temporary gates, the electrostatic control gates (110) being distinct and spaced apart from each other, then e) etching cavities (150) in the dielectric insulating material (128) such that the cavities (150) comprise at least one side wall formed by one of the dielectric spacers (114), then f) etching the portion of temporary material (160), then g) producing a semiconductor layer (120) comprising at least a first zone (122) configured to serve as an electrical conduction channel of the FET microelectronic device (100),arranged under the electrostatic control gates (110) and the dielectric spacers (114) in at least one location formed by the etching of the portion of temporary material (160), and such that the semiconductor layer (120) extends, without discontinuity with the first zone (122), forming second zones (124) covering at least part of the sides of the dielectric spacers (114) and which are not arranged directly against the temporary gates, the second zones (124) forming source (116) / drain (118) regions then h) production, on the substrate (102), of source and drain contacts (116 / 118) each arranged in one of the cavities (150) and electrically coupled to the first zone (122) of the semiconductor layer (120) by the second zones (124) of the semiconductor layer (120),and such that second regions (124) of the semiconductor layer (120) extend between the source (116) / drain (118) contacts and the dielectric spacers (114), and wherein the method further comprises providing a gate dielectric layer disposed between each of the electrostatic control gates and the first region of the semiconductor layer., 10. Method according to claim 9, further comprising a step of depositing the layer (112) of gate dielectric implemented: - during step d), in the locations formed by the etching of the temporary grids, the electrostatic control grids (110) then being produced on the layer (112) of grid dielectric, and / or - between steps c) and d), under the temporary gates and the dielectric spacers (114), in at least one location formed by the etching of the portion of temporary material (160), the semiconductor layer (120) then being produced by covering the layer (112) with gate dielectric.