Doped polycrystalline sic wafer with improved flatness and electrical conductivity, and method for producing such a wafer

Abstract

The invention relates to a wafer made of polycrystalline SiC that has a preferred crystal orientation, this wafer being characterised in that, on each of the faces thereof: (i) the C422 texture coefficient thereof is less than 40%; and (ii) the C220 + C200 + C400 texture coefficient thereof is greater than 50% and preferably greater than 80%. This wafer can be produced by means of a CVD method. The thus-obtained rough blank can be thinned by means of grinding and polishing. The flatness, electrical conductivity and thermal conductivity thereof, which are important properties for a microelectronic substrate, can be improved by heat treatment.

Description

[0001] DESCRIPTION

[0002] Title: Doped polycrystalline SiC plate with improved flatness and electrical conductivity, and method of manufacturing such a plate

[0003] Technical field

[0004] The invention relates to the field of materials science, and more particularly to the field of materials that can be used to manufacture substrates for integrated circuits, and to methods for producing these materials. It relates more specifically to polycrystalline silicon carbide. This material, like all materials for microelectronic substrates, is implemented in the form of thin wafers (for which those skilled in the art often use the English term "wafer"), typically circular. SiC is particularly suitable for the manufacture of substrates for use in power electronic components. SiC wafers must meet very strict specifications with regard to their flatness, the homogeneity of their properties, and the absence of defects.

[0005] The present invention presents a new type of polycrystalline SiC wafers usable for the manufacture of integrated circuit substrates; these wafers are made of beta-type SiC and have particular crystallographic characteristics.

[0006] Since integrated circuits are generally deposited on surfaces of a single-crystal semiconductor, in the case of a polycrystalline silicon carbide wafer, the electronically active surface (i.e. the surface on which the integrated circuits are deposited) must be specially prepared by transferring a layer of single-crystal SiC. This method of preparation by transferring a layer of single-crystal SiC is not part of the present invention.

[0007] The present invention also relates to a new method for manufacturing such a beta-type polycrystalline silicon carbide wafer capable of receiving, in a subsequent manufacturing step, the transfer of a layer of monocrystalline SiC.

[0008] State of the art

[0009] Since the beginning of microelectronics, the vast majority of microelectronic circuits have been manufactured on a single-crystal silicon substrate. For some specific applications, semiconductor silicon is not the ideal substrate, but it is used for lack of anything better. Silicon carbide (abbreviated SiC), on the other hand, is a remarkable semiconductor material: It has a wide band gap, a high breakdown field, high charge carrier mobility at saturation, and high thermal conductivity. This combination of exceptional physical properties gives it excellent voltage resistance, as well as the passage of very high current densities, even at high temperatures. The article "Power Components in SiC - Technology" by D. Tournier, published in 2007 as part D-3120 in the Engineering Techniques collection, provides an introduction to the subject.

[0010] SiC is therefore a material perfectly suited for the manufacture of power components required for the efficient conversion of electrical energy in applications such as electrical power distribution, renewable energies, and electric vehicles. The use of SiC makes it possible to advantageously replace silicon-based transistors such as insulated gate bipolar transistors (commonly abbreviated IGBT, Insulated Gate Bipolar Transistor) with power components such as metal-oxide gate field effect transistors (commonly abbreviated MOSFET, Metal Oxide Semiconductor Field Effect Transistor) with a voltage withstand of the order of kilovolts and much lower energy losses during switching.In these power components, voltage and temperature resistance can become limiting factors when designing electronic components and the electronic boards on which these components are installed. The recent development of the electric vehicle would greatly benefit from the use of such SiC power components to improve energy efficiency when converting direct current from the batteries into alternating current usable by the motor. The cost and availability of these components nevertheless remain obstacles to the adoption of this technology, and for this reason silicon is still widely used as a substrate in specific applications for which SiC would offer technical advantages.

[0011] According to the state of the art, silicon carbide substrates intended to receive the deposition of microelectronic circuits are generally circular wafers. They are manufactured industrially using the PVT (Physical Vapor Transfer) process, which consists of sublimating a SiC powder at high temperature (> 2200°C) and condensing the vapors on a seed to obtain an ingot or "ball" of monocrystalline SiC. Monocrystalline SiC substrates (wafers) are then sliced ​​from this monocrystalline ingot. After thinning and polishing, a layer of crystalline SiC is deposited by epitaxy on one of the faces of this substrate, in order to obtain a crystal with the fewest possible defects. After epitaxy, these wafers will be ready to accommodate the manufacture of electronic components.

[0012] Improvements in the PVT industrial process over the last thirty years have significantly reduced the density of the main crystalline defects in these substrates, such as dislocations and micro-pipes, which had a significant impact on the reliability of SiC components. In addition, it has made it possible to increase the size of the substrates (wafers) up to a diameter of 150 mm as standard, soon to increase to 200 mm. Despite industrial efforts, the PVT process remains complex to master, not very productive and consumes a significant amount of energy because it requires maintaining an oven at very high temperature for around a hundred hours.

[0013] Furthermore, for power components, the lowest possible RON resistance in on-mode is a key criterion for improving the system's energy efficiency by limiting Joule heating during current flow. In these applications, monocrystalline SiC is doped both to enable the fabrication of the component's p / n junctions and to reduce its resistivity in contact with the drain. The addition of nitrogen makes it possible to dope the substrate during crystal growth. As standard, "n"-doped wafers have a resistivity of around 20 mOhm.cm. It becomes very difficult to reduce the resistivity below this threshold without degrading the quality of the crystal, because excessive doping creates stresses that promote additional dislocations in the crystal.

[0014] A new technology currently being developed would allow the use of a low-cost SiC substrate (wafer) with improved electrical performance to be combined with a thin layer of high-quality monocrystalline SiC in which the microelectronic component would be manufactured. The monocrystalline SiC layer is attached to the substrate by a molecular bonding process as described in WO 01 / 18873 (Commissariat à l'Energie Atomique), which also ensures minimal contact resistance between the substrate and the attached monocrystalline layer. Document EP 3 018696 A1 describes an embodiment of such a process, which results in a monocrystalline SiC layer attached to a polycrystalline SiC substrate (hereinafter referred to as "p-SiC" or "p-SiC Wafer").

[0015] These p-SiC substrates must meet strict requirements for electrical resistance, thermal conductivity, and flatness. "Dummy wafer" prototype products are currently available on the market, sold by companies such as Ferrotec. These wafers, with a diameter of 150 mm and a thickness of 750 μm as standard, are used to balance a full load of monocrystalline SiC wafers in certain processes to improve uniformity.

[0016] According to the state of the art, p-SiC wafers are obtained by depositing polycrystalline SiC by CVD on a cylindrical graphite substrate. The SiC obtained under these conditions is of the beta type, and of the 3C polytype. After removing by machining the SiC layer deposited on the periphery of the cylinder until accessing the graphite, two SiC discs can be separated from the two faces of the cylinder by oxidation of the graphite in air. This is described in patent applications JP 1994 340994 and JP 1997 296361.

[0017] However, it quickly became apparent that the resulting wafers exhibited deformation (Bow and Warp) that was unacceptable for the intended application. The Bow and Warp parameters represent the flatness of a wafer intended for the semiconductor industry and are known to those skilled in the art of semiconductor substrates for microelectronics (only the English words are used for these parameters, which we write here with a capital letter); they will be described in greater detail below and can be measured according to the SEMI MF1390 standard. The processes described in the two Japanese documents cited above find a solution to the problem, thanks to the repetition of several deposition steps of small thicknesses of less than 100 μm. Indeed, for a sufficiently thick deposit, the increase in the grain diameter generates an internal compressive stress. The conical grains repel each other as they grow.This physical mechanism is demonstrated by P. Chaudhari in the publication "Grain growth and Stress relief in thin films", published in Journal of Vacuum Science and Technology 9, 520 (1972), which is a basic document for any specialist in the deposition of layers from a vapor phase. The process described in JP 1994 340994 and JP 1997 296361 makes it possible to obtain thick layers of p-SiC of several hundred microns by limiting the increase in internal compressive stresses and therefore makes it possible to limit their deformations once detached from the graphite.

[0018] Japanese patent JP 3648 112 B2 describes a similar process that alternates the deposition of layers with tensile and compressive stresses, in order to cancel the stress moment integrated over the entire thickness of the deposit. This mechanical moment is indeed the origin of the deformation observed when the p-SiC disk is removed from its graphite substrate. It is however important to note that the processes as described above are not favorable for achieving low resistivity and good thermal conductivity through the thickness of the wafer because of the multiple interfaces separating the layers in its thickness. The search for a single-layer solution to the problem would be more favorable.

[0019] US Patent 10,934,634 B2 describes the production of a p-SiC wafer with excellent flatness from a single layer of SiC deposited by CVD on a graphite substrate. A sufficiently thick deposit, typically 2 mm, has an upper part where the variation in grain diameter is stabilized. Since the compressive stress no longer changes in this part (as demonstrated in the cited publication by Chaudhari), it is then possible to extract by machining a slice with a thickness of 350 μm which has a near-zero stress gradient like the grain sizes in the thickness and therefore to integrate a near-zero mechanical moment over the thickness. The expected effect is a very low deformation of the wafer.However, the cost and energy expended by such a process is probably unfavorable, since approximately 1.65 mm of the 2 mm CVD-deposited layer must be removed by grinding and polishing to obtain the wafer at the desired thickness of 350 pm with the desired flatness.

[0020] To reduce manufacturing costs, it would be optimal to grow by CVD at high speed a p-SiC layer of thickness as close as possible to the final thickness with a grain size stabilized very quickly after the start of layer growth, to avoid any unnecessary extra thickness that would become necessary to reduce or eliminate the grain size gradient.

[0021] At the Transducers & Eurosensors 2007 conference, XA Fu et al. published a paper entitled "Nitrogen doped polycrystalline 3C-SiC films deposited by LPCVD for MEMS applications." In this paper, the authors studied the deposition of SiC for doping gas levels (NH3) varying from 2% to 12% in mole fraction of the silicon precursor (Dichlorosilane). To obtain a resistivity below 20 mohm.cm under these conditions, the dopant level must exceed 5%. A higher dopant level leads to an increase in the residual stress without increasing the stress gradient. In this study, the deposition is carried out at low temperature 900°C and low pressure favoring crystal growth exclusively along the (111) axis, but with an extremely slow deposition rate of 0.6 pm / h. Significant doping does not appear to modify under these conditions the crystalline orientation of the deposited thin layer, measured by X-ray diffraction (XRD) analysis.In the publication by HKE Latha et al. published in 2014 in the journal Mater. Res. Express 1 015902, the effects of high doping of 3C-SiC obtained by CVD are studied using methyltrichlorosilane (MTCS) as a precursor of silicon and carbon, and NH3 as a doping agent. The deposition conditions are 1040°C at low pressure. The growth rate of the deposit reaches about 5 pm / h, much higher than the previous case, but still very insufficient to produce large thicknesses (several hundred microns) in an economically viable manner. An influence of the doping level on the crystal orientation and grain size is observed under these conditions. A high doping level is accompanied by a coarsening of the grain size and their crystal orientation axis is modified according to X-ray diffraction (XRD) analysis.

[0022] Patent application WO 2021 / 060515 (Tokai Carbon) proposes a process for obtaining a p-SiC substrate with a thickness between 500 pm and 6 mm, at a high deposition temperature close to 1500°C. The deposition time is between 5 h and 15 h, i.e. deposition rates above 100 pm / h, particularly suitable for industrial production. The doping of the p-SiC is obtained by adding nitrogen to the mixture. To obtain a sufficiently flat substrate, the patent proposes a process that varies the SiC precursor concentration during deposition, in order to reduce the excessively steep grain size gradient in the deposit. This process is proposed for nitrogen mass concentrations between 200 ppm (2.8 x 10 19 atoms / cm 3 ) and 1000 ppm (1.38 x 10 20 atoms / cm 3). Beyond 1000 ppm, it is noted that an excessive concentration of nitrogen in p-SiC would generate significant defects in the crystals and deformation of the substrate.

[0023] Thus, a high concentration of nitrogen dopant in the p-SiC material is potentially a limiting factor for achieving good flatness, but is desirable for achieving low electrical resistivity. These conflicting trends must be taken into account when attempting to fabricate a p-SiC raw substrate by CVD with low resistivity (e.g. < 10 mOhm.cm) and sufficient flatness to be able to grind a p-SiC wafer with as little material as possible. Regarding the flatness of the CVD raw substrate, it must be kept in mind that removing material by grinding from a surface as hard as SiC is a time-consuming and expensive process, and in addition, any material thickness removed by grinding is material that is lost.Indeed, the manufacturing cost of the p-SiC wafer must reach a sufficiently low level to be able to serve as a substrate combined with a thin layer of monocrystalline SiC in power electronics applications. According to the state of the industrial technique, the nominal thickness of the finished p-SiC wafer is 350 pm for a nominal diameter of 150 mm. A thicker raw product (raw blank) is manufactured from a CVD deposition process on a graphite substrate. For economic reasons, once detached from the graphite, the p-SiC blank must not exceed a thickness of 1 mm; typically 750 pm and preferably 600 pm are targeted, in order to obtain a reasonable CVD deposition time and to reduce the thickness to be removed by grinding and polishing, to a maximum of 650 pm, typically 400 pm, preferably 250 pm respectively.It should be noted in this context that one would generally wish to minimize the thickness of material that must be removed by grinding, knowing that SiC results from a high-temperature manufacturing process, and is one of the hardest materials known, after diamond.

[0024] The warp of a 350 μm thick wafer with a diameter of six inches must be less than 50 μm after grinding and polishing to comply with microelectronics standards. To achieve this objective, an intermediate blank must first be prepared by grinding from the raw blank detached from the graphite. This will then serve as a starting point for preparing, by fine grinding followed by polishing, the p-SiC wafer onto which a monocrystalline layer of SiC will then be transferred. The difference between the initial thickness of the raw blank and the deformation measured on the said raw blank must not be less than the thickness of the intermediate blank. This means that the volume of the ground intermediate (cylindrical) blank must be included in the volume of the raw blank (see Figure 1).

[0025] In the present invention, the inventors sought to optimize the manufacture of a polycrystalline SiC plate having a high dopant level (for example n-type, such as nitrogen or phosphorus) typically greater than 5 x 10 19 atoms / cm 3 , preferably greater than 10 20 atoms / cm 3 , to typically achieve a material resistivity of less than 15 mOhm.cm and preferably less than 10 mOhm.cm. The thermal conductivity of the material should typically be greater than 200 W / mK, but a value greater than 250 W / m / K is preferred, despite a high N dopant content which can affect the thermal conductivity by generating additional crystal defects harmful to the propagation of phonons. A polycrystalline SiC plate is also sought which has excellent surface homogeneity of its grain size, and preferably a fine grain. Objects of the invention

[0026] It results from the work carried out by the inventors of the present application that a massive plate of polycrystalline SiC (denoted here “p-SiC”) of beta type can be obtained by chemical vapor deposition (CVD) operating in a temperature range from approximately 1300 K to approximately 1800 K on a substrate comprising a graphite surface.In this method, a gas mixture is introduced into a heated enclosure so as to create a gas phase comprising at least one gaseous precursor of silicon and / or carbon, at least one doping gas comprising at least one doping atom, such as nitrogen and / or phosphorus, and a carrier gas, said gas mixture decomposing on the surface of said graphite substrate to form a layer of beta-type polycrystalline SiC on said graphite surface of said substrate, and said method being characterized in that the temperature in the reactor is between 1450 K and 1650 K and the total partial pressure of said gaseous precursors is less than 350 mbar, and preferably less than 300 mbar. This deposition is carried out on the graphite surface of a substrate comprising a graphite surface; said substrate may be a graphite plate.This substrate, and more particularly this graphite plate, is advantageously circular, so as to allow the direct production of a circular SiC disc.

[0027] According to an advantageous embodiment of this deposition method, said gas phase comprises trichloromethylsilane as a precursor of silicon and carbon. Said doping gas is advantageously selected from the group formed by: NH3, N2H4, N2, H2NCH3.

[0028] This process deposits a layer of polycrystalline silicon carbide (p-SiC) which can then be separated from the graphite surface on which it was formed; this produces a p-SiC plate whose thickness can be reduced by grinding and then polishing both sides.

[0029] Thus, a polycrystalline SiC wafer can be produced. This wafer can be a raw blank, which can then undergo rectification steps to become an intermediate blank for the manufacture of a polycrystalline SiC substrate (wafer) capable of receiving a transfer of a layer of monocrystalline SiC to form a wafer usable for the manufacture of a substrate for the deposition of integrated circuits. Said wafer, said raw blank and said intermediate blank represent objects of the present invention, as will be explained later. They advantageously have a particular microstructure and crystallographic texture, as will be explained below. In a typical embodiment, the wafer according to the invention undergoes material removal on one and / or the other of these two faces before exhibiting the properties described.

[0030] A first object of the present invention is a polycrystalline SiC plate of beta type having a preferential crystalline orientation, said plate being characterized in that on each of its faces:

[0031] (i) its texture coefficient C422 is less than 40%, and

[0032] (ii) its texture coefficient C220 + C200 + C400 is greater than 50%, and preferably greater than 80%.

[0033] According to a first aspect of this first subject of the invention, its electrical resistivity is less than 10 mOhm.cm, preferably less than 5 mOhm.cm, and even more preferably less than 3 mOhm.cm.

[0034] According to a second aspect of this first subject of the invention, which can be combined with the first aspect, said plate is doped with nitrogen with a nitrogen content, measured by secondary ion mass spectroscopy (SIMS), greater than 5 x 10 19 atoms / cm3 , preferably greater than 1 x 10 20 atoms / cm 3 , and even more preferably greater than 1.5 x 10 20 atoms / cm 3 .

[0035] According to a third aspect of this first subject of the invention, which can be combined with the first and / or the second aspect, said plate is doped with phosphorus with a phosphorus level, measured by secondary ion mass spectroscopy, greater than 5 x 10 19 atoms / cm 3 , preferably greater than 1 x 10 20 atoms / cm 3 , and even more preferably greater than 1.5 x 10 20 atoms / cm 3 .

[0036] According to a fourth aspect of this first subject of the invention, which can be combined with the first and / or the second and / or the third aspect, on each of the two faces of said plate its texture coefficient C422 is less than 20%, preferably less than 15%, and even more preferably less than 10%.

[0037] According to a fifth aspect of this first subject of the invention, which can be combined with the first and / or the second and / or the third and / or the fourth aspect, said plate is doped with nitrogen with a nitrogen or phosphorus content, measured by secondary ion mass spectroscopy, greater than 5 x 10 19 atoms / cm 3 , said plate having an electrical resistivity of less than 5 mOhm.cm and a preferential crystalline orientation, and said plate being characterized in that on each of its two faces:

[0038] (i) its texture coefficient C422 is less than 20%, and

[0039] (ii) its texture coefficient C220 + C200 + C400 is greater than 60%, and preferably greater than 80%.

[0040] According to a sixth aspect of this first subject of the invention, which can be combined with the first and / or the second and / or the third and / or the fourth and / or with the fifth aspect, said plate is a raw blank resulting from a vapor deposition process, which has undergone at least one heat treatment step at a temperature between 1,800°C and 2,300°C, preferably between 1,850°C and 2,200°C, more preferably between 1,900°C and 2,150°C, and even more preferably between 1,950°C and 2,150°C, knowing that, before or after said heat treatment, said raw blank has been freed, at least on its face which was in contact with a growth substrate, of a material thickness of at least 100 μm, and knowing that preferably, during this heat treatment said plate is kept flat on a flat surface.

[0041] According to a seventh aspect of this first subject of the invention, which can be combined with the first and / or the second and / or the third and / or the fourth and / or with the fifth and / or with the sixth aspect, said plate is an intermediate blank for the manufacture of a wafer obtained by grinding a raw blank according to the sixth aspect of this first subject.

[0042] According to an eighth aspect of this first subject of the invention, which can be combined with the first and / or the second and / or the third and / or the fourth and / or with the fifth and / or with the sixth and / or with the seventh aspect, the thickness of said plate is less than 550 pm, preferably less than 500 pm, more preferably less than 450 pm, and even more preferably between 355 pm and 420 pm.

[0043] According to a ninth aspect of this first subject of the invention, which can be combined with the first and / or the second and / or the third and / or the fourth and / or with the fifth and / or with the sixth and / or with the seventh and / or with the eighth aspect, said plate has a diameter of between 140 mm and 165 mm, a thickness of between 350 pm and 450 pm and a deformation characterized by a Warp of less than 100 pm, preferably less than 50 pm and even more preferably less than 30 pm. According to a tenth aspect of this first subject of the invention, which can be combined with the first and / or the second and / or the third and / or the fourth and / or with the fifth and / or with the sixth and / or with the seventh and / or with the eighth and / or with the ninth aspect, said plate has a thickness of between 350 pm and 400 pm.

[0044] According to an eleventh aspect of this first subject of the invention, which can be combined with the first and / or the second and / or the third and / or the fourth and / or with the fifth and / or with the sixth and / or with the seventh and / or with the eighth and / or with the ninth and / or with the tenth aspect, said plate has a diameter of between 185 mm and 210 mm, and a thickness of between 500 pm and 650 pm, preferably of between 500 pm and 600 pm.

[0045] According to a twelfth aspect of this first subject of the invention, which can be combined with the first and / or the second and / or the third and / or the fourth and / or with the fifth and / or with the sixth and / or with the seventh and / or with the eighth and / or with the ninth and / or with the tenth and / or with the eleventh aspect, said plate has a deformation characterized by a Warp of less than 70 pm, preferably less than 50 pm and even more preferably less than 40 pm.

[0046] According to a thirteenth aspect of this first subject of the invention, which can be combined with the first and / or the second and / or the third and / or the fourth and / or with the fifth and / or with the sixth and / or with the seventh and / or with the eighth and / or with the ninth and / or with the tenth and / or with the eleventh and / or with the twelfth aspect, on each of the two faces of said plate, the contribution C200 + C400 is greater than 1%, more preferably greater than 2%, and even more preferably greater than 5%.

[0047] According to a fourteenth aspect of this first subject of the invention, which can be combined with the first and / or the second and / or the third and / or the fourth and / or with the fifth and / or with the sixth and / or with the seventh and / or with the eighth and / or with the ninth and / or with the tenth and / or with the eleventh and / or with the twelfth and / or with the thirteenth aspect, said plate has a thermal conductivity greater than 250 W / (mK), preferably greater than 260 W / (mK), and more preferably greater than 270 W / (mK). According to a fifteenth aspect of this first subject of the invention, which can be combined with the first and / or the second and / or the third and / or the fourth and / or with the fifth and / or with the sixth and / or with the seventh and / or with the eighth and / or with the ninth and / or with the tenth and / or with the eleventh and / or with the twelfth and / or with the thirteenth and / or with the fourteenth aspect, said plate has been obtained by a CVD process.

[0048] According to a sixteenth aspect of this first subject of the invention, which can be combined with the first and / or the second and / or the third and / or the fourth and / or with the fifth and / or with the sixth and / or with the seventh and / or with the eighth and / or with the ninth and / or with the tenth and / or with the eleventh and / or with the twelfth and / or with the thirteenth and / or with the fourteenth and / or with the fifteenth aspect, said plate is characterized by:

[0049] An electrical resistivity of less than 5 mOhm.cm, and preferably less than 3 mOhm.cm, a doping rate, measured by SI MS, which is greater than 1 x 10 20 atoms / cm 3 , and preferably even greater than 1.5 x 10 20 atoms / cm 3, on each of its two faces, a texture coefficient C220 + C200 + C400 greater than 60%, and preferably greater than 80%, on each of its two faces, a texture coefficient C422 less than 15%, and preferably less than 10%, on each of its two faces, a contribution C200 + C400 greater than 2%, and preferably greater than 5%, a thermal conductivity greater than 260 W / (mK), preferably greater than 270 W / (mK).

[0050] According to a seventeenth aspect of this first subject of the invention, which can be combined with the first and / or the second and / or the third and / or the fourth and / or with the fifth and / or with the sixth and / or with the seventh and / or with the eighth and / or with the ninth and / or with the tenth and / or with the eleventh and / or with the twelfth and / or with the thirteenth and / or with the fourteenth and / or with the fifteenth and / or with the sixteenth aspect, said plate is characterized by:

[0051] An electrical resistivity of less than 5 mOhm.cm, and preferably less than 3 mOhm.cm, a doping rate, measured by SI MS, greater than 1 x 10 20 atoms / cm 3 , and preferably even greater than 1.5 x 10 20 atoms / cm 3 , on each of its two faces, a texture coefficient C220 + C200 + C400 greater than 80%, on each of its two faces, a texture coefficient C422 less than 15%, and preferably less than 10%, on each of its two faces, a contribution C200 + C400 greater than 5%, a thermal conductivity greater than 260 W / (mK), preferably greater than 270 W / (mK).

[0052] According to an eighteenth aspect of this first subject of the invention, which can be combined with the first and / or the second and / or the third and / or the fourth and / or with the fifth and / or with the sixth and / or with the seventh and / or with the eighth and / or with the ninth and / or with the tenth and / or with the eleventh and / or with the twelfth and / or with the thirteenth and / or with the fourteenth and / or with the fifteenth and / or with the sixteenth aspect and / or with said seventeenth aspect, said plate is characterized by the fact that it has undergone a removal of material on one and / or the other of these two faces before presenting at least one of the characteristics or properties according to the first subject of the invention or any one of its eighteen aspects.

[0053] A second subject of the invention is a method for manufacturing a beta-type polycrystalline SiC plate comprising a step of chemical vapor deposition of a layer of polycrystalline SiC on the graphite surface of a substrate comprising a graphite surface, in which a mixture of gases is introduced into a heated enclosure so as to create a gas phase comprising:

[0054] - at least one gaseous precursor of silicon and / or carbon,

[0055] - at least one doping gas comprising at least one nitrogen and / or phosphorus atom,

[0056] - a carrier gas, said gas mixture decomposing on the surface of said graphite substrate to form a layer of polycrystalline SiC on said graphite surface of said substrate, and said method being characterized in that

[0057] - the temperature in said heated enclosure is between 1450 K and 1650 K and the total partial pressure of said gaseous precursors is less than 350 mbar, and preferably less than 300 mbar,

[0058] - the chemical vapor deposition step is followed by at least one step of heat treatment of said polycrystalline SiC layer, at a temperature between 1,800°C and 2,300°C, preferably between 1,850°C and 2,200°C, more preferably between 1,900°C and 2,150°C, and even more preferably between 1,950°C and 2,150°C.

[0059] According to a first aspect of this second subject of the invention, said method is characterized in that the temperature in said heated enclosure is between 1450 K and 1650 K and the total partial pressure of said gaseous precursors is less than 300 mbar.

[0060] According to a second aspect of this second subject of the invention, which can be combined with the first aspect, the chemical vapor deposition step is followed by at least one step of heat treatment of said polycrystalline SiC plate, at a temperature between 1,900°C and 2,150°C.

[0061] According to a third aspect of this second subject of the invention, which can be combined with the first and / or the second aspect, said heat treatment is carried out at a temperature between 1950°C and 2150°C.

[0062] According to a fourth aspect of this second subject of the invention, which can be combined with the first and / or the second and / or the third aspect, said doping gas is selected from the group formed by: NH3, N2H4, N2, H2NCH3.

[0063] According to a fifth aspect of this second subject of the invention, which can be combined with the first and / or the second and / or with the third and / or with the fourth aspect, said doping gas is present in said heated enclosure in a concentration selected so as to lead in said polycrystalline SiC plate to a nitrogen or phosphorus level, measured by secondary ion mass spectroscopy, greater than 5 x 10 19 atoms / cm 3 , preferably greater than 1 x 10 20 atoms / cm 3 , and even more preferably greater than 1.5 x 10 20 atoms / cm 3 .

[0064] According to a sixth aspect of this second subject of the invention, which can be combined with the first and / or the second and / or the third and / or the fourth and / or the fifth aspect, during this heat treatment, the plate or the raw blank is kept flat on a flat surface.

[0065] According to a seventh aspect of this second subject of the invention, which can be combined with the first and / or the second and / or the third and / or the fourth and / or the fifth and / or the sixth aspect, said raw blank or plate has been freed, before or after said heat treatment, at least on its face which was in contact with a growth substrate, of a material thickness of at least 100 μm.

[0066] According to an eighth aspect of this second subject of the invention, a SiC wafer having been manufactured by the chemical vapor deposition method according to the second subject of the invention is supplied, or such a wafer is manufactured by said chemical vapor deposition method, said supplied or manufactured wafer having, on each of its two faces, optionally measured after removal of a material thickness of at least 100 μm, a texture coefficient C422 of less than 30% and a texture coefficient C220 of greater than 60%, and said heat treatment is carried out according to the second subject of the invention, knowing that this eighth aspect of this second subject of the invention can be combined with the first and / or the second and / or the third and / or the fourth and / or the fifth aspect and / or the sixth aspect and / or the seventh aspect of this second subject of the invention.

[0067] Figures

[0068] Figures 1 to 8 illustrate different aspects of the invention.

[0069] [Fig. 1] schematically shows the measurement of the parameter called “Warp” which expresses a particular aspect of the flatness defect of a semiconductor wafer.

[0070] [Fig. 2] shows schematically and simplified a vertical cross-section through a reactor according to the invention which makes it possible to manufacture a blank for a polycrystalline SiC substrate according to the invention.

[0071] [Fig. 3] refers to Example 1 and shows an image obtained by backscattered electron scanning electron microscopy of a cross-section of a p-SiC plate obtained by a CVD process outside the invention, before heat treatment at 2000 °C. The white bar at the bottom right indicates a length of 100 pm.

[0072] [Fig. 4] refers to Example 1 and shows a backscattered electron scanning electron microscopy image of a cross-section of a p-SiC plate obtained by a CVD process outside the invention, after heat treatment at 2000 °C. The white bar at the bottom right indicates a length of 100 pm. The sample comes from a p-SiC plate obtained at the same time (same reactor, same experimental conditions, same test) as the one from which the sample in Figure 3 was derived. [Fig. 5] refers to Example 2 and shows a backscattered electron scanning electron microscopy image of a cross-section of a p-SiC plate obtained by a CVD process outside the invention, before heat treatment at 2000 °C. The white bar at the bottom right indicates a length of 100 pm.

[0073] [Fig. 6] refers to Example 2 and shows an image obtained by backscattered electron scanning electron microscopy of a cross-section of a p-SiC plate obtained by a CVD process outside the invention, after heat treatment at 2000 °C. The white bar at the bottom right indicates a length of 100 pm. The sample comes from a p-SiC plate obtained at the same time (same reactor, same experimental conditions, same test) as the one from which the sample in Figure 5 was derived.

[0074] [Fig. 7] refers to Example 3 and shows an image obtained by backscattered electron scanning electron microscopy of a cross-section of a p-SiC plate obtained by a CVD process according to the invention, before heat treatment at 2000 °C. The white bar at the bottom right indicates a length of 100 pm.

[0075] [Fig. 8] refers to Example 3 and shows an image obtained by backscattered electron scanning electron microscopy of a cross-section of a p-SiC plate obtained by a CVD process outside the invention, after heat treatment at 2000 °C. The white bar at the bottom right indicates a length of 100 pm. The sample comes from a p-SiC plate obtained at the same time (same reactor, same experimental conditions, same test) as the one from which the sample in Figure 7 was obtained.

[0076] [Fig. 9] shows a diffractogram obtained with X-ray radiation of wavelength 1.5406 Angstrom on a beta-type polycrystalline SiC plate obtained according to the invention by the CVD process, before heat treatment. Figures a), b), c), d), e) and f) show different 2theta angle zones, and the scale of the vertical axis may differ from one figure to another, to show the low intensity peaks.

[0077] [Fig. 10] shows the same type of diffractogram as [Fig. 9], for the same plate as that of [Fig. 9], but after heat treatment according to the invention.

[0078] Detailed description

[0079] The term "plate" should be understood here in its broadest sense, which includes in particular the objects designated below as "raw blank", "heat-treated raw blank", "intermediate blank" and "slice" (or "wafer"). These objects have a generally flat shape.

[0080] Those skilled in the art of semiconductor substrates for microelectronics know the different ways to characterize the overall flatness of wafers: these different parameters are known by the terms or acronyms Bow (the distance between the surface and the plane corresponding to the best fit in the center of the unfixed wafer, see standard ASTM F534 “Standard Test Method for Bow of Silicon Wafers” point 3.1.2), Warp (the sum of the maximum positive and negative deviations from the plane corresponding to the best fit for an unfixed wafer, see standard ASTM F1390 “Standard test Method for Measuring Warp on Silicon Wafers by Automated Non-Contact Scanning”), TTV (Total Thickness Variation, i.e.the difference between the maximum and minimum thickness values ​​for a fixed wafer, see ASTM F657 “Standard Test Method for Measuring Warp and Total Thickness Variation on Silicon Slices and Wafers by a Non-contact Scanning Method”), TIR (Total Indicated Reading, i.e. the sum of the maximum positive and negative deviations from the plane corresponding to the best fit for a fixed wafer), SRAD (Spherical Reference Measurement, expressing a radius of curvature for the sphere corresponding to the best fit); other acronyms express parameters to characterize the local flatness of wafers, in particular: LFPD (Local Focal Plane Deviation, i.e. the maximum distance between the wafer surface and the plane corresponding to the best fit (above or below the surface of the unfixed wafer), for a given area) and LTV (Local Thickness Variation, i.e.the difference between the maximum and minimum values ​​of unfixed wafer thickness, for a given area).

[0081] In the context of the present invention, the flatness of the wafers is characterized by the parameter commonly called "Warp". This parameter refers to the algebraic difference of the deviations of the wafer with respect to a reference plane. Figure 1 schematically illustrates the determination of this parameter from a surface profile by the algebraic difference of the ordinates B and C of the disc placed on a base plane.

[0082] One could also determine from the surface profile a median plane (typically by using an algorithm implementing a least squares method) and calculate the Warp from the deviations from the median plane which gives the same result as long as the median plane is parallel to the base plane. If the median plane is not parallel to the base plane then the measurement method with respect to the base plane increases that with respect to the median plane. We now describe a new process for depositing a rough beta-type p-SiC blank which contributes to the solution of the problem posed.

[0083] This deposition method represents the first step of a method for manufacturing a polycrystalline SiC wafer according to the invention. It uses the chemical vapor deposition (CVD) technique, which is implemented in a heated enclosure. The method involves a gas mixture comprising at least one silicon precursor gas (such as a silane or a chlorosilane) and / or at least one carbon precursor gas (such as an alkane or an alkene), and / or at least one silicon and carbon precursor gas (such as methyltrichlorosilane, abbreviated MTCS), and at least one doping gas comprising nitrogen (for example NH3, N2H4, N2) and / or phosphorus. Said doping gas may also be a carbon and / or silicon precursor (for example an amine such as H2NCH3). These gases may be diluted in a carrier gas, which may be a reducing gas such as hydrogen and / or an inert gas such as argon.

[0084] By way of example, a gaseous composition for implementing the method according to the invention may comprise a carbon precursor, a silicon precursor, a doping gas, the carrier gas. Another example is a gaseous composition which comprises a silicon and carbon precursor, a silicon precursor, a carbon precursor, a doping gas, the carrier gas.

[0085] In a particular embodiment of this deposition method, said gas phase comprises trichloromethylsilane, and preferably does not comprise other silicon and / or carbon precursors. Said doping gas is advantageously selected from the group formed by: NH3, N2H4, N2, H2NCH3.

[0086] This gas mixture is introduced into a high-temperature reactor where the precursor gases are decomposed and react on the surface to form the 3C-SiC polytype. This material is particularly suitable for combination with a monocrystalline SiC layer, due to its mechanical and thermal resistance properties, its compatibility with thermal expansion and its purity. It can also be doped with nitrogen up to very high levels, typically 10 20 atoms / cm 3and have a resistivity much lower than 20 Ohm. cm, without degradation of the quality of the substrate which would be detrimental to the manufacture of power components. Finally, it is a material capable of subsequently withstanding the high temperature processes that the wafer will have to undergo during the manufacture of the electronic component. The temperature of the reactor during CVD deposition of SiC must be between approximately 1,300 K and approximately 1,800 K, and preferably between approximately 1,350 K and approximately 1,700 K, more preferably between approximately 1,400 K and approximately 1,650 K, and even more preferably between approximately 1,450 K and approximately 1,650 K. The total pressure in the reactor advantageously does not exceed 350 mbar, and preferably does not exceed 300 mbar.

[0087] In an advantageous embodiment of the method for manufacturing the p-SiC plate according to the invention, the deposition is carried out by the CVD route on a graphite surface of a substrate comprising a graphite surface. Very advantageously, said substrate is a fine-grained and purified isostatic graphite substrate, this to avoid any contamination and degassing of impurities during the deposition. For example, to obtain a wafer with a diameter of 150 mm, the deposition is carried out on a disc-shaped graphite cylinder, with a diameter approaching a nominal of 150 mm and a thickness greater than 2 mm to ensure sufficient flatness of the substrate. The reactor may comprise a plurality of these discs, the diameter of which may be identical or different. The two faces of the discs preferably have a flatness < 15 μm, obtained by sufficiently precise machining.The coefficient of thermal expansion of isostatic graphite is carefully chosen to be compatible with the SiC layer during cooling after deposition. A substrate marketed by MERSEN under the designation “grade 2303” can be used.

[0088] The progress of a typical embodiment of this method for depositing a rough blank that can be used to produce a p-SiC plate according to the invention is now described, and a reactor in which this deposition method can be carried out is first described in relation to FIG. 2, by way of example. This deposition method takes place in a reactor 1 of a particular type. It comprises a reaction chamber 2, which contains a reaction space 3, a heating space 4 and a reaction gas discharge space 5. Said chamber 2 is designed to be able to reach low pressures down to a minimum of a few tens of millibar by pumping the gases to an effluent treatment device (not shown in the figure). The precursor gases are admitted into the reaction space 3 of the reactor 1 through a plurality of injectors 11 supplied by a gas line 8 called the precursor gas inlet.The reaction gases leave the reaction space 3 towards the discharge space 5, from where they are sucked through an outlet nozzle 10 into the gas line 9 called the reaction gas outlet. The heating space 4 comprises a plurality of heating elements 6, typically solenoids. Graphite cylinders or discs 12, also called substrates here, are loaded into the enclosure 2; for simplicity, Figure 2 does not show the supports which hold said substrates 12 in the reactor 1.

[0089] The deposition chamber 2 is heated by induction of a magnetic field in a graphite susceptor 7 inside which the precursor gases (for example silanes, alkanes and / or methylchlorosilanes), the carrier gases (for example hydrogen and / or argon), the doping gas (for example NH3, amines and / or N2) will circulate. The graphite substrates 12 are in thermal equilibrium inside the reaction space 3 heated by the susceptor 7 at a temperature generally between 1300 K and 1700 K (measured by a thermocouple), and more preferably between 1350 K and 1650 K. The gas mixture is introduced by nozzles or injectors 11 allowing a homogeneous distribution of the gas flow in the enclosure 2. In this temperature range, the deposition rates can vary within fairly wide ranges, from pm / h to more than 100 pm / h.The total partial pressure of said gaseous precursors is advantageously less than 350 mbar, and preferably less than 300 mbar.

[0090] To achieve a minimum p-SiC deposition thickness of approximately 600 μm, the gas injection time can vary from a few hours to several tens or even hundreds of hours depending on the conditions chosen. The control parameters indicated above can be adjusted to obtain the product according to the invention, as will be explained in greater detail in relation to the examples. Thus, it is possible to obtain high-quality p-SiC plates at economically satisfactory conditions, allowing them to be used in electronic applications substituting monocrystalline SiC produced by the traditional PVT process.

[0091] When the target thickness for deposition on the surface of the graphite substrate 12 is reached, the injection of precursor gases into the furnace is stopped and the enclosure is cooled to room temperature to be discharged. The graphite discs 12 coated with a thick layer of SiC deposit are then machined, then oxidized in air, typically at 900°C, to remove any graphite residue. A raw SiC disc is recovered for each face.

[0092] The deformation of the disc, raw blank, is measured using a white light confocal sensor that scans the surface of the SiC disc that was in contact with the graphite. To perform this measurement, the face of the disc on the CVD deposition side is placed on a support. The difference between the maximum and minimum elevation of the surface scanned by the sensor relative to the support plane of the measuring tool is measured. The graphite-side surface was a flat reference before being detached from the graphite. After detachment from the graphite, this surface becomes warped due to the stress relaxation of the deposited layer. This warped surface can be interpolated by a median plane, using the least squares method. If this median plane is parallel to the support plane, the deformation measurement is equal to the warp. This method of measuring the deformation increases the warp measurement in the general case.

[0093] The raw blank resulting from the deposition process which has just been described has (possibly after having been stripped, at least on its face which was in contact with the growth substrate, of a material thickness of approximately 100 μm or more), particular crystallographic characteristics, namely a preferential crystalline orientation which is characterized on each of its two faces by:

[0094] (i) its texture coefficient C422 is less than 40%, and

[0095] (ii) its texture coefficient C220 is greater than 50%, and preferably greater than 80%.

[0096] Preferably, its texture coefficient C422 is less than 30% and its texture coefficient C220 is greater than 70%. Even more preferably, its texture coefficient C422 is less than 30% and its texture coefficient C220 is greater than 80%.

[0097] As we have just seen, the method for manufacturing a p-SiC plate according to the invention comprises a first step in which silicon carbide is deposited from a vapor phase on the graphite surface of a substrate having a graphite surface, to obtain a raw blank of polycrystalline silicon carbide (abbreviated here as "p-SiC"), having a first thickness.

[0098] According to an essential characteristic of the invention, this rough blank is subjected to a specific heat treatment. The heat treatment method according to the invention is described here.

[0099] In a second step, the said rough blank is subjected to a heat treatment of between 1,800°C and 2,300°C, to obtain a heat-treated rough blank; it is always polycrystalline silicon carbide. During this heat treatment, the rough blank is advantageously kept flat on a flat surface.

[0100] In a third step, said heat-treated rough blank is subjected to a grinding treatment on both sides, to obtain an intermediate blank made of polycrystalline silicon carbide with a second thickness. This grinding treatment takes place in several sub-steps; it is known as such.

[0101] The second and third stages can be interchanged, and the heat treatment can also be carried out on a partially ground blank, so that the third stage is carried out partly before the second stage and partly after the second stage.

[0102] This intermediate blank can be transformed by various polishing steps (which will possibly be preceded by one or more fine grinding steps) into a polycrystalline SiC wafer ready to receive a deposit of a thin layer of monocrystalline silicon carbide (hereinafter referred to as "m-SiC"), in particular by layer transfer techniques. These polishing steps and this deposit of a thin layer of m-SiC are known as such and are not part of the present invention.

[0103] According to an essential technical characteristic of the invention, the blank, which may be a raw blank or an intermediate blank, is subjected to a specific heat treatment, which has been identified above as the “second step” of the method according to the invention, and which will now be described in greater detail. This specific heat treatment leads to a specific modification of the size of the grains and their crystallographic orientation, which is only observed in the case where the raw or intermediate blank made of p-SiC has certain specific crystallographic characteristics. More particularly, this heat treatment is carried out at a temperature between 1,800°C and 2,300°C, preferably between 1,850°C and 2,200°C, more preferably between 1,900°C and 2,150°C, and even more preferably between 1,950°C and 2,150°C.Its duration is advantageously at least 10 minutes, and is advantageously between about 1 hour and about 12 hours, and preferably between about 2 hours and about 9 hours. Too long a duration can lead to unwanted recrystallization, with too short a duration the heat treatment can be ineffective. Typically, to carry out this heat treatment the blank is loaded into a furnace at room temperature or warm, and the furnace is heated to the desired temperature, then maintained at this temperature, and finally allowed to cool, to unload the furnace at room temperature or warm; the treatment times indicated then relate to the temperature zone indicated, and not to the total duration of the thermal cycle.

[0104] By means of this specific heat treatment, a rough or intermediate rough of p-SiC of the beta type can be obtained, which has favorable crystallographic characteristics. More precisely, the rough or intermediate rough of p-SiC treated with heat has a preferential crystal orientation which is characterized in that on each of its faces:

[0105] (i) its texture coefficient C422 is less than 40%, and

[0106] (ii) its texture coefficient C220 + C200 + C400 is greater than 50%, and preferably greater than 80%.

[0107] Preferably, the C200 + C400 contribution is greater than 1%, more preferably greater than 2%, and even more preferably greater than 5%. It is this C200 + C400 contribution to the crystallographic orientation characterized by a very dominant C220 texture which is generated by the heat treatment to which the raw blank is subjected in said second step.

[0108] Advantageously, after this heat treatment called here "second step", said raw or intermediate blank has on each of its two faces a texture coefficient C422 which is less than 20%, preferably less than 15%, and even more preferably less than 10%. It may be for example a raw blank which has been stripped, before or after said heat treatment, at least on its face which was in contact with a growth substrate, of a material thickness of at least 100 μm.

[0109] Generally speaking, the heat treatment indicated above does not lead to the appearance of an alpha phase. Without wishing to be bound by this hypothesis, the inventors believe that in the case of doped SiC, it is the presence of doping elements which blocks the transformation of beta-type polycrystalline SiC into alpha-type polycrystalline SiC.

[0110] The applicant has found that the heat treatment indicated above only leads to a rough blank having these favorable crystallographic characteristics on both of its faces in the case where the rough or intermediate blank before heat treatment had certain specific crystallographic characteristics, namely, on at least one of its faces, (i) a texture coefficient C422 which is less than 30%, and (ii) a texture coefficient C220 which is greater than 60%, and preferably greater than 80%.

[0111] Heat treatment of such a blank first leads to a rearrangement of crystallographic defects at the grain boundaries (which leads to the relaxation of residual stresses at the grain boundaries), then to recrystallization by nucleation at the grain boundaries, followed by coarsening of these grains. Thus, the initial grain size can influence the microstructure obtained after heat treatment. The inventors found that this is not, however, sufficient to explain the difference in behavior between samples whose physical properties and flatness improve during heat treatment and those which do not show significant improvement.The nature of the crystallographic defects is also decisive: to facilitate recrystallization that effectively relaxes stresses, small grains must be bordered by high-angle grain boundaries (HAGBs). These high-angle grain boundaries contain particularly high stored energy and are therefore more mobile than low-angle grain boundaries. Their internal energy is the driving force for the rearrangement of the grain boundary defects. In the process according to the invention, it is the particular texture of the blank subjected to heat treatment that ensures the presence of such high-angle grain boundaries.

[0112] Empirically, the grains may have an average diameter (measured in a plane perpendicular to the z axis, for example by EBSD) greater than or equal to 5 pm, in particular greater than or equal to 10 pm, or even 20 pm or 50 pm in certain support substrates 20 after the aforementioned heat treatment. In particular, the grains of orientation (200) and (400) have an average diameter greater than or equal to 5 pm, in particular greater than or equal to 10 pm, or even 20 pm or 50 pm, as a result of the heat treatment which causes the coalescence and recrystallization of certain grains of orientation (220).

[0113] When measuring the average diameter of a grain, it is considered that different crystals forming one or more twins constitute a single grain and not separate grains. Thus, the size of the grains tends to increase during heat treatment, their average diameter being able to be multiplied by at least 2, frequently by 5 or even by 10 or 50, depending on the conditions and duration of the heat treatment. This is particularly the case for grains of orientation (220), which prove to have a greater tendency to coalescence and recrystallization than in particular grains (422). Thus, raw discs whose microstructure has a C422 texture coefficient of less than 40% and a sum of texture coefficients C22o+C2oo+C4oo greater than 50% prove to be particularly sensitive to heat treatments.However, the increase in grain size during heat treatment is correlated with an increase in thermal conductivity, which therefore makes it possible to achieve high thermal conductivity values, which are preferably greater than 250 W / (mK), more preferably greater than 260 W / (mK), and even more preferably greater than 270 W / (mK). The coalescence of neighboring grains also significantly changes their morphology, since CVD growth tends to be highly oriented along the direction of the raw disc thickness, with grains before heat treatment extending mainly along the Z axis visible in Figure 7. As visible in Figure 8, the heat treatment results in the appearance of grains with very different morphology.

[0114] In particular, the raw disc or support substrate comprises grains having an aspect ratio, defined as being the ratio between, in the numerator, the length of the grain along the Z axis and, in the denominator, the diameter of the grain along a direction perpendicular to the Z axis, less than or equal to 10, in particular less than or equal to 5, in particular less than or equal to 3. In particular, at least 5% of the grains have such an aspect ratio.

[0115] The heat-treated rough blank can then be ground to obtain an intermediate rough blank; this is the subject of the third step mentioned above. This grinding has two aims: firstly, it represents a necessary step to be able to proceed with the polishing of the surface, in order to prepare it for the deposition of a layer of m-SiC, this deposition being able to be carried out in particular by a layer transfer technique. Secondly, the grinding (which typically proceeds by successive removal of material on both faces of the rough blank) makes it possible to obtain a p-SiC slice at the final thickness, which has a high flatness.

[0116] The intermediate blank advantageously has a thickness close to the final thickness targeted for the p-SiC wafer ready to receive the m-SiC layer (such a polished wafer being commonly called a “wafer”), which subsequently allows it to be used, on this m-SiC face, as a substrate for the deposition of microelectronic circuits according to the usual manufacturing techniques in this field.

[0117] More specifically, the thickness of said intermediate blank is advantageously less than 550 pm, preferably less than 500 pm, more preferably less than 450 pm, and even more preferably between 355 pm and 420 pm.

[0118] Such an intermediate blank, and in the same way a polished wafer, have all the crystallographic characteristics indicated above, namely a preferential crystalline orientation which is characterized in that on each of its faces: (i) its texture coefficient C422 is less than 40%, and (ii) its texture coefficient C220 + C200 + C400 is greater than 50%, and preferably greater than 80%.

[0119] Preferably, the C200 + C400 contribution is greater than 1%, more preferably greater than 2%, and even more preferably greater than 5%. Advantageously, said polished wafer has on each of its two faces a texture coefficient C422 which is less than 20%, preferably less than 15%, and even more preferably less than 10%.

[0120] According to one aspect of the invention, the method according to the invention makes it possible to obtain a polycrystalline SiC plate which has an electrical resistivity of less than 10 mOhm.cm, preferably less than 5 mOhm.cm, and even more preferably less than 3 mOhm.cm.

[0121] According to another aspect of the invention, the method according to the invention makes it possible to obtain a polycrystalline SiC plate which is doped with nitrogen with a nitrogen content, measured by secondary ion mass spectroscopy, greater than 5 x 10 19 atoms / cm 3 , preferably greater than 1 x 10 20 atoms / cm 3 , and even more preferably greater than 1.5 x 10 20 atoms / cm 3 .

[0122] Without wishing to be bound by this theory, the inventors believe that the heat treatment of the plate allows, among other things, a better diffusion of the nitrogen dopant, and leads to an incorporation of nitrogen atoms in the crystallographic network which is electronically more efficient.

[0123] In a first advantageous embodiment, such a p-SiC plate, which may typically be an intermediate blank or a polished wafer, has a diameter of between 140 mm and 165 mm, a thickness of between 350 μm and 450 μm and a deformation characterized by a Warp of less than 50 μm, preferably less than 40 μm and even more preferably less than 30 μm. Preferably, such a plate has a thickness of between 350 μm and 400 μm.

[0124] In a second advantageous embodiment, such a p-SiC plate, which may typically be an intermediate blank or a polished wafer, has a diameter of between 185 mm and 210 mm, a thickness of between 500 μm and 650 μm and a deformation characterized by a warp of less than 70 μm, preferably less than 50 μm and even more preferably less than 40 μm. Preferably, such a plate has a thickness of between 500 μm and 600 μm. Examples

[0125] Examples 1 to 3 illustrate certain aspects of the invention, but do not limit its scope.

[0126] In these examples, diffraction peaks were collected by an X-ray diffractometer of the PANalytical X'Pert PRO MPD type using the 0-20 method over an angle range of 10° to 135° (scale 2 0). Over this range, the ten diffraction peaks shown in Table 1 were considered for 3C SiC, classified according to increasing Miller indices (hkl); these diffraction peaks are characteristic of beta-type SiC.

[0127] Table 1: Diffraction peaks taken into account

[0128] A texture coefficient Chki (for N=10 peaks) is calculated from the intensity of peak l h ki proportional to the area under the peak of the sample and the theoretical intensity l 0 h ki of a powder which can be obtained from the theoretical % published by the ICDD (International Centre for Diffraction Data). Chkl = (Ihkl / lo hkl) / (1 / N x (I hkl / lo hkl)) •

[0129] The texture coefficient in this case varies over a range from 0 to 10. It can also be expressed in %. It allows quantifying the average preferential orientation of the crystallites of the deposited layer relative to the normal to the surface of the sample. In these examples, the carbon source and the silicon source were the same molecule, namely methyl trichlorosilane (abbreviated MTCS). The nitrogen source doping gas was NH3. By modifying the few key parameters of the CVD process (temperature, partial pressure of the precursor, % of doping gas). It is possible to change the orientation of the deposited layer and its texture. This will have an impact on the intrinsic stress gradient of the deposit, making it possible to obtain a Warp on the raw blank consistent with the objective.

[0130] Example 1: Texture with mostly coarse grains oriented (422) mostly mixed with a fine texture of small grains oriented (220)

[0131] An intermediate p-SiC blank was prepared by grinding and polishing from a raw blank obtained by a CVD process outside the invention. To prepare the raw blank, an 800 μm layer was deposited on a graphite substrate at a temperature of 1600 K, a partial pressure of 16 mbar of MTCS and a molar fraction of NH3 of 6%.

[0132] Figures 3 and 4 show two images obtained by scanning electron microscopy of backscattered electrons of a cross-section, before (Figure 3) and after (Figure 4) a heat treatment at 2000 °C. In each of these figures the white bar indicates a length of 100 pm.

[0133] Before the heat treatment according to the invention, during which the blank was kept flat on a flat surface, the intermediate blank shows an orientation characterized by a dominant texture coefficient C422, presenting very large grains oriented according to the texture coefficients gathered below:

[0134] Ci ii +C222 + C5n = 20%; C220 = 7%; C422 = 54%.

[0135] Figure 3 shows very large grains oriented (422) predominantly or (111) minorly, conical in shape with diameters up to 100 μm. A few small grains (220) smaller than 10 μm are very much in the minority. Figure 3 shows a continuous growth in grain diameter over the first 500 microns. This growth in grain size can be evaluated for each ordinate of the reference frame by counting the number of intersections of a horizontal line of constant ordinate with the grain boundaries on the EBSD image. After a heat treatment according to the invention, during which the blank was kept flat on a flat surface, no significant change in the microstructure and grain orientation is observed.

[0136] On the raw blank before heat treatment, the deposit obtained contains a nitrogen concentration measured by SI MS (Secondary Ion Mass Spectroscopy) of 6.8 x 10 20 nitrogen atoms per cm 3 and an electrical resistivity measured at 0.9 mOhm.cm by the 4-point method, well below the targeted upper limit. The deformation measured on the raw wafer is very significant with a Warp of 580 pm. The thermal conductivity of the layer is also deduced by a thermal diffusivity measurement using the laser flash method. We obtain 130 W / m / K which is below the targeted objective. After heat treatment, the Warp and internal stresses remain high, and the electrical resistivity and thermal conductivity hardly change.

[0137] This example shows that the heat treatment according to the invention does not lead to an improvement in the crystallographic and physical properties when the initial texture of the blank before heat treatment has a dominant C422 texture. A significant number of wafers were produced according to this example; out of a total of 16 discs produced, the average deformation is 630 pm with a standard deviation of 153 pm. It is concluded that it will not be possible to produce a p-SiC wafer by grinding from a raw disc with a thickness of less than 1000 pm.

[0138] After several deposits under these conditions, the observed texture remains preferentially oriented (422) with the texture coefficient C422 > 50% and Cin+C222 + C5n > 15% and C220 < 10%.

[0139] Example 2:

[0140] An intermediate p-SiC blank was prepared by grinding and polishing from a raw blank obtained by a CVD process outside the invention. To prepare the raw blank, a p-SiC layer with a thickness of approximately 800 μm was deposited on a flat graphite substrate by operating the CVD reactor at a temperature of 1530 K, a partial pressure of 12 mbar of MTCS and a molar fraction of NH3 of 5%.

[0141] Figures 5 and 6 show two images obtained by scanning electron microscopy of backscattered electrons of a cross-section, before (see Figure 5) and after (see Figure 6) a heat treatment at 2000 °C according to the invention, during which the blank was held flat on a flat surface. In each of these figures the white bar indicates a length of 100 pm.

[0142] A preferentially oriented texturing (220) was observed with the following texture coefficients: Cin+C222 +C5n = 2%; C220 = 90%; C422 = 3%.

[0143] The layer contained a nitrogen concentration, measured by SIMS, of 2.7 x 10 20 nitrogen atoms per cm 3 , and had an electrical resistivity of 10 mOhm.cm, measured by the four-point method. The thermal conductivity, deduced from a thermal diffusivity measurement using the laser flash method, was 130 W / m / K. This value was below the target; the tree-like texture no longer appears to promote good thermal conductivity, being barely visible in the lower part of the section.

[0144] The deformation measured on the raw blank without heat treatment is low. On a total of 16 wafers produced, the average deformation was 160 pm, with a standard deviation of 85 pm. This would allow the fabrication of wafers for p-SiC wafers from a raw disc with a thickness of less than 1000 pm at a reasonable cost.

[0145] However, the texture is inhomogeneous in depth at the start of growth, which is evident when the face of the plate which was in contact with the graphite surface of the growth substrate is characterized by X-ray diffraction, by carrying out successive rectification steps: the face on the substrate side is very predominantly oriented (111)+(222)+(511) over a very significant depth, which does not allow this inhomogeneous zone to be removed in depth by rectification under reasonable economic conditions.

[0146] After heat treatment on the intermediate blank with a thickness of approximately 400 μm (see Figure 6), a very significant growth in grain size is also observed on the upper part of the section, preferentially oriented (220). On the other hand, the lower part of the section representing the substrate face, still preferentially oriented (111)+(222)+(511), does not show any change in grain size due to the heat treatment.

[0147] This observed grain size inhomogeneity is highly detrimental. We thus observe that the Warp of this intermediate blank degrades beyond 250 pm in most cases, making it impossible to obtain a wafer with a Warp conforming to the objective. Example 3: Fine grain texture oriented (220)

[0148] An intermediate p-SiC blank was prepared by grinding and polishing from a raw blank obtained by a CVD process according to the invention. To prepare the blank, an 800 μm layer was deposited on a graphite substrate by operating at a temperature of 1550 K, a partial pressure of 15 mbar of MTCS and a molar fraction of NH3 of 4%. The orientation observed before said heat treatment is a preferentially oriented (220) texturing with texture coefficients gathered below:

[0149] Ciii+C222 + C5ii = 2%; C220 = 91%; C422 = 4%

[0150] The C200 + C400 contribution was zero.

[0151] The layer contained a nitrogen concentration measured by SIMS of 1.8 x 10 20 nitrogen atoms per cm 3and an electrical resistivity measured at 10 mOhm.cm by the 4-point method. The thermal conductivity of the layer is deduced by a thermal diffusivity measurement using the laser flash method. We obtain 240 W / m / K which is above the target. Despite small grains, the tree-like texture seems to promote good thermal conductivity, despite high doping.

[0152] The deformation measured on the raw blank before annealing is also very good. On a total of 16 discs produced, the average deformation is 210 pm with a standard deviation of 82 pm. This makes it possible to produce p-SiC wafers by grinding from a raw disc with a thickness of less than 1,000 pm at a reasonable cost.

[0153] After several deposits under these conditions, the observed texture is very preferentially oriented (220) with the texture coefficient C220 > 90% and C422 < 10%.

[0154] An intermediate p-SiC blank was prepared by grinding and polishing from a rough blank obtained by a CVD process according to the invention. Figures 7 and 8 show images obtained by backscattered electron scanning electron microscopy of a cross-section of the rough blank before heat treatment (see Figure 7) and of the intermediate blank after (see Figure 8) heat treatment at 2000 °C. In each of these figures the white bar indicates a length of 100 μm.

[0155] The raw blank showed a dominant C220 texture coefficient, with a significant (111) component close to the interface with the graphitic surface on which the blank was deposited. This thickness of the raw blank rich in Cm texture was removed by grinding during the manufacture of the intermediate blank. After a heat treatment according to the invention, during which the blank was kept flat on a plane surface, a significant evolution of the microstructure and grain orientation is observed: the small grains of (220) orientation tend to coalesce and a mixed orientation (111) + (220) + (200) is obtained. Few small grains of (111) orientation are observed. The C200 + C400 contribution appears after the heat treatment; it is equal to 5% after heat treatment.

[0156] The warp decreases due to the heat treatment and is within the specification, which coincides with a more uniform distribution of the grain size in the thickness of the intermediate blank. The electrical resistivity decreases to 1.2 mOhm.cm and the thermal conductivity increases to 270 W / m / K. This example is in accordance with the invention.

[0157] Example 4: Verification of the crystallographic structure

[0158] The crystallographic structure of a plate referenced BJ2-22-19-3G was compared before and after heat treatment according to the invention (in this case at approximately 2,000°C for a duration of between approximately 1 h and approximately 10 h). This plate relates to example 3.

[0159] [Fig. 9] shows the diffractogram before heat treatment, [Fig. 10] after heat treatment. In each of these figures, the diffractogram is first shown in its full width, see [Fig. 9a] and [Fig. 10a], then by 2theta segment using an intensity factor scale adapted to the different peaks, which may be different from one 2theta segment to another. The vertical bars represent the indexing of the peaks.

[0160] In the plate before heat treatment, we note the presence of two low intensity peaks representing stacking faults of the 3C polytype. These peaks (around 33.5° to 33.9° - see [Fig. 9b] and 65.3° with two satellites around 64.6° and 65.9° - see [Fig. 9d]) disappear after heat treatment. We do not see any peak characteristic of alpha-type SiC, either before or after heat treatment.

Claims

Claims 1. Polycrystalline beta-type SiC plate having a preferential crystalline orientation, said plate being characterized in that on each of its faces: (i) its texture coefficient C422 is less than 40%, and (ii) its texture coefficient C220 + C200 + C400 is greater than 50%, and preferably greater than 80%.

2. Polycrystalline SiC plate according to claim 1, characterized in that its electrical resistivity is less than 10 mOhm.cm, preferably less than 5 mOhm.cm, and even more preferably less than 3 mOhm.cm.

3. Polycrystalline SiC plate according to any one of claims 1 to 2, characterized in that it is doped with nitrogen with a nitrogen content, measured by secondary ion mass spectroscopy, greater than 5 x 10 19 atoms / cm 3 , preferably greater than 1 x 10 20 atoms / cm 3, and even more preferably greater than 1.5 x 10 20 atoms / cm 3 .

4. Polycrystalline SiC plate according to any one of claims 1 to 3, characterized in that on each of its two faces its texture coefficient C422 is less than 20%, preferably less than 15%, and even more preferably less than 10%.

5. Polycrystalline SiC plate according to any one of claims 1 to 4, doped with nitrogen with a nitrogen content, measured by secondary ion mass spectroscopy, greater than 5 x 10 19 atoms / cm 3 , said plate having an electrical resistivity of less than 5 mOhm.cm and a preferential crystalline orientation, and said plate being characterized in that on each of its two faces: (i) its texture coefficient C422 is less than 20%, and (ii) its texture coefficient C220 + C200 + C400 is greater than 60%, and preferably greater than 80%.

6. Polycrystalline SiC plate according to any one of claims 1 to 5, characterized in that it is a raw blank resulting from a vapor deposition process, which has undergone at least one heat treatment step at a temperature between 1,800 °C and 2,300 °C, preferably between 1,850 °C and 2,200 °C, more preferably between 1,900 °C and 2,150 °C, and even more preferably between 1,950 °C and 2,150 °C, knowing that, before or after said heat treatment, said raw blank has been stripped, at least on its face which was in contact with a growth substrate, of a material thickness of at least 100 μm, and knowing that preferably, during this heat treatment, said plate is kept flat on a flat surface.

7. Polycrystalline SiC plate according to any one of claims 1 to 5, characterized in that it is an intermediate blank for the manufacture of a wafer obtained by grinding a raw blank according to claim 6.

8. Polycrystalline SiC plate according to claim 7, characterized in that its thickness is less than 550 pm, preferably less than 500 pm, more preferably less than 450 pm, and even more preferably between 355 pm and 420 pm.

9. Polycrystalline SiC plate according to any one of claims 1 to 8, characterized in that it has a diameter of between 140 mm and 165 mm, a thickness of between 350 pm and 450 pm and a deformation characterized by a Warp of less than 100 pm, preferably less than 50 pm and even more preferably less than 30 pm.

10. Polycrystalline SiC plate according to claim 9, characterized in that it has a thickness of between 350 pm and 400 pm.

11. Polycrystalline SiC plate according to any one of claims 1 to 7, characterized in that it has a diameter of between 185 mm and 210 mm, a thickness of between 500 pm and 650 pm, preferably between 500 pm and 600 pm, and in that it has a deformation characterized by a Warp of less than 70 pm, preferably less than 50 pm and even more preferably less than 40 pm.

12. Polycrystalline SiC plate according to any one of claims 1 to 11, characterized in that the C200 + C400 contribution is greater than 1%, more preferably greater than 2%, and even more preferably greater than 5%.

13. Polycrystalline SiC plate according to any one of claims 1 to 12, characterized in that it has a thermal conductivity greater than 250 W / (mK), preferably greater than 260 W / (mK), and more preferably greater than 270 W / (mK).

14. Polycrystalline SiC plate according to any one of claims 1 to 13, characterized in that it was obtained by a CVD process.

15. Polycrystalline SiC plate according to any one of claims 1 to 14, characterized in that it has: an electrical resistivity of less than 5 mOhm.cm, and preferably less than 3 mOhm.cm, a doping rate, measured by SI MS, which is greater than 1 x 10 20 atoms / cm 3 , and preferably even greater than 1.5 x 10 20 atoms / cm 3, on each of its two faces, a texture coefficient C220 + C200 + C400 greater than 60%, on each of its two faces, a texture coefficient C422 less than 15%, and preferably less than 10%, on each of its two faces, a contribution C200 + C400 greater than 2%, and preferably greater than 5%, a thermal conductivity greater than 260 W / (mK), preferably greater than 270 W / (mK).

16. Polycrystalline SiC plate according to any one of claims 1 to 15, characterized in that it has: an electrical resistivity of less than 5 mOhm.cm, and preferably less than 3 mOhm.cm, a doping rate, measured by SI MS, greater than 1 x 10 20 atoms / cm 3 , and preferably even greater than 1.5 x 10 20 atoms / cm 3, on each of its two faces, a texture coefficient C220 + C200 + C400 greater than 80%, on each of its two faces, a texture coefficient C422 less than 15%, and preferably less than 10%, on each of its two faces, a contribution C200 + C400 greater than 5%, a thermal conductivity greater than 260 W / (mK), preferably greater than 270 W / (mK).

17. Method for manufacturing a polycrystalline SiC plate according to any one of claims 1 to 16 comprising a step of chemical vapor deposition of a polycrystalline SiC plate on the graphite surface of a substrate (12) comprising a graphite surface, in which a mixture of gases is introduced into a heated enclosure (2) so as to create a gas phase comprising: - at least one gaseous precursor of silicon and / or carbon, - at least one doping gas comprising at least one nitrogen atom, - a carrier gas, said gas mixture decomposing on the surface of said graphite substrate (12) to form a polycrystalline SiC layer on said graphite surface of said substrate, and said method being characterized in that the temperature in said heated enclosure (2) is between 1450 K and 1650 K and the total partial pressure of said gaseous precursors is less than 350 mbar, and preferably less than 300 mbar, the chemical vapor deposition step is followed by at least one step of heat treatment of said polycrystalline SiC layer, at a temperature between 1800 °C and 2300 °C, preferably between 1850 °C and 2200 °C, more preferably between 1900 °C and 2150 °C, and even more preferably between 1950 °C and 2150 °C, knowing that preferably, during this heat treatment the rough blank is held flat on a flat surface.

18. Method according to claim 17, characterized in that in said heated enclosure the total partial pressure of said gaseous precursors is less than 300 mbar.

19. Method according to claim 17 or 18, characterized in that - the total partial pressure of said gaseous precursors in said enclosure is less than 300 mbar and - the heat treatment step is carried out at a temperature between 1900°C and 2150°C.

20. Method according to any one of claims 17 to 19, characterized in that said heat treatment is carried out at a temperature between 1950°C and 2150°C.

21. Method according to any one of claims 17 to 20, characterized in that said doping gas is selected from the group formed by: NH3, N2H4, N2, H2NCH3.

22. Method according to any one of claims 17 to 21, characterized in that said doping gas is present in said heated enclosure in a concentration selected so as to lead in said polycrystalline SiC plate to a nitrogen or phosphorus level, measured by secondary ion mass spectroscopy, greater than 5 x 10 19 atoms / cm 3 , preferably greater than 1 x 10 20 atoms / cm 3 , and even more preferably greater than 1.5 x 10 20 atoms / cm 3 .

23. Method according to any one of claims 1 to 22, characterized in that during said heat treatment, the plate is kept flat on a flat surface.

24. Method according to any one of claims 1 to 23, characterized in that said plate has been freed, before or after said heat treatment, at least on the face which was in contact with a growth substrate, of a material thickness of at least 100 μm.

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