Heterostructure based on single-element atomic layers integrable in a substrate of a semiconductor electronic device and manufacturing method such a heterostructure

Abstract

A heterostructure (1) based on single-element atomic layers can be integrated into a substrate of a semiconductor electronic device. The heterostructure (1) comprises a first two-dimensional layer (3) made with a first air-sensitive material, a second two-dimensional layer (4) made with a second air-sensitive material, and a protective layer (5). A conductive layer (2) covers a portion of the first two-dimensional layer (3), so that the uncovered part (O) of the first two-dimensional layer (3) is exposed to an oxidizing atmosphere and the uncovered part (O) is oxidized.

Description

[0001] Title: “Heterostructure based on single-element atomic layers integrable in a substrate of a semiconductor electronic device and manufacturing method such a heterostructure”.

[0002] DESCRIPTION

[0003] Technical Field

[0004] The invention relates to a heterostructure based on single-element atomic layers that can be integrated into a substrate for a semiconductor electronic device, in accordance with the preamble of claim 1.

[0005] In particular, but not exclusively, the invention relates to a heterostructure that can be integrated into a substrate of a field effect transistor, the field effect transistor equipped with the heterostructure, the manufacturing method of the heterostructure as well as the manufacturing method of the transistor.

[0006] State of the art

[0007] The technical characteristics and the manufacturing method of a heterostructure based on single-element atomic layers which can be integrated in a semiconductor electronic device are known in the state of the art.

[0008] For example, in the article “Two-dimensional silicene-stanene heterostructures by epitaxy" by Dhungana et al. (Adv. Funct. Mater. 2021, 2102797) a heterostructure comprising several layers is described. In particular, this heterostructure comprises in order: a layer of silver, a layer of stanene, a layer of silicene and a layer of alumina.

[0009] The use of heterostructures for manufacturing semiconductor electronic devices, such as field effect transistors, is also known in the state of the art. In fact, patent US10242884 describes a method for manufacturing a field effect transistor comprising a heterostructure. In detail, the heterostructure used includes silver, silicene and alumina. Once the heterostructure is produced, it is turned upside down and connected to a transistor substrate and the metal layer is at least partially removed, to obtain electrodes.

[0010] Also, the article “ Silicon nanosheet: crossover between multilayer silicene and diamond-like growth regime" by Grazianetti and others (ACS Nano 2017, 11, 3376-3382) discloses a field effect transistor with a heterostructure which comprises a silicene multilayer.

[0011] Also known in the state of the art is a graphene transistor comprising a plurality of graphene layers underlying a conductive later with an oxidized portion of the upper graphene layer from WO 2012 / 169720 Al . Moreover, a device with a conductive layer laid on molybdenum disulfide and silver layers is described in the article “ Ultraviolet Light-Induced Persistent and Degenerated Doping in MoS2 for Potential Photocontrollable Electronics Applications" by Zhang Rongjie et Al.

[0012] State of the art problem

[0013] However, it has been found that the silicene in the transistor described in US10242884 degrades in about two minutes when exposed to air, making it unusable except for a limited period of time.

[0014] Furthermore, to avoid compromising the silicene, it is necessary to remove the silver using special substances, such as potassium iodide, which involve an increase in costs in terms of both time and additional industrial operations.

[0015] On the other hand, the transistor described by Grazianetti and others has a longer life than that of patent US 10242884. However, the silicene multilayer described by Grazianetti and others degrades in a time equal to two days, preventing the operation of the transistor after these two days, like that described in US10242884. Scope of the Invention

[0016] In this context, the technical scope of the present invention is to limit the degradation of the hetero structure and, in particular, of a layer comprising a material sensitive to air, thus allowing its use in a semiconductor electronic device, such as for example a field effect transistor, for a longer time than those of the state of the art.

[0017] Furthermore, the technical task underlying the present invention is that of avoiding production processes other than those actually necessary for manufacturing the heterostructure based on single-element atomic layers and the semiconductor electronic device integrating this heterostructure into its substrate.

[0018] The technical task and the aims specified are substantially achieved by a heterostructure based on single-element atomic layers comprising the technical characteristics set forth in one or more of the appended claims.

[0019] The heterostructure based on single-element atomic layers according to the present invention solves the technical problem since it comprises a second two- dimensional layer, between the conductive layer and the first two-dimensional layer sensitive to air which allows to protect the active layer.

[0020] Advantageously, this second two-dimensional layer is also made of a material sensitive to air and is capable of oxidizing when exposed to an oxidizing atmosphere, preventing oxidation and / or degradation of the first two-dimensional layer.

[0021] LIST OF FIGURES

[0022] Further characteristics and advantages of the present invention will appear more clearly from the indicative, and therefore non-limiting, description of a preferred but not exclusive embodiment of a heterostructure based on single-element atomic layers, as illustrated in the attached drawings in which:

[0023] - Figure 1 shows a heterostructure based on single-element atomic layers according to the present invention;

[0024] - Figures 2a-2d show construction steps of the heterostructure of figure 1;

[0025] - Figure 3 shows a semiconductor electronic device comprising the heterostructure of figure 1,

[0026] - Figure 4a shows a Raman spectrum of the heterostructure of figure 2d,

[0027] - Figures 4b and 4c show Raman spectra of the heterostructure of figure 1,

[0028] - Figure 5a shows a Raman spectrum of a heterostructure comprising three second two-dimensional layers,

[0029] - Figures 5b and 5c show Raman spectra of the heterostructure comprising three second two-dimensional layers, when the conductive layer is at least partially removed;

[0030] - Figure 6a shows an X-ray photoemission (XPS) spectrum of a second two- dimensional layer made of a second air-sensitive material of the heterostructure,

[0031] - Figures 6b and 6c show an XPS spectrum of a two-dimensional protective layer and a first two-dimensional layer made of a first air-sensitive material,

[0032] - Figure 7 shows a flow chart for manufacturing the heterostructure of Figure 1;

[0033] - Figure 8 shows a flow chart for manufacturing a semiconductor electronic device of figure 3.

[0034] DETAILED DESCRIPTION

[0035] The present description is about a heterostructure 1 based on single-element atomic layers that can be integrated into a substrate for a semiconductor electronic device 10.

[0036] Referring to figure 1, here the heterostructure 1 is represented according to the present invention, before the heterostructure 1 is integrated with semiconductor electronic device 10.

[0037] As it will be explained later, the heterostructure 1 can be integrated into a substrate 11, making with the substrate 11, once it is integrated, the semiconductor electronic device 10.

[0038] Referring to figure 2a it appears that the heterostructure 1 comprises a plurality of overlapped layers and, in particular along the growth direction (which in the case of the enclosed figures, it means the direction to the direction of the axis of the ordinates of a Cartesian triad), the heterostructure 1 comprises a growth layer 20, a conductive layer 2, a first two-dimensional layer 3 made of a first air-sensitive material XI, a second two-dimensional layer 4 made of a second air-sensitive material X2 and a protective layer 5. It should be noted that the first air-sensitive material XI is different from the second air-sensitive material X2.

[0039] In the context of the present invention, for air-sensitive material is intended any two-dimensional material that degrades when exposed to air.

[0040] It should also be noted that, due to the air-sensitivity of the first and second materials, the encapsulation, hence the protective layer 5, is necessary to prevent oxidation or degradation, which would modify or lose the material properties by converting the metastable structure of the air-sensitive material into a more stable one.

[0041] As mentioned, the different layers are superimposed on each other and in particular it should be pointed out that the conductive layer 2 is superimposed to the tridimensional growth layer 20 so that a lower surface of the conductive layer 2 is placed on an upper surface of the growth layer 20, a lower surface of the first two- dimensional layer 3 is superimposed to an upper surface of the conductive layer 2, a lower surface of the second two-dimensional layer 4 is superimposed to an upper surface of the first two-dimensional layer 3 and a lower surface of the protective layer 5 is superimposed to an upper surface of the second two-dimensional layer 4.

[0042] With additional details, two consecutive layers, made of different materials, are joined together in order to form a so-called heterojunction, i.e. an interface between two consecutive layers.

[0043] It should be pointed out that an upper surface of the protective layer 5, opposite to the lower surface of the protective layer 5, is free, meaning that it is not in contact with any other layer of the heterostructure 1.

[0044] In an embodiment, the first air-sensitive material XI is a first xene and the second air-sensitive material X2 is a second xene.

[0045] As known to the skilled person, with xene is meant a nanoelemental two- dimensional crystal and with a honeycombed lattice which is not necessarily planar.

[0046] It should be noted that the xenes are metastable structures resulting in generally poor air-stability and thus high air-sensitivity.

[0047] In other words, the first xene XI and the second xene X2 are different from each other and, in particular, the first and the second xene XI, X2 comprise respectively materials of Groups from III to VI of the periodic table. The first and the second xene XI e X2 are, for example, borophene, silicene, germanene, stanene, phosphorene and / or tellurene.

[0048] In the preferred embodiment of the heterostructure 1, the first air-sensitive material XI is stanene and the second air-sensitive material X2 is silicene.

[0049] According to an aspect, the growth layer 20 is, for example, made of mica. According to the preferred embodiment, the protective layer 5 is a two-dimensional layer and it is made with the first xene XI .

[0050] According to an alternative embodiment, the protective layer 5 is a two- dimensional layer and it is made with the second xene X2.

[0051] According to an additional alternative embodiment, the protective layer 5 is a tridimensional layer made of alumina.

[0052] As shown in figure 1, wherein the heterostructure 1 has been turned upside down of 180° compared to the one shown in figures 2a-2d and it has also undergone etching, which will be explained later, the conductive layer 2 covering only partially the upper surface of the first two-dimensional layer 3.

[0053] In this way, advantageously, the uncovered part O of the upper surface of the first two-dimensional layer 3 is exposed to an oxidant atmosphere. This causes an oxidation of the first two-dimensional layer 3 in those areas without the conductive layer 2 since the first air-sensitive material XI reacts to air, and it oxidizes.

[0054] Thus, the uncovered part O is oxidized, as it will be described later, and it is able to protect the second air-sensitive material X2 from its subsequent oxidation. Said protective feature of the oxidized part O, as it can be observed in the graphs later shown and discussed, allows to increase the lifetime of the heterostructure 1 and thus of the semiconductor electronic device 10 which integrates in its substrate the heterostructure 1.

[0055] In other words, the first two-dimensional layer 3, which in the context of the experimental phase is stanene, acts as a protective layer for the second two- dimensional layer 4, which is silicene.

[0056] More in detail, relating to the uncovered part O, that is the oxidized one, it should be noted that the heterostructure 1 comprises two portions 2a, 2b of the conductive layer 2 which cover a respective portion of the upper surface of the first two-dimensional layer 3.

[0057] Thus, considering the oxidized part O, that is the uncovered part O of the upper surface of the first two-dimensional layer 3, it is interposed between said two portions 2a, 2b of the conductive layer 2.

[0058] In particular, the two portions 2a, 2b of the conductive layer 2 are placed on the side ends of the first two-dimensional layer 3 so that the oxidized part O is interposed between the two portions 2a, 2b of the conductive layer 2, as shown in figure 1.

[0059] Preferably, the two portions 2a, 2b are spaced out with respect to a spacing direction (which in the present case represented in the annexed figures is the one parallel to the abscissa axis of a Cartesian triad).

[0060] In other words, the removed portion of the conductive layer 2 creates a sort of channel between the two portions 2a, 2b of the conductive layer 2.

[0061] From tests carried out by the Applicant, the heterostructure 1 is stable for at least a month, as shown in figures 4a-4c thanks to the fact that the uncovered part O of the upper surface of the first two-dimensional layer 3 is oxidized in order to protect the second two-dimensional layer 4.

[0062] In fact, also referring to figures 4a-4c, those graphs show spectra obtained via Raman spectroscopy. Those graphs show the Raman shift, in cm'1, on the abscissa axis and the intensity, on the ordinate axis.

[0063] As known to the skilled person, the Raman shift is the energy difference between an incident monochromatic light beam and the detected light beam, after scattering with a sample. The intensity represents the number of events measured by a detector for a respective Raman shift.

[0064] In particular, figure 4a shows a first spectrum obtained via Raman spectroscopy of the heterostructure shown in figure 2d, that is the heterostructure which comprises the conductive layer 2, the first and the second two-dimensional layer 3, 4 and the protective layer 5. Specifically, the conductive layer 2 is made of silver, the first two- dimensional layer 3 of a first air-sensitive material XI is made of stanene, the second two-dimensional layer 4 of a second air-sensitive material X2 is made of silicene and the protective layer 5 is made of alumina. Differently from the heterostructure of figure 1, in the heterostructure 1 shown in figure 2a the conductive layer 2 covers completely the first two-dimensional layer 3 of a first air-sensitive material XI . This circumstance is represented in the graph of figure 4a which shows a peak frequency between 515 and 525 cm'1. In fact, as known by the skilled person, said peak is due to the scattering of silicene of the first two-dimensional layer 3.

[0065] Now referring to figure 4b, a graph obtained by Raman spectroscopy of the heterostructure 1 is shown therein, according to the present invention, that is shown in figure 1. The graph of figure 4b shows a Raman spectroscopy after one hour since the uncovered part O has been exposed, that is after an hour the first two-dimensional layer 3 has been exposed to the oxidizing environment.

[0066] Similarly, figure 4c shows a Raman spectrum of the heterostructure 1 after the uncovered part O has been exposed to the oxidizing environment for a month.

[0067] As it can be noticed, graphs of figures 4b-4c shown the same peak of figure 4a between 515 and 525 cm'1. This means that the heterostructure 1, according to the present invention, thanks to the protection of the second air-sensitive material X2 through the oxidized part O, has the same response characteristics even after the removal of the conductive layer 2, up to a month.

[0068] In other words, even when the first two-dimensional layer 3 is exposed to the oxidizing atmosphere, the second air-sensitive material X2, which in the context of the experimental phase is silicene, of the second two-dimensional layer 4 maintains its structure, i.e. it remains silicene.

[0069] From experimental testing, it can be seen that the first two-dimensional layer 3 is oxidized, once it is exposed to the oxidizing atmosphere, and impedes the degradation of the second two-dimensional layer 4.

[0070] Referring to images of figures 6a-6c, they show experimental graphs obtained through XPS spectroscopy. As known to the skilled person, the graphs of figures 6a- 6c are obtained by progressively varying an incident angle of incident X-rays, with respect to the upper surface of the protective layer 5. These graphs show the binding energy on the abscissa axis, in eV, and the intensity on the ordinate axis.

[0071] As known by the skilled person, a sample is hit by an electromagnetic radiation in the X-ray region, leading to a release in photoelectrons. Figure 6a shows a graph related to an XPS analysis of the second two-dimensional layer 4, made of silicene.

[0072] It should be noted that figure 6a shows a first curve (SiO2) with a respective first peak and a second curve (Si) with a respective peak, which has a higher intensity than the first peak. The first curve (SiO2) of figure 6a is related to the presence of oxidized silicon and it is related to the presence of oxidized silicon, while the second curve (Si) of figure 6a is related to the presence of silicon. Thus, this indicates that the silicon in the second two-dimensional layer 4 is for the most part unoxidized. It also turns out that the silicon is partially oxidized for examples along the edges exposed to the oxidizing atmosphere.

[0073] Figures 6b and 6c show graphs related to XPS analysis of the bidensional protective layer 5 and of the first two-dimensional layer 3, in the embodiment wherein they are made of stanene. With more details, the embodiment in which the two- dimensional protective layer 5 and the first two-dimensional layer 3 are made of stanene is a representative case since, as it is known to the skilled person, stanene is the most reactive xene among those comprised in Groups from III to VI.

[0074] In more detail, figure 6b shows the graph related to the analysis of the two- dimensional protective layer 5 and of the first two-dimensional layer 3, wherein the X-rays graze with respect to the upper surface of the protective layer 5. In other words, said experimental condition is more sensitive to the protective layer 5. Figure 6c shows the graph related to the analysis of the two-dimensional protective layer 5 and of the first two-dimensional layer 3, wherein the X-rays make an angle preferably equal to 80° with respect to the upper surface of the protective layer 5. In other words, this last experimental condition is more sensitive to the first two-dimensional layer 3.

[0075] From XPS graphs, it turns out that both figure 6b and figure 6c show a first curve (SnO2) with a respective first peak and a second curve (Sn) with a respective second peak, with a lower intensity than the first peak. From experimental data shown before, it emerges that both the protective two-dimensional layer 5 and the first two- dimensional layer 3 are oxidized.

[0076] It should be noted that the angle resolved XPS spectroscopy measurements carried out at the two-dimensional protective layer 5 show that the two-dimensional protective layer 5 is more oxidized than the first two-dimensional layer 3. It is reasonable to expect that, due to symmetry, the measurements performed at the first two-dimensional layer 3 behave in the same way.

[0077] Preferably, the heterostructure 1 can comprise aside from the first and the second two-dimensional layer 3, 4 even further layers, each of them could be made of the first air-sensitive material XI and / or the second air-sensitive material X2 and / or the third air-sensitive material X3. It should be noted that the third air-sensitive material X3 is different from at least one of first air-sensitive material XI and second air-sensitive material X2.

[0078] Independently from the number of further layers that the heterostructure 1 can comprise, it should be noted that those further layers are placed between the conductive layer 2 and the protective layer 5.

[0079] For example, the heterostructure 1 can comprise a third two-dimensional layer made of the first air-sensitive material XI and / or with the second air-sensitive material X2.

[0080] The third two-dimensional layer defines an upper surface and a lower surface, wherein the upper surface of the third two-dimensional layer is place on the lower surface of the second two-dimensional layer 4 and the lower surface of the third two- dimensional layer is placed on the upper surface of the protective layer 5.

[0081] In an additional embodiment, not disclosed in the figures, the heterostructure 1 can comprise aside from the first two-dimensional layer 3, the second two- dimensional layer 4 and the third two-dimensional layer also an additional fourth two- dimensional. For example, such heterostructure 1 comprises the first two-dimensional layer 3 made of the first air-sensitive material XI, while the other two-dimensional layers (that is the second 4, the third and the fourth) are made of the second airsensitive material X2. In particular, the first two-dimensional layer 3 is a stanene, while the second two-dimensional layer 4, the third and the fourth are silicene.

[0082] Said heterostructure 1 comprises also the conductive layer 2 and the protective layer 5. Specifically, the conductive layer 2 is made of silver and the protective layer 5 is made of alumina.

[0083] Also, this last type of heterostructure 1 has been tested by the Applicant, and the results are shown in graphs of figures 5a-5c.

[0084] The graphs of figures 5a-5c are obtained, also in this case, by Raman spectroscopy.

[0085] In particular, the graph of figure 5a shows a peak frequency between 515 e 525 cm'1, similarly to the one of graph of figure 4a, due to silicon scattering in the form of silicene.

[0086] Figure 5b shows a Raman spectrum of a heterostructure 1 one day after the uncovered part O has been exposed and the figure 5c shows a Raman spectrum of the heterostructure 1 one month after the uncovered part O has been exposed to the oxidizing environment.

[0087] It should be noted that in figures 5b and 5c the same peak of figure 5a between 515 and 525 cm'1is present.

[0088] Similarly, to what happened to the heterostructure 1 of figure 1, the structure of the second 4, of the third and the fourth two-dimensional layer made of the second air-sensitive material X2 appears unchanged, up to a month, after a portion of the conductive layer 2 is removed. In other words, even when the first two-dimensional layer 3 is exposed to the oxidizing atmosphere, the second air-sensitive material X2, which in the context of the experimental phase is silicene, keeps unchanged its properties. Additionally, not only the silicene of the second two-dimensional layer 4 remains unchanged over time, but also the silicene of the third and the fourth two- dimensional layer.

[0089] From experimental testing, it turns out that the first two-dimensional layer 3 is oxidized, once it is exposed to the oxidizing atmosphere, and prevents the degradation of the second 4, of the third and of the fourth two-dimensional layer. In other words, the first two-dimensional layer 3, which in the context of the experimental stage is stanene, acts like a protective layer for the second 4, the third and the fourth two- dimensional layer.

[0090] Having described the heterostructure 1, it will be now illustrated, also with reference to figure 7, a manufacturing method 100 of the heterostructure 1.

[0091] The manufacturing method of the heterostructure 1 comprises a step 101 of supplying a growth layer 20, a step 102 of supplying a conductive layer 2, a step 103 of supplying a first air-sensitive XI, a step 104 of supplying a second air-sensitive material X2 and a step 105 of supplying a protective layer 5. The manufacturing method of the heterostructure 1 comprises a step 106 of depositing on the conductive layer 2 the first air-sensitive material XI to make a first two-dimensional layer 3.

[0092] Preferably, the conductive layer 2 is deposited on the upper surface of the growth layer 20.

[0093] Preferably, the first air-sensitive material XI is deposited on the lower surface of the conductive layer 2.

[0094] In the preferred embodiment, the first air-sensitive material XI is stanene.

[0095] The manufacturing method of the heterostructure 1 comprises a step 107 of depositing on the first two-dimensional layer 3 the second air-sensitive material X2, to make a second two-dimensional layer 4.

[0096] Preferably, the second air-sensitive material X2 is deposited on the lower surface of the first two-dimensional layer 3.

[0097] In the preferred embodiment, the second air-sensitive material X2 is silicene.

[0098] The manufacturing method of the heterostructure 1 comprises a step 108 of depositing on the second two-dimensional layer 4 the protective layer 5.

[0099] Preferably, the protective layer 5 is deposited on the lower surface of the second two-dimensional layer 4.

[0100] It should be noted, referring to figure 2, that the growth direction of the heterostructure 1 is the one indicated with the axis Y.

[0101] Advantageously, the method comprises a step 109 of removing at least partially the conductive layer 2 to expose a part O of the first two-dimensional layer 3.

[0102] In other words, to make the heterostructure 1, the step 109 involves removing at least partially the conductive layer 2, exposing the uncovered part O of the first two- dimensional layer 3. Preferably, the conductive layer 2 is removed at least partially by etching. Preferably, a solution comprising potassium iodide- and iodine-based etchant was used to remove at least partially the conductive layer 2.

[0103] Later, the method comprises a step 110 of oxidizing the uncovered part O of the first two-dimensional layer 3.

[0104] Said oxidizing step usually occurs by simple exposure to air of the uncovered part O.

[0105] In an alternative embodiment, the method comprises a step of depositing the protective layer 5 on the upper surface of the third two-dimensional layer.

[0106] If the heterostructure 1 comprises more air-sensitive two-dimensional layers (that is the number of two-dimensional layers is greater than two), the method comprises a step of depositing on the lower surface of the second two-dimensional layer 4 the first XI and / or the second X2 and / or the third X3 air-sensitive material, to make at least a third two-dimensional layer.

[0107] Having so far illustrated the heterostructure 1 and its manufacturing method, it will be now described the semiconductor electronic device 10 comprising the heterostructure 1 and its manufacturing process.

[0108] Referring to figure 3, it is noted that the semiconductor electronic device 10 comprises in its layers the heterostructure 1 and, in particular, it comprises a substrate 11 and three electrical terminals, respectively, 12, 13 e 14.

[0109] In detail, the semiconductor electronic device 10 is the product of the combinations of the heterostructure 1 and the substrate 11. In other words, is obvious to a skilled person that the electronic device does not work as long as the substrate 11 is isolated, that is it is not jointed to the heterostructure 1.

[0110] The heterostructure 1 defines an upper surface la and a lower surface lb. The upper surface la of the heterostructure 1 is found on the upper surface of the conductive layer 2 and the lower surface lb of the heterostructure 1 is found on the lower surface of the protective layer 5. The lower surface lb of the heterostructure 1 is placed on the first face 1 la of the substrate 11.

[0111] In particular, the substrate 11 defines a first face I la and a second face 11b, opposite to the first face I la, wherein the upper surface of the protective layer 5 is superimposed to the first face 1 la of the substrate 11 and the second face 1 lb (or rather a portion of it) acts as an electric terminal 14.

[0112] Moreover, the electric terminals 12 and 13 of the semiconductor electronic device 10 correspond to the portions of the conductive layer 2 not removed during the manufacturing of the heterostructure 1.

[0113] The three electric terminals 12, 13 and 14 of the electronic device 10 are functional to the operation of the electronic device 10 being responsible for causing electric currents to flow to and from the electronic device 10 when suitably polarized.

[0114] In the preferred embodiment, the electronic device 10 takes the form of a field effect transistor and in that case the first terminal 12 can be identified as he source electrode, the second terminal 13 can be identified as the drain electrode or vice versa while the third terminal 14 can be identified as the gate electrode.

[0115] Having described the transistor 10, a method 200 of manufacturing this transistor 10 will now be illustrated.

[0116] Referring to figure 8, the method of manufacturing the semiconductor electronic device 10 comprises a step 201 of providing a heterostructure 1 made accordingly with what was previously described.

[0117] Then, the method 200 involves a step 202 of providing the substrate 11 defining a first face 1 la and a second face 1 lb, opposite to the first face 1 la, as shown in figure 8.

[0118] Advantageously the method 200 comprises a step 203 of placing the heterostructure 1 in such a way that the upper surface of the protective layer 5 faces the first face I la of the substrate 11 and a step 204 of associating in order to put in contact the upper surface of the protective layer 5 with the first face 1 la of the substrate 11.

[0119] In this way, once the heterostructure 1 is associated to the substrate 11, the electronic device 10 is made.

[0120] Later, the method 200 involves a step 205 of contacting electrically the first and the second portion of the conductive layer 2 to make a first and a second electric terminal.

[0121] The method 200 involves a step 206 of contacting electrically the second face 1 lb of the substrate 11 to make a third electric terminal.

[0122] In order to associate the heterostructure 1 to the substrate 11, the heterostructure 1 and the substrate 11 are positioned in surface contact such that they are coupled.

[0123] Clearly a skilled person, in order to satisfy contingent and specific needs, may make numerous modifications and variations to the configurations described above. However, these variants and modifications are all contained within the scope of protection of the invention as defined by the following claims.

Claims

CLAIMS1. Heterostructure (1) based on single-element atomic layers that can be integrated into a substrate for a semiconductor electronic device, said heterostructure (1) comprising:- a conductive layer (2) defining an upper surface and a lower surface,- a first two-dimensional layer (3) made of a first air-sensitive material (XI), said first two-dimensional layer (3) defining an upper surface and a lower surface, the upper surface of the first two-dimensional layer (3) being placed one the lower surface of the conductive layer (2),- a second two-dimensional layer (4) made of a second air-sensitive material (X2) different from the first air-sensitive material (XI), said second two-dimensional layer (4) defining an upper surface and a lower surface, the upper surface of the second two- dimensional layer (4) being placed on the lower surface of the first two-dimensional layer (3),- a protective layer (5), defining an upper surface and a lower surface, the upper surface of the protective layer (5) being placed on the lower surface of the second two- dimensional layer (4), wherein said conductive layer (2) partially covers a portion of the upper surface of the first two-dimensional layer (3), the uncovered part (O) of said upper surface of the first two-dimensional layer (3) being oxidized.

2. Heterostructure (1) according to claim 1, comprising at least a third two-dimensional layer made of the first air-sensitive material (XI) and / or with the second air-sensitive material (X2) and / or a third air-sensitive material (X3), the third two-dimensional layer defining an upper surface and a lower surface, the upper surface of the third two- dimensional layer being placed on the lower surface of the second two-dimensional layer (4), the lower surface of the third two-dimensional layer being placed on the upper surface of the protective layer (5).

3. Heterostructure (1) according to claim 2, comprising a plurality of two-dimensional layers (7) made of the first air-sensitive material (XI) and / or the second air-sensitive material (X2) and / or the third air-sensitive material (X3).

4. Heterostructure (1) according to any of the preceding claims, wherein the two- dimensional first air-sensitive material (XI), the two-dimensional second air-sensitive material (X2) and / or the two-dimensional third air-sensitive material (X3) comprise materials of Groups from III to VI of the periodic table.

5. Heterostructure (1) according to claim 4, wherein said first, second and / or third two- dimensional air-sensitive material (XI, X2, X3) comprises one of the following elements: borophene, silicene, germanene, stanene, phosphorene and tellurene.

6. Heterostructure (1) according to claim 1, comprising at least two portions of the conductive layer (2) covering a respective portion of the upper surface of the first two- dimensional layer (3) and said oxidized part of said upper surface of the first two- dimensional layer (3) being interposed between said two portions of conductive layer (2).

7. Heterostructure (1) according to claim 1, wherein the protective layer (5) is a two- dimensional layer made of the oxidized first air-sensitive material (XI).

8. Heterostructure (1) according to claim 1, wherein the protective layer (5) is made of alumina.

9. Heterostructure (1) according to claim 1, wherein the conductive layer (2) is made ofsilver.

10. Semiconductor electronic device (10), comprising:- a substrate (11) defining a first face (I la) and a second face (11b), opposite to the first face (I la),- a first electrical terminal (12), a second electrical terminal (13) and a third electrical terminal (14), characterized in that it comprises a heterostructure (1) according to any claims from 1 to 9, said heterostructure (1) defining an upper surface (la) and a lower surface (lb), the upper surface (la) of the heterostructure (1) being found on the upper surface of the conductive layer (2), the lower surface (lb) of the heterostructure (1) being found on the lower surface of the protective layer (5), the lower surface (lb) of the heterostructure (1) being placed on the first face (I la) of the substrate (11), said first electrical terminal (12) and said second electrical terminal (13) being placed respectively at a first and a second portion of the conductive layer (2) of said heterostructure, said third electrical terminal (14) being placed at the second face (1 lb) of the substrate (11).

11. Manufacturing method of an heterostructure (1) according to any of the preceding claims form 1 to 9, said method comprising the following steps:- providing a growth layer (20);- providing the conductive layer (2),- providing the first air-sensitive material (XI),- providing the second air-sensitive material (X2),- providing the protective layer (5),- depositing on the conductive layer (2) said first air-sensitive material (XI), to make a first two-dimensional layer (3),- depositing on the first two-dimensional layer (3) said second air-sensitive material (X2), to make a second two-dimensional layer (4),- depositing on the second two-dimensional layer (4) said protective layer (5), said method being characterized in that it comprises the following steps:- removing at least partially the conductive layer (2), exposing a part (O) of the first two-dimensional layer (3),- oxidizing the uncovered part (O) of the first two-dimensional layer (3).

12. Manufacturing method of a semiconductor electronic device according to claim 10, said method comprising the following steps:- providing the heterostructure (1),- providing the substrate (11) defining the first face (I la) and the second face (11b), opposite to the first face (I la), characterized by the fact it comprises the steps of:- placing the heterostructure (1) so that the lower surface (lb) of the heterostructure (1) is facing the first face (1 la) of the substrate (11),- associating the lower surface (lb) of the heterostructure (1) to the first face (I la) of the substrate (11) said second face (1 lb) of the substrate (11) being free,- electrically connecting said first and second portion of conductive layer (2) of said heterostructure (1) to make the first and the second electrical terminal,- electrically connecting said second face (11b) of said substrate (11) to make a third electric terminal.

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