Interconnection structure of an integrated circuit

Abstract

Interconnection Structure of an Integrated Circuit This description relates to a method comprising the following steps: providing an integrated circuit (1) comprising: a stack of first (5), second (7), and third (9) insulating layers; contacts (11) through the first layer (5); and a component (13) comprising an electrical contact region (15) in the second layer (7); etching an opening (35) in the third layer (9), directly above the contact region (15); depositing a fourth insulating layer (37) filling the opening (35); etching another opening (43) to the contact region (15) through the opening (35) in the third insulating layer (9); and forming a metal layer by filling the other opening with a metal (45). Figure for the abstract: Fig. 7

Description

Title of the invention: Interconnection structure of an integrated circuit Technical field

[0001] This description relates generally to integrated circuits, and more particularly to the interconnection structures of integrated circuits and the manufacturing processes of these interconnection structures. Previous technique

[0002] Integrated circuits are known comprising a semiconductor layer, a stack of insulating layers resting on the semiconductor layer, and an interconnection structure resting on the stack of insulating layers. These circuits include electrical contact vias resting on and in contact with electrical contact areas formed from the semiconductor layer and passing through a portion of the stack of insulating layers, and at least one electronic component comprising an electrical contact region disposed at an intermediate level of the stack of insulating layers, between the level of the vertices of the electrical contact vias and the first metal level of the interconnection structure, i.e., the metal level closest to the semiconductor layer. Summary of the invention

[0003] In the integrated circuits described above, the known electrical connections between the first metal layer and electrical contact regions located between the top of the contact vias and the first metal layer present various drawbacks. The manufacturing processes for these known electrical connections also present various drawbacks.

[0004] There is a need to overcome all or part of the drawbacks of these known electrical connections and / or their manufacturing processes.

[0005] One embodiment overcomes all or part of the disadvantages of known electrical connections as described above.

[0006] An embodiment overcomes all or part of the drawbacks of known manufacturing processes for electrical connections between the first metal level of an interconnecting structure and an electrical contact region as described above.

[0007] One embodiment provides a method for manufacturing an interconnection structure comprising the following successive steps: a) provide an integrated circuit comprising: a first insulating layer; a second insulating layer resting on the first layer; a third insulating layer resting on the second layer; electrical contacts passing through the first layer; and a component of which an electrical contact region is located in the second layer and is covered by a portion of that second layer; b) to engrave a first opening through the third layer and directly above the contact region, the engraving of the first opening being stopped before the contact region; c) deposit a fourth insulating layer so as to fill the first opening and cover the third layer; d) etch a second opening through the fourth layer to the contact region so that the second opening passes through the third insulating layer at the level of the first opening; and e) form a metal level of the interconnecting structure by filling the second opening with at least one metal.

[0008] According to one embodiment, in step a), the electrical contacts have vertices located below the second insulating layer.

[0009] According to one embodiment, in step a), the integrated circuit further comprises first electrically conductive vias passing through the second insulating layer and extending from a corresponding electrical contact to said third layer.

[0010] According to one embodiment, third openings are engraved at the same time as the second opening in step d), each third opening being engraved in line with one of the first vias and up to said first via.

[0011] According to one embodiment, step d) comprises the deposition of a first layer of photosensitive resin and the alignment of an exposure mask of the first layer of resin with said first vias.

[0012] According to one embodiment, in step a), a fifth insulating layer covers the contact region, and, in step d), the etching of the second opening comprises a first etching up to said fifth layer followed by a second etching through the fifth layer and up to the contact region.

[0013] According to one embodiment, the first engraving is selective with respect to the third insulating layer and the fifth insulating layer.

[0014] According to one embodiment, in step d), the third openings are engraved up to the third layer during the first engraving, then up to the first vias during the second engraving.

[0015] According to one embodiment, step b) includes the deposition of a second layer of photosensitive resin and the alignment of an exposure mask of the second layer of resin with said contact region.

[0016] According to one embodiment, in step d), the first opening has lateral dimensions less than corresponding lateral dimensions of the contact region.

[0017] According to one embodiment, step e) comprises the deposition of said at least one metal in order to fill the second opening and cover the fourth insulating layer, and a mechano-chemical polishing step up to the fourth insulating layer.

[0018] According to one embodiment, in step a), the first insulating layer rests on a semiconducting layer, preferably provided with electrical contact zones in contact with corresponding electrical contacts.

[0019] According to one embodiment, in step a), the electrical contact region of the component is an upper contact region, the component further comprising a lower contact region located above the upper contact region, the lower contact region being in contact with a vertex of one of said electrical contacts, preferably, the component being a memory point of a phase-change memory, a memory point of a magnetic memory, or a memory point of a resistive oxide-based memory.

[0020] Another embodiment provides for an integrated circuit comprising: a first insulating layer; a second insulating layer resting on the first layer; a third insulating layer resting on the second layer; electrical contacts passing through the first layer; a component comprising an electrical contact region located in the second layer below the level of the top face of the second layer; a fourth insulating layer resting on the upper surface of the third insulating layer; and a first metal level of a circuit interconnection structure comprising a portion extending from an upper face of the fourth layer to the contact region and resting partly on and in contact with the second insulating layer, preferably on and in contact with a shoulder defined by the second insulating layer.

[0021] According to one embodiment, the first level of metal is obtained by implementing the process described. Brief description of the drawings

[0022] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0023] [fig. 1] the [fig.1] represents by a schematic and cross-sectional view, an integrated circuit at one stage of an implementation method of a manufacturing process of an interconnection structure of the integrated circuit;

[0024] [fig.2] Fig.2 represents, by a schematic and cross-sectional view, the circuit of the [fig.l] at another stage of the manufacturing process;

[0025] [fig.3] Fig.3 represents, by a schematic and cross-sectional view, the circuit of the [fig.2] at another stage of the manufacturing process;

[0026] [fig.4] Fig.4 represents, by a schematic and cross-sectional view, the circuit of the [fig.3] at another stage of the manufacturing process;

[0027] [fig.5] Fig.5 represents, by a schematic and cross-sectional view, the circuit of the [fig.4] at another stage of the manufacturing process;

[0028] [fig.6] Fig.6 represents, by a schematic and cross-sectional view, the circuit of the [fig.5] at another stage of the manufacturing process;

[0029] [fig-7] Fig. 7 represents, by a schematic and cross-sectional view, the circuit of the [fig.6] at another stage of the manufacturing process; and

[0030] [fig.8] Fig.8 represents, by a schematic and cross-sectional view, the circuit of the [fig.7] at another stage of the manufacturing process. Description of the implementation methods

[0031] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0032] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the usual electronic components of integrated circuits have not been detailed, as the embodiments, embodiment variants, implementation methods, and implementation variants described are compatible with these usual electronic components and with the manufacturing processes for these usual components.

[0033] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0034] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0035] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0036] Figure 1 represents, by way of a schematic and cross-sectional view, a single-stage integrated circuit 1 of an implementation method for manufacturing a structure integrated circuit interconnection 1.

[0037] The integrated circuit 1 includes a semiconductor layer 3, for example made of silicon. The layer 3 may be a semiconductor substrate. The semiconductor layer 3 may also be a semiconductor layer resting on an insulating layer itself resting on a support, the layer 3 then being commonly called the SOI layer ("Semiconductor On Insulator").

[0038] The circuit 1 comprises an insulating layer 5 resting on the semiconductor layer 3, preferably in contact with the layer 3. Preferably, an upper face of the layer 5, that is, a face of the layer 5 opposite the layer 3, is flat. The layer 5 is, for example, made of a single insulating layer or of a stack of several insulating layers, possibly of different materials. By way of example, the layer 5 comprises a silicon nitride layer (not detailed in [Fig. 1]) resting on and in contact with the layer 3, and a silicon oxide layer (not detailed in [Fig. 1]) resting on and in contact with the silicon nitride layer.

[0039] The circuit 1 includes an insulating layer 7 resting on the layer 5. The layer 7 is, for example, made of a single insulating layer or a stack of several insulating layers, possibly made of different materials. By way of example, the layer 7 is a single layer of silicon dioxide (SiO2).

[0040] The circuit 1 includes an insulating layer 9 resting on the layer 7, preferably in contact with the layer 7. At the step in [fig.1], the layer 9 has an upper face, that is to say a face opposite to the layer 3, exposed.

[0041] According to one embodiment, layer 9 is a diffusion barrier layer and / or an etching stop layer.

[0042] By way of example, layer 9 is a silicon carbon nitride or silicon carbonitide (SiCN) layer, or a silicon nitride (SiN) layer, preferably a SiCN layer.

[0043] The circuit 1 comprises electrical contact vias, or electrical contacts, 11 extending through the layer 5. Preferably, as shown in [Fig. 1], the electrical contacts 11 do not penetrate the insulating layer 7. In other words, the upper level of the electrical contacts 11 is located below the level of the lower face of the layer 7. Put another way, the tops of the electrical contacts 11 are located below the layer 7. Preferably, as shown in [Fig. 1], the electrical contacts 11 are flush with the upper face of the insulating layer 5. By way of example, the electrical contacts 7 are made of tungsten (W).

[0044] The circuit 1 includes an electronic component 13. The component 13 includes an electrical contact region, or electrode, 15. The electrode 15 is located at an intermediate level of layer 7. In other words, the electrode 15 is therefore arranged or buried in layer 7, above the level of the lower face of layer 7 and below the level of a portion of the upper face of layer 7 above electrode 15, with part of the thickness of layer 7 then covering electrode 15. Put another way, electrode 15 is located below layer 9, separated from it by a portion of layer 7, and is located above the level of the vertices of the electrical contacts 11. As an example, electrode 15 is made of titanium nitride (TiN) or tantalum nitride (TaN).

[0045] According to one embodiment, the electrode 15 is covered with an insulating layer 17, for example of silicon nitride (SiN) or silicon carbon nitride (SiCN), preferably of SiN. In this example, an insulating layer 23 is interposed between the electrode 15 and the layer 17, or, in other words, the layer 23 rests on and is in contact with the electrode 15 and the layer 17 rests on and is in contact with the layer 23. The layer 23 is, for example, made of SiN or SiCN, preferably SiN. The layer 23 has, for example, in a top view, the same surface area as the electrode 15 that it covers. This results, for example, from the fact that layer 23 corresponds to a hard mask used to define by etching the electrode 15 in a layer of the material of electrode 15. In the example shown, layer 17 also covers the sides of component 13, in particular the sides of layer 23, and rests, on either side of component 13, on layer 5, preferably in contact with layer 5.In this example, layer 7 rests in contact with layer 17. Layer 17 is preferably a diffusion barrier layer and / or an etching stop layer. In particular, in this example where layer 17 covers layer 5 on both sides of component 13, this layer 17 serves as a diffusion barrier layer for the electrical contact material 11.

[0046] In the example shown, component 13 is a memory location of a phase-change memory, for example, PCRAM (Phase Change Random Access Memory). In this example, component 13 comprises a stack consisting successively, from bottom to top in [Fig. 1], of a lower electrical contact region, or lower electrode, 19, a phase-change material 21, for example, a GST-type alloy, electrode 15 forming the upper electrode of component 13, and the insulating layer 23. Preferably, layers 19, 21, 15, and 23 of the stack of component 13 are self-aligned, with layer 23 corresponding, for example, to the hard mask of the etching used to define component 13. The lower electrode 19 is in contact with the apex of an electrical contact 11.It should be noted that the electrode 15 can be made of a material other than TaN or TiN, in particular, in the case of a memory point 13 of a phase change memory, of a material comprising metal and whose deposition, for example a chemical vapor deposition, is compatible. with the deposition of the phase change material 21.

[0047] The circuit 1 includes contact zones, or contact re-establishment zones, in particular contact zones 25 formed from layer 3, for example by silicification of portions of layer 3, or of portions of epitaxial zones from layer 3. In other words, layer 3 is provided with contact zones 25. Each contact zone 25 of layer 3 is associated with a corresponding electrical contact 11, the foot, or base, of the contact 11 then being in contact with the zone 25.

[0048] According to one embodiment, as shown in [Fig. 1], the circuit 1 further comprises electronic components 27 formed in and / or on layer 3. In the example of [Fig. 1], only one component 27 is shown, namely a MOS (Metal Oxide Semiconductor) transistor. The components 27 include contact areas, in particular contact areas 25 of layer 3. For example, the transistor 27 of [Fig. 1] comprises a drain contact area 25 and a source contact area 25. Although this is not illustrated in [Fig. 1], the circuit 1 further comprises electronic components 27 formed in and / or on layer 3.[l] The components 27 may include contact areas other than contact areas of layer 3, for example located at an intermediate level of layer 5, i.e., these contact areas are above the level of the lower face of layer 5 and below the level of the upper face of layer 5, with a portion of the thickness of layer 5 then covering this contact area. For example, transistor 27 includes a gate contact area (not shown) at an intermediate level of layer 5, an electrical contact similar to the electrical contacts 11, preferably formed at the same time as the contacts 11, having its base in contact with the gate contact area of ​​transistor 27, and its apex at the same level as the apexes of the contacts 11.

[0049] As shown in [Fig. 1], when the circuit 1 comprises a first part with components 13 (on the right in [Fig. 1]) and a second part with components 27 (on the left in [Fig. 1]), the top face of layer 9 may exhibit a level difference between these two parts (schematically separated by a double curved line in [Fig. 1]). In particular, the top face of layer 9 may be at a first level in the first part and at a second level lower than the first level in the second part. By way of example, the level difference between the two parts of the circuit 1 may be, for example, between 0 nm and 30 nm, for example, equal to or substantially equal to 15 nm.

[0050] According to one embodiment, the circuit 1 comprises electrically conductive vias 29. These vias 29 pass through the layer 7 to make contact with the electrical contact apex 11. In other words, the vias 29 penetrate the layer 7 from its upper face, up to corresponding contacts 11. Preferably, the vias 29 are flush with the upper face of the layer 7, their apexes then being coated with the layer 9 which can therefore serve as a diffusion barrier layer for the material of the vias 29. As an example, the vias 29 are made of tungsten (W), cobalt (Co) or copper (Cu), preferably tungsten.

[0051] The process described below in relation to Figures 2 to 8 aims to form a first metal level of an interconnection structure of the circuit 1, that is to say the metal level of the interconnection structure closest to layer 3, or, in other words, the metal level of the interconnection structure closest to the contact regions 15 and / or the contact zones 25.

[0052] In this description, the term "metal level of an interconnection structure" means a set of portions of the same metallic layer arranged at the same level in the interconnection structure, the metallic layer being, for example, a single metallic layer or several metallic layers, possibly made of different materials. Furthermore, the term "interconnection structure" means a set of portions of metallic layers embedded in insulating layers and connected to each other by conductive vias passing through these insulating layers, the portions of metallic layers being organized into several metal levels.

[0053] More particularly, the process described below aims to form the first metal level of the interconnection structure of a circuit of the type of circuit 1 of [fig.1], as well as electrical connections between this first metal level and electrodes 15, or even electrical connections between this first metal level with vias 29, in order to electrically connect the electronic components 13, or even 27, of the circuit to the interconnection structure.

[0054] Fig. 2 represents circuit 1 of Fig. 1 at one stage of an implementation method of such a process.

[0055] An etching mask 31 has been formed on the layer 9, the mask 31 comprising openings 33 (only one opening 33 being visible in [fig.2]) opposite each electrode 15 of a component 13. Preferably, the lateral dimensions of the opening 33, for example measured in a plane parallel to the upper surface of the layer 3, are less than that of the electrode 15.

[0056] Although not visible in [Fig. 2], in top view, the electrode 15 may have an elongated shape (for example, along a direction orthogonal to the plane of [Fig. 2]), for example, a substantially rectangular shape. In this case, one or more openings 33 may be provided above the electrode 15 of the component 13. For example, an elongated opening 33 may be provided along the longitudinal direction of the electrode 15 in top view, for example, to form an electrical connection between the first metal layer and the electrode 15, having the shape of a metal line. According to another example, several openings 33 may be provided, for example, sen possibly circular, aligned in the longitudinal direction of electrode 15 in top view, for example to form several electrical connections between the first metal level and electrode 15 having the form of several conductive vias.

[0057] The mask 31 and the openings 33 it comprises are obtained by depositing one or more layers of photosensitive resin, exposing the resin with an exposure mask, and developing the exposed resin. In one embodiment, the exposure mask is aligned with the electrode 15. Aligning this exposure mask with the vias 29 could have been considered, but this would have led to larger alignment errors between the opening 33 and the electrode 15, which is undesirable.

[0058] According to one embodiment, the mask 31 comprises three layers of resins, namely a layer of carbon resin, a layer of anti-reflective resin, and a layer of photosensitive resin. The openings 33 are then defined through these resin layers.

[0059] According to one embodiment, the mask 31 corresponds to one or more layers of hard mask deposited before the resin layer(s), the openings 33 being etched in the hard mask 31 from corresponding openings previously formed in the resin layer(s) resting on the hard mask 31. By way of example, the hard mask 31 comprises a titanium nitride (TiN) layer, a silicon nitride (SiN) layer or a carbon layer.

[0060] Fig. 3 represents circuit 1 of Fig. 2 at a subsequent step of the process.

[0061] An opening 35 has been etched through layer 9, directly above electrode 15. More In particular, the opening 35 is engraved from an opening 33 of the mask 31 ([fig.2]), then the mask 31 was removed.

[0062] The etching of the aperture 35 can be stopped on the layer 7, or as shown in [fig.3], in the layer 7. Preferably, when the layer 9 has a difference in level between the first part of the circuit 1 comprising the components 13 and the second part of the circuit 1 comprising the components 27, the aperture 35 penetrates the layer 7 so as to catch up, or compensate, for this difference in level in subsequent etching stages.

[0063] Although not illustrated, the etching of the opening 35 can be stopped on the layer 17 covering the electrode 15 of the component 13.

[0064] By way of example, the opening 35 has a depth between 30 nm and 50 nm, for example equal to 40 nm, the depth of the opening being for example measured from the upper surface of the layer 9 to the bottom of the opening 35.

[0065] The aperture 35 advantageously has lateral dimensions, for example measured in a plane parallel to the upper face of layer 3, that are smaller than those of the electrode 15. This results in particular from the fact that layer 9 is thin or not very thick, that is to say that it has a thickness for example between 10 nm and about 20 nm, for example equal to or approximately equal to 20 nm.

[0066] Fig. 4 represents circuit 1 of Fig. 3 at a subsequent step of the process.

[0067] An insulating layer 37 was deposited so as to fill the opening 35 and to Layer 9 is covered. Layer 37 corresponds to an insulating layer of the interconnection structure of circuit 1. Layer 37 may, for example, consist of a single insulating layer or a stack of several insulating layers, possibly made of different materials. A chemical mechanical polishing (CMP) step of layer 37 may be performed.

[0068] By way of example, layer 37 is made of silicon oxycarbide (SiOC). According to another example, layer 37 comprises a lower layer resting on, and preferably in contact with, layer 9, and an upper layer resting on this lower layer, the upper layer generally being made of a material with a dielectric constant lower than that of the material of the lower layer, for example in a material with a dielectric constant less than 2.6, for example equal to 2.5.

[0069] By way of example, for a given integrated circuit technology, layer 37 has a thickness between 150 nm and 200 nm, for example equal to or substantially equal to 175 nm.

[0070] Fig. 5 represents circuit 1 of Fig. 4 at a subsequent step of the process.

[0071] An etching mask 39 was formed on layer 37, the mask 39 comprising a aperture 41 opposite the aperture 35 filled with layer 37, or, in other words, opposite electrode 15. Furthermore, in the case where the circuit 1 includes vias 29, the mask 39 also includes apertures 41 opposite the vias 29.

[0072] Although this is not visible in [fig.5], in top view, the same opening 41 can comprise several parts each opposite a different opening 35.

[0073] The mask 39 and the openings 41 it comprises are obtained by depositing a layer of photosensitive resin, exposing the resin with an exposure mask, and developing the exposed resin. In one embodiment, the exposure mask is aligned with the vias 29.

[0074] Although not detailed here, the mask 39 may correspond to a layer of resin with openings 41, or to at least one layer deposited before the resin and through which the openings 41 are engraved from corresponding openings formed in the resin, such a layer being generally called a hard mask layer.

[0075] According to one embodiment, the mask 39 comprises a hard mask layer, for example a titanium nitride (TiN) layer.

[0076] Fig. 6 represents circuit 1 of Fig. 5 at a subsequent step of the process.

[0077] An opening 43 was engraved through layer 37 from opening 41 of the mask 39 ([fig.5]) opposite electrode 15, and openings 43' were simultaneously etched from the openings 41 of mask 39 ([fig.5]) opposite vias 29. Mask 39 was then removed.

[0078] The etching is selective with respect to layer 9 and layer 17, or, in other words, is selective with respect to the material of layer 9 and the material of layer 17. For example, for layers 9 and 17 in SiCN or in SiN, for example a layer 9 in SiCN and a layer 17 in SiN, the etching, for example a dry etching, can be a fluorocarbon-based etching, for example based on C4F8.

[0079] The etching of the aperture 43 is stopped on the layer 17 covering the electrode 15, the aperture 43 then passing through the aperture 35 etched in the step of [fig.4], without changing the dimensions of the aperture 35 because the etching is selective with respect to the layer 9. The aperture 43 is therefore etched through the layer 37, and, when the etching described in the step of [fig.5] is stopped before the layer 17, through a part of the layer 7.

[0080] Furthermore, in the case where the circuit 1 includes vias 29, the etching of each opening 43' is stopped on layer 9.

[0081] Fig. 7 represents circuit 1 of Fig. 6 at a subsequent step of the process.

[0082] At the step in [Fig. 7], the etching of the aperture 43 is continued as far as electrode 15. Furthermore, at the same time, the etching of the apertures 43' is continued until each aperture 43' reaches the apex of a corresponding via 29. In other words, the etching of the aperture 43 is continued through layer 17 to electrode 15, in this example by passing through layer 23, and, when the circuit 1 includes vias 29, the etching of the apertures 43' is simultaneously continued through layer 9 to the apexes of the vias 29. During the etching of [Fig. 7], portions of layer 9 exposed during the etching of the aperture 43 described in relation to [Fig. 6] are also etched. As a result, as shown in [fig.7], the opening 43 has a shoulder defined by layer 7, for example at the top face of layer 7. In other words, layer 7 forms a shoulder in the opening 43.The dimensions of this shoulder are at least partly determined by the lateral dimensions of the opening 35 engraved in step [fig.3]. In addition, the dimensions of this shoulder determine at least partly the lateral dimensions of the bottom of the opening 43 at the electrode 15.

[0083] The steps in Figures 6 and 7 correspond in practice to an etching step of an opening 43 extending from the upper face of the layer 37 to the electrode 15, and, in the case where the circuit includes vias 29, to etching openings 43' extending from the upper face of the layer 37 to the tops of these vias 29, this etching step being implemented here by two successive etchings.

[0084] Fig. 8 represents circuit 1 of Fig. 7 at a subsequent step of the process.

[0085] At this stage, the first metal level Ml of the interconnection structure of the circuit 1 is formed by depositing at least one metal layer 45 so as to fill the openings 43 and cover the layer 37, then by performing a planarization step by chemical mechanical polishing or CMP ("Chemical Mechanical Polishing") up to the layer 37 so as to remove the part of the layer 45 disposed above the level of the top face of the layer 37.

[0086] By way of example, a single layer 45 of copper is deposited in the step of [fig.8].

[0087] The first metal level Ml of the interconnection structure of the circuit 1 thus obtained comprises a portion (on the right in [Fig. 8]) disposed above the electrode 15. This portion of the metal level Ml, which fills the opening 43, extends from the upper face of the layer 37 to the electrode 15 with which it is in contact, and rests partly on and in contact with the layer 7, for example on and in contact with the upper face of the layer 7. In other words, the portion of the metal level Ml disposed above the electrode 15 and filling the opening 43 rests partly on the shoulder formed by the layer 7 in the opening 43. Put yet another way, the metal level Ml extends into the layer 37 and comprises, above the electrode 15, a portion provided with an extension that extends through an opening 35 in layer 9, then through layer 7 to electrode 15.This extension has, at the level of the shoulder formed by layer 7 in the opening 43, for example at the level of the upper face of layer 7, lateral dimensions, for example measured in a plane parallel to the upper face of layer 3, which are smaller below the shoulder than above the shoulder. Put another way, the metal layer M1 comprises a portion in contact with electrode 15, this portion comprising a lower part in contact with electrode 15 and an upper part traversing layer 37 through its entire thickness, the lower part having, at the level where it is in contact with the upper part, smaller lateral dimensions than the upper part, and the upper part resting partly on the shoulder defined by layer 7. In this example, lateral portions of the upper part rest on layer 7.

[0088] The level of metal Ml obtained is in contact with the electrode 15 of component 13.

[0089] Furthermore, in the case where the circuit 1 includes vias 29, the metal level Ml is in contact with the tops of these vias 29.

[0090] The process continues with steps (not shown) of forming the other metal layers of the interconnecting structure, for example, during deposition, etching, and CMP steps of insulating and metallic layers to form these other metal layers and the conductive vias electrically connecting the metal layers of the interconnecting structure. These subsequent steps are within the capabilities of a person skilled in the art.

[0091] Although a single component 13 is shown in Figures 1 to 8, in practice the circuit 1 may comprise several components 13, for example, several thousand components 13 in the case where these are memory points. In this case, the steps described in relation to Figures 1 to 8 are carried out simultaneously for all the components 13 of the circuit 1, the circuit 1 possibly comprising different components 13. Similarly, the circuit 1 may comprise several components 27, for example, several thousand components 27. In this case, the steps described in relation to Figures 1 to 8 for manufacturing the metal level M1 in contact with the vias 29 electrically connecting, via the contacts 11, the metal level M1 to the contact areas 25 of the component 27 shown in these Figures 1 to 8, are carried out simultaneously for all the vias 29 associated with these components 27.

[0092] Furthermore, although only one circuit 1 has been described, in practice several circuits 1 are fabricated simultaneously from the same layer 3, the set of these circuits 1 then forming a wafer of circuits 1. The steps described in relation to Figures 1 to 8 are then preferably carried out simultaneously for all the circuits 1 of the same wafer, and then, once the fabrication of the circuits 1 and their interconnection structures is complete, the circuits 1 are separated by cutting the wafer. In this case, the layer deposition steps described above are carried out over the entire exposed surface of the wafer, these deposits being referred to as full-wafer depositions.

[0093] In the process described above, the lateral dimensions of the portion of the metal level Ml at the electrode 15 are at least partly determined by the lateral dimensions of the opening 35 engraved in the step of [fig.3]. One might have thought of omitting the step of etching the opening 35, and directly etching an opening from the upper face of the layer 37 to the electrode 15. However, the opening obtained in this way, without prior etching of the opening 35, would have had lateral dimensions at the electrode 15 that would have been larger than those of the opening 43 obtained by the process described in relation to Figures 1 to 8. In particular, the opening etched without a prior opening 35 could have extended onto the sides of the component 13, which would have led to the formation of a layer of metal M1 in contact with the electrode 15, but also with layers underlying the electrode 15, thus short-circuiting these layers of the component 13.To overcome this, one could have considered increasing the lateral dimensions of electrode 15, but this would have led to an increase in the surface area of ​​circuit 1, which is undesirable. Thus, the process described in relation to Figures 1 to 8 makes it possible to obtain a level of metal Ml in contact with an electrode 15 having smaller dimensions than if the process were implemented without the step of etching the opening 35 described in relation to Figure 1. [fig-3].

[0094] By way of example, the inventors have observed that with the process described above in relation to figures 1 to 8, it is possible to engrave an opening 43 whose bottom has, at the level of a corresponding electrode 15, minimum lateral dimensions less than 40 nm, for example equal to or substantially equal to 30 nm, which allows the electrode 35 to have corresponding lateral dimensions for example less than 60 nm, for example equal to or substantially equal to 50 nm.

[0095] Furthermore, in the process described in relation to Figures 1 to 8, in the step of etching the aperture 43 (Figures 6 and 7) up to the electrode 15, it is not necessary for the aperture 41 of the mask 39, from which the aperture 43 is etched, to be perfectly aligned with the electrode 15, since the aperture 35 allows for the correction of any alignment error. This would not have been the case without the prior aperture 35, because the etched aperture could then have exposed the sides of the component 13.

[0096] Furthermore, rather than manufacturing the metal level Ml in contact with the electrode 15 of the component 13, it could have been considered, during the formation of the vias 29, to simultaneously form an additional via 29 whose base would have been in contact with the electrode 15 and whose top would have been flush with the upper face of the layer 7. However, compared to the process described in relation to Figures 1 to 8, this would have required a greater thickness of layer 7 between the component 13 and the layer 9, which would have led to longer vias 29 and therefore to greater parasitic capacitances, in particular for the vias 29 allowing to electrically connect the areas 25 of components 27 to the metal level Ml, which is not desirable.

[0097] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, although an example has been described in connection with Figures 1 to 8 in which the component 13 is a memory point such as a memory point of a phase-change memory, the described method can be implemented with other components comprising a contact region located at an intermediate level between the level of the vertices of the contact vias 11 and the layer 9 on which the first metal level M1 of a circuit interconnection structure will rest, for example, a memory point of a magnetic type memory or an oxide-based resistive memory, or a component other than a memory point.Furthermore, a person skilled in the art is able to modify the various materials indicated above as examples by adapting the described process, in particular to respect the engraving selectivities described.

[0098] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Claims

1. A method of manufacturing an interconnection structure comprising the following successive steps: a) providing an integrated circuit (1) comprising: a first insulating layer (5); a second insulating layer (7) resting on the first layer; a third insulating layer (9) resting on the second layer; electrical contact vias (11) passing through the first layer (5); first electrically conductive vias (29) passing through the second insulating layer (7) and extending from a corresponding electrical contact via (11) to said third layer (9); and a memory point (13) of a phase change memory, an electrical contact region (15) of the memory point (13) being located in the second layer (7) and being covered by a part of this second layer (7);b) etching a first opening (35) through the third layer (9) and directly above the contact region (15), the etching of the first opening (35) being stopped before the contact region (15); c) depositing a fourth insulating layer (37) so as to fill the first opening (35) and to cover the third layer (9); d) etching a second opening (43) through the fourth layer (37) to the contact region (15) so that the second opening (43) passes through the third insulating layer (9) at the first opening (35); and e) forming a metal level (Ml) of the interconnection structure by filling the second opening with at least one metal (45).;

2. A method according to claim 1, wherein, in step a), the electrical contact vias (11) have tops located below the second insulating layer (7).

3. A method according to claim 1 or 2, wherein third openings (43') are etched at the same time as the second opening (43) in step d), each third opening (43') being etched directly above one of the first vias (29) and up to said first via (29).

4. The method of claim 3, wherein step d) comprises depositing a first layer of photosensitive resin and aligning an insolation mask of the first layer of resin with said first vias (29).

5. A method according to any one of claims 1 to 4, wherein, at step a), a fifth insulating layer (17) covers the contact region (15), and, in step d), the etching of the second opening (43) comprises a first etching up to said fifth layer (17) followed by a second etching through the fifth layer and up to the contact region (15).

6. The method of claim 5, wherein the first etching is selective with respect to the third insulating layer (9) and the fifth insulating layer (17).

7. Method according to claims 3 and 5, wherein, in step d), the third openings (43') are etched up to the third layer (9) during the first etching, then up to the first vias (29) during the second etching.

8. A method according to any one of claims 1 to 7, wherein step b) comprises depositing a second layer of photosensitive resin and aligning an exposure mask of the second layer of resin with said contact region (15).

9. A method according to any one of claims 1 to 8, wherein, in step b), the first opening (35) has lateral dimensions smaller than corresponding lateral dimensions of the contact region (15).

10. A method according to any one of claims 1 to 9, wherein step e) comprises depositing said at least one metal (45) so as to fill the second opening (43) and to cover the fourth insulating layer (37), and a step of chemical mechanical polishing down to the fourth insulating layer.

11. Method according to any one of claims 1 to 10, wherein, in step a), the first insulating layer (5) rests on a semiconductor layer (3), preferably provided with electrical contact areas (25) in contact with corresponding electrical contact vias (11).

12. A method according to any one of claims 1 to 11, wherein, in step a), the electrical contact region (15) of the memory point (13) is an upper contact region, the memory point further comprising a lower contact region (19) located directly above the upper contact region (15), the lower contact region being in contact with a vertex of one of said electrical contact vias (11).

13. An integrated circuit (1) comprising: a first insulating layer (5); a second insulating layer (7) resting on the first layer (5); a third insulating layer (9) resting on the second layer (7); electrical contact vias (11) passing through the first layer (5); a memory point (13) of a phase change memory, the memory point (13) comprising an upper electrical contact region (15) located in the second layer (7) below the upper face of the layer (7), and a lower electrical contact region (19) in contact with a vertex of one of the electrical contact vias (11); a fourth insulating layer (37) resting on an upper face of the third insulating layer (9); and a first metal level (Ml) of an interconnection structure of the circuit (1) comprising a portion extending from an upper face of the fourth layer (37) to the upper electrical contact region (15) and resting partly on and in contact with the second insulating layer (7), preferably on and in contact with a shoulder defined by the second insulating layer, the first metal level (Ml) being the metal level of the interconnection structure closest to a semiconductor layer (3) of the circuit (1).

14. Circuit according to claim 13 wherein said first metal level (Ml) is obtained by implementing the method according to any one of claims 1 to 12.

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