METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE ON INSULATION OF THE SOI OR SIGEOI TYPE BY NEED AND STRUCTURE FOR MANUFACTURING SUCH A SUBSTRATE

Abstract

A process for manufacturing a semiconductor-on-insulator substrate (SOI) by BESOI comprising the following steps: a) providing a structure comprising a first substrate (110), a first arrest layer (111) of SiGe having an atomic percentage of Ge less than or equal to 30%, an intermediate layer (112), a second arrest layer (113) of SiGe having a thickness less than the thickness of the first arrest layer and an atomic percentage of Ge greater than or equal to 20%, optionally an active region formed of a silicon layer (114) or a stack of active layers of Si and SiGe, a dielectric layer (121), a second substrate (120); b) thinning and then etching the first silicon substrate (110), from the first main face to the second main face; c) successively removing the first arrest layer (111), the intermediate layer (112), and optionally the second arrest layer (113) to obtain an SOI substrate or SiGeOI.Figure for the abridged version: 4B.

Description

Title of the invention: METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE ON SOI OR SIGEOI TYPE INSULATOR BY NEED AND STRUCTURE FOR MANUFACTURING SUCH A SUBSTRATE Technical field

[0001] The present invention relates to the general field of semiconductor-on-insulator substrates, for example of the SOI or SiGeOI type.

[0002] The invention relates to a method for manufacturing a semiconductor-on-insulator substrate by BESOI.

[0003] The invention also relates to a structure for manufacturing a semiconductor-on-insulator substrate by BESOI.

[0004] The invention finds applications in numerous industrial fields, and in particular for 3D integration.

[0005] The invention is particularly interesting since it makes it possible to manufacture SOI substrates, and in particular FDSOI type substrates, at low temperature. STATE OF THE PRIOR ART

[0006] There are several methods for manufacturing a silicon on insulator (SOI) substrate.

[0007] One of the methods consists of implanting hydrogen into a silicon substrate. The substrate is then bonded by molecular adhesion to another substrate, then a heat treatment is carried out at a temperature typically above 400°C to induce a fracture at the hydrogen-implanted area. This fracture causes the assembly of bonded substrates to separate at the hydrogen-implanted area. This produces an SOL substrate. However, such a thermal budget is not compatible with all technologies. In addition, SOI substrates obtained by a Smart-Cut® type process must then be subjected to:

[0008] - to a thermal oxidation thinning step followed by removal of the oxide and / or a high temperature process (typically above 1000°C) to remove residual surface roughness from the fracture process, and

[0009] - at a high temperature annealing step (typically at a temperature above 900°C) to eliminate implantation defects.

[0010] However, such a thermal budget is not compatible with all technologies.

[0011] In order to overcome this drawback, it is possible to manufacture an SOI substrate with a BESOI (“Bonded and Etch back Silicon On Insulator”) type process.

[0012] This method consists of bonding two silicon substrates 10, 20: a donor substrate 10 and a handling substrate 20. The handling substrate 20 is covered by an oxide layer 21 ([Fig.lA]). The donor substrate 10 is then thinned until an active silicon layer of the desired thickness is obtained, typically from 100 nm to a few micrometers ([Fig.1B]). Alternatively, it is possible to have the oxide layer on the donor substrate 10 or on both the donor substrate 10 and the handling substrate 20. One of the main advantages of this technology is the implementation of bonding with a low thermal budget: bonding at 300°C may be sufficient to obtain the required properties.

[0013] However, one of the current challenges is to obtain SOI substrates having a very thin active layer of silicon, in particular of the order of ten nanometers or even less and with very low variability of this thickness on the wafer, typically less than 10% of the thickness of the active layer.

[0014] To accurately determine the end of the thinning step of a BESOI process, it is possible to use a stop layer 11 ([Fig.2]). The stop layer 11 is formed on the handling substrate 10, then the active silicon layer of the desired thickness. The two substrates 10, 20 are then fixed to each other. The substrate 10 is thinned down to the stop layer 11 and then this stop layer 11 is removed. An SOI substrate with a thin active layer is then obtained.

[0015] For example, document US 5,013,681 describes a method for manufacturing an SOI substrate by BESOI with one or two stop layers. One of the stop layers may be SiGe. The method with a stop layer comprises, for example, the following steps:

[0016] - forming a barrier layer in an alloy of silicon and germanium, for example by chemical vapor deposition (CVD) or molecular beam epitaxy (MBE) at a temperature of 400°C to 900°C, on a first silicon substrate, the barrier layer having a thickness of between 10 nm and 500 nm,

[0017] - forming a layer of silicon having a thickness between 20 nm and 1 pm, on the barrier layer at a temperature of 400°C to 900°C, then oxidize it to obtain an oxide layer on the surface,

[0018] - bonding the stack thus obtained onto a second silicon substrate covered by an oxide layer, the annealing temperature being between 700°C and 1000°C,

[0019] - polishing, for example by CMP, the first stack, up to the stop layer, then remove the stop layer, for example by etching.

[0020] However, this document is silent on how to choose the thickness of the layers.

[0021] However, the step of thinning the donor substrate is generally carried out by mechanical grinding in order to quickly remove a large quantity of material from the donor substrate 10 and thus quickly obtain reasonable thicknesses for the rest of the process. This step locally leads to thickness variations ([Fig. 3A]). This inhomogeneity can be characterized by the total thickness variation (hereinafter called TTV for 'Thickness Total Variation'). It can be represented schematically by a slope (as in [Fig. 3B]). In addition, even if subsequently, the material removal is carried out by chemical etching and / or by chemical-mechanical polishing (CMP), the TTV can be slightly reduced but these inhomogeneities remain.

[0022] Thus, when the stop layer is reached in the thinning step, we define the thickness variation due to the thinning / etching of the silicon by TTV arrival (or 'TTV landing'). The function of the stop layer is to reduce this arrival thickness variation. An ideally perfect stop layer will reduce the TTV arrival to zero. However, in most practical cases a thickness variation is transferred to the stop layer and defined as transferred TTV. The stop layer 11 must therefore have a minimum thickness preferably at least equal to the transferred TTV so that the thickness variation due to the etching of the silicon substrate 10 is 'absorbed' in the stop layer 11 and does not propagate to the underlying active silicon layer 12 ([Fig. 3A] and 3B).

[0023] With the most recent thinning machines ('grinding'), the material removal can be quite homogeneous and the TTV is quite low (typically less than or equal to 1000 nm, for example of the order of 500 nm). A single stop layer may be sufficient to manufacture an SOI substrate by BESOI with low thicknesses and thickness variations of the transferred layer.

[0024] But for many machines, especially for less expensive machines and / or for older generation machines, the first thinning step can lead to high TTVs (typically greater than or equal to 2000nm or even greater than or equal to 2500nm). A single stop layer is then no longer sufficient. It is then necessary to have a structure with several stop layers.

[0025] However, the choice of the nature and thickness of these barrier layers is not obvious because it is necessary to take into account numerous parameters such as the critical thickness of plastic relaxation of the barrier layers and the total thickness of the structure which must remain in a pseudomorphic state. Statement of the invention

[0026] An object of the present invention is to provide a method for manufacturing a semiconductor-on-insulator substrate, for example Silicon on Insulator (SOI) or SiGe on insulator (SiGeOI), by BESOI remedying at least in part the drawbacks of the prior art, which can be implemented in many thinning machines, even the least efficient (which can lead to TTVs greater than or equal to 2000nm or even greater than or equal to 2500nm), and making it possible to manufacture an SOI substrate having at the end of the process a good quality active silicon layer.

[0027] For this, the present invention proposes a method for manufacturing a semiconductor-on-insulator substrate, in particular a silicon-on-insulator or SiGe-on-insulator type substrate, by BESOI comprising the following steps:

[0028] a) providing a structure comprising:

[0029] - a first silicon substrate, comprising a first main face and a second main face,

[0030] - a first SiGe barrier layer having a first thickness and a atomic percentage of Ge less than or equal to 30%, and preferably between 15% and 30%, the first barrier layer being in contact with the second main face of the first substrate,

[0031] - an intermediate layer of silicon or SiGe, the atomic percentage of Ge of the intermediate layer being at least 10% or even at least 15% lower than the atomic percentage in Ge of the first barrier layer,

[0032] - a second SiGe barrier layer having a second lower thickness to the first thickness of the first layer and an atomic percentage of Ge greater than or equal to 20%, the atomic percentage of Ge of the intermediate layer being at least 10% or even at least 15% lower than the atomic percentage of Ge of the second barrier layer,

[0033] - optionally, an active zone formed from an active silicon layer or a stack of active layers comprising at least one silicon layer and at least one SiGe layer preferably having an atomic percentage of Ge of between 20% and 35%,

[0034] - a dielectric layer, for example made of silicon oxide or silicon nitride,

[0035] - a second substrate, for example made of silicon.

[0036] b) thinning the first silicon substrate, from the first main face, so as to remove a first part of the first substrate and to leave a second part of the substrate, the second part having, for example, a thickness less than or equal to 50 pm, for example between 30 and 50 pm, preferably less than or equal to 30 pm, for example between 20 and 30 pm, even more preferably less than or equal to 20 pm, for example between 10 and 20 pm, even more preferably less than or equal to 10 pm, for example between 2.5 and 10 pm, the thinning step b) being able to lead to a variation in the total thickness of the first thinned substrate greater than or equal to 2000nm, and preferably greater than or equal to 2500nm,

[0037] c) successively remove:

[0038] - the second part of the first substrate, for example, by chemical etching, up to the second main face of the first substrate, so as to reach the first stop layer,

[0039] - the first stop layer, for example by chemical etching,

[0040] - the intermediate layer, for example by chemical etching,

[0041] - optionally, the second stop layer, for example by chemical etching, whereby a semiconductor-on-insulator substrate is obtained comprising a substrate covered by a dielectric layer and an active zone or a substrate covered by a dielectric layer and the second SiGe barrier layer.

[0042] The invention is fundamentally distinguished from the prior art by the use of a structure comprising two SiGe barrier layers. These barrier layers have particular thicknesses and germanium concentrations. With such a structure, at the end of the BESOI process, a very high-quality semiconductor-on-insulator substrate, for example SOI or SiGeOI, is obtained. In particular, the SOI substrate has an active silicon layer having a very low total thickness variation induced by the process (TTV for 'Total Thickness Variation') which can go down to the sub-nanometric scale. Thus, the active layer can be very thin (typically with a thickness less than or equal to 10 nm).

[0043] Such a structure is particularly interesting for the manufacture of advanced BESOI implementing thinning steps with thinning machines that are less efficient and / or less expensive than those of the latest generations. Indeed, this structure makes it possible to compensate for TTVs of 2000 nm or more or even 2500 nm or more.

[0044] Advantageously, the first barrier layer has an atomic percentage of Ge less than or equal to 25%, and preferably greater than or equal to 20%.

[0045] Advantageously, the second barrier layer has an atomic percentage of Ge greater than or equal to 20%, and preferably less than or equal to 40%.

[0046] The first barrier layer and the second barrier layer may have the same or different Ge concentrations. For example, both barrier layers may have a Ge concentration of 20%.

[0047] Advantageously, the second thickness is at least two times less than the first thickness. The second thickness is for example 5 to 10 times less than the first thickness. Even more advantageously, the second thickness is at least 10 times less than the first thickness.

[0048] The first barrier layer has a thickness, for example, less than 200 nm. Advantageously, the first barrier layer has a thickness between 50 nm and 150 nm, for example 70-80 nm, and an atomic concentration of Ge of 25%.

[0049] Advantageously, the second barrier layer has a thickness less than or equal to 20 nm. Preferably, it has a thickness between 8 nm and 20 nm, for example 10 nm, and an atomic concentration of Ge of 30 to 40%, for example 40%. The second barrier layer, having a high concentration of Ge, can be very thin. The use of barrier layers of low thickness is advantageous from an economic point of view but also to reduce the degradation of the TTV introduced by the epitaxy process and to minimize the risk of formation of dislocations (critical thickness).

[0050] Advantageously, the intermediate layer and / or the active silicon layer have a thickness between 5 nm and 100 nm, preferably from 10 to 20 nm, for example 10 nm.

[0051] The thickness of the silicon intermediate layer is chosen so as to obtain a structure having a thickness less than the critical thickness of the structure to maintain the multilayer in a pseudomorphic state. The choice of a small thickness is also advantageous to minimize the production cost. It is also advantageous to reduce the thickness of the epitaxial layer to reduce the TTV. On the other hand, a thicker intermediate layer makes it possible to compensate for the stress of the SiGe layer.

[0052] Advantageously, the structure provided in step a) is obtained according to the following steps:

[0053] i) providing a first stack comprising:

[0054] - a first silicon substrate,

[0055] - a first SiGe barrier layer having a first thickness and a atomic percentage in Ge less than or equal to 30%, and preferably between 15% and 30%,

[0056] - an intermediate layer of silicon or SiGe, the atomic percentage of Ge of the intermediate layer being at least 10% or even at least 15% lower than the atomic percentage in Ge of the first barrier layer,

[0057] - a second SiGe barrier layer having a second lower thickness at the first thickness of the first layer and an atomic percentage of Ge greater than or equal to 20%, the atomic percentage of Ge of the intermediate layer being at least 10% lower than the atomic percentage of Ge of the second barrier layer,

[0058] - possibly an active zone formed from an active silicon layer or a stack of active layers comprising at least one silicon layer and at least one SiGe layer preferably having an atomic percentage of Ge of between 20% and 35%,

[0059] ii) providing a second stack comprising a second substrate, for example, made of silicon, covered by a dielectric layer, for example made of silicon oxide,

[0060] iii) fixing the first stack on the second stack, so as to have the dielectric layer in contact with the second barrier layer or with the active zone where appropriate.

[0061] The process for manufacturing the structure can in particular be carried out at low temperature (typically less than 500°C and preferably less than or equal to 300°C, or even less than or equal to 200°C).

[0062] The process has many advantages:

[0063] - do not use boron for the stop layer, which avoids contaminating the silicon,

[0064] - fabricate SOI substrates ('SOI wafer') with a low thermal budget (with bonding at 200°C, we obtain a bonding of 4 J / m2 for a Si / SiO2 interface) and without having the disadvantages linked to ion implantation, for example the presence of defects in the transferred layers,

[0065] - being able to manufacture an SOI substrate having a thin active layer compatible with the specifications of an FDSOI ('Fully Depleted Silicon on Insulator') technology, conventionally obtained by a Smart-Cut® type process,

[0066] - allow integration on a substrate containing circuits sensitive to high temperatures.

[0067] The invention also relates to a structure for manufacturing a silicon-on-insulator semiconductor substrate comprising:

[0068] - a first silicon substrate,

[0069] - a first SiGe barrier layer having a first thickness and a atomic percentage in Ge less than or equal to 30%, and preferably between 15% and 30%,

[0070] - an intermediate layer of silicon or SiGe, the atomic percentage of Ge of the intermediate layer being at least 10% or even at least 15% lower than the atomic percentage in Ge of the first barrier layer,

[0071] - a second SiGe barrier layer having a second lower thickness to the first thickness of the first layer and an atomic percentage of Ge greater than or equal to 20%, the atomic percentage of Ge of the intermediate layer being at least 10% or even at least 15% lower than the atomic percentage of Ge of the second barrier layer,

[0072] - optionally, an active zone formed from an active silicon layer or a stack of active layers comprising at least one silicon layer and at least one SiGe layer preferably having an atomic percentage of Ge of between 20% and 35%,

[0073] - a dielectric layer, for example made of silicon oxide,

[0074] - a second substrate, for example made of silicon.

[0075] Advantageously, the structure comprises:

[0076] - a first silicon substrate,

[0077] - a first SiGe stop layer having a thickness between 50 nm and 150 nm and an atomic concentration of Ge of 20% to 25%,

[0078] - an intermediate layer of silicon,

[0079] - a second SiGe barrier layer having a thickness between 8 nm and 20 nm, by example lOnm, and an atomic concentration in Ge of 20% to 40%,

[0080] - an active silicon layer,

[0081] - a layer of silicon oxide,

[0082] - a second silicon substrate.

[0083] Other characteristics and advantages of the invention will emerge from the additional description which follows.

[0084] It goes without saying that this additional description is given only as an illustration of the subject of the invention and must in no case be interpreted as a limitation of this subject. Brief description of the drawings

[0085] The present invention will be better understood on reading the description of exemplary embodiments given purely for informational purposes and in no way limiting, with reference to the appended drawings in which:

[0086] [Fig.lA]

[0087] [Fig. IB] previously described, schematically represent in section different stages of a method of manufacturing an SOI substrate by BESOI according to the prior art.

[0088] [Fig.2] previously described, represents schematically and in section, a structure for obtaining an SOI substrate by BESOI, the structure comprising a stop layer, according to the prior art.

[0089] [Fig.3A]

[0090] [Fig.3B], previously described, represent schematically and in section, thickness variations after thinning of a silicon substrate in a structure comprising a barrier layer, according to the prior art.

[0091] [Fig.4A]

[0092] [Fig.4B]

[0093] [Fig.4C]

[0094] [Fig.4D]

[0095] [Fig.4E]

[0096] [Fig.4F]

[0097] [Fig.4G] schematically represent in section different steps of a method of manufacturing an SOI substrate by BESOI according to a particular embodiment of the invention.

[0098] [Fig.5] is a graph representing the transferred TTV as a function of the Landing TTV for SiGe barrier layers of different concentrations, horizontal lines represent critical thicknesses of SiGe barrier layers at 20, 30 and 40%.

[0099] [Fig.6] is a graph representing the TTV transferred at the interfaces of a structure with two SiGe stop layers, for different Ge concentrations, and for a TTV landing of 500nm.

[0100] [Fig.7] is a graph representing the TTV transferred at the interfaces of a structure with two SiGe stop layers, for different Ge concentrations, and for a TTV landing of 2000nm.

[0101] [Fig.8] is a graph representing the TTV transferred at the interfaces of a structure with two SiGe stop layers, for different TTV landings, and for a Ge concentration of 20%.

[0102] The different parts represented in the figures are not necessarily on a uniform scale, in order to make the figures more readable.

[0103] The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with each other.

[0104] Further, in the following description, terms that depend on the orientation, such as "above", "below", etc., of a structure apply with the assumption that the structure is oriented as illustrated in the figures.

[0105] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0106] We first refer to Figures 4A to 4G which represent different steps of a method for manufacturing an SOI substrate by BESOI. The method comprises the following steps:

[0107] a) providing a multi-layer structure 100 to be thinned, obtained for example, according to the following sub-steps i), ii) and iii):

[0108] i) providing a first stack comprising successively:

[0109] - a first silicon substrate 110 (called donor substrate) comprising a first main face and a second main face,

[0110] - a first stop layer 111 in SiGe having a first thickness and a atomic percentage in Ge less than or equal to 30%, and preferably between 15% and 30%,

[0111] - an intermediate layer 112 made of silicon or SiGe,

[0112] - a second stop layer 113 in SiGe having a second lower thickness at the first thickness of the first layer and an atomic percentage in Ge greater than or equal to 20%,

[0113] - possibly an active zone formed from an active layer (114) of silicon ([Fig.4A]) or a stack of active layers formed of at least one silicon layer and at least one SiGe layer preferably having an atomic percentage of Ge between 20% and 35%,

[0114] ii) providing a second stack comprising a second substrate, for example made of silicon 120 (called the handling substrate) covered by a dielectric layer 121, for example made of silicon oxide or silicon nitride ([Fig.4A]),

[0115] iii) fixing the first stack on the second stack, the dielectric layer 121 being in contact with the active zone or with the second stop layer 113 ([Fig.4B]),

[0116] b) progressively thinning the first silicon substrate 110, from the first main face of this substrate, so as to remove a first part of the first substrate 110 and to leave a second part of the substrate 110, the second part having, for example, a thickness less than 30 and 50 pm, preferably between 20 and 30 pm, even more preferably between 10 and 20 pm, even more preferably between 2.5 and 10 pm, the thinning step possibly leading to a total variation in thickness greater than or equal to 2000 nm, and preferably greater than or equal to 2500 nm,

[0117] ([Fig.4C]),

[0118] c) successively remove:

[0119] - the second part of the first substrate 110, for example, by chemical etching, to the second main face of the first substrate 110, so as to reach the first stop layer 111 ([Fig.4D]),

[0120] - the first stop layer 111 ([Fig.4E]),

[0121] - the intermediate layer 112 ([Fig.4F]),

[0122] - possibly, the second stopping layer 113, whereby a semiconductor-on-insulator substrate comprising a substrate 120 covered by a dielectric layer 121 and an active zone or a substrate 120 covered by a dielectric layer 121 and the second SiGe barrier layer 113 ([Fig.4G]).

[0123] When the second stop layer 113 is removed and the first stack comprises an active zone, in particular an active silicon layer 114, an SOI type substrate is obtained.

[0124] When the second barrier layer 113 is not removed and the first stack does not include an active zone, a SiGeOI type substrate is obtained. The second barrier layer 113 then also plays the role of active layer.

[0125] The first stack provided in step i) comprises a first substrate 110, two etch stopping layers 111, 113 (ESL for 'etch stopping layer'), an intermediate layer 112 and possibly an active zone.

[0126] The first substrate 110 comprises two main faces: a first main face and a second main face.

[0127] The first stop layer 111 is in contact with the second main face of the first substrate 110.

[0128] The first stop layer 111 has a thickness making it possible to absorb the variation in thickness resulting from the thinning step and / or the etching step of the first substrate 110.

[0129] The second barrier layer 113 has a thickness making it possible to absorb the variation in thickness resulting from the etching of the intermediate layer 112.

[0130] These thicknesses are advantageously compatible with the critical thickness of plastic relaxation in order to avoid the formation of dislocations. Generally speaking, the smallest possible thickness will be chosen to minimize the degradation of the TTV due to epitaxy and / or the etching step. The thicknesses of the layers of the first stack also depend on the selectivities during etching. The greater the selectivity, the smaller the thickness of the barrier layer can be.

[0131] Preferably, the second thickness is at least two times less than the first thickness, and even more preferably, the second thickness is at least 10 times less than the first thickness.

[0132] Preferably, the first barrier layer 111 has an atomic percentage of Ge greater than or equal to 20% and / or less than or equal to 25%.

[0133] Preferably, the second barrier layer 113 has an atomic percentage of Ge greater than or equal to 20% and / or less than or equal to 40%.

[0134] For example, the first barrier layer 111 has a thickness between 50 nm and 150 nm and an atomic concentration of Ge of 25%.

[0135] For example, the second barrier layer 113 has a thickness between 5 nm and 20 nm, for example 10 nm, and an atomic concentration in Ge of 40%.

[0136] The thicknesses of the first barrier layer 111 and of the second barrier layer 113 advantageously comply with the criterion of the critical thickness of plastic relaxation detailed, for example, in the article by Hartmann et al. (J. Appl. Phys. 110, 083529 (2011)).

[0137] The intermediate layer 112 makes it possible to absorb the variation in thickness. The intermediate layer is made of Si or SiGe.

[0138] The atomic percentage of Ge in the intermediate layer is at least 10% or even at least 15% lower than the atomic percentage of Ge in the first barrier layer.

[0139] The atomic percentage of Ge in the intermediate layer being at least 10% or even at least 15% lower than the atomic percentage of Ge in the second barrier layer.

[0140] Such percentages make it possible to have good selectivity between the intermediate layer and the stopping layers.

[0141] When etching the upper layer, the stop layer is not or only slightly etched, which makes it possible to stop the etching thanks to a difference in etching selectivity.

[0142] The active zone may be formed from an active silicon layer 114 or from a so-called active stack of active layers. The stack of active layers comprises at least one silicon layer and at least one SiGe layer. In particular, the stack comprises at least two layers. It may comprise more than 2 layers, for example from 3 to 21 layers. The stack is formed from an alternation of Si layers and SiGe layers. For example, it may contain 10 Si layers.

[0143] The atomic percentage of the SiGe layer or layers of the stack is between 20% and 35%, preferably between 20% and 30%.

[0144] The intermediate layer 112 and / or the active layer 114 made of silicon preferably have a thickness between 5 nm and 30 nm, for example 10-20 nm.

[0145] To obtain this first stack provided in step i), the first SiGe barrier layer 111, the intermediate layer 112, the second SiGe barrier layer 113 and finally the active zone are formed on the first silicon substrate 110. These layers are preferably formed by epitaxy.

[0146] The second stack provided in step ii) comprises a dielectric layer 121, in particular an oxide layer which can be formed on the second substrate 120 by thermal oxidation. The dielectric layer 121 can have a thickness of 10 to 1000 nm. The dielectric layer 121 acts as a bonding layer.

[0147] Alternatively, the first stack comprises a dielectric layer. According to another alternative, the first stack comprises a first dielectric layer and the second stack comprises a second dielectric layer.

[0148] The two stacks are fixed to each other (step iii), preferably by molecular bonding. At the end of step iii), the second barrier layer 113 is positioned between the dielectric layer 121 and the intermediate layer 112.

[0149] The structure thus obtained successively comprises:

[0150] - a first silicon substrate 110,

[0151] - a first stop layer 111 in SiGe having a first thickness and a atomic percentage of Ge less than or equal to 30%, and preferably between 15% and 30%, the thickness of the first layer advantageously respecting the criterion of the criterion thickness,

[0152] - an intermediate layer 112,

[0153] - a second stop layer in SiGe 113, having a second lower thickness the first thickness of the first layer,

[0154] - possibly an active zone for example an active layer in silicon 114,

[0155] - a dielectric layer 121,

[0156] - a second substrate, for example made of silicon 120.

[0157] By way of illustration and not limitation, according to an alternative embodiment, the structure may comprise:

[0158] - a first silicon substrate 110,

[0159] - a first stop layer 111 in SiGe of 80 nm having an atomic percentage in Ge of 25%,

[0160] - a 10 nm 112 silicon intermediate layer,

[0161] - a second 10 nm SiGe 113 stop layer having an atomic percentage in Ge of 40%,

[0162] - a 10 nm active layer of silicon 114,

[0163] - a layer of silicon oxide 121 of 145 nm,

[0164] - a second silicon substrate 120.

[0165] According to another variant embodiment, the structure may comprise:

[0166] - a first silicon substrate 110,

[0167] - a first stop layer 111 in SiGe having a thickness between 200 and 240 nm and an atomic concentration of Ge of 20%,

[0168] - an intermediate layer 112 in silicon of 15 to 30 nm,

[0169] - a second stop layer 113 in SiGe having a thickness between 10 nm and 20 nm, and an atomic concentration of Ge of 30%,

[0170] - an active layer of silicon 114 of 5 to 50nm,

[0171] - a layer of silicon oxide 121,

[0172] - a second silicon substrate 120.

[0173] Such structures are stable. The thickness of a multilayer structure is defined by: [Math 1] with ti the thickness of a layer i

[0174] Advantageously, this thickness is less than the critical thickness of the multilayer structure given in the article Hartmann et al. cited previously.

[0175] The critical thickness depends in particular on the average germanium concentration of the barrier layers defined by: [Math 2] With Xi the germanium concentration of the barrier layer i, t; the thickness of the barrier layer i, i an integer (in the case of two barrier layers i is equal to 1 or 2)

[0176] During step b), the first substrate 110 is thinned. At least a first part of the first substrate is removed from the first main face.

[0177] Preferably, the first substrate 110 is thinned at least in part, or even completely, by thinning by mechanical lapping also called grinding. This step leads to a large variation in the total thickness of the thinned substrate.

[0178] Advantageously, the removal of the first substrate 110 takes place in two sub-steps.

[0179] In a first sub-step, thinning by mechanical lapping is carried out to quickly remove a first portion of the first substrate 110 from the first main face. Typically, a thickness of a few hundred or tens of micrometers is removed, down to a thickness typically less than 30 or 50 μm, or less than 20 or 30 μm or even less than 10 μm. A first portion can be removed so as to have a second portion whose thickness is less than 5 μm. After thinning by mechanical lapping, the total thickness variation (TTV) at the surface of the first thinned substrate can be greater than or equal to 2000 nm or greater than or equal to 2500 nm. It can also be less, for example, the total thickness variation (TTV) at the surface of the first thinned substrate can be 500 nm.

[0180] Then in a second sub-step, chemical mechanical polishing (CMP) and / or chemical etching (wet and / or dry) is carried out, making it possible to remove the second part of the first substrate 110 more finely up to the second main face of the first substrate 110 (step c).

[0181] Advantageously, the second sub-step makes it possible to obtain a surface without defects, and in particular without scratches.

[0182] At the end of the second sub-step, the TTV remains greater than or equal to 2000 nm or even greater than or equal to 2500 nm.

[0183] At the end of step b), the first substrate 110 has been thinned down to the second main substrate.

[0184] The thickness variation when the second main face of the first substrate 110 in contact with the first barrier layer 111 is reached is called the arrival TTV ('TTV landing'). This thickness variation is at least partly transferred to the first barrier layer. The total thickness variation transferred to the first barrier layer is called the transferred TTV.

[0185] [Fig.5] represents the TTV transferred to a SiGe stop layer after the removal of a silicon layer, with a TEAH solution, for different arrival TTVs. This graph also represents the critical thicknesses te for SiGe layers having concentrations of 20%, 30% and 40%. This figure makes it possible to determine the minimum thickness of a SiGe layer to completely remove silicon by etching and stop the etching inside the SiGe layer, without removing it completely (in other words without reaching the underlying layer).

[0186] The values ​​of the critical thicknesses come from the article by Hartmann et al. cited above.

[0187] [Fig.5] shows for example that a Si layer with an arrival TTV of 3500 nm could be etched using a 20% pseudomorphic SiGe layer of about 240 nm. For an arrival TTV of 2000 nm, a 30% or even 35% SiGe layer could be used. However, the critical thicknesses of these layers are not compatible with the concentrations necessary to absorb the arrival TTVs.

[0188] [Fig.6] represents the variation of transferred thickness as a function of the interfaces of a structure obtained according to a typical removal sequence Si / interface 1 / SiGe / interface 2 / Si / interface 3 / SiGe / interface 4 / Si with a low arrival TTV ('TTV landing'), here 500nm. To obtain a sub-nanometric transferred TTV (i.e. having a value lower than Inm), a SiGe stop layer having an atomic concentration of at least 25% is sufficient.

[0189] [Fig.7] this time represents the variation of total thickness transferred as a function of the interfaces (same interfaces as for [Fig.6]) with a strong arrival TTV (TTV landing), here 2000nm. It would seem tempting to choose a first stop layer with concentrations of 30% or 35%, but their thicknesses would not be compatible with the critical thicknesses ([Fig.5]). Several stop layers are therefore necessary to be able to obtain a sub-nanometric TTV for the active layer.

[0190] [Fig.8] represents the evolution of the transferred TTV with 20% SiGe stop layers for different landing TTVs (from 1000nm to 3000nm) with the same interfaces as for [Fig.6]. It is clear from this figure that with an arrival TTV of 3000nm, a single stop layer leads to a TTV of the order of 10nm which is unacceptable in the case of advanced microelectronic applications. On the other hand, with two 20% SiGe stop layers, we obtain upon arrival at the active layer a TTV introduced by the thinning process of less than 1nm.

[0191] After step c), the other layers of the first stack are successively removed until a substrate of the SOI or SiGeOI type is obtained (step c):

[0192] - the first stop layer 111, by selective etching with stop on the layer intermediate,

[0193] - the intermediate layer 112, by selective etching with stopping on the second stop layer, and

[0194] - possibly the second stop layer 113 by selective etching with stop on the active area when present.

[0195] During steps b) and c), each of the elements (layer or substrate) to be etched advantageously exhibits etching selectivity relative to the underlying layer.

[0196] The first substrate 110 may have an etching selectivity with respect to the first stop layer 111 of, for example, between 10 and 100, preferably between 10 and 50.

[0197] The first barrier layer 111 may have a selectivity with respect to the intermediate layer 112 of, for example, between 10 and 500, preferably between 30 and 150.

[0198] The intermediate layer 112 may have a selectivity with respect to the second barrier layer 113 of, for example, between 10 and 100, preferably between 10 and 50.

[0199] The second barrier layer 113 may have a selectivity with respect to the active zone and in particular with respect to the active zone 114 of, for example, between 10 and 500, preferably between 30 and 150.

[0200] These different engravings can be dry or wet engravings.

[0201] An anisotropic silicon etching solution will be chosen, in particular a solution of TMAH (Tetramethylammonium Hydroxide), TEAH (Tetraethylammonium Hydroxide), KOH, or NH4OH.

[0202] By way of illustration, the silicon is removed by wet etching with a dilute solution, for example, between 2% and 10% and preferably 6% of TEAH at a temperature for example between 60°C and 90°C. Alternatively, it is possible to use a 5% TMAH solution for example at 60°C. It is also possible to choose a diluted ammonia solution of 1 to 5%, for example 4%, at 60°C.

[0203] Silicon can also be removed by dry etching, in particular fluorine-type plasma etching.

[0204] The first barrier layer 111 and / or the second barrier layer 113 are advantageously removed by wet etching.

[0205] The SiGe etching solution is, for example, an acetic acid / HF / H 2 O2 mixture, a SCI solution (mixture of ammonia NH4OH, hydrogen peroxide H2O2 and water) at room temperature or hot, a 5% H2O2 solution hot (for example at 60°C), a sulfuric acid solution hot (for example at 180°C), an SPM solution (“Sulfuric peroxide mixture”), a CARO solution, a Piranha solution (a mixture of sulfuric acid, for example, heated to 180°C, and hydrogen peroxide).

Claims

Claims

1. A method of manufacturing a semiconductor-on-insulator substrate by BESOI comprising the following steps: a) providing a structure successively comprising: - a first substrate (110) made of silicon, comprising a first main face and a second main face, - a first barrier layer (111) made of SiGe having a first thickness and an atomic percentage of Ge less than or equal to 30%, and preferably between 15% and 30%, the first barrier layer (111) being in contact with the second main face of the first substrate (110), - an intermediate layer (112) made of silicon or SiGe, the atomic percentage of Ge of the intermediate layer being at least 10% lower than the atomic percentage of Ge of the first barrier layer (111), - a second barrier layer (113) made of SiGe having a second thickness less than or equal to 20 nm, the second thickness being less than the first thickness of the first layer,the second barrier layer (113) having an atomic percentage of Ge greater than or equal to 20%, the atomic percentage of Ge of the intermediate layer being at least 10% lower than the atomic percentage of Ge of the second barrier layer (113), - a dielectric layer for example made of silicon oxide (121), - a second substrate for example made of silicon (120), b) thinning the first substrate (110) made of silicon, from the first main face, so as to remove a first part of the first substrate and leave a second part of the substrate, the second part having, for example, a thickness less than or equal to 50 pm, c) successively removing: - the second part of the first substrate (110), for example, by chemical etching, up to the second main face of the first substrate (110), so as to reach the first barrier layer (HD, - the first barrier layer (111), for example by chemical etching, - the intermediate layer (112),for example by chemical etching, whereby a semiconductor-on-insulator substrate is obtained comprising a substrate (120) covered by a dielectric layer (121) and the second SiGe barrier layer (113).

2. Method according to claim 1, wherein: - the structure provided in step a) further comprises, between the second barrier layer (113) and the dielectric layer (121), an active zone formed of a silicon active layer (114) or a stack of active layers comprising at least one silicon layer and at least one SiGe layer preferably having an atomic percentage of Ge of between 20% and 35%; and - step c) further comprises, after the removal of the intermediate layer (112), the removal of the second barrier layer (113), for example by chemical etching, whereby a semiconductor-on-insulator substrate is obtained comprising a substrate (120) covered by a dielectric layer (121) and an active zone (114).

3. 3. Method according to claim 1 or 2, characterized in that the thinning step b) leads to a variation in the total thickness of the first thinned substrate (110) greater than or equal to 2000nm, in particular greater than or equal to 2500nm.

4. 4. Method according to any one of claims 1 to 3, characterized in that the second thickness is at least twice less than the first thickness and preferably at least 10 times less than the first thickness.

5. 5. Method according to one of the preceding claims, characterized in that the first stop layer (111) has an atomic percentage of Ge less than or equal to 25%, and preferably greater than or equal to 20%.

6. 6. Method according to any one of the preceding claims, characterized in that the second barrier layer (113) has an atomic percentage of Ge greater than or equal to 20%, and preferably less than or equal to 40%.

7. 7. Method according to any one of the preceding claims, characterized in that the first barrier layer (111) has a thickness between 50 nm and 150 nm, for example 120 nm, and an atomic concentration in Ge of 25%.

8. 8. Method according to any one of the preceding claims, characterized in that the second barrier layer (113) has a thickness between 8 nm and 20 nm, for example 10 nm, and an atomic concentration of Ge of 40%.

9. Method according to any one of claims 1 and 3 to 8, characterized in that the structure provided in step a) is obtained according to the following steps: i) providing a first stack successively comprising: - a first silicon substrate (110), - a first barrier layer (111) of SiGe having a first thickness and an atomic percentage of Ge less than or equal to 30%, and preferably between 15% and 30%, - an intermediate layer (112) of silicon or SiGe, the atomic percentage of Ge of the intermediate layer (112) being at least 10% lower than the atomic percentage of Ge of the first barrier layer (111), - a second barrier layer (113) of SiGe having a second thickness less than or equal to 20 nm, the second thickness being less than the first thickness of the first layer, the second barrier layer (113) having an atomic percentage of Ge greater than or equal to at 20%,the atomic percentage of Ge of the intermediate layer being at least 10% lower than the atomic percentage of Ge of the second barrier layer (113), ii) providing a second stack comprising a second silicon substrate (120) covered by a dielectric layer (121) for example made of silicon oxide, iii) fixing the first stack on the second stack, so as to have the dielectric layer (121) in contact with the second barrier layer (113).,

10. 10. Method according to any one of claims 2 to 8, characterized in that the structure provided in step a) is obtained according to the following steps: i) providing a first stack successively comprising: - a first silicon substrate (110), - a first barrier layer (111) of SiGe having a first thickness and an atomic percentage of Ge less than or equal to 30%, and preferably between 15% and 30%, - an intermediate layer (112) of silicon or SiGe, the atomic percentage of Ge of the intermediate layer (112) being

11. at least 10% lower than the atomic percentage of Ge in the first barrier layer (111), - a second barrier layer (113) made of SiGe having a second thickness less than or equal to 20 nm, the second thickness being less than the first thickness of the first layer, the second barrier layer (113) having an atomic percentage of Ge greater than or equal to 20%, the atomic percentage of Ge of the intermediate layer being less than at least 10% of the atomic percentage of Ge of the second barrier layer (113), - an active zone formed from an active silicon layer (114) or a stack of active layers comprising at least one silicon layer and at least one SiGe layer preferably having an atomic percentage of Ge of between 20% and 35%, ii) providing a second stack comprising a second silicon substrate (120) covered by a dielectric layer (121) for example made of silicon oxide, iii) fixing the first stack on the second stack, so as to have the dielectric layer (121) in contact with the active zone.

11. Structure (100) for manufacturing a silicon-on-insulator semiconductor substrate according to a method according to any one of the preceding claims comprising: - a first silicon substrate (110), - a first stop layer (111) in SiGe having a first thickness and an atomic percentage in Ge less than or equal to 30%, and preferably between 15% and 30%, - an intermediate layer (112) of silicon or SiGe, the atomic percentage of Ge of the intermediate layer being at least 10% lower than the atomic percentage of Ge of the first barrier layer, - a second barrier layer (113) made of SiGe having a second thickness less than or equal to 20 nm, the second thickness being less than the first thickness of the first layer, the second barrier layer (113) having an atomic percentage of Ge greater than or equal to 20%, the atomic percentage of Ge of the intermediate layer being less than at least 10% of the atomic percentage of Ge of the second barrier layer (113), - a dielectric layer (121) for example made of silicon oxide, - a second substrate for example made of silicon (120).

12. 12. Structure (100) according to claim 11, further comprising, between the second barrier layer (113) and the dielectric layer (121), an active zone formed of an active layer (114) of silicon or of a stack of active layers comprising at least one layer of silicon and at least one layer of SiGe preferably having an atomic percentage of Ge of between 20% and 35%.

13. / V.

13. Structure according to claim 12, characterized in that it comprises: - a first silicon substrate (110), - a first barrier layer (111) of SiGe having a thickness between 50 nm and 150 nm and an atomic concentration of Ge of 20% to 25%, - an intermediate layer (112) of silicon, - a second barrier layer (113) of SiGe having a thickness between 8 nm and 20 nm, for example 10nm, and an atomic concentration of Ge of 20% to 40%, - an active layer of silicon (114), - a layer of silicon oxide (121), - a second silicon substrate (120).

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