METHOD FOR MANUFACTURING A MULTILAYER STRUCTURE

Abstract

METHOD FOR MANUFACTURING A MULTILAYER STRUCTURE One aspect of the invention relates to a method for manufacturing a multilayer structure (100), comprising the following steps: providing a stack comprising a substrate (31) and a dielectric layer (32) disposed on the substrate, the substrate (31) being formed of a semiconductor material having a resistivity greater than or equal to 500 Ω.cm; etching trenches (40) extending through the dielectric layer (32) and opening onto the substrate (31); etching the substrate (31) isotropically and selectively with respect to the dielectric layer (32) to form first cavities (50) in the substrate (31); and deposit (S4) a layer for trapping mobile electrical charges (60) on walls of the first cavities (50) and on side walls of the trenches (40), so as to plug the trenches (40) in the dielectric layer (32), thus closing the first cavities (50) in the substrate (31).Figure to be published with the abbreviation: Figure 3D.

Description

Title of the invention: METHOD FOR MANUFACTURING A MULTILAYER STRUCTURE Technical field

[0001] The present invention relates to semiconductor substrates used to manufacture integrated circuits, and more particularly radio frequency (RF) circuits. STATE OF THE ART

[0002] Different types of substrate can be used to manufacture integrated circuits. The substrate is generally chosen according to the type of circuit to be manufactured: radio frequency (RF) circuits, logic circuits based on MOS transistors, image sensors, etc.

[0003] Among the substrates of interest, we can cite the silicon-on-insulator or SOI multilayer structure (for "Silicon On Insulator" in English). The SOI multilayer structure successively comprises a silicon support layer, an electrically insulating layer, generally a so-called buried oxide layer (or BOX layer, for "buried oxide layer" in English), and a thin film of monocrystalline silicon, also called active layer. The active layer is so named because it is intended to receive active components, typically MOS transistors (acronym for "Metal Oxide Semiconductor"). The conduction channel of the MOS transistors is formed in the active layer. The SOI structure offers in particular the possibility of manufacturing fully depleted transistors (or FDSOI, for "Fully Depleted SOI") or partially depleted transistors (or PDSOI "Partially Depleted SOI").

[0004] [Fig.l] shows another multilayer structure 10, derived from the SOI structure and commonly used for the manufacture of RF integrated circuits, such as RF signal transceiver modules integrated in mobile phones (so-called “front-end” modules).

[0005] This multilayer structure 10, called “TR-SOI”, successively comprises a support layer 11 made of high resistivity silicon, a trap-rich layer 12, a buried oxide layer 13 and an active layer 14 made of monocrystalline silicon. The trap-rich layer 12 prevents the phenomenon of parasitic conduction at the interface between the support layer 11 and the buried oxide layer 13, this phenomenon usually being caused by free electrons which accumulate at the interface under the effect of the fixed positive charges contained in the buried oxide layer 13. Thanks to the trap-rich layer 12, the electrons are trapped and can no longer circulate. The effective resistivity of the support layer 11 is thus increased compared to a multilayer structure without a trap-rich layer (structure called “HR-SOI”). The trap-rich layer 12 can be made of polycrystalline silicon. The traps are located at the grain boundaries of the polycrystalline silicon.

[0006] The TR-SOI 10 structure greatly improves the RF performance of integrated circuits manufactured from this structure, particularly in terms of linearity and crosstalk. The passive elements (inductances, capacitors, etc.) formed above the active layer 14 benefit from a better quality factor.

[0007] [Fig.2] shows in schematic sectional view another multilayer structure 20 suitable for radiofrequency applications and described in document WO2017 / 212160A1.

[0008] This multilayer structure 20 successively comprises a support substrate 21 made of high resistivity silicon, a dielectric layer 22 made of silicon dioxide arranged on the support substrate 21, an active layer 23 made of monocrystalline silicon arranged on the dielectric layer 22 and trenches 24 extending into the support substrate 21 from the interface between the support substrate 21 and the dielectric layer 22. The walls of the trenches 24 are lined with a material 25 having properties for trapping mobile electrical charges. The remaining part of the trenches 24 is filled with a gas or a gas mixture, for example air. The trenches are thus preserved in the state of cavities.

[0009] Thanks to these cavities, the effective resistivity of the support substrate 21 is further increased.

[0010] The manufacture of the multilayer structure 20 comprises a step of transferring the dielectric layer 22 and the active layer 23 onto the support substrate 21. This transfer can be accomplished using a bonding technique (direct or by molecular adhesion) such as the Smart Cut™ process. However, it remains complex to implement, because the bonding interface is not entirely made of silicon. More particularly, bonding is made difficult by the presence of the trenches 24. Summary of the invention

[0011] There is therefore a need to provide a method for manufacturing a multilayer structure provided with cavities which is simpler to implement.

[0012] According to a first aspect of the invention, there is a tendency to satisfy this need by providing a manufacturing method comprising the following steps: • provide a stack comprising a substrate and a dielectric layer disposed on the substrate, the substrate being formed from a semiconductor material having a resistivity greater than or equal to 500 Q.cm; • etch trenches extending through the dielectric layer and emerging on the substrate; • etching the substrate isotropically and selectively with respect to the dielectric layer to form first cavities in the substrate; and • depositing a layer for trapping mobile electric charges on walls of the first cavities and on side walls of the trenches, so as to plug the trenches in the dielectric layer, thus closing the first cavities in the substrate.

[0013] In a preferred embodiment of the manufacturing method, the stack provided further comprises an active layer arranged on the dielectric layer and a protective layer arranged on the active layer, the etching of the trenches further extending into the active layer and into the protective layer.

[0014] According to a development of this preferred embodiment, second cavities are formed in the active layer at the same time as the first cavities in the substrate, by etching the active layer isotropically and selectively with respect to the dielectric layer and the protective layer, and in which the second cavities are filled with the layer for trapping mobile electrical charges.

[0015] The method according to the first aspect of the invention may also have one or more of the following characteristics, considered individually or in all technically possible combinations: • the step of providing the stack comprises an operation of thermal oxidation of a surface of the substrate, an operation of nitriding the surface of the substrate or an operation of depositing the dielectric layer on the substrate; • the method further comprises a step of removing a portion of the mobile electric charge trapping layer deposited on the dielectric layer; • the trenches further extend into part of the substrate; • each trench has a width between 20 nm and 100 nm; • each trench has a length between 50 pm and 2000 pm; • each trench has a depth between 50 nm and 300 nm; • the trenches are of identical dimensions; • the trenches are disjointed and extend in the dielectric layer along planes parallel to each other and perpendicular to a main face of the substrate; • the trenches are spaced two by two by a distance such that the first cavities merge into a larger cavity during the substrate etching step; • the trenches are spaced two by two at a distance of between 300 nm and 5000 nm; • the trenches communicate with each other and form a mesh in the dielectric layer; • the trenches have a first repetition pitch of between 100 nm and 5000 nm in a first direction and a second repetition pitch of between 100 nm and 5000 nm in a second direction intersecting the first direction; • each first cavity has a width between 200 nm and 5000 nm; • each first cavity has a length between 50 pm and 2000 pm; and • each first cavity has a depth between 100 nm and 2500 nm; • the first cavities are of identical dimensions.

[0016] A second aspect of the invention relates to a method of manufacturing an integrated circuit, comprising the following steps: • manufacturing a multi-layer structure by carrying out a method according to the first aspect of the invention; • form passive components on the multilayer structure, vertical to the first cavities.

[0017] The method according to the second aspect of the invention may also comprise one or more of the steps below, considered individually or in all technically possible combinations: • a step of forming electrical insulation trenches before the step of etching the trenches; • a step of forming active components in a first zone of the multilayer structure, the first zone being devoid of first cavities, the passive components being formed in a second zone of the multilayer structure, distinct from the first zone and provided with the first cavities; • a step of total removal of the dielectric layer before the step of forming the active components; • a step of forming at least one level of electrical interconnection connecting the active components, the passive components being formed on said at least one level of electrical interconnection.

[0018] A third aspect of the invention relates to a multilayer structure comprising: • a substrate; • a dielectric layer placed on the substrate; • trenches extending through the dielectric layer to the substrate; • first cavities extending into the substrate, from the interface between the substrate and the dielectric layer; • a layer for trapping mobile electrical charges completely filling the trenches in the dielectric layer and lining the walls of the first cavities made in the substrate.

[0019] In a preferred embodiment, the multilayer structure further comprises: • an active layer placed on the dielectric layer; • second cavities arranged in the active layer and filled at least partially by the layer for trapping mobile electrical charges. BRIEF DESCRIPTION OF THE FIGURES

[0020] Other characteristics and advantages of the invention will emerge clearly from the description given below, for information purposes only and in no way limiting, with reference to the following figures: • [Fig.l], previously described, represents a multilayer structure according to the prior art, which can be used as a starting substrate for the manufacture of radiofrequency integrated circuits; • [Fig.2], previously described, represents another multilayer structure according to the prior art, also suitable for radiofrequency applications; • Figures 3A to 3E represent a first mode of implementation of the method for manufacturing a multilayer structure according to the first aspect of the invention; • Figures 4A to 4E represent a second mode of implementation of the multilayer structure manufacturing method; • [Fig.5] is a 3D view of the multilayer structure obtained following the process of Figures 4A to 4E; • Figures 6A to 6D represent a variant implementation of the method for manufacturing a multilayer structure according to Figures 4A to 4E; • [Fig.7] is a 3D view of the multilayer structure obtained following the process of Figures 6A to 6D; and • [Fig.8] represents a step in the integrated circuit manufacturing process according to the second aspect of the invention.

[0021] For clarity, identical or similar elements are identified by identical reference signs throughout the figures. DETAILED DESCRIPTION

[0022] Figures 3A to 3E show steps S1 to S5 of a manufacturing method of a multilayer structure 100, according to a first embodiment of the invention.

[0023] Step S1 of [Fig.3A] consists of providing a stack 30 comprising a substrate 31 and a dielectric layer 32 arranged on the substrate 31.

[0024] The substrate 31, also called the support layer, is formed from a high-resistivity semiconductor material, for example high-resistivity silicon. A semiconductor material is here described as high-resistivity when its electrical resistivity is greater than or equal to 500 Ω.cm. Such resistivity makes it possible to reduce the leakage currents between the different components (active or passive) formed on the substrate and the eddy currents in the substrate, thus limiting the resulting Joule effect losses.

[0025] The dielectric layer 32 is formed from a material capable of being selectively etched relative to the material of the substrate 31. The dielectric layer 32 may in particular be made of a silicon oxide (for example silicon dioxide, or SiO2) or a silicon nitride (e.g. Si3N4).

[0026] The step S1 of providing the stack 30 advantageously comprises a thermal oxidation operation (or a nitriding operation) of the surface of the substrate 31 in order to form the dielectric layer 32. A good quality interface can thus be obtained. Alternatively, the step S1 of providing the stack 30 may comprise an operation of depositing the dielectric layer 32 on the substrate 31, for example by plasma-enhanced chemical vapor deposition (or PECVD) or low-pressure chemical vapor deposition (or LPCVD).

[0027] In this first embodiment, the substrate 31 is a so-called “bulk” substrate, i.e. composed solely of semiconductor material (as opposed to innovative substrates such as the SOI substrate). The thickness of the dielectric layer 32 is preferably between 50 nm and 100 nm.

[0028] The dielectric layer 32 may optionally consist of a stack of several sub-layers, for example a silicon oxide sub-layer topped with a silicon nitride sub-layer (STI integration).

[0029] In step S2 of [Fig.3B], trenches 40 are etched through the dielectric layer 32 until reaching the substrate 31. These trenches 40 can be formed using an anisotropic etching technique, such as reactive ion etching (RIE). Each trench 40 preferably has a width L1 of between 20 nm and 100 nm, a length of between 50 pm and 2000 pm and a depth PI of between 50 nm and 300 nm. The width L1, also called the “critical dimension”, is the smallest dimension of the trenches 40 in a plane parallel to the main face of the substrate 31 (the one on which the dielectric layer 32 is arranged). It is measured here in the section plane of [Fig.3B]. The length of the trenches 40 is measured perpendicular to the section plane of [Fig.3B]. The depth PI of the trenches 40 is measured perpendicular to the main face of the substrate 31.

[0030] Advantageously, the trenches 40 further extend into a portion of the substrate 31, as shown in [Fig. 3B]. The depth PI' of the trenches 40 within the substrate 31 is preferably between 50 nm and 200 nm.

[0031] In step S3 of [Fig.3C], first cavities 50 are formed in the substrate 31 by etching it isotropically and selectively with respect to the dielectric layer 32. For example, a CF4 / N2 / O2 plasma can be used to etch (isotropically) a silicon substrate 31 selectively with respect to a SiO2 dielectric layer 32.

[0032] The first cavities 50 in the substrate 31 communicate with the trenches 40 in the dielectric layer 32. Indeed, the substrate 31 is etched starting from the trenches 40. When these open onto the upper face of the substrate 31, the first cavities 50 generally have the shape of a half-cylinder. When the trenches 40 also extend partially into the substrate 31, the first cavities 50 have a more elongated shape and extend deeper into the substrate 31.

[0033] Preferably, each of the first cavities 50 has a width L2 of between 200 nm and 5000 nm and a depth P2 of between 100 nm and 2500 nm. The length of the first cavities 50 is substantially equal to the length of the trenches 40, for example of between 50 μm and 2000 μm.

[0034] The trenches 40 may have identical dimensions, although this is not necessary to obtain the first cavities 50. In the same way, the first cavities 50 may have identical dimensions (this is the case when the trenches 40 have identical dimensions).

[0035] Next, in step S4 of [Fig.3D], a mobile electric charge trapping layer 60 is formed on walls of the first cavities 50 and on side walls of the trenches 40. A mobile electric charge trapping layer designates a layer comprising traps capable of capturing mobile electric charges.

[0036] The trapping layer 60 advantageously has an electrical resistivity greater than 50 Q.cm for frequencies between 100 MHz and 100 GHz. Thus, the trapping layer 60 prevents or significantly limits the propagation of electrical signals whose frequency is between 100 MHz and 100 GHz.

[0037] The trapping layer 60 is deposited so as to plug the trenches 40 in the dielectric layer 32, thereby closing the first cavities 50 in the substrate 31. preferably, a conformal deposition technique such as low pressure chemical vapor deposition (LPCVD) is used during step S4. The trapping layer 60 is then of constant thickness, preferably between 10 nm and 50 nm, and follows the contours of the substrate 31 and the dielectric layer 32. In particular, the trapping layer 60 covers all the side walls of the trenches 40 and all the walls of the first cavities 50. It also extends to the surface of the dielectric layer 32.

[0038] On the other hand, the trapping layer 60 does not completely fill the first cavities 50. The remaining part of the first cavities 50 is filled with a gas or a gas mixture, for example air or other gases introduced into the deposition reactor. The pressure prevailing in the first cavities 50 can be very low (it is in particular a function of the partial pressures of the gases introduced into the deposition reactor), in order to arrive at a quasi-vacuum configuration. It is preferably between 1 Pa and 100 Pa.

[0039] The trapping layer 60 is preferably formed from a material having properties for trapping mobile electrical charges (electrons), such as polycrystalline silicon.

[0040] Alternatively, the trapping layer 60 is made of a dielectric material, preferably an oxide such as SiO2 or a nitride such as SiN.

[0041] Finally, step S5 of [Fig.3E] is an optional step consisting of removing the portion of the trapping layer 60 deposited on the dielectric layer 32. This removal can be accomplished by etching, for example using a plasma, or by chemical-mechanical polishing (CMP).

[0042] Thus, with reference to [Fig.3E], the multilayer structure 100 comprises: • substrate 31; • the dielectric layer 32 arranged on the substrate 31; • the trenches 40 extending through the dielectric layer 32 to the substrate 31; • the first cavities 50 extending into the substrate 31, from the interface between the substrate 31 and the dielectric layer 32; • the trapping layer 60 completely filling the trenches 40 in the dielectric layer 32 and lining the walls of the first cavities 50 arranged in the substrate 31 (without however completely filling them).

[0043] As is known in the field of SOI multilayer structures for radiofrequency applications, a dielectric layer (e.g. SiO2) on a semiconductor substrate comprises positive charges. These charges are compensated by negative charges coming from the substrate, at the interface with the dielectric layer. These charges generate a parasitic conduction layer of surface conduction layer (PSC) in the substrate under the dielectric layer, which reduces the effective resistivity of the substrate. Electrical performances sensitive to substrate resistivity (such as signal linearity, insertion loss level, quality factors of passive components, etc.) are therefore significantly degraded by the presence of this conduction layer.

[0044] The first cavities 50 and the trapping layer 60 (when the latter is not made of dielectric material) limit the surface area on which the mobile electrical charges accumulate. In addition, they prevent the movement of these electrical charges in the substrate 31 at the interface with the dielectric layer 32. The electrical charges are forced to bypass the first cavities 50, thus passing through areas of the substrate 31 of higher resistivity (the deeper the first cavities 50, the more pronounced this bypass effect is). As a result, the effective resistivity of the substrate 31 is greatly improved.

[0045] The plugs formed by the trapping layer 60 through the dielectric layer 32 and the presence of the trapping layer 60 on the ceiling of the first cavities 50 are recognizable elements of the method of manufacturing a multilayer structure according to the invention.

[0046] Figures 4A to 4E represent a second embodiment of the multilayer structure manufacturing method. This second embodiment differs from the first embodiment (Figs. 3A-3E) mainly in the type of substrate used as the starting point of the manufacturing method: an SOI type substrate rather than a bulk substrate.

[0047] Thus, the stack 30 provided in step S1 of [Fig.4A] comprises, in addition to the substrate (or support layer) 31 made of high resistivity semiconductor material and the dielectric layer 32, an active layer 33 arranged on the dielectric layer 32 and a protective layer 34 arranged on the active layer 33.

[0048] The active layer 33 is preferably a thin film of semiconductor material, intrinsic or doped, for example monocrystalline silicon, germanium, silicon-germanium alloy or a III-V semiconductor material. The active layer 33 is more particularly intended for the manufacture of active components, typically transistors. Its thickness is preferably between 6 nm and 200 nm.

[0049] The purpose of the protective layer 34 is to protect the active layer 33 during the subsequent steps of the manufacturing process of the multilayer structure. It can also serve as a hard mask layer and / or an etch stop layer during a manufacturing process of an integrated circuit from the multilayer structure. The protective layer 34 may comprise several superimposed sub-layers, for example a first sub-layer 34a made of SiO2 and a second sub-layer 34b made of SiN arranged on the first sub-layer 34a.

[0050] The dielectric layer 32 constitutes the electrically insulating layer of the SOI substrate (also called buried oxide layer or BOX, in the case of an oxide such as SiO2). In this second embodiment, the thickness of the dielectric layer 32 is advantageously between 20 nm and 400 nm.

[0051] After step S2 of etching the trenches 40 represented by [Fig.4B], the trenches 40 extend through the active layer 33 and the protective layer 34 (in addition to the dielectric layer 32 and, possibly, a part of the substrate 31).

[0052] [Fig.4C] represents step S3 of etching the substrate 31, allowing the formation of the first cavities 50. When the material of the substrate 31 and the material of the active layer 33 are of the same nature (for example silicon), or more generally when they are both sensitive to the etching chemistry used in step S3, the active layer 33 is further etched and second cavities 70 are formed in the active layer 33 at the same time as the first cavities 50 in the substrate 31. The etching is isotropic and selective with respect to the dielectric layer 32 and the protective layer 34.

[0053] [Fig.4D] represents step S4 of deposition of the trapping layer 60. In addition to completely filling the trenches 40 and covering the walls of the first cavities 50, the trapping layer 60 fills the second cavities 70 in the active layer 33. The second cavities 70 are preferably completely filled by the trapping layer 60.

[0054] Finally, the upper portion of the trapping layer 60 (deposited on the protective layer 34) is removed in step S5 represented by [Fig.4E]. All or part of the protective layer 34 can also be removed during this step S5. For example, the second sub-layer 34b made of SiN can be removed (by selective etching or CMP).

[0055] The multilayer structure 200 obtained at the end of the manufacturing method according to the second embodiment ([Fig.4E]) comprises, in addition to the elements of the electronic structure 100 ([Fig.3E]), the active layer 33, the second cavities 70 partially or entirely filled with the trapping layer 60, and possibly the protective layer 34.

[0056] [Fig. 5] is a 3D view of the multilayer structure 200 after having completely removed the protective layer 34. This figure shows that the first cavities 50 can form a network of galleries which communicate with each other. More particularly, a first part of the first cavities 50 can extend in a first direction X and a second part of the first cavities 50 can extend in a second direction Y intersecting (i.e. not parallel) to the first direction X.

[0057] Such a multilayer structure 200 is obtained by etching trenches in step S2 40 which communicate with each other and form a mesh in the dielectric layer 32. Preferably, the trenches 40 have a first repetition pitch (also called spatial period) Px between 100 nm and 5 pm in the first direction X and a second repetition pitch PY between 100 nm and 5 pm in the second direction Y. For example, the trenches 40 form a rectangular mesh (second direction Y perpendicular to the first direction X). The first repetition pitch Px may be equal to the second repetition pitch PY (square mesh).

[0058] In an alternative embodiment not shown in the figures, the trenches 40 are disjointed and all extend along planes parallel to each other and perpendicular to the main face of the substrate 31. They may further have a repetition pitch Px in the first direction X, preferably between 50 nm and 5 pm. The first cavities 50 then all extend parallel to each other in the second direction Y.

[0059] Figures 6A to 6D represent steps S2 to S5 according to an alternative implementation of the multilayer structure manufacturing method. This alternative is applicable to the case of a solid substrate and to the case of an SOI substrate.

[0060] In this implementation variant, the trenches 40 extend parallel to each other (for example in the second direction Y). Furthermore, the distance d between two consecutive trenches 40 (measured in the first direction X; cf. [Fig. 6A]) and the conditions of the isotropic and selective etching (chemistry, duration, etc.) of step S3 ([Fig. 6B]) are chosen so that the first cavities 50 merge into a first large cavity 50'. The ceiling of this first large cavity 50', constituted by portions of the dielectric layer 32, is held by the ends (located in planes parallel to the section plane of [Fig. 6B]). In the case of an SOI substrate, the second cavities 70 also merge into a second large cavity 70'. Steps S4 and S5 of the manufacturing process (see [Fig.6C] and [Fig.6D]) are then carried out in the manner described in relation to Figures 3D-3E or 4D-4E.

[0061] [Fig.6D] shows in sectional view the multilayer structure 300 obtained at the end of this implementation variant (with the first protective sub-layer 34a).

[0062] [Fig. 7] represents the same multilayer structure 300 in 3D (but without the first protective sub-layer 34a). Advantageously, the trenches 40 have a repetition pitch Px in the first direction X, preferably between 300 nm and 5 pm.

[0063] Thus, thanks to a greater spacing of the trenches 40 (and therefore a greater spatial period), a wider cavity can be obtained in the substrate 31. The distance d between two consecutive trenches 40 is advantageously between 300 nm and 5000 nm. This distance d can vary from one pair of trenches 40 to another. In other words, it is not necessary for the trenches 40 to be regularly spaced (nor for them to have identical dimensions) to obtain the first large cavity 50'.

[0064] Preferably, the first large cavity 50' has a width L3 of between 5 pm and 20 pm. Its length and depth may be respectively identical to the length and depth P2 of the first cavities 50 when they are disjointed (respectively between 50 pm and 2000 pm and between 100 nm and 2500 nm).

[0065] By providing several groups of trenches 40 (spaced or not regularly), it is possible to obtain in the substrate 31 several first large distinct cavities 50' (i.e. non-communicating).

[0066] The multilayer structure manufacturing method described above in relation to Figures 3A-3E, 4A-4E and 6A-6D is simple to implement and easily reproducible, because it only uses techniques mastered in the microelectronics industry (photolithography, deposition, etching and CMP). It does not include any transfer or bonding step, which can be complicated if the surface is structured. It also makes it possible to produce various configurations of multilayer structure provided with cavities (these configurations being independent of the electronic components that can be formed subsequently on the multilayer structure).

[0067] Furthermore, it can be easily integrated into a method for manufacturing an integrated circuit, for example of the radiofrequency type. Steps S2 to S5 can in particular be accomplished immediately after forming electrical insulation trenches 80 called STI (for “Shallow Trench Isolation” in English) in the SOI substrate (see [Fig.4A]) or the bulk substrate (covered with the dielectric layer 32). The hard mask layer used to form the STI 80 can be retained to form all or part of the protective layer 34 of the second embodiment (and more particularly the second sub-layer 34b in SiN).

[0068] [Fig. 8] represents a step of the integrated circuit manufacturing process. After forming the multilayer structure 100, 200 or 300, the integrated circuit manufacturing process 400 comprises a step of forming passive components 90 on the multilayer structure. Before the step of forming the passive components 90, the integrated circuit manufacturing process 400 may also comprise a step of forming active components 91 on the multilayer structure and a step of forming one or more electrical interconnection levels 92 connecting the active components 91.

[0069] The active components 91 are for example transistors. They are preferably formed in the active layer 33 of the SOI substrate or on the surface of the solid substrate 31, in other words in the part called FEOL (front-end of line) of the integrated circuit 400. In the case of a solid substrate, the dielectric layer 32 is entirely removed before forming the active components 91 on the surface of the substrate.

[0070] The passive components 90 are, for example, coils, capacitors, resistors, etc. They are located vertically above the first cavities 50 in the substrate 31 in order to optimize their electrical performance. They are preferably formed above the electrical interconnection levels 92 (or metal levels). Like the electrical interconnection levels 92, the passive components 90 belong to the so-called BEOL (“back-end of line” in English) part of the integrated circuit 400.

[0071] The active components 91 may be formed in a first zone Z1 of the multilayer structure, while the passive components 90 are formed in a second zone Z2. The second zone Z2 is distinct from the first zone Z1 and provided with the first cavities 50. The first and second zones Z1-Z2 are preferably separated by an electrical insulation trench 80.

Claims

Claims

1. Method for manufacturing an integrated circuit (400), comprising the following steps: - manufacturing a multilayer structure (100, 200, 300) by performing the following steps: • providing (SI) a stack (30) comprising a substrate (31) and a dielectric layer (32) arranged on the substrate, the substrate (31) being formed from a semiconductor material having a resistivity greater than or equal to 500 Q.cm; • etching (S2) trenches (40) extending through the dielectric layer (32) and opening onto the substrate (31); • etching (S3) the substrate (31) isotropically and selectively with respect to the dielectric layer (32) to form first cavities (50) in the substrate (31); and • depositing (S4) a mobile electric charge trapping layer (60) on walls of the first cavities (50) and on side walls of the trenches (40), so as to plug the trenches (40) in the dielectric layer (32), thus closing the first cavities (50) in the substrate (31); - forming passive components (90) on the multi-layer structure (100, 200, 300), vertically above the first cavities (50).

2. The method of claim 1, further comprising a step (S5) of removing a portion of the mobile electric charge trapping layer (60) deposited on the dielectric layer (32).

3. Method according to one of claims 1 and 2, wherein the stack (30) provided comprises an active layer (33) arranged on the dielectric layer (32) and a protective layer (34) arranged on the active layer (33), the etching of the trenches (40) further extending into the active layer (33) and into the protective layer (34).

4. The method of claim 3, wherein second cavities (70) are formed in the active layer (33) at the same time as the first cavities (50) in the substrate (31), by etching the active layer (33) isotropically and selectively with respect to the dielectric layer (32) and the protective layer (34), and in which the second cavities (70) are filled by the mobile electric charge trapping layer (60).

5. Method according to any one of claims 1 to 4, in which the trenches (40) are disjoint and extend in the dielectric layer (32) along planes parallel to each other and perpendicular to a main face of the substrate (31).

6. Method according to claim 5, in which the trenches (40) are spaced two by two by a distance (d) such that the first cavities (50) merge into a larger cavity (50') during the step (S3) of etching the substrate (31).

7. A method according to any one of claims 1 to 4, wherein the trenches (40) communicate with each other and form a mesh in the dielectric layer (32).

8. Method according to claim 7, in which the trenches have a first repetition pitch (Px) between 100 nm and 5000 nm in a first direction (X) and a second repetition pitch (PY) between 100 nm and 5000 nm in a second direction (Y) intersecting the first direction (X).

9. A method according to any one of claims 1 to 8, further comprising a step of forming electrical insulation trenches (80) before the step (S2) of etching the trenches (40).

10. Method according to any one of claims 1 to 9, further comprising a step of forming active components (91) in a first zone (Zl) of the multilayer structure (100, 200, 300), the first zone (Zl) being devoid of first cavities (50), the passive components (90) being formed in a second zone (Z2) of the multilayer structure, distinct from the first zone (Zl) and provided with the first cavities (50).

11. The method of claim 10, further comprising a step of forming at least one electrical interconnection level (92) connecting the active components (91), the passive components (90) being formed on said at least one electrical interconnection level (92).

12. Integrated circuit (400) comprising: - a multilayer structure (100, 200, 300) comprising: • a substrate (31) formed from a semiconductor material having a resistivity greater than or equal to 500 Q.cm; • a dielectric layer (32) arranged on the substrate (31); • trenches (40) extending through the dielectric layer (32) to the substrate (31); • first cavities (50) extending into the substrate (31), from the interface between the substrate (31) and the dielectric layer (32); and • a mobile electric charge trapping layer (60) lining the walls of the first cavities (50) arranged in the substrate (31) and completely filling the trenches (40) in the dielectric layer (32), thus closing the first cavities (50) in the substrate (31); - passive components (90) arranged on the multilayer structure (100, 200, 300), vertically above the first cavities (50).

13. The integrated circuit (400) of claim 12, wherein the multilayer structure (200, 300) further comprises: - an active layer (33) arranged on the dielectric layer (32); - second cavities (70) arranged in the active layer (33) and filled at least partially by the mobile electrical charge trapping layer (60).

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