Photonic-electronic integrated circuit chip and its manufacturing process
The photonic-electronic integrated circuit chip on a semiconductor-on-insulator substrate addresses the challenges of integrating electronic and photonic circuits by forming the electronic circuit in a thicker region than the photonic interface, enhancing optical confinement and enabling efficient optical communication with minimal metallic interconnections.
Patent Information
- Application Number
- FR2021011256
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2021-10-22
- Publication Date
- 2025-01-17
- Estimated Expiration
- 2041-10-22
AI Technical Summary
Existing methods for integrating electronic and photonic circuits on the same chip face challenges due to conflicting manufacturing requirements and high light losses in waveguides, particularly in silicon-on-insulator substrates, making industrialization difficult.
A photonic-electronic integrated circuit chip is developed on a semiconductor-on-insulator substrate with a buried dielectric layer, where the electronic circuit part is formed in a thicker region of the active layer than the photonic interface, minimizing the impact of the buried oxide layer and optimizing optical confinement for high-quality interconnections.
This approach enables efficient intra- and inter-chip optical communication with minimal metallic interconnections, overcoming the limitations of previous integration methods by ensuring the electronic circuit operation is not adversely affected and achieving optimized optical interconnections.
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Abstract
Description
Title of the invention: Photonic-electronic integrated circuit chip and its manufacturing method Technical field
[0001] The field of the invention is that of integrated circuits, more particularly that of photonic-electronic integrated circuits comprising electronic and photonic parts on the same chip. Prior art
[0002] Heterogeneous computing involves different electronic circuits such as central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), neural network accelerators and shared memory resources.
[0003] These electronic circuits are generally connected together using metal wires / connectors to form a multi-core processing unit achieving the desired computing power. This type of assembly, however, limits bandwidth and power density.
[0004] Photonics constitutes a promising technology for providing intra- or inter-chip optical communications that can overcome the limitations of electrical interconnections.
[0005] 2.5D or 3D integration thus makes it possible to associate a part of an electronic circuit with a photonic interconnection interface. Such integration requires photonic interposers and vertical copper interconnections, but the aforementioned limitations cannot be fully overcome.
[0006] This is why we are seeking to combine electronics and photonics on the same chip even though such a combination proves difficult due to the opposing requirements, particularly in terms of manufacturing, of each of these technologies.
[0007] For example, we know from the article by Sun, C., Wade, M., Lee, Y. et al. entitled “Single-chip microprocessor that communicates directly using light”, Nature 528, 534-538 (2015) a solution for co-integration on the same silicon-on-insulator (SOI) substrate of an electronic circuit with optical devices providing interconnection functions for the electronic circuit by means of optical paths.
[0008] This solution consists of providing an SOI substrate which comprises a thin surface layer of silicon separated from a support substrate by a buried oxide layer and structuring the thin surface layer of silicon to form both the body electronic transistors and the core of optical waveguides. Since the buried oxide layer of the SOI substrate is thin (<200 nm), light propagating in the waveguides is likely to escape evanescently into the support substrate, which can lead to high losses in the waveguides. To solve this problem, this solution recommends selective removal of the substrate after electrical encapsulation of the chip in order to etch away the support substrate under the regions containing optical devices.
[0009] This selective post-encapsulation removal, however, proves to be complex to carry out, making this solution difficult to industrialize. Statement of the invention
[0010] The invention aims to propose a simpler solution for monolithic integration on the same substrate of a part of an electronic circuit with a photonic interconnection interface ensuring intra- or inter-chip optical communication for the part of the electronic circuit with a minimal quantity of metal interconnections.
[0011] To this end, the invention proposes, according to a first aspect, a photonic-electronic integrated circuit chip formed on a semiconductor-on-insulator substrate, which silicon-on-insulator substrate comprises a buried dielectric layer and an active layer of semiconductor material. The chip comprises an electronic circuit portion and a photonic interface for interconnecting the electronic circuit portion co-integrated in the active layer. The electronic circuit portion is formed in a region of the active layer whose thickness is greater than the thickness of a region of the active layer in which said photonic interface is formed.
[0012] Some preferred but non-limiting aspects of this chip are as follows: - the region of the active layer in which said photonic interface is formed is sandwiched between the buried dielectric layer and a surface dielectric region and the region of the active layer in which the electronic circuit part is formed is devoid of a surface dielectric layer; - the thickness of the region of the active layer in which the electronic circuit part is formed is greater than 0.2 pm, preferably greater than 0.5 pm; - the thickness of the region of the active layer in which said photonic interface is formed is between 0.2 pm and 0.5 pm; - the buried dielectric layer has a thickness greater than Ipm, preferably greater than 2pm; - the photonic interface comprises at least one waveguide; - the photonic interface further comprises a photonic circuit part active. - the electronic circuit part includes a transistor logic module; - the transistors are of the FinFET or GAAFET type.
[0013] According to a second aspect, the invention relates to a semiconductor-on-insulator substrate comprising a buried dielectric layer and an active layer of semiconductor material. A region of the active layer intended for the formation of a part of an electronic circuit is of greater thickness than the thickness of a region of the active layer intended for the formation of a photonic interface for interconnecting the part of the electronic circuit.
[0014] According to a third aspect, the invention relates to a method of manufacturing a semiconductor-on-insulator substrate according to the second aspect, comprising transferring the active layer from a donor substrate to a support substrate.
[0015] Some preferred but non-limiting aspects of this method are as follows: - it further comprises localized etching of the transferred active layer to form the region of the active layer intended for the formation of the photonic interconnection interface; - it further comprises the formation of a dielectric layer on the surface of the region of the active layer intended for the formation of the photonic interconnection interface; - it further comprises the formation of the region of the active layer intended for the formation of the electronic circuit part by means of localized epitaxy. - the formation of the region of the active layer intended for the formation of the electronic circuit part is preceded by the steps of oxidation of the transferred active layer to form a dielectric layer and of localized removal of the dielectric layer, the dielectric layer remaining after localized removal serving as a mask for the localized epitaxy; - it includes the formation of a dielectric layer on the surface of a region of the active layer which has not been subject to localized epitaxy.
[0016] According to a fourth aspect, the invention relates to a method of manufacturing a photonic-electronic integrated circuit chip, comprising the following steps: - manufacturing a semiconductor-on-insulator substrate in accordance with the method according to the third aspect; - formation of a part of an electronic circuit in the region of the active layer intended for the formation of a part of an electronic circuit; - formation of a photonic interconnection interface in the region of the active layer intended for the formation of a photonic interconnection interface of the electronic circuit part.
[0017] The manufacture of the semiconductor substrate on insulator comprises, before or after all or part of the formation of the photonic interconnection interface, the formation of a dielectric layer on the surface of the region of the active layer intended for the formation of the photonic interconnection interface. Brief description of the drawings
[0018] Other aspects, aims, advantages and characteristics of the invention will appear better on reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and made with reference to the appended drawings in which:
[0019] [Fig-1] is a schematic of a photonic-electronic integrated circuit chip in accordance with the invention;
[0020] [Fig.2] is a schematic sectional view of a Si donor substrate monocrystalline;
[0021] [Fig.3] is a schematic sectional view illustrating the formation of a layer surface dielectric of the monocrystalline Si donor substrate;
[0022] [Fig.4] is a schematic sectional view illustrating the formation, by implantation of ionic species, of a weakening plane in the donor substrate of [Fig.2] to delimit an active layer of monocrystalline Si to be transferred;
[0023] [Fig.5] is a schematic sectional view illustrating the assembly of the donor substrate of [Fig.3] and a support substrate;
[0024] [Fig.6] is a schematic sectional view illustrating the detachment of the substrate donor along the embrittlement plane to transfer the active layer of monocrystalline Si onto the support substrate;
[0025] [Fig.7] is a schematic sectional view illustrating a localized etching of the active layer of monocrystalline Si following detachment of [Fig.6];
[0026] [Fig.8] is a schematic sectional view illustrating an oxidation of the active layer of monocrystalline Si following the localized etching of [Fig.7];
[0027] [Fig.9] is a schematic sectional view illustrating localized removal of the layer oxide formed by the oxidation of [Fig.8];
[0028] [Fig. 10] is a schematic sectional view illustrating oxidation of the layer active monocrystalline Si following detachment from [Fig.6];
[0029] [Fig. 11] is a schematic sectional view illustrating localized shrinkage of the layer oxide formed by the oxidation of [Fig. 10];
[0030] [Fig. 12] is a schematic sectional view illustrating localized epitaxy using the remaining oxide layer as a mask following its localized removal from [Fig. 11].
[0031] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS
[0032] With reference to [Fig. 1], the invention relates to a photonic-electronic integrated circuit chip formed on a semiconductor-on-insulator substrate, which silicon-on-insulator substrate comprises a buried dielectric layer 11 and an active layer of semiconductor material 12, for example monocrystalline silicon. The buried dielectric layer 11 typically separates the active layer of semiconductor material 12 from a support substrate 20.
[0033] The chip according to the invention comprises, co-integrated in the active layer 12, an electronic circuit part CEI, CE2 and a photonic interconnection interface IPI of the electronic circuit part. In the example of [Fig.l], the photonic interconnection interface IPI acts as an intra-chip interface ensuring the interconnection of two electronic circuit parts CEI and CE2. The invention also extends to a photonic interconnection interface IPI acting as an inter-chip interface ensuring the interconnection of an electronic circuit part integrated into the chip with an electronic circuit part integrated into another chip.
[0034] Each part of the IEC, CE2 electronic circuit may comprise a transistor logic module, for example based on FinFET (“Fin Field-Effect Transistor”) or GAAFET (“Gate-All-Around Field-Effect Transistor”) type transistors.
[0035] The photonic interface IPI typically comprises at least one waveguide. It may also comprise a part of an active photonic circuit, such as for example an electro-optical modulator or a laser transferred to the IPI interface.
[0036] According to the invention, the electronic circuit part CEI, CE2 is formed in a region of the active layer RE1, RE2 whose thickness is greater than the thickness of a region of the active layer RP in which said photonic interface IPI is formed.
[0037] The thickness of the region of the active layer RE1, RE2 in which the electronic circuit part CEI, CE2 is formed may be greater than 0.2 pm, preferably greater than 0.5 pm.
[0038] The thickness of the region of the active layer RP in which the photonic interface IPI is formed can be between 0.2 pm and 0.5 pm.
[0039] The buried dielectric layer may have a thickness greater than 200nm, for example a thickness greater than 1 μm, preferably greater than 2 μm.
[0040] In a preferred embodiment, the region of the active layer RP in which said photonic interface IPI is formed is sandwiched between the buried dielectric layer 11 and a surface dielectric region 21 and the region of the active layer RE1, RE2 in which the electronic circuit part CEI, CE2 is formed is devoid of a surface dielectric layer. The thickness of the surface dielectric region 21 typically corresponds to the difference in thickness between the region of the active layer RP in which said photonic interface IPI is formed and the region of the active layer RE1, RE2 in which the electronic circuit part CEI, CE2 is formed.
[0041] The chip according to the invention is thus manufactured on a semiconductor-on-insulator substrate having a thick buried oxide layer. The region of the active layer intended for the formation of the electronic circuit part is sufficiently thick so that the operation of this part is not adversely influenced by the buried oxide layer. And the region of the active layer intended for the formation of the photonic interconnection interface has a thickness and optical confinement optimized for the formation in a horizontal plane of quality optical interconnections.
[0042] According to another aspect, the invention relates to a semiconductor-on-insulator substrate comprising a buried dielectric layer 11 and an active layer of semiconductor material 12. In this substrate, a region of the active layer RE1, RE2 intended for the formation of an electronic circuit part CEI, CE2 is of greater thickness than the thickness of a region of the active layer RP intended for the formation of a photonic interconnection interface IPI of the electronic circuit part.
[0043] The invention also relates to a method for manufacturing such a semiconductor-on-insulator substrate, this method comprising a transfer of the active layer from a donor substrate to a support substrate. Such a transfer typically comprises bonding the donor substrate and the support substrate with an oxide layer at the bonding interface and can be carried out in accordance with BESOI technology by thinning on the back face of the donor substrate or in accordance with Smart Cut™ technology by detachment at a weakening plane previously formed by implantation of ionic species in the donor substrate.
[0044] Various examples of such a manufacturing method using Smart Cut™ technology are described below. With reference to [Fig. 2], such a method may begin by providing a donor substrate 10 of which at least a surface portion is made of semiconductor material. The figures show a solid substrate 10 of monocrystalline Si. With reference to [Fig. 3], the method comprises a step of forming an oxide layer 11 on the donor substrate 10, this oxide layer being intended to form all or part of the buried dielectric layer 11 mentioned above.
[0045] According to another embodiment, the method comprises a step of forming the oxide layer 11 on the support substrate 20.
[0046] With reference to [Fig. 4], the method further comprises an implantation of ionic species in the donor substrate 10 so as to form a weakening plane 13 delimiting an active layer of monocrystalline Si to be transferred 12. The implanted species typically comprise hydrogen and / or helium. A person skilled in the art is able to define the required implantation energy and dose.
[0047] When the oxide layer is formed on the support substrate 20, due to the absence of such an oxide layer on the donor substrate, the weakening plane 13 can be formed deeper in the donor substrate, which ultimately makes it possible to transfer a thicker active layer 12.
[0048] With reference to [Fig. 5], the method comprises, after said implantation, bonding the donor substrate 10 and a support substrate 20. The bonding is a direct bonding obtained by molecular adhesion of the surfaces brought into contact. With reference to [Fig. 6], the method then comprises detaching the donor substrate 10 along the embrittlement plane 13 so as to transfer the active layer of monocrystalline Si 12 onto the support substrate 20. In a known manner, this detachment can be caused by a heat treatment, a mechanical action, or a combination of these means. The remainder 10' of the donor substrate can possibly be recycled for another use.
[0049] One or more finishing operations can then be applied to the transferred active layer of monocrystalline Si 12. It is for example possible to carry out smoothing, cleaning or even polishing, for example by chemical mechanical polishing (CMP), to remove the defects linked to the implantation of the ionic species and reduce the roughness of the transferred active layer of monocrystalline Si 12.
[0050] In a possible embodiment, the implantation energy is such that the thickness of the transferred active layer 12 is suitable for producing a part of an electronic circuit, this thickness being for example greater than 0.2 μm, preferably greater than 0.5 μm. In such a case, as shown in [Fig. 7], the method may comprise a localized etching of the transferred active layer 12 to form a region of the active layer RP intended for the formation of a photonic interconnection interface. A non-etched region makes it possible to form a region of the active layer RE1, RE2 intended for the formation of a part of an electronic circuit. The method may continue with the formation of a dielectric layer 21 on the surface of the region of the active layer intended for the formation of the photonic interconnection interface. This formation may comprise, as shown in FIGS. 8 and 9, a thermal oxidation of the active layer 12 followed by a localized removal of the oxide layer thus formed at the level of the region(s) of the active layer intended for the formation of a part of an electronic circuit. In an alternative embodiment, this formation may comprise a localized oxidation of the active layer, carried out at the level of the region(s) of the active layer intended for the formation of a photonic interconnection interface by exploiting a masking of the other regions of the active layer, for example with a nitride-based mask.
[0051] In another embodiment variant, following the localized etching illustrated by [Fig.7], the method may comprise the formation of all or part of the photonic interconnection interface before the formation of the dielectric layer 21. For example, the method may comprise the shaping of a waveguide in the etched region RP before proceeding with the formation of the dielectric layer 21 on the waveguide. This waveguide is thus well confined in the dielectric layer, which makes it possible to further minimize optical losses.
[0052] In another possible embodiment, the implantation energy is such that the thickness of the transferred active layer 12 is not directly suitable for producing a part of an electronic circuit. In such a case, the method comprises forming the region of the active layer intended for forming the part of the electronic circuit by means of epitaxy.
[0053] In a first variant of this other embodiment, the method comprises, following the detachment illustrated in [Fig. 6], a step consisting, as represented by [Fig. 10], in forming, for example by means of thermal oxidation, a dielectric layer 14 on the transferred active layer 12, then a step consisting, as represented by [Fig. 11], in carrying out a localized removal of the dielectric layer 14 at the level of the region(s) of the active layer intended for the formation of a part of an electronic circuit, the remaining dielectric forming the surface layer 21 covering the region of the active layer intended for the formation of a photonic interface. As represented in [Fig.12], localized epitaxy serving to thicken the active layer at the level of the region(s) of the active layer intended for the formation of a part of an electronic circuit is then carried out, the remaining dielectric layer 21 after its localized removal being able to serve as a mask for the localized epitaxy.
[0054] In a second variant, the formation of the region of the active layer intended for the formation of the electronic circuit part comprises a localized epitaxy which is carried out directly at the end of the detachment illustrated in [Fig.6]. This localized epitaxy is followed by an oxidation making it possible to form the surface layer 21 covering the region of the active layer intended for the formation of a photonic interface. This oxidation can be a localized oxidation forming a dielectric layer on the surface of a region of the active layer which has not been subject to localized epitaxy. Alternatively, it may be a full plate oxidation which is then followed by localized removal to retain only the surface layer 21 covering the region of the active layer intended for the formation of a photonic interface.
[0055] In a third embodiment, full-plate epitaxy is carried out following the detachment illustrated in [Fig. 6]. This epitaxy is followed by localized etching and oxidation to form the surface layer 21 covering the region of the active layer intended for the formation of a photonic interface.
[0056] The invention also relates to a method for manufacturing a photonic-electronic integrated circuit chip as previously described, in particular in connection with [Fig. 1]. This method comprises the following steps: - manufacturing a semiconductor substrate on insulator in accordance with the process, various variants of which have been set out above; - formation of a part of an electronic circuit in the region of the active layer intended for the formation of a part of an electronic circuit; - formation of a photonic interconnection interface in the region of the active layer intended for the formation of a photonic interconnection interface of the electronic circuit part.
[0057] In this method, the manufacturing of the semiconductor substrate on insulator may comprise, before or after all or part of the formation of the photonic interconnection interface, the formation of the dielectric layer 21 on the surface of the region of the active layer intended for the formation of the photonic interconnection interface.
Claims
Claims
1. A photonic-electronic integrated circuit chip formed on a semiconductor-on-insulator substrate, which semiconductor-on-insulator substrate comprises a buried dielectric layer (11) and an active layer of semiconductor material (12), said chip comprising an electronic circuit portion (CEI, CE2) and an interconnecting photonic interface (IPI) of the electronic circuit portion co-integrated in the active layer and being characterized in that the electronic circuit portion (CEI, CE2) is formed in a region of the active layer (RE1, RE2) whose thickness is greater than the thickness of a region of the active layer (RP) in which said photonic interface (IPI) is formed.
2. The chip of claim 1, wherein the active layer region (RP) in which said photonic interface is formed is sandwiched between the buried dielectric layer (11) and a surface dielectric region (21) and the active layer region in which the electronic circuit portion is formed is devoid of a surface dielectric layer.
3. Chip according to one of claims 1 and 2, wherein the thickness of the region of the active layer (RE1, RE2) in which the electronic circuit part is formed is greater than 0.2 pm, preferably greater than 0.5 pm.
4. Chip according to one of claims 1 to 3, wherein the thickness of the region of the active layer (RP) in which said photonic interface is formed is between 0.2pm and 0.5pm.
5. Chip according to one of claims 1 to 4, in which the buried dielectric layer (11) has a thickness greater than 1 pm, preferably greater than 2 pm.
6. Chip according to one of claims 1 to 5, in which the photonic interface comprises at least one waveguide and, preferably, a part of an active photonic circuit.
7. Chip according to one of claims 1 to 6, in which the electronic circuit part comprises a transistor logic module, the transistors being for example of the FinFET or GAAFET type.
8. A method of manufacturing a semiconductor-on-insulator substrate comprising a support substrate (20), a dielectric layer (11) and a separate active layer of semiconductor material (12) of the support substrate by the dielectric layer, a region of the active layer (RP) intended for the formation of a part of an electronic circuit being of greater thickness than the thickness of a region of the active layer (RE1, RE2) intended for the formation of a photonic interface for interconnecting the part of the electronic circuit, the method comprising a transfer of the active layer (12) from a donor substrate (10) to the support substrate (20), said transfer comprising a bonding of the donor substrate and the support substrate with the dielectric layer (11) at the bonding interface.
9. The method of claim 8, further comprising localized etching of the transferred active layer to form the region of the active layer for forming the photonic interconnect interface.
10. The method of claim 9, further comprising forming a dielectric layer on the surface of the region of the active layer for forming the photonic interconnect interface.
11. The method of claim 8, further comprising forming the region of the active layer for forming the electronic circuit portion by means of localized epitaxy.
12. A method according to claim 11, wherein the formation of the region of the active layer intended for the formation of the electronic circuit part is preceded by the steps of oxidizing the transferred active layer to form a dielectric layer (14) and localized removal of the dielectric layer, the remaining dielectric layer (21) after localized removal serving as a mask for the localized epitaxy.
13. A method according to claim 11, comprising forming a dielectric layer (21) on the surface of a region of the active layer which has not been subject to localized epitaxy.
14. A method of manufacturing a photonic-electronic integrated circuit chip, comprising the following steps: - manufacturing a semiconductor-on-insulator substrate in accordance with the method according to claim 8; - forming an electronic circuit part in the region of the active layer intended for the formation of an electronic circuit part;
15. - formation of a photonic interconnection interface in the region of the active layer intended for the formation of a photonic interconnection interface of the electronic circuit part. The method of claim 14, wherein the fabrication of the semiconductor-on-insulator substrate comprises, before or after all or part of the formation of the photonic interconnect interface, the formation of a dielectric layer on the surface of the region of the active layer intended for the formation of the photonic interconnect interface.