Method for manufacturing high-voltage transistors on a silicon-on-insulator substrate

Abstract

The process for manufacturing at least one high-voltage transistor (HV_NMOS, HV_PMOS) in and on a high-voltage region (HV_REG) of a silicon-on-insulator (SOI) substrate comprising a semiconductor film (FLM) having a first thickness (E1), electrically isolated from a carrier substrate (BLK) by a buried dielectric layer (BOX), includes epitaxial growth of the semiconductor film (FLM) to a second thickness (E2, E3) greater than the first thickness (E1), selectively in the high-voltage region (HV_REG). Figure for the abstract: Fig 11

Description

Title of the invention: Method for manufacturing high-voltage transistors on a silicon-on-insulator type substrate

[0001] Embodiments and implementations relate to microelectronics, in particular the fabrication of semiconductor devices comprising high-voltage transistors in and on a substrate of the SOI type (known by the English term “Silicon On Insulator” for “silicon on insulator” in French).

[0002] Semiconductor devices on SOI type substrates or also called “FDSOI” for “Fully Depleted Silicon On Insulator” typically integrate semiconductor components such as MOS type transistors (for “Metal Oxide Semiconductor”).

[0003] MOS transistors operating at different voltage ranges can be manufactured from the same SOI substrate capable of giving them better performance than a monolithic silicon substrate (usually referred to by the English term "bulk"). For example, so-called high-voltage MOS transistors can be designed in cointegration with other semiconductor components on an SOI substrate.

[0004] However, high-voltage transistors manufactured from an SOI substrate undergo the phenomenon of hot carrier degradation (also known by the acronym "HCI" for "Hot Carrier Injection"). Hot carrier degradation results in a long-term drift in the threshold voltage and the linear and saturated currents of the transistors, leading to a degradation in the performance of the high-voltage transistors.

[0005] Consequently, additional steps for providing a localized monolithic substrate region in the SOI substrate are conventionally provided for the manufacture of high-voltage transistors, so as to limit the phenomenon of degradation by hot carriers. In particular, the electronic components, in particular the high-voltage transistors, produced in the localized monolithic region are formed in the carrier substrate while the components of other regions are formed on a thin film isolated from the carrier substrate by a buried silicon oxide layer.

[0006] Furthermore, the localized monolithic substrate region does not allow in particular the "completely deserted" effect, nor an advantageous "partially deserted" effect of SOI techniques. This limits the performance of high-voltage transistors formed on the carrier substrate, in particular in terms of control of short channels, density and disparities of characteristics between the transistors.

[0007] There is a need to design, from a silicon-on-insulator type substrate, high-voltage transistors which do not suffer from the aforementioned drawbacks and to increase their reliability.

[0008] A solution is therefore proposed making it possible to form, in a region of the SOI substrate, a thin film having a thickness sufficiently high to make it possible to manufacture high-voltage transistors in this region of the substrate without causing a loss of performance during the operation of these transistors, in particular without undergoing the phenomena of degradation by hot carriers.

[0009] According to one aspect, there is provided a method of manufacturing at least one high-voltage transistor in and on a high-voltage region of a silicon-on-insulator type substrate comprising a semiconductor film having a first thickness, electrically insulated from a carrier substrate by a buried dielectric layer.

[0010] The method comprises epitaxial growth of the semiconductor film, to a second thickness greater than the first thickness, selectively in the high-voltage region.

[0011] It is thus proposed to increase the thickness of the semiconductor film selectively, that is to say only in the high-voltage region of the silicon-on-insulator type substrate, and not in another "first" region of said substrate. The first region, distinct from the high-voltage region, may for example be a low-voltage region in and on which transistors operating at lower voltage ranges than the high-voltage transistors may be formed, for example voltages lower than 2 volts, while the high-voltage transistors may be intended to operate at voltages higher than 2 volts for example.

[0012] Therefore, the method according to this aspect makes it possible to form, in the high-voltage region where the high-voltage transistors are manufactured, a semiconductor film that is thick enough to avoid the phenomenon of degradation by hot carriers, but also thin enough to benefit from the performance advantages of silicon-on-insulator devices and thus improve the performance of the high-voltage transistors.

[0013] According to one embodiment, the method comprises epitaxial growth of the carrier substrate in a localized monolithic region of the silicon-on-insulator type substrate, wherein said growth of the semiconductor film in the high-voltage region is carried out simultaneously with the growth of the carrier substrate in the localized monolithic region.

[0014] It is thus possible to achieve “free” growth of the semiconductor film since this is achieved during the same step as the growth of the carrier substrate provided in the localized monolithic region.

[0015] According to one embodiment, said growth of the carrier substrate in the region monolithic localized growth comprises forming a hard mask covering the semiconductor film in the high-voltage region and exposing the semiconductor film in the localized monolithic region, oxidizing the semiconductor film in the localized monolithic region, and etching selectively removing the oxidized semiconductor film and the buried dielectric layer in the localized monolithic region; and wherein said growth of the semiconductor film in the high-voltage region comprises etching adapted to remove the hard mask in the high-voltage region prior to said epitaxial growth of the semiconductor film in the high-voltage region.

[0016] This mode of implementation makes it possible to limit the number of additional masks necessary for carrying out the growth of the semiconductor film in the high-voltage region and makes it possible to benefit from the pooling of the growth step of the carrier substrate in the monolithic region.

[0017] According to one embodiment, said growth of the semiconductor film comprises a formation of a dedicated hard mask uncovering the semiconductor film in the high-voltage region, prior to said epitaxial growth of the semiconductor film in the high-voltage region.

[0018] This mode of implementation makes it possible to control the thickness of the semiconductor film in the high-voltage region independently of the constraints of another epitaxy step.

[0019] It is thus possible to set the thickness of the semiconductor film in the high-voltage region to a size specifically sized for high-voltage transistors.

[0020] According to one embodiment, the method comprises forming a gate region of said at least one high-voltage transistor on the semiconductor film having the second thickness of the high-voltage region, and forming conduction regions of said at least one high-voltage transistor in the semiconductor film having the second thickness of the high-voltage region.

[0021] The semiconductor film in the high-voltage region can be used to form the conduction regions of MOS-type transistors intended to operate at relatively high voltages, of the order of 3.3 volts for example.

[0022] According to one embodiment, the second thickness of the semiconductor film in the high-voltage region is small enough to generate a completely deserted state throughout the thickness of the semiconductor film in the presence of a channel region of said at least one high-voltage transistor.

[0023] Indeed, a semiconductor film in a completely deserted state makes it possible to ensure better electrostatic control of the channel of high-voltage transistors and to reduce short channel effects.

[0024] According to one embodiment, the first thickness is less than or equal to 7 nm and the second thickness is between 20 nm and 25 nm.

[0025] A second thickness of the semiconductor film less than or equal to 25 nm makes it possible to obtain a completely deserted semiconductor film and a second thickness of the film greater than or equal to 20 nm makes it possible to limit “impact ionization”. Impact ionization generates hot carriers which are likely to be stored in the gate dielectric regions of the high-voltage transistors, which degrades the performance of the transistors.

[0026] According to another aspect, there is provided a semiconductor device comprising at least one high-voltage transistor disposed in and on a high-voltage region of a silicon-on-insulator substrate comprising a semiconductor film, electrically insulated from a carrier substrate by a buried dielectric layer, wherein the semiconductor film has a first thickness in a first region different from the high-voltage region and has a second thickness greater than the first thickness in the high-voltage region.

[0027] According to one embodiment, said at least one high-voltage transistor comprises a gate region arranged on the semiconductor film having the second thickness in the high-voltage region, and conduction regions formed in the semiconductor film having the second thickness in the high-voltage region.

[0028] According to one embodiment, the second thickness of the semiconductor film in the high-voltage region is small enough to generate a completely deserted state throughout the thickness of the semiconductor film in the presence of a channel region of said at least one high-voltage transistor.

[0029] According to one embodiment, the first thickness is less than or equal to 7 nm and the second thickness is between 20 nm and 25 nm.

[0030] Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments and implementations, which are in no way limiting, and the appended drawings in which:

[0031] [Fig.l]

[0032] [Fig.2]

[0033] [Fig.3]

[0034] [Fig.4]

[0035] [Fig.5]

[0036] [Fig.6]

[0037] [Fig.7]

[0038] [Fig.8]

[0039] [Fig.9]

[0040] [Fig. 10]

[0041] [Fig. 11] schematically illustrate methods of implementing and producing the invention.

[0042] [Fig.l] schematically illustrates the result of a step 100 of a method for manufacturing at least one high-voltage transistor HV_NM0S, HV_PMOS ([Fig. 11]).

[0043] Step 100 comprises obtaining a substrate of the silicon-on-insulator SOI type and forming a hard mask HD_MSK1. The SOI substrate comprises a carrier substrate BLK, a buried dielectric layer BOX and a semiconductor film FLM. The material of the carrier substrate BLK and the semiconductor film FLM is typically silicon. The buried dielectric layer BOX is typically a layer of silicon oxide of formula SiO2.

[0044] The semiconductor film FLM has a first thickness El and is electrically insulated from the carrier substrate BLK by the buried dielectric layer BOX. For example, the thickness El of the semiconductor film is less than or equal to 7 nm, preferably between 4 nm and 7 nm.

[0045] The silicon-on-insulator SOI substrate has at least three distinct regions: a low-voltage region LV_REG, a high-voltage region HV_REG and a localized monolithic region LBLK_REG.

[0046] The high-voltage transistors HV_NMOS, HV_PMOS will be fabricated in and on the high-voltage region HV_REG of the silicon-on-insulator SOI substrate and may be designed to operate at voltages between 2 volts and 5 volts.

[0047] The low-voltage region LV_REG is used for the manufacture of “low-voltage” MOS transistors, for example designed to operate at voltages lower than 2 volts.

[0048] The localized monolithic region LBLK_REG can be used for the fabrication of contact points POL_BLK of the carrier substrate BLK, or other types of semiconductor components, such as bipolar transistors BJT for example.

[0049] The hard mask HD_MSK1 may be a silicon nitride mask of formula Si3 N4. The hard mask HD_MSK1 covers the semiconductor film FLM in the low-voltage region LV_REG and in the high-voltage region HV_REG and uncovers the semiconductor film FLM in the monolithic region LBLK_REG.

[0050] Figures 2 to 6 illustrate the results of steps 110 to 114 of a first embodiment of the method.

[0051] [Fig.2] illustrates the result of a step 110 of oxidation of the semiconductor film FLM in the localized monolithic region LBLK_REG. For example, the semiconductor film FLM can be oxidized using conventional oxidation techniques known to those skilled in the art. Following the oxidation, the oxidized semiconductor film FLM_OX can form with the buried dielectric layer BOX a homogeneous layer of silicon oxide SiO2.

[0052] [Fig.3] illustrates the result of a step 111 of forming a resin mask RES_MSK.

[0053] At this step 111, the resin mask RES_MSK covers the hard mask HD_MSK1 in the low-voltage region LV_REG and the oxidized semiconductor film FLM_OX in the localized monolithic region LBLK_REG. The hard mask HD_MSK1 is uncovered in the high-voltage region HV_REG.

[0054] [Fig.4] illustrates the result of a step 112 of etching the hard mask HD_MSK1. The etching 112 is adapted to remove the hard mask HD_MSK1 in the regions which are not covered by the resin mask RES_MSK, i.e. in particular in the high-voltage region HV_REG. At the end of step 112, the resin mask RES_MSK is removed.

[0055] [Fig.5] illustrates the result of a step 113 of etching the semiconductor film oxidized FLM_0X. The etching step 113, which may be for example a wet etching, is configured to selectively etch the silicon oxide and not etch, or etch with a dynamic much lower than the etching dynamic of the silicon oxide, the crystalline silicon of the semiconductor film FLM and of the carrier substrate BLK. Thus, step 113 makes it possible to selectively remove the oxidized semiconductor film FLM_OX and the buried dielectric layer BOX in the localized monolithic region LBLK_REG.

[0056] Consequently, at the end of step 113, the silicon semiconductor film FLM is uncovered in the high-voltage region HV_REG and the silicon carrier substrate BLK is uncovered in the localized monolithic region LBLK_REG. The hard mask HD_MSK1 now only covers the semiconductor film FLM in the low-voltage region LV_REG.

[0057] [Fig.6] illustrates the result of a step 114 of epitaxial growth of the semi- FLM conductor and BLK carrier substrate. Epitaxy allows crystalline silicon to be grown from the exposed crystalline silicon layers, i.e. the FLM semiconductor film in the high-voltage region HV_REG and the BLK carrier substrate in the localized monolithic substrate region LBLK_REG.

[0058] Thus, in this mode of implementation, the growth of the semiconductor film FLM is carried out “free of charge” during the same step 114 shared with the growth of the carrier substrate BLK in the localized monolithic region LBLK_REG.

[0059] In particular, it is appropriate to choose an additional thickness Esupl so that the carrier substrate layer BLK in the localized monolithic region LBLK_REG reaches the same height as the surface layers of the other regions of the SOI substrate, for example the surface of the semiconductor film FLM in the low-voltage region LV_REG.

[0060] Since the growth of the FLM semiconductor film is subordinate to the growth of the carrier substrate BLK, the FLM semiconductor film grows in thickness additional Esupl, in the high-voltage region HV_REG.

[0061] Thus, a second total thickness E2 of the FLM semiconductor film is obtained in the high-voltage region HV_REG which corresponds to the sum of the first thickness El and the additional thickness Esupl, and is therefore greater than the first thickness El. The additional thickness Esupl may be between 10 nm and 25 nm for example. The second total thickness E2 is greater than or equal to 20 nm, and is preferably between 20 nm and 25 nm. The second thickness E2 is, for example, 25 nm for a first thickness El equal to 7 nm and an additional thickness Esupl equal to 18 nm. It may be advantageous to define a second thickness E2 less than or equal to 25 nm so as to guarantee that the FLM semiconductor film is completely deserted.However, these values ​​are given as a non-limiting example and it is possible to provide a more or less thick FLM semiconductor film, for example for a second thickness E2 less than 20 nm or greater than 25 nm, and consequently without benefiting from the entirely deserted effect.

[0062] The growth of the FLM semiconductor film makes it possible to form, in the high-voltage region HV_REG where the high-voltage transistors are manufactured, an FLM semiconductor film that is thick enough to avoid the phenomenon of degradation by hot carriers, but also thin enough to benefit from the performance advantages of silicon-on-insulator devices and thus improve the performance of the high-voltage transistors.

[0063] In this regard, the second total thickness E2 of the FLM semiconductor film in the high-voltage region HV_REG is small enough to generate a completely deserted state in the entire thickness of the FLM semiconductor film in the presence of a channel region of the high-voltage transistor HV_NMOS, HV_PMOS.

[0064] Indeed, a semiconductor film in a completely deserted state makes it possible to ensure better electrostatic control of the channel of high-voltage transistors and to reduce short channel effects.

[0065] Figures 7 to 10 illustrate the results of steps 120 to 123 of a second embodiment of the method which initially begins at step 100 described previously in relation to [Fig.l].

[0066] [Fig. 7] illustrates the result of steps 120 corresponding to a conventional formation of the localized monolithic substrate region LBLK_REG. In particular, steps 120 comprise steps 100, 110, 113 and 114 described previously in relation to Figures 1, 2, 5 and 6, without implementing steps 111 and 112 described previously in relation to Figures 3, 4, so that the hard mask HD_MSK1 also covers the semiconductor film FLM in the high-voltage region HV_REG during the epitaxial growth step 114, thus carried out exclusively in the localized monolithic region LBLK_REG.

[0067] [Fig.8] illustrates the result of an etching step 121 adapted to completely remove the mask HD_MSK1, i.e. in the low-voltage region LV_REG and in the high-voltage region HV_REG.

[0068] [Fig.9] illustrates the result of a step 122 of forming and etching a mask dedicated hard mask HD_MSK2 for the growth of the FLM semiconductor film in the high voltage region HV_REG. The hard mask HD_MSK2 is typically a silicon nitride mask and is grown on the FLM semiconductor film of the SOL substrate

[0069] The silicon nitride layer is etched so as to expose only the semiconductor film FLM in the high-voltage region HV_REG and to cover the SOI substrate outside the high-voltage region HV_REG, i.e. in particular the semiconductor film FLM in the low-voltage region LV_REG and the carrier substrate BLK in the localized monolithic region LBLK_REG.

[0070] [Fig. 10] illustrates the result of a step 123 of epitaxial growth of the FLM semiconductor film in the high-voltage region HV_REG.

[0071] The epitaxial growth at step 123 corresponds substantially to the growth of step 114 described previously in relation to [Fig.6], but does not depend on the growth of the BLK carrier substrate carried out in the localized monolithic region LBLK_REG.

[0072] As a result, the FLM semiconductor film can grow by an additional thickness Esup2, selectively in the high-voltage region HV_REG.

[0073] Thus, a second total thickness E3 of the semiconductor film FLM is obtained in the high-voltage region HV_REG which corresponds to the sum of the first thickness El and the additional thickness Esup2, and is therefore greater than the first thickness EL

[0074] An additional etching step (not shown) can be performed to remove the hard mask HD_MSK2 in the low-voltage region LV_REG and in the localized monolithic region LBLK_REG.

[0075] This second embodiment of the method thus makes it possible to control the thickness of the FLM semiconductor film in the high-voltage region independently of the constraints of another epitaxy step, for example those that may be imposed by the growth of the carrier substrate BLK as described in step 114 of the method according to the first embodiment. It is thus possible to parameterize the second total thickness E3 of the FLM semiconductor film in the high-voltage region to a size specifically sized for the high-voltage transistors HV_NMOS, HV_PMOS.

[0076] The additional thickness Esup2 can be between 10 nm and 25 nm for example. The second total thickness E3 is greater than or equal to 20 nm and is preferably between 20 nm and 25 nm. The second thickness E3 is, for example, 25 nm for a first thickness El equal to 7 nm and an additional thickness Esup2 equal to 18 nm. It is advantageous to define a second thickness E3 less than 25 nm so as to guarantee that the FLM semiconductor film is entirely deserted. However, these values ​​are given as a non-limiting example and it is possible to provide a more or less thick FLM semiconductor film, for example for a second thickness E3 less than 20 nm or greater than 25 nm, and consequently without benefiting from the entirely deserted effect.

[0077] In summary, the method described in relation to figures 1 to 10 makes it possible to form the semiconductor film FLM having a second thickness E2 in the high-voltage region HV_REG equal to the sum of the first thickness El and the additional thickness Esupl, or alternatively, a second total thickness E3 equal to the sum of the first thickness El and the additional thickness Esup2 which may be different from the additional thickness Esupl obtained during the first mode of implementation of the method.

[0078] [Fig. 11] illustrates a semiconductor device DISP obtainable from the manufacturing method described in relation to Figures 1 to 10.

[0079] The semiconductor device DISP comprises at least one high-voltage transistor HV_NMOS, HV_PMOS arranged in and on the high-voltage region HV_REG of the silicon-on-insulator substrate SOL. For example, a high-voltage transistor HV_NMOS of the NMOS type and a high-voltage transistor HV_PMOS of the PMOS type may be arranged in and on the high-voltage region HV_REG. Each of the high-voltage transistors HV_NMOS, HV_PMOS comprises a gate region G arranged on the semiconductor film FLM in the high-voltage region HV_REG and conduction regions, i.e., a drain region D and a source region S, implanted in the semiconductor film FLM in the high-voltage region HV_REG. The high-voltage transistors HV_NMOS, HV_PMOS are typically MOS transistors intended to operate at voltages between 2 volts and 5 volts.

[0080] A gate dielectric layer HV_G0X is conventionally arranged between the gate region G of the HV_NMOS, HV_PMOS transistors and the FLM semiconductor film

[0081] As a reminder, the second total thickness E2 or E3, depending on the mode of implementation of the method described previously, of the semiconductor film FLM in the high-voltage region HV_REG is sufficiently small to generate a completely deserted state in the entire thickness of the semiconductor film FLM located opposite the gate region G of the high-voltage transistor, when the channel region of the high-voltage transistor HV_NMOS, HV_PMOS is formed.

[0082] By "sufficiently small" is meant for example that the second total thickness E2 or E3 of the FLM semiconductor film in the high-voltage region HV_REG does not exceed 25 nm.

[0083] Furthermore, low-voltage transistors LV_MOS may be arranged in and on the semiconductor film FLM in the low-voltage region LV_REG. The gate regions G and the conduction regions S and D of the LV_MOS transistors are formed analogously to the gate regions G and the conduction regions S and D of the high-voltage transistors HV_NM0S, HV_PMOS. The low-voltage transistors LV_MOS are typically MOS transistors intended to operate at voltages below 2 volts.

[0084] Furthermore, a bipolar transistor BJT can be realized in and on the carrier substrate BLK in the localized monolithic region LBLK_REG.

[0085] A POL_BLK contact is typically formed in the localized monolithic region LBLK_REG in order to polarize the carrier substrate BLK in the different regions LV_REG, LBLK_REG, HV_REG of the silicon-on-insulator substrate SOL

Claims

Claims

1. Method for manufacturing at least one high-voltage transistor (HV_NMOS, HV_PMOS) in and on a high-voltage region (HV_REG) of a silicon-on-insulator (SOI) substrate comprising a semiconductor film (FLM) having a first thickness (El), electrically insulated from a carrier substrate (BLK) by a buried dielectric layer (BOX), the method comprising: - epitaxial growth of the semiconductor film (FLM), up to a second thickness (E2, E3) greater than the first thickness (El), selectively in the high-voltage region (HV_REG), wherein the second thickness (E2, E3) of the semiconductor film (FLM) in the high-voltage region (HV_REG) is small enough to generate a completely deserted state throughout the thickness of the semiconductor film (FLM) in the presence of a channel region of said at least one high-voltage transistor (HV_NMOS, HV_PMOS), the method further comprising epitaxial growth of the carrier substrate (BLK) in a localized monolithic region (LBLK_REG) of the silicon-on-insulator (SOI) substrate, wherein said growth of the semiconductor film (FLM) in the high-voltage region (HV_REG) is carried out simultaneously with the growth of the carrier substrate (BLK) in the localized monolithic region (LBLK_REG).

2. The method of claim 1, wherein said growth of the carrier substrate (BLK) in the localized monolithic region (LBLK_REG) comprises: - formation of a hard mask (HD_MSK1) covering the semiconductor film (FLM) in the high-voltage region (HV_REG) and uncovering the semiconductor film (FLM) in the localized monolithic region (LBLK_REG), - an oxidation of the semiconductor film (FLM) in the localized monolithic region (LBLK_REG), and an etching selectively removing the oxidized semiconductor film (FLM_OX) and the buried dielectric layer (BOX) in the localized monolithic region (LBLK_REG); and wherein said growth of the semiconductor film (FLM) in the high-voltage region (HV_REG) comprises: - an etching adapted to remove the hard mask (HD_MSK1) in the high-voltage region (HV_REG) prior to said epitaxial growth of the semiconductor film (FLM) in the high-voltage region (HV_REG).

3. Method according to one of claims 1 or 2, comprising a formation of a gate region (G) of said at least one high-voltage transistor (HV_NMOS, HV_PMOS) on the semiconductor film (FLM) having the second thickness (E2) of the high-voltage region (HV_REG), and a formation of conduction regions (S, D) of said at least one high-voltage transistor (HV_NMOS, HV_PMOS) in the semiconductor film (FLM) having the second thickness (E2) of the high-voltage region (HV_REG).

4. Method according to one of the preceding claims, in which the first thickness (El) is less than or equal to 7 nm and the second thickness (E2) is between 20 nm and 25 nm.

5. Semiconductor device comprising at least one high-voltage transistor (HV_NMOS, HV_PMOS) arranged in and on a high-voltage region (HV_REG) of a silicon-on-insulator (SOI) substrate comprising a semiconductor film (FLM), electrically insulated from a carrier substrate (BLK) by a buried dielectric layer (BOX), wherein the semiconductor film (FLM) has a first thickness (El) in a first region (LV_REG) different from the high-voltage region and has a second thickness (E2, E3) greater than the first thickness (El) in the high-voltage region (HV_REG), wherein the second thickness (E2, E3) of the semiconductor film (FLM) in the high-voltage region (HV_REG) is sufficiently small to generate a completely deserted state throughout the thickness of the semiconductor film (FLM) in the presence of a channel region of said at least one high-voltage transistor (HV_NMOS, HV_PMOS).

6. A semiconductor device according to claim 5, wherein said at least one high-voltage transistor (HV_NMOS, HV_PMOS) comprises a gate region (G) disposed on the semiconductor film (FLM) having the second thickness (E2, E3) in the high-voltage region (HV_REG), and conduction regions (S, D) formed in the semiconductor film (FLM) having the second thickness (E2, E3) in the high-voltage region (HV_REG).

7. Semiconductor device according to one of claims 5 or 6, in which the first thickness (El) is less than or equal to 7 nm and the second thickness (E2) is between 20 nm and 25 nm.

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