Phase-change memory cell

Abstract

Phase-Change Memory Cell This description relates to a phase-change memory cell (300) comprising: – a first layer of a phase-change material (215); – a heating element (209) located beneath the first layer (215); – a second insulating layer (203) covering one side of the heating element (209); and – a third insulating layer (205) interposed between the first and second layers (215, 203), made of a material having a higher density than the material of the second layer (203). Figure for the abbreviation: Fig. 3A

Description

Title of the invention: Phase-change memory cell technical field

[0001] This description relates generally to electronic devices, and more particularly to memory devices comprising memory cells based on a phase change material, also called phase change memory cells. Previous technique

[0002] In a phase-change memory cell, the phase-change material is capable of alternating, under the effect of heat, between a crystalline, electrically conductive phase and an amorphous, electrically insulating phase. The crystalline and amorphous phases of the phase-change material of a memory cell allow the definition of two memory states for that cell, corresponding, for example, to the logic values ​​1 and 0 respectively. The heat required for the phase change is generally produced by Joule heating, for example, by means of a heating element located near the phase-change material and carrying an electric current resulting from a voltage pulse applied between the conduction terminals of the heating element. Summary of the invention

[0003] In order to obtain phase-change memory cells with increased energy efficiency, it would be desirable to optimize the thermal performance of current phase-change memory cells so that the electrical energy required to heat the phase-change material is as low as possible. Advantageously, this would allow memory devices incorporating such cells to have lower energy consumption than current phase-change memory devices.

[0004] An embodiment overcomes all or part of the disadvantages of known phase-change material-based memory cells and known memory devices incorporating such cells.

[0005] To this end, one embodiment provides a phase-change memory cell comprising: - a first layer made of a phase-change material; - a heating element located under the first layer; - a second insulating layer covering one side of the heating element; and - a third insulating layer placed between the first and second layers, made of a material with a higher density than the material of the second layer.

[0006] According to one embodiment, the second layer is made of silicon carbide or silicon carbonitride.

[0007] According to one embodiment, the third layer is made of silicon carbide, silicon nitride, silicon carbonitride, germanium nitride, carbon nitride or carbon.

[0008] According to one embodiment, the third layer is made of the same material as the second layer.

[0009] According to one embodiment, the second and third layers are made of silicon carbide.

[0010] According to one embodiment, the second and third layers are made of silicon nitride.

[0011] According to one embodiment, the cell further comprises a first conduction electrode located under and in contact with a face of the heating element opposite the first layer and a second conduction electrode located on and in contact with a face of the first layer opposite the heating element.

[0012] According to one embodiment, the heating element has an L-shaped form.

[0013] According to one embodiment, the cell further comprises a stack comprising a fourth encapsulation layer covering the lateral faces of the first, second and third layers and a fifth encapsulation layer covering the fourth layer and having a lower density than the fourth layer.

[0014] According to one embodiment, the cell further comprises a sixth encapsulation layer covering the fifth layer and having a density greater than that of the fifth layer.

[0015] One embodiment provides a method for manufacturing a phase-change memory cell comprising the following successive steps: a) deposit, on a substrate, a first insulating layer and a second insulating layer covering the first insulating layer, the second insulating layer being made of a material having a higher density than the material of the second insulating layer; b) to form, in a trench passing through the first and second insulating layers, a heating element, one side of which is covered by the first and second insulating layers; and c) deposit, on the side of the second insulating layer, a third layer of a phase-change material.

[0016] According to one embodiment, the process further comprises, between steps b) and c), successive steps of depositing a fourth encapsulation layer coating the lateral faces of the first, second and third layers and of a fifth encapsulation layer covering the fourth layer and having a lower density than that of the fourth layer.

[0017] According to one embodiment, the process further comprises, after the deposition of the fifth layer and before the deposition of the third layer, a step of deposition of a sixth encapsulation layer coating the fifth layer and having a density greater than that of the fifth layer.

[0018] Furthermore, one embodiment provides for a phase-change memory cell comprising: - a first layer made of a phase-change material; - a heating element located under the first layer; - a second insulating layer covering one side of the heating element; and - a first stack comprising a third encapsulation layer covering the lateral faces of the second layer and a fourth encapsulation layer covering the third layer and being made of a material having a lower density than the material of the third layer.

[0019] According to one embodiment, the fourth layer is coated with a second stack comprising an alternation of encapsulation layers having densities substantially equal to those of the third and fourth layers.

[0020] According to one embodiment, the fourth layer is coated with a second stack comprising successive encapsulation layers having decreasing densities, lower than those of the fourth layer.

[0021] According to one embodiment, the successive encapsulation layers of the second stack are made of the same material.

[0022] According to one embodiment, the cell further comprises a sixth encapsulation layer, coating the fourth layer or the second stack, the sixth layer having a higher density than the fourth layer.

[0023] According to one embodiment, the cell further comprises a first conduction electrode located under and in contact with a face of the heating element opposite the first layer and a second conduction electrode located on and in contact with a face of the first layer opposite the heating element.

[0024] According to one embodiment, the cell further comprises a third stack comprising a seventh encapsulation layer covering the lateral faces of the first layer and the second conduction electrode and an eighth encapsulation layer covering the seventh layer and having a lower density than that of the seventh layer.

[0025] According to one embodiment, the cell further comprises a ninth layer interposed between the first and second layers and having a density greater than that of the second layer, the second layer being made of silicon carbide or silicon carbonitride.

[0026] According to one embodiment, the ninth layer is made of silicon carbide, silicon nitride or silicon carbonitride and has a higher density than the second layer.

[0027] According to one embodiment, the ninth layer is made of germanium nitride, carbon nitride or carbon.

[0028] One embodiment provides a method for manufacturing a phase-change memory cell comprising the following successive steps: a) deposit, on a substrate, at least one first thermally insulating layer; (b) to form, in a trench passing through said at least one first layer, a heating element, one side of which is coated by said at least one first layer; and (c) form a first stack comprising a second encapsulation layer covering the lateral faces of said at least a first layer and a third encapsulation layer covering the second layer, the third layer being made of a material having a lower density than the material of the second layer.

[0029] According to one embodiment, the process further comprises, after step c), a step d) of depositing a fourth encapsulation layer covering the third layer and having a density greater than that of the third layer. Brief description of the drawings

[0030] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0031] [Fig.1A] and [Fig.1B] are cross-sectional views illustrating, schematically and partially, an example of a memory device comprising memory cells based on a phase-change material;

[0032] the [Fig.2A], [Fig.2B], [Fig.2C], [Fig.2D], [Fig.2E], [Fig.2F], [Fig.2G], [Fig.2H] and [Fig. 2I] are cross-sectional views illustrating, schematically and partially, a manufacturing process for a memory device comprising memory cells based on a phase-change material according to one embodiment; and

[0033] [Fig.3A] and [Fig.3B] are cross-sectional views illustrating, schematically and partially, a memory device comprising memory cells based on a phase-change material according to one embodiment. Description of the implementation methods

[0034] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may to have identical structural, dimensional and material properties.

[0035] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the control elements and circuits of the phase-change memory cells of the described memory devices, which may include selection and electrical connection elements, are not detailed, as the described embodiments are compatible with the control elements and circuits of conventional phase-change memory cells.

[0036] Unless otherwise specified, when referring to two elements connected between them, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or linked via one or more other elements.

[0037] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0038] Unless otherwise specified, the expressions "approximately", "about", "Approximately" and "of the order of" mean within 10%, preferably within 5%.

[0039] Fig. 1A and Fig. 1B are cross-sectional views, respectively along plane AA of Fig. 1B and along plane BB of Fig. 1A, illustrating schematically and partially an example of a memory device 100 comprising memory cells 101 based on a phase-change material, or phase-change memory cells 101. Plane AA of Fig. 1B is substantially orthogonal to plane BB of Fig. 1A.

[0040] By way of example, the memory device 100 is a non-volatile memory, for example an EEPROM (Electrically Erasable Programmable Read-Only Memory). The programming of each memory cell 101 of the memory device 100 is, for example, carried out after the device 100 has been manufactured and can then be modified several times during its use.

[0041] In the example shown, the memory cells 101 are formed in and on a substrate 103, for example a wafer or a piece of wafer made of a semiconductor material, for example silicon.

[0042] In the illustrated example, each memory cell 101 includes a contact re-establishment element 105, for example a conductive via, formed in the substrate 103. The element The contact element 105 extends through the thickness of the substrate 103 from a face 103T of the substrate 103 (the upper face of the substrate 103, in the orientation of Figures IA and IB). By way of example, the contact element 105 is made of an electrically conductive material, for example a metal, for example copper (Cu) or tungsten (W), or a metal alloy, for example titanium nitride (TiN) or tantalum nitride (TaN).

[0043] In the example shown, each memory cell 101 further comprises a resistive heating element 107 located on and in contact with the contact element 105 of the cell. In this example, the heating element 107 has a general L-shape comprising a horizontal portion extending laterally on and in contact with the upper face of the underlying contact element 105, and a vertical portion extending from one end of the horizontal portion along a direction substantially orthogonal to the face 103T of the substrate 103. The heating element 107 is made of an electrically conductive material. By way of example, the heating element is made of a metal or a metal alloy.

[0044] In the illustrated example, the heating element 107 of each cell 101 is interposed laterally between two electrically and thermally insulating regions 109. More precisely, in this example, the insulating regions 109 cover all the lateral faces of the heating element 107 parallel to the plane BB of [Fig. 1A] as well as the face of the horizontal part of the heating element 107 opposite the face 103T of the substrate 103. In the orientation of Figures IA and IB, the upper faces of the insulating regions 109 are flush with the upper face of the vertical part of the heating element 107. By way of example, the insulating region 109 is made of silicon nitride (SiN).

[0045] In the example shown, each memory cell 101 further comprises a region made of a phase-change material 111. In the orientation of Figures IA and IB, the phase-change material region 111 covers the upper faces of the insulating regions 109 and the vertical part of the heating element 107 of the cell. By way of example, the region 111 is made of a so-called "chalcogenide" material, that is to say, a material or alloy comprising at least one chalcogen element, for example, a material from the germanium telluride (GeTe) or germanium-antimony-telluride (GeSbTe, also designated by the acronym "GST") family.

[0046] In the example illustrated in Figures IA and IB, the upper face of the phase-change material region 111, in other words the face of the region 111 opposite the substrate 103, is coated with an electrically conductive region 113. By way of example, the electrically conductive region 113 is made of a metal or a metal alloy, for example titanium nitride (TiN).

[0047] Although not illustrated in Figures IA and IB, the electrically conductive region 113 can be coated, on the side of its face opposite the region in material to phase change 111, of a dielectric region intended to confine heat inside cell 101.

[0048] In the example shown, each cell 101 further comprises an encapsulation layer 115 covering the sides of the stack formed by the insulating regions 109, the phase-change material region 111, and the electrically conductive region 113. More specifically, the encapsulation layer 115 covers the lateral faces of the insulating regions 109, the lateral faces of the phase-change material region 111, and the lateral faces and the top face of the conductive region 113. In the illustrated example, the encapsulation layer 115 also covers the lateral faces of the heating element 107 parallel to the plane of [Fig. 1A], which are not covered by the insulating regions 109. The encapsulation layer 115 can also, as in the example illustrated in Figures IA and IB, extend between the memory cells 101.More specifically, in this example, the encapsulation layer 115 covers parts of the face 103T of the substrate 103 which are not covered by either the insulating regions 109 or the heating element 107.

[0049] Although not detailed in the figures, the memory cells 101 of the device 100 are, for example, arranged in a matrix. More precisely, the device 100 may, for example, comprise first rows, called bit lines, corresponding to rows of memory cells 101 parallel to each other and extending along a direction orthogonal to the plane of [Fig. 1B], and second rows, called word lines, corresponding to rows of memory cells 101 parallel to each other and orthogonal to the bit lines.

[0050] Although not detailed in Figures IA and IB, the contact re-establishment element 105 of each memory cell 101 passes, for example, through the substrate 103 and allows the horizontal part of the heating element 107 above to be connected to a conduction terminal of a selection element, not shown, for example a MOS (Metal-Oxide-Semiconductor) transistor, located on the side of a face of the substrate 103 opposite face 103T. The selection transistor, or selector, allows each memory cell 101 of the device 100 to be selected individually.As an example, selector transistors each include another conduction terminal connected to a node for applying a reference potential, for example, ground, and a control terminal (gate) to which a control voltage is applied, intended, depending on its value, to allow or prevent current flow between the conduction terminals (source and drain) of the transistor. Selector transistors for memory cells 101 that are part of the same word row, for example, have a common gate, extending, for example, along a direction orthogonal to the plane of the word row. the [Fig.IA],

[0051] In addition, all the memory cells forming part of the same bit line are for example interconnected, by their conductive regions 113, by means of a common electrode not shown in figures IA and IB.

[0052] The memory cells 101 of the memory device matrix 100 can store data by changing the phase of the material constituting their respective regions 111. Generally, phase-change materials are materials capable of alternating, under the effect of a temperature variation, between a crystalline phase and an amorphous phase, the amorphous phase having a higher electrical resistance than the crystalline phase. In the case of the memory cells 101, this phenomenon is exploited to obtain a conducting state, allowing current to flow between the contact re-establishment element 105 and the conductive region 113, when the material of region 111 is in the crystalline phase, and a blocking state, preventing current from flowing between the contact re-establishment element 105 and the conductive region 113, when at least part of the material of region 111 is in the amorphous phase.In this description, for simplicity, we assume that the entire region 111 undergoes phase changes. However, in practice, phase changes may occur in only a part of region 111, for example located on and in contact with the upper face of the heating element 107.

[0053] The switching states (region 111 in crystalline phase) and blocking states (region 111 in amorphous phase) of each memory cell 101 correspond, for example, to logic values ​​1 and 0 respectively. During the switching of cell 101 between logic states 1 and 0, the contact re-establishment element 105 and the conductive region 113 are, for example, subjected to a control voltage pulse causing current to flow through the heating element 107. This current causes, by Joule effect and then by radiation and / or conduction within the structure of cell 101, a temperature rise in region 111 from its lower face, located opposite the heating element 107.

[0054] More specifically, to switch the memory cell from logic state 1 to logic state 0, the region 111 is heated by means of the heating element 107, for example, to a temperature Tl and for a duration dl. The temperature Tl and the duration dl are chosen so as to induce a phase change of the material in region 111 from the crystalline phase to the amorphous phase. The temperature Tl is, for example, higher than the melting temperature of the material undergoing the phase change. As an example, the temperature Tl is between 600 and 1000 °C and the duration dl is less than 500 ns.

[0055] Conversely, to switch the memory cell 101 from logic state 0 to logic state 1, the region 111 is heated by means of the heating element 107, by For example, at a temperature T2 lower than the temperature T1 and for a duration d2 greater than the duration d1. The temperature T2 and the duration d2 are chosen so as to induce a phase change of the material in region 111 from the amorphous phase to the crystalline phase. The temperature T2 is, for example, higher than the melting temperature of the material in region 111. As an example, the temperature T2 is approximately equal to the temperature T1 and the duration d2 is less than 1 ps.

[0056] After the memory device 100 is manufactured and before any writing or programming operations are performed, the phase-change material region 111 of each memory cell 101 is, for example, in a crystalline phase. In other words, the memory device 100 is, before writing, in an initial state where all its cells 101 contain the same logic value (the value 1, in this example). Data storage operations can then be performed in the memory device 100 by changing the phase of the regions 111 of some of the memory cells 101 from the crystalline phase to the amorphous phase, corresponding in this example to a logic value 0, while the regions 111 of the other part of the cells 101 are maintained in their initial state, that is, in the crystalline phase corresponding in this example to the logic value 1.

[0057] To read one of the phase-change memory cells 101 of the device 100, the cell is selected by biasing the gate of the associated selection transistor. A current, with a value sufficiently low to prevent any unintentional phase change, is then induced in the cell 101 by applying a potential difference between the conductive region 113 and the contact re-establishment element 105. An electrical resistance between the conductive region 113 and the contact re-establishment element 105 can then be measured. This electrical resistance reflects the logic value, 0 or 1, previously stored in the memory cell 101.

[0058] Although not detailed in Figures IA and IB, the device 100 may include other layers, for example layers of dielectric materials, arranged on the side of the face 103T of the substrate 103.

[0059] Figs. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H and 2I are cross-sectional views illustrating, schematically and partially, successive stages of a manufacturing process for a memory device 200 comprising memory cells 201 based on a phase-change material according to an embodiment.

[0060] The memory device 200 of Figures 2A to 21 includes elements in common with the memory device 100 of Figures IA and IB. These common elements will not be described again below.

[0061] Figure 2A is a cross-sectional view illustrating more precisely a structure obtained after a deposition step, on the side of face 103T of the substrate 103, of a stack of thermally insulating layers 203 and 205. In the example shown, the insulating layer 203 covers the upper face 103T of the substrate 103 and the upper face of the contact elements 105 which are flush with face 103T. In this example, the insulating layer 205 covers the face of the insulating layer 203 opposite the substrate 103 (the upper face of the insulating layer 203, in the orientation of Figure 2A).

[0062] According to one embodiment, the insulating layer 203 is made of a material having a density, or a bulk density, lower than that of the material of the insulating layer 205. The insulating layer 203 is for example made of silicon carbide (SiC) or silicon carbonitride (SiCN).

[0063] The insulating layer 205 is, for example, made of silicon nitride (SiN), silicon carbonitride, germanium nitride (GeN), carbon nitride (CN), or carbon (C). Alternatively, the insulating layers 203 and 205 are both made of silicon carbide (SiC) or silicon nitride (SiN), and the insulating layer 205 has a higher density than the insulating layer 203. In this case, the layer 203 has, for example, a density between 0.5 and 1.5 g / cm³ and the layer 205 has, for example, a density greater than 2 g / cm³. As an example, the insulating layer 203 has a thickness between 50 nm and 150 nm, for example equal to about 80 nm, and the insulating layer 205 has a thickness between 5 nm and 50 nm, for example equal to about 20 nm.

[0064] Layers 203 and 205 are, for example, both electrically insulating.

[0065] Fig. 2B is a cross-sectional view illustrating a structure obtained after a trenching step 207 in the insulating layers 203 and 205. For the sake of simplification, only one trench 207 is shown in Fig. 2B.

[0066] In the example shown, the trench 207 extends from the upper face of the layer 205 to the face 103T of the substrate 103, crossing completely through the layers 203 and 205. In this example, parts of the upper faces of two adjacent contact elements 105 and a part of the face 103T of the substrate 103 located between the two contact elements 105 are exposed at the bottom of the trench 207.

[0067] The trenches 207 are, for example, substantially parallel to each other and extend along a direction substantially orthogonal to the plane of [Fig. 2B]. The trenches 207 laterally separate disjoint parts of layers 203 and 205. In this example, the parts of layers 203 and 205 separated by the trenches 207 are substantially parallel to each other and extend along a direction substantially orthogonal to the plane of [Fig. 2B].

[0068] By way of example, the trenches 207 are formed by photolithography followed by etching.

[0069] [Fig. 2C] is a cross-sectional view illustrating a structure obtained after a deposition step, on the side of face 103T of the substrate 103, of an electrically conductive layer 209 coated with an electrically insulating layer 211.

[0070] In the example shown, the electrically conductive layer 209 covers the walls and bottom of the trenches 207 and extends laterally over and in contact with the upper face of the layer 205. More specifically, in this example, the electrically conductive layer 209 covers the sides and upper face of the parts of the layer 205 remaining after the formation of the trenches 207, the sides of the parts of the layer 203 remaining after the formation of the trenches 207, and the parts of the upper faces of the contact re-establishment elements 105 and of the face 103T of the substrate 103 previously exposed at the bottom of the trenches 207. The insulating layer 211 covers the face of the conductive layer 209 opposite the substrate 103 (the upper face of the conductive layer 209, in the orientation of [Fig. 2C]).

[0071] By way of example, the conductive layer 209 has a thickness between 1 nm and 20 nm, for example equal to about 3 nm, and the insulating layer 211 has a thickness between 5 nm and 100 nm, for example equal to about 20 nm.

[0072] In the example illustrated in [Fig.2C], layers 209 and 211 do not fill, i.e. do not completely fill, trench 207. This example is not limiting, however, as the stack formed by layers 209 and 211 can fill trench 207.

[0073] By way of example, the conductive layer 209 is made of a metal or a metal alloy, for example titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitide (TiCN) or silicon-titanium nitride (TiSiN).

[0074] By way of example, the insulating layer 211 is made of silicon nitride (SiN) or silicon carbide (SiC).

[0075] Fig. 2D is a cross-sectional view illustrating a structure obtained after an anisotropic etching step of layers 209 and 211. More specifically, in the example shown, the etching rate of layers 209 and 211 is greater along a direction orthogonal to the face 103T of the substrate 103 than in directions parallel to the face 103T.

[0076] In the example illustrated in [Fig. 2D], the portions of layers 209 and 211 located directly above the portions of layers 203 and 205, in other words, the portions of layers 209 and 211 not located within the trenches 207, are eliminated. In [Fig. 2D], two disjoint portions of the conductive layer 209 remain within each trench 207, covering opposite sides and extending onto opposite parts of the bottom of the trench 207. Each portion of the conductive layer 209 has a general L-shape, a horizontal portion of which covers at least part of the surface. peri of one of the contact recovery elements 105 and of which a vertical part covers the sides of the parts of the insulating layers 203 and 205 located near the contact recovery element 105.

[0077] Each L-shaped part of the conductive layer 209 corresponds to a heating element of a memory cell 201 of the device 200, for example identical or analogous to the heating elements 107 of the cells 101 of the device 100 previously described in relation to Figures IA and IB.

[0078] Furthermore, in the illustrated example, there remain disjointed portions of the insulating layer 211 located within the L-shaped sections formed by the portions of the layer 209. Each portion of the insulating layer 211 specifically covers the upper face of the horizontal portion of the L formed by the portion of the layer 209, and the face of the vertical portion of the L facing the horizontal portion of the L. In the example shown, the portions of the insulating layer 211 have a flared shape. More precisely, each portion of the insulating layer 211 is wider in the vicinity of the horizontal portion of the L formed by the associated portion of the layer 209 than in the vicinity of the end of the vertical portion of the L opposite the horizontal portion.

[0079] Fig. 2E is a cross-sectional view illustrating a structure obtained after a deposition step, on the side of face 103T of substrate 103, of an electrically and thermally insulating layer 213.

[0080] In the example shown, the insulating layer 213 fills the trenches 207 and covers the upper face of the parts of the layer 205 previously exposed after the anisotropic etching step. In the illustrated example, the insulating layer 213 also covers the free faces of the parts of the layers 209 and 211 remaining after the anisotropic etching step, as well as the parts of the face 103T of the substrate 103 and the parts of the upper faces of the contact elements 105 previously exposed after the anisotropic etching step.

[0081] The insulating layer 213 is, for example, made of the same material as the insulating layer 203, for example silicon carbide (SiC). Alternatively, the layer 213 is made of a different material than the material of the layer 203, for example silicon dioxide (SiO2).

[0082] Fig. 2F and Fig. 2G are cross-sectional views, respectively along plane AA of Fig. 2G and along plane BB of Fig. 2F, illustrating a structure obtained after a step of thinning the insulating layer 213 and then deposition, on the side of face 103T of the substrate 103, of a layer of a phase change material 215 and an electrically conductive layer 217. Plane AA of Fig. 2G is substantially orthogonal to plane BB of Fig. 2F.

[0083] In the example shown, only parts of the insulating layer 213 located inside the trenches 207 remain after the thinning step, the parts of the insulating layer 213 located directly above the portions of the insulating layers 203 and 205 being completely removed. Furthermore, in this example, the thinning of the insulating layer 213 is carried out in such a way as to reduce the thickness of the insulating layer 205 and the height of the portions of layers 209 and 211 remaining after the anisotropic etching step. In the illustrated example, each portion of layer 209 is separated from the opposite portion of layer 213 by a thickness of material in layer 211 greater than or equal to approximately 20 nm.

[0084] In the example shown, the phase-change material layer 215 coats the upper surfaces of the thinned portions of layers 205, 209, 211, and 213. In this example, the conductive layer 217 coats the upper surface of the phase-change material layer 215. The compositions of the phase-change material layer 215 and the conductive layer 217 are, for example, identical or similar to the compositions of regions 111 and 113 of the memory cells 101 of the device 100.

[0085] By way of example, the phase change material layer 215 has a thickness between 20 nm and 100 nm, for example equal to about 50 nm, and the conductive layer 217 has a thickness between 10 nm and 100 nm, for example equal to about 50 nm.

[0086] In the example shown, the contact resumption elements 105 and the parts of the conductive layer 217 form conduction electrodes of the cell 201.

[0087] Fig. 2H and Fig. 21 are cross-sectional views, respectively along plane AA of Fig. 21 and along plane BB of Fig. 2H, illustrating a structure obtained after a step of forming trenches 219 and 221 and then deposition of an encapsulation layer 223 on the side of face 103T of substrate 103. Plane AA of Fig. 21 is substantially orthogonal to plane BB of Fig. 2H.

[0088] In the example shown, trenches 219 and 221 extend vertically in the structure, from the top face of layer 217 to face 103T of substrate 103. As an alternative, trenches 219 may be omitted.

[0089] The trenches 219 are, for example, substantially parallel to each other and extend along a direction substantially orthogonal to the plane of [Fig. 2H]. The trenches 219 laterally separate the memory cells 201 that are part of the same word line of the memory device 200. Furthermore, the trenches 221 are substantially parallel to each other and extend along a direction substantially orthogonal to the plane of [Fig. 21]. The trenches 221 laterally separate the memory cells 201 that are part of the same bit line of the memory device 200.

[0090] As an example, trenches 219 and 221 are formed by photolithography and then engraving.

[0091] At the end of the trench formation step 219 and 221, the heating element and the The phase change material regions of each memory cell 201 are electrically isolated from the heating elements and from the phase change material regions of neighboring memory cells 201.

[0092] In the illustrated example, the encapsulation layer 223 covers the structure comprising the portions of the insulating layers 203, 205, and 213, the portions of the phase-change material layer 215, and the electrically conductive layer 217 of each memory cell 201. More specifically, the encapsulation layer 223 covers all the lateral faces of the portions of the insulating layers 203, 205, and 213, all the lateral faces of the portions of the phase-change material layer 215, and all the lateral faces and the upper face of the portions of the conductive layer 217, as well as the lateral faces of the L-shaped portion of the layer 209 parallel to the plane of [Fig. 2H], not covered by the insulating layers 203, 205, and 213. The encapsulation layer 223 can further extend between the memory cells 201, as in the example illustrated in figures 2H and 21.In this example, layer 223 more specifically covers parts of face 103T of substrate 103 which are not covered by parts of insulating layers 203 and 213, nor by heating element 209.

[0093] Although not illustrated, the memory device 200 may further include selection elements, for example MOS transistors, located on the side of a face of the substrate 103 opposite the face 103T as previously described in relation to Figures IA and IB for the memory device 100. In general, the memory device 200 exhibits, for example, identical or analogous operation to the device 100 of Figures IA and IB.

[0094] One advantage of the memory device 200 in Figures 2H and 21 is that layer 203 provides better thermal insulation for the memory cell 201, resulting in a more uniform heat distribution in the phase-change material of layer 215, particularly compared to the memory cell 101. Consequently, the electrical energy required to heat the phase-change material is lower in the case of memory device 200 than in the case of memory device 100. Advantageously, this allows memory device 200 incorporating cells 201 to have lower energy consumption than memory device 100 incorporating cells 101.

[0095] Furthermore, an advantage of the manufacturing process for the memory device 200 described above in relation to Figures 2A to 21 lies in the fact that it allows the insulating layer 205 to be interposed between the layer 203 and the phase-change material layer 215. The insulating layer 205 advantageously allows the chemical stabilization of the layer 203 during the heating of the phase-change material layer 215 during the programming operations of the memory cell 201. More particularly This also prevents the material of layer 203 from coming into contact with the material of layer 215 in the immediate vicinity of the heating element 209, thus avoiding undesirable chemical reactions between the material of layer 203 and the material of layer 215 during heating. This allows for the use of a wider variety of materials for layer 203, particularly those with a better thermal insulation coefficient, than materials that could be in direct contact with layer 215 in the immediate vicinity of the heating element 209.

[0096] Figures [Fig. 3A] and [Fig. 3B] are cross-sectional views, respectively along plane AA of [Fig. 3B] and along plane BB of [Fig. 3A], schematically and partially illustrating a memory device 300 comprising memory cells 301 based on a phase-change material according to one embodiment. Plane AA of [Fig. 3B] is substantially orthogonal to plane BB of [Fig. 3A].

[0097] Although Figures 3A and 3B illustrate an example in which the stacking formed by layers 203 and 205 has lateral dimensions substantially identical to those of the stacking formed by layers 215 and 217, the stacking formed by layers 215 and 217 may, as an alternative, have lateral dimensions different from those of the stacking formed by layers 203 and 205.

[0098] Device 300 of Figures 3A and 3B includes elements common to Device 200 of Figures 2H and 21. These common elements will not be detailed again below. Device 300 of Figures 3A and 3B differs from Device 200 of Figures 2H and 21 in that Device 300 includes memory cells 301 having several encapsulation layers with different densities.

[0099] In the example shown, the memory cells 301 include an encapsulation layer 303 covering the structure comprising the portions of the insulating layers 203, 205 and 213 of each memory cell 301. More precisely, the encapsulation layer 303 covers all the lateral faces of the portions of the insulating layers 203, 205 and 213, as well as the lateral faces of the L-shaped portion of the layer 209 parallel to the plane of [Fig. 3A], not covered by the insulating layers 203, 205 and 213. The encapsulation layer 303 can further extend between the memory cells 301, as in the example illustrated in Figures 3A and 3B. In this example, layer 303 more specifically covers parts of face 103T of substrate 103 which are not covered by parts of insulating layers 203 and 213, nor by heating element 209.

[0100] According to one embodiment, the encapsulation layer 303 is coated with at least one other encapsulation layer 305 (only one other encapsulation layer 305, in the example shown) of a material having a lower density than that of the layer 303. By way of example, the layer 305 is made of the same material as the layer 303, for example silicon carbide, but has a lower density than the layer 303. Alternatively, the layer 305 is made of a different material than the layer material 303. As an example, encapsulation layers 303 and 305 are respectively made of silicon nitride (SiN) and silicon carbide (SiC).

[0101] In the example shown, a dielectric filling material 307 coats the encapsulation layer 305 and fills the gaps between the memory cells 301. In this example, the filling material 307 is flush with the top face of the insulating layers 205 and 213.

[0102] In the example illustrated in Figures 3A and 3B, the memory cells 301 comprise another encapsulation layer 313 covering the structure comprising the portions of the phase-change material layer 215 and the electrically conductive layer 217 of each memory cell 301. More specifically, the encapsulation layer 223 covers all the lateral faces of the portions of the phase-change material layer 215 and all the lateral faces and the upper face of the portions of the conductive layer 217. The encapsulation layer 313 may further extend between the memory cells 301, as in the example illustrated in Figures 3A and 3B. In this example, the layer 313 more particularly covers the upper faces of the encapsulation layers 303 and 305 and of the filler material 307.

[0103] In the example shown, the encapsulation layer 313 is coated with at least one other encapsulation layer 315 (only one other encapsulation layer 315 in the example shown) of a material having a lower density than that of the layer 313. By way of example, the layer 315 is made of the same material as the layer 313, for example silicon carbide, but has a lower density than the layer 313. Alternatively, the layer 315 is made of a different material than the material of the layer 313. By way of example, the encapsulation layers 313 and 315 are respectively made of the same materials and have respectively the same densities as the encapsulation layers 303 and 305.

[0104] The device 300 is obtained, for example, by a manufacturing process analogous to that of the device 200 described above in relation to Figures 2A to 21. By way of example, the heating elements 209 of the memory cells 301 are individualized after the deposition of the insulating layer 213, then the encapsulation layers 303 and 305 and the filling material 307 are deposited on the structure on the side of the upper face 103T of the substrate 103. The encapsulation layers 303 and 305, the filling material 307 and the insulating layer 213 are then thinned until the insulating layer 205 is reached, the layer 205 also being able to be thinned during this step. The phase change material layer 215 and the conductive layer 217 can then be deposited and structured, for example by photolithography and then etching, so as to individualize the phase change material layer 215 and the conductive layer 217 of the memory cells 301.Finally, the encapsulation layers 313 and 315 can be successively deposited on the structure of the . side of face 103T of substrate 103.

[0105] Although an example embodiment has been described in relation to Figures 3A and 3B in which the encapsulation layers 303 and 305 and the filler material 307 are deposited before the phase change material layer 215, it could alternatively be provided that the encapsulation layers 303 and 305 are deposited after the phase change material layer 215, for example after the deposition of layer 217. In this case, the encapsulation layers 313 and 315 can be omitted, the stacking of the encapsulation layers 303 and 305 then replacing the encapsulation layer 223 of Figures 2H and 21.

[0106] An advantage of the memory device 300 in Figures 3A and 3B lies in the fact that the stacking of the encapsulation layers 303 and 305 provides better thermal insulation of the memory cell 301, and therefore a more uniform heat distribution in the phase-change material of layer 215, particularly compared to the memory cell 101. As a result, the electrical energy required to heat the phase-change material is lower in the case of the memory device 300 than in the case of the memory device 100. Advantageously, this allows the memory device 300 incorporating the cells 301 to have lower energy consumption than the memory device 100 incorporating the cells 101.

[0107] Furthermore, an advantage of the memory device 300 in Figures 3A and 3B is that the higher-density encapsulation layer 303, respectively 313, is interposed between the lower-density layer 305, respectively 315, and the phase-change material layer 215 in the vicinity of the hottest point of layer 215, i.e., near the surface of layer 215 in contact with the heating element 209. The encapsulation layer 303, respectively 313 thus chemically stabilizes layer 305, respectively 315 during the heating of the phase-change material layer 215 during the programming operations of the memory cell 301. More specifically, this prevents undesirable chemical reactions between the material of layer 305, respectively 315 and the material of layer 215 during heating.

[0108] Although stacks consisting each of only two encapsulation layers 303, 313 and 305, 315 have been illustrated, it would be possible, as an alternative: - to coat the encapsulation layer 305, respectively 315, with another encapsulation layer having a lower density than the encapsulation layer 305, respectively 315, for example a silicon carbide layer less dense than the layer 305, respectively 315; - to coat the encapsulation layer 305, respectively 315, with another layer encapsulation having a higher density than encapsulation layer 305, respectively 315, for example a silicon nitride layer or a silicon carbide layer denser than layer 305, respectively 315; - to coat the encapsulation layer 305, respectively 315, with another stack comprising an alternation of encapsulation layers of the type of layers 303 and 305, respectively 313 and 315, and which may terminate with a layer having a density substantially equal to that of the encapsulation layer 303, respectively 313, for example a silicon nitride layer; or - to coat the encapsulation layer 305, respectively 315, with another stack of encapsulation layers, in different materials or in the same material, having densities lower than those of the layer 305, respectively 315, and decreasing as one moves away from the layer 305, respectively 315, for example so as to obtain an encapsulation layer in a single material, for example silicon carbide, having a density gradient, said encapsulation layer being coated with an external layer having a high density, substantially equal to that of the encapsulation layer 303, respectively 313, for example a layer in silicon nitride.

[0109] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, the embodiment of memory device 300 in Figures 3A and 3B can be transposed by those skilled in the art to memory device 100 in Figures 1A and 1B.

[0110] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional specifications given above. In particular, a person skilled in the art is able to choose the deposition and etching techniques to be used to create the different layers and regions of the described devices.

Claims

Demands

1. Phase-change memory cell (200; 300) comprising: - a first layer of a phase-change material (215); - a heating element (209) located under the first layer (215); - a second insulating layer (203) covering a flank of the heating element (209); and - a third insulating layer (205) interposed between the first and second layers (215, 203), of a material having a higher density than the material of the second layer (203).

2. Cell according to claim 1, wherein the second layer (203) is made of silicon carbide or silicon carbonitride.

3. Cell according to claim 1 or 2, wherein the third layer (205) is made of silicon carbide, silicon nitride, silicon carbonitride, germanium nitride, carbon nitride or carbon.

4. Cell according to any one of claims 1 to 3, wherein the third layer (205) is made of the same material as the second layer (203).

5. Cell according to claim 4, wherein the second and third layers (203, 205) are made of silicon carbide.

6. Cell according to claim 1, wherein the second and third layers (203, 403) are made of silicon nitride.

7. Cell according to any one of claims 1 to 6, further comprising a first conduction electrode (105) located below and in contact with a face of the heating element (209) opposite the first layer (215) and a second conduction electrode (217) located on and in contact with a face of the first layer (215) opposite the heating element (209).

8. Cell according to any one of claims 1 to 7, wherein the heating element (209) has an L-shaped form.

9. Cell according to any one of claims 1 to 8, further comprising a stack having a fourth encapsulation layer (303) covering the lateral faces of the first, second and third layers (203, 205, 215) and a fifth encapsulation layer (305) covering the fourth layer (303) and having a lower density than the fourth layer (303).

10. Cell according to claim 9, further comprising a sixth encapsulation layer covering the fifth layer (305) and having a density greater than that of the fifth layer (305).

11. A method for manufacturing a phase-change memory cell (201; 301) comprising the following successive steps: a) depositing, on a substrate (103), a first insulating layer (203) and a second insulating layer (205) covering the first insulating layer (203), the second insulating layer being made of a material having a higher density than the material of the first insulating layer (203); b) forming, in a trench through the first and second insulating layers (203, 205), a heating element (209) one side of which is covered by the first and second insulating layers (203, 205); and c) depositing, on the side of the second insulating layer (205), a third layer of a phase-change material (215).

12. A method according to claim 11, further comprising, between steps b) and c), successive steps of depositing a fourth encapsulation layer (303) covering the lateral faces of the first, second and third layers (203, 205, 215) and a fifth encapsulation layer (305) covering the fourth layer (303) and having a density lower than that of the fourth layer (303).

13. A method according to claim 12, further comprising, after the deposition of the fifth layer (305) and before the deposition of the third layer (215), a step of deposition of a sixth encapsulation layer coating the fifth layer (305) and having a density greater than that of the fifth layer (305).

Images