Logical data processing circuit integrated into a data storage circuit

Abstract

The invention relates to a data storage circuit comprising: a memory cell array; a logic processing circuit configured to perform a logic operation having N binary data operands stored in N input memory cells with N ≥ 2; the second input / output nodes of said input memory cells being connected by a common bit line; the logic processing circuit comprising: a transimpedance amplifier stage configured to provide an analog read signal from the voltage of the common bit line; a comparator for comparing the analog read signal to a first adjustable reference voltage to generate a digital output signal corresponding to the result of the logic operation; a control unit configured to adjust the reference voltage to an amplitude chosen from N distinct predetermined amplitudes, depending on the type of logic operation. Figure for the abstract: Fig. 2a

Description

Title of the invention: Logical data processing circuit integrated in a data storage circuit Scope of application

[0001] The invention generally relates to data storage circuits based on non-volatile memory cells. More particularly, the invention relates to the field of designing computational memory circuits or in-memory computing circuits. The invention relates to a data storage circuit for performing elementary Boolean logic operations within the storage circuit itself. Problem raised

[0002] Generally speaking, a system on a chip comprises memory circuits for storing data and calculation circuits for performing logical and arithmetic operations. Data exchange operations between the memory circuits and the calculation circuits are very energy-intensive and reduce the calculation performance of the system. In this context, emerging non-volatile memory technologies make it possible to produce memory circuits capable of performing both the storage function and the calculation function. In this case, we speak of a "computation circuit in the memory". This makes it possible to avoid data transfers between the storage means and the calculation means, and thus, makes it possible to reduce energy consumption and improve the calculation speed.

[0003] However, the development of “in-memory computing circuits” solutions presents several challenges and constraints such as: - The use of large peripheral circuits to the memories to process the results. This considerably increases the circuit area and the complexity of physical implementation. - Constraints on the accuracy of the calculations performed. More specifically, this problem occurs when executing algorithms requiring parallel calculations.

[0004] For example, in a conventional Von Neumann type architecture, up to 90% of the energy consumption is lost in the transfer between the computing unit and the memory.

[0005] Thus, there is a need to design new architectures for computing circuits in memory, which are less complex and at the same time present a reduction in electrical consumption and an improvement in computing performance in terms of speed and precision.

[0006] Prior art / State of the art restrictions

[0007] The scientific publication entitled “Processing In-Memory Architecture with On-Chip Transfer Leaming Function for Compensating Characteristic Variation, “ by M. Hayashikoshi et al presents a data storage circuit configured to perform logic processing within the memory array itself. The presented solution requires the addition of several additional transistors in each memory cell to connect the memory points together according to a predetermined connection. This has a disadvantage consisting of the considerable increase in the area occupied by the storage circuit. The increase in area generates additional manufacturing and integration costs. Response to the problem and provision of a solution

[0008] To address the technical problems discussed above, the invention proposes a data storage circuit comprising a non-volatile memory array and a data processing circuit configured to read operands from said array, and perform elementary logic operations from the read data without transferring the data outside the storage circuit. It is thus possible for the person skilled in the art to implement more complex algorithms from the elementary logic functions in the memory.

[0009] The operating principle of the data storage circuit according to the invention is compatible with a memory matrix of the ferroelectric type with variable electrical polarization or of the resistive type with variable conductive filament or a mixed resistive and capacitive memory matrix.

[0010] The device according to the invention can be produced with a considerably greater number of memory cells than known solutions. This offers the advantage of multiplying storage and calculation capacities at the same time. This makes it possible to obtain a device compatible with the execution of complex calculation algorithms within the storage circuit itself. In addition, the device is capable of parallelizing a considerable number of data processing operations to obtain better performance.

[0011] The invention further relates to a thin-film structure for producing the memory cells according to the invention. This elementary structure has the advantage of compatibility with the manufacturing techniques of the semiconductor industry. Thus, the device according to the invention has reduced production costs.

[0012] Furthermore, in the specific case of ferroelectric type memories, an additional problem arises: reading the data corresponding to a high logic state (x=1) is destructive of said data. In this context, the processing circuit of data according to the invention makes it possible to rewrite the data read (x=l) in the memory cell after each reading operation so as to carry out a non-destructive reading operation. The rereading operation is fully integrated by the data processing circuit according to the invention. There is no need to recopy the data into buffer memories before reading, nor to transfer said data to external circuits. This makes it possible to reduce the implementation complexity of the storage circuit. This also makes it possible to reduce the energy consumption of the storage circuit by limiting the data exchanges at the input and / or output of the storage circuit. Summary / Claims

[0013] The subject of the invention is a data storage circuit comprising: - a memory cell array such that each memory cell comprises: • an elementary non-volatile storage component having a first electrode and a second electrode, • a first input / output node connected to the second electrode, a second input / output node, a selection node; • and a selection transistor having a gate connected to the selection node and connecting the first electrode to the second input / output node, - a logic processing circuit configured to perform a logic operation having as operands N binary data stored in N input memory cells with N>2; the second input / output nodes of said input memory cells being connected by a common bit line; the logic processing circuit comprising: • a transimpedance amplifier stage configured to provide an analog read signal from the common bit line voltage; • a comparator intended to compare the analog reading signal with a first adjustable reference voltage to generate a digital output signal corresponding to the result of the logic operation; • a control unit configured to adjust the reference voltage to an amplitude chosen from among N distinct predetermined amplitudes, depending on the type of logic operation.

[0014] According to a particular aspect of the invention, the data storage circuit further comprises a sequencer configured to apply: - a write and read control signal on the first input / output node of each of the input memory cells; - a selection signal on the selection node of each cell input memories.

[0015] According to a particular aspect of the invention, the first input / output nodes of said input memory cells are connected by a common source line.

[0016] According to a particular aspect of the invention, the capacitive transimpedance amplifier stage comprises: - an operational amplifier having: a first input connected to the second input / output node of the input memory cells, and a second input for receiving a second reference voltage; and an output for providing said analog read signal; - a feedback impedance mounted between the output and the first input of the operational amplifier.

[0017] According to a particular aspect of the invention, the logic processing circuit further comprises a reset switch mounted between the output and the first input of the operational amplifier.

[0018] According to a particular aspect of the invention, the feedback impedance is a capacitive impedance and in which the elementary storage components of the input memory cells are of the ferroelectric type with variable electrical polarization. Each memory cell can have a first or a second logic state corresponding respectively to different levels of charges stored in the associated elementary storage component.

[0019] According to a particular aspect of the invention, each elementary storage component of the input memory cells has a first predetermined capacity, and in which the feedback impedance is a capacitive element having a second capacity greater than N times said first predetermined capacity.

[0020] According to a particular aspect of the invention, the N predetermined amplitudes are ordered in decreasing order, and the logic processing circuit is configured to perform a logic operation by executing the following steps: i. a reset step for discharging the capacitive element, biasing the first input of the operational amplifier to the second reference voltage and adjusting the first reference voltage to the maximum amplitude among the N predetermined amplitudes; ii. a step of reading a first input memory cell by turning on its selection transistor and applying a read control signal to its first input / output node having an amplitude substantially equal to the second reference voltage so as to generate a transfer of charges from the elementary storage component of the selected memory cell to its associated capacitive element. a step of adjusting the first reference voltage by the control unit in adjusting the amplitude of the first reference voltage to the next order amplitude among the N predetermined amplitudes when the binary data read in the previous step is a high logic state; iii. repeat steps ii) and iii) for the N input memory cells; iv. a step of adjusting the first reference voltage to a predetermined value completed, depending on the type of the logic operation, among the N amplitudes by the control unit to generate a digital output signal corresponding to the result of the logic operation.

[0021] According to a particular aspect of the invention, each elementary storage component of the input memory cells has a first predetermined capacitance, and in which the feedback impedance is achieved by N capacitive elements mounted in parallel, each capacitive element being associated with an input memory cell and having a second capacitance greater than or equal to said first predetermined capacitance.

[0022] According to a particular aspect of the invention, the logic processing circuit is configured to perform a logic operation by executing the following steps:

[0023] i') a reset step to discharge the capacitive elements, polarize the first input of the operational amplifier to the second reference voltage and adjusting the first reference voltage to the maximum amplitude among the N predetermined amplitudes;

[0024] ii') a step of reading a first input memory cell by putting its selection transistor into the on state and by applying a reading control signal to its first input / output node having an amplitude substantially equal to the second reference voltage so as to generate a transfer of charges from the elementary storage component of the selected memory cell to its associated capacitive element.

[0025] iii') repeat step ii') for the N input memory cells;

[0026] iv') a step of adjusting the first reference voltage to a predetermined value, according to the type of the logic operation, among the N amplitudes to generate a digital output signal corresponding to the result of the logic operation.

[0027] According to a particular aspect of the invention, the sequencer circuit is configured to, following the reading of data corresponding to the second logic state in a selected memory cell, apply a control signal, to the first input / output node of said selected memory cell, having an amplitude lower than the second reference voltage and maintain the selection transistor of the selected memory cell in an on state so as to restore, in its elementary storage component, a charge level corresponding to the second logic state.

[0028] According to a particular aspect of the invention, said first logical state corresponds to a uncharged state of an elementary storage component, said sequencer circuit is such that, following the reading of data corresponding to a first logic state, said sequencer circuit is configured to make said selection transistor of the selected memory cell non-conductive before modifying the control signal on the first input / output node to a new value, to maintain the memory cell just read in an uncharged state.

[0029] According to a particular aspect of the invention, the elementary storage component of an input memory cell is of the FeRAM type or of the FTJ ferroelectric tunnel junction type.

[0030] According to a particular aspect of the invention, the feedback impedance is a resistive impedance. The elementary storage components of the input memory cells are of the resistive type with variable conductive filament.

[0031] According to a particular aspect of the invention, the logic processing circuit is configured to perform a logic operation by executing the following steps: a. a reset step for biasing the first input of the operational amplifier to the second reference voltage and adjusting the first reference voltage to the maximum amplitude among the N predetermined amplitudes; b. a step of reading the input memory cells, by turning on their selection transistors in parallel or sequentially, and by applying a positive reading control signal to their first input / output nodes; c. a step of adjusting the first reference voltage to a predetermined value, according to the type of the logic operation, among the N amplitudes, by the control unit, to generate a digital output signal corresponding to the result of the logic operation.

[0032] According to a particular aspect of the invention, during the step of adjusting the first reference voltage according to the type of the logic operation, the control unit is configured to adjust the first reference voltage to the minimum amplitude among the N predetermined amplitudes when the logic operation is of the AND type.

[0033] According to a particular aspect of the invention, during the step of adjusting the first reference voltage according to the type of the logic operation, the control unit is configured to adjust the first reference voltage to the maximum amplitude among the N predetermined amplitudes when the logic operation is of the OR type. Brief description of the drawings

[0034] Other characteristics and advantages of the present invention will appear better on reading the description which follows in relation to the following appended drawings.

[0035] [Fig.1a] illustrates a sectional view of an example of an elementary component of a ferroelectric memory cell with variable electrical polarization compatible with the invention.

[0036] [Fig.lb] illustrates an electrical modeling of a ferroelectric memory cell with variable electrical polarization compatible with the invention.

[0037] [Fig.2a] illustrates an electrical diagram of a first embodiment of the circuit of processing according to the invention connected to N=3 ferroelectric memory cells with variable electrical polarization.

[0038] [Fig.2b] illustrates the operating steps of the processing circuit according to first embodiment of the invention for performing an elementary logical operation.

[0039] [Fig.2c] illustrates the adjustment of the first reference voltage of the comparator of the processing circuit according to the first embodiment of the invention for performing a three-operand AND type logic operation.

[0040] [Fig.2d] illustrates the adjustment of the first reference voltage of the comparator of the processing circuit according to the first embodiment of the invention to carry out a three-operand OR type logic operation.

[0041] [Fig.3a] illustrates an electrical diagram of a second embodiment of the circuit processing according to the invention connected to N=3 ferroelectric memory cells with variable electrical polarization.

[0042] [Fig.3b] illustrates an electrical diagram of a third embodiment of the circuit processing according to the invention connected to N=3 ferroelectric memory cells with variable electrical polarization.

[0043] [Fig.3c] illustrates the operating steps of the processing circuit according to third embodiment of the invention for performing an elementary logical operation.

[0044] [Fig.4a] illustrates an electrical diagram of a fourth embodiment of the circuit processing according to the invention connected to N=3 ferroelectric memory cells with variable electrical polarization.

[0045] [Fig.4b] illustrates the operating steps of the processing circuit according to fourth embodiment of the invention for performing an elementary logical operation.

[0046] [Fig.4c] illustrates a flowchart of the memory cell control signals following when reading a low logic state (x=0) by the processing circuit according to the fourth embodiment of the invention.

[0047] [Fig.4d] illustrates a flowchart of the memory cell control signals following the reading of a high logic state (x=l) by the processing circuit according to the fourth embodiment of the invention.

[0048] [Fig.5] illustrates a sectional view of an example of an elementary component of a resistive memory cell with variable conductive filament compatible with the invention.

[0049] [Fig.6a] illustrates an electrical diagram of a fifth embodiment of the circuit processing according to the invention connected to N=3 resistive memory cells with variable conductive filament.

[0050] [Fig.6b] illustrates the operating steps of the processing circuit according to the fifth embodiment of the invention to carry out an elementary logic operation.

[0051] The invention is compatible with a memory matrix of the ferroelectric type with variable electrical polarization or of the resistive type with variable conductive filament or a mixed resistive and capacitive memory matrix. We will begin by describing the invention in the context of a storage circuit with memories of the ferroelectric type with variable electrical polarization. [Fig.1a] presents a structural example of an elementary NVM component of a ferroelectric memory cell with variable electrical polarization, more precisely a component of the FeRAM type.

[0052] In the example illustrated, the elementary component NVM is composed of the stack of thin layers in the following order: a first layer C1 made of an electrically conductive material forming a first electrode ELI; a second layer C2 made of a dielectric and ferroelectric material and a third layer C3 made of electrically conductive material forming a second electrode EL2. The second layer C2 is referred to in the remainder of the description as the “central layer”.

[0053] The stack of thin layers forms a MIM (acronym for Metal-Insulator-Metal) type structure acting as a capacitive element with a capacitor C. The ferroelectric nature of the central layer C2 induces the following behavior: when a positive electrical voltage is applied to the upper electrode EL2, the polarization of the electric dipoles of the central layer is directed in a so-called "negative" direction. Conversely, when a positive electrical voltage is applied to the lower electrode EL2, the polarization of the electric dipoles is directed in a so-called "positive" direction. The direction of the electrical polarization in the central layer C2 corresponds to a state of equilibrium maintained even in the absence of the electric field induced by the voltage applied to one of the electrodes ELI or EL2, hence the operation in ferroelectric memory.

[0054] Thus, the following convention is chosen as an example: when an NVM memory component is configured to store binary data in the low logic state (x= 0), an electrical write voltage is temporarily applied to the upper electrode EL2 (illustrated by polarization +) so as to obtain a polarization directed in a “negative” direction in the central layer C2. Conversely, when an NVM memory component is configured to store binary data in the high logic state (x= 1), an electrical write voltage is temporarily applied to the lower electrode ELI (illustrated by polarization -) so as to obtain a polarization directed in a “positive” direction in the central layer C2.

[0055] [Fig. 1a] illustrates an elementary NVM component of the FeRAM type compatible with the invention. We emphasize that it is also possible to implement the invention with elementary components of the ferroelectric tunnel junction (FTJ) type and any other type of ferroelectric non-volatile memory technology with variable electrical polarization.

[0056] [Fig.lb] illustrates an electrical diagram of a ferroelectric memory cell CMÿ with variable electrical polarization compatible with the invention. The memory cell comprises CMÿan elementary memory component NVM, a selection transistor Tl, a first input / output node SL, a second input / output node BL and a selection node WL. The memory cell CMy is intended to be integrated in a matrix comprising a plurality of bit lines (bit line in English), a plurality of word lines (word line in English) and a plurality of source lines (source line in English). The first input / output node SL is intended to be connected to a source line associated with the memory cell CMÿ. The second input / output node BL is intended to be connected to a bit line associated with the memory cell CMÿ. The selection node WL is intended to be connected to a word line associated with the memory cell CMÿ.

[0057] Within a memory cell CMÿ, the first input / output node SL is connected to the second electrode EL2 of the elementary memory component NVM. The selection transistor T1 has a gate connected to the selection node WL. The selection transistor T1 connects the first electrode ELI of the elementary memory component NVM to the second input / output node BL. The elementary component NVM behaves like a capacitive element having a variable capacitance depending on the direction of the electrical polarization of the central ferroelectric layer C2. The memory cell CMÿ is thus modeled by a compact 1C1T architecture. This allows direct action on the electrodes ELI and EL2 of the capacitive element when the transistor T1 is in the on state.

[0058] [Fig.2a] illustrates an electrical diagram of a first embodiment of the processing circuit according to the invention connected to N=3 ferroelectric memory cells with variable electrical polarization. The description of a logic operation with N=3 operands is given for illustrative purposes and is not limiting. The invention makes it possible to carry out elementary logic operations for N>=2 operands stored in as many memory cells.

[0059] The storage circuit according to the invention comprises a matrix 2 of memory cells CMÿ as described in figures 1a and 1b and at least one data processing circuit 3. For the sake of simplification, the entire memory matrix 2 is not presented and is limited to the presentation of the input memory cells CMb CM2 and CM3 containing respectively the input binary data xl, x2 and x3.

[0060] The input memory cells CMb CM2 and CM3 share the same bit line forming a second input / output node BL common to said cells. The CMB input memory cells CM2 and CM3 share the same source line forming a first input / output node SL common to said cells. The selection nodes WL1, WL2 and WL3 of each of the CMB input memory cells CM2 and CM3 are distinct.

[0061] The logic processing circuit 3 is connected to the second common input / output node BL of the input memory cells CMh CM2 and CM3 through an activation switch i3. The activation switch i3 makes it possible to isolate the node BL from the logic processing circuit 3 if necessary. The parasitic capacitance CBL seen by the second input / output node BL is shown here in order to facilitate understanding of the invention.

[0062] The logic processing circuit 3 comprises a capacitive trans-impedance amplifier stage 31 (translation of the term into English Capacitive Trans-Impedance Amplifier); a comparator 32, a control unit 34, a sequencer circuit 33 and a reset switch 11.

[0063] Generally, the transimpedance amplifier stage 31 is configured to provide an analog read signal Vsl_ao for each of the operands xl, x2, x3. The comparator 32 is configured to compare the analog read signal Vsl_ao with a first adjustable reference voltage VREF_cmp to generate a digital output signal Vsl_cmp. The control unit 34 is configured to adjust the first reference voltage VREF_cmp to an amplitude chosen from N=3 predetermined amplitudes VREF1, VREF2, VREF3 such that VREF1>VREF2>VREF3.

[0064] According to the first embodiment of the invention, the capacitive transimpedance amplifier stage 31 comprises an operational amplifier AO associated with a capacitive feedback impedance (CCR). The operational amplifier AO has a first input el_ao connected to the second input / output node BL of the input memory cells; a second input e2_ao for receiving a second reference signal VREF0; and an output sl_ao for providing said analog read signal Vsl_ao. The capacitive feedback impedance CCR is mounted between the output sl_ao and the first input el_ao of the operational amplifier. This type of assembly makes it possible to perform a direct reading of the quantity of charges contained in the elementary component NVM and not a reading of a voltage variation on the node BL. This assembly thus makes it possible to perform a reading operation whose precision is independent of the parasitic capacitance CBL.

[0065] In the illustrated embodiment, the capacitive feedback impedance CCR is produced by a single capacitive element Capl. The function of the capacitive feedback impedance CCR is to convert the quantity of charges supplied by the elementary component NVM (similar to a capacitive element) into an electrical voltage applied between the output sl_ao and the input el_ao. Let Q be the quantity of charge supplied

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[0072] by an input memory cell which stores data in a high logic state. In the case where the logic processing circuit 3 is intended to carry out logic operations with N operands, the capacitive element Capl is capable of receiving a quantity of charge greater than or equal to NxQ. In other words, if we assimilate the elementary component NVM of each input memory cell having a capacity equal to C0, the capacity Cl of the capacitive element Capl is greater than or equal to NxCO. The operational amplifier AO has a dual function: - maintain the BL node at a fixed potential equal to the potential of the second reference signal VREF0 when the read activation switch i3 is on. - generate an analog Vsl_ao read signal having an amplitude dependent on the amount of charge transmitted from the elementary component NVM to the capacitive feedback impedance CCR during a cell read operation and during an elementary logic operation calculation step. The comparator 32 has a first input el_cmp connected to the output sl_ao of the operational amplifier; a second input e2_cmp for receiving said first adjustable reference signal VREF_cmp; and an output sl_cmp for providing a digital reading signal Vsl_cmp resulting from the comparison of the analog reading signal Vsl_ao with the first adjustable reference signal VREF_cmp. The control unit 34 is configured to control the amplitude of the first reference voltage VREF_cmp when executing a predetermined elementary logic operation. It is a circuit configured according to a state machine implemented using logic gates. The action of the control unit 34 on the first reference voltage VREF_cmp will be detailed in a later section. Optionally, the processing circuit 3 comprises a first feedback activation switch i2 between the capacitive feedback impedance CCR and the first input el_ao of the operational amplifier. The comparator 32 and the operational amplifier AO are each biased by a supply voltage VDD and the electrical ground GND. The sequencer circuit 33 is configured to control the application: - a VSL write and read control signal on the first SL input / output node of the associated memory cell; - and a selection signal VWL1, VWL2, VWL3 on each selection node WL1, WL2 and WL3 of the input memory cells. The reset switch it is connected between the output sl_ao and the first input el_ao of the operational amplifier. When the reset switch it is in the on state, the capacitive feedback impedance CCR is discharged. This discharge also induces the reset of the analog output signal Vsl_ao to a potential equal to that of the second VREFO reference signal.

[0073] Advantageously, closing the reset switch 11 allows the cumulative charges on the second input / output node BL to be dissipated due to leakage currents. Indeed, for advanced technological nodes, there is an increase in leakage currents coming from the gates of the transistors of the operational amplifier AO connected to the second input / output node BL. These leakage currents cause an accumulation of charges at the level of the parasitic capacitance CB1. This induces potential fluctuations at the level of the second input / output node BL. Hence the specific interest of the reset switch 11 in this case.

[0074] All of the switches i1, i2 and i3 are controlled by control means not shown to simplify the illustration. The switches i1, i2 and i3 are made by CMOS transistors as an example.

[0075] In order to perform an elementary logic operation having as operands the data xl, x2 and x3, the logic processing circuit 3 according to the first embodiment is configured to perform the steps detailed in the flowchart of [Fig.2a]. The switch i3 is closed to establish the connection between the input memory cells and the logic processing circuit 3.

[0076] The first step (i) is a reset step obtained by the following configuration: the reset switch i1, the feedback activation switch i2 are closed. The sequencer 33 generates a selection signal VWL so as to put the selection transistor T1 in a blocking state. The sequencer 33 generates a write and read control signal VSL on the first input / output node SL equal to the electrical ground. In addition, the control unit 34 is configured to adjust the first reference voltage VREF_cmp to the maximum amplitude VREF1. The maximum amplitude is used to detect a minimum amplitude variation of the analog output voltage Vsl_ao when a high logic state is read.

[0077] This step (i) makes it possible to discharge the capacitive feedback impedance CCR and to bias the first input el_ao of the operational amplifier to the second reference signal VREFO. Thus, following the reset, the input / output node BL and the output sl_ao are biased to the second reference signal VREFO (VBL= Vsl_ao= VREFO); the voltage across the capacitive feedback impedance CCR is zero; the reference voltage of the comparator 32 is at VREF1; and the output of the comparator sl_cmp is at a low logic state (Vsl_cmp=0).

[0078] The second step (ii) is a step of reading the first input memory cell CMi. The reset switch i1 is open, the switches i2 and i3 are closed (on state) and only the selection transistor T1 of the first input memory cell CMi is in the on state. The sequencer 33 is configured during this step to apply a selection signal VWL1 making it possible to set theselection transistor Tl in the on state (a rising edge in the case of an NMOS for example). The selection transistors of the second and third input memory cells are maintained in the off state. This results in the creation of a connection path between the elementary component NVM and the capacitive feedback element CCR. In addition, the sequencer 33 is configured to apply a positive read control signal VSL to the first input / output node SL. This results in the application of a quasi-zero potential difference across the terminals of the elementary component NVM. Thus, the combination of the quasi-zero voltage across the terminals of the elementary component NVM and its connection with the capacitive feedback element CCR induces a transfer of the charges previously stored in the elementary component NVM to the capacitive feedback element CCR.The amount of charge transferred depends on the logic state previously stored in the first input memory CMThis induces a variation of the electrical voltage VCCR across the capacitive feedback impedance CCR. The value of the electrical voltage across the capacitive feedback impedance CCR depends on the amount of charge supplied by the elementary component NVM. This induces a variation of the analog output signal Vsl_ao which passes to VREFO-VCCR.

[0079] The amplitude VREF1 is chosen so as to obtain the behavior described below according to the content of a read input memory cell. In the case where x=1 is stored in the elementary component NVM, we obtain Vsl_ao= VREFO-VCCR < VREF1 with VCCR of the order of a few hundred millivolts. We thus obtain Vsl_cmp=VDD corresponding to a high logic level. Conversely, in the case where x=0 is stored in the elementary component NVM, we obtain Vsl_ao= VREFO-VCCR > VREF1 and therefore Vsl_cmp=GND corresponding to a low logic level. In the illustrated case, the comparator 32 is an inverting comparator circuit. Conversely, it is possible to implement a non-inverting comparator circuit according to the design choices of the person skilled in the art.

[0080] It should be emphasized that the charges are transferred entirely to the capacitive feedback impedance CCR during this step. The parasitic capacitance CBL does not receive these charges because it is maintained at a voltage equal to VREF0 thanks to the operational amplifier AO throughout the operation. The processing circuit 3 according to the invention thus makes it possible to carry out a reading operation in the charge domain independent of the value of the parasitic capacitance CBL.

[0081] This results in obtaining the following configuration at the end of step ii): in the case where x=0 is stored in the elementary component NVM, a quasi-zero quantity of charge Qo is accumulated in the capacitive feedback impedance CCR. In the case where x=1 is stored in the elementary component NVM, a quantity of charge Qi» Qo is accumulated in the capacitive feedback impedance CCR.

[0082] The control unit 34 receives the digital output signal Vsl_cmp corresponding to the result of reading the first memory cell at the end of the previous step.

[0083] The third step (iii) consists of a step of adjusting the first reference voltage VREF_cmp by the control unit 33 by adjusting the amplitude of the first reference voltage according to the result of the previous reading step. If the data read is xl=0, the control unit 33 is configured to maintain the first reference voltage VREF_cmp at its current state, namely VREF1 in this case. If the data read is xl=1, the control unit 33 is configured to adjust the amplitude of the first reference voltage VREF_cmp to the next amplitude level among the sequence of N amplitudes VREF1 to VREF3.

[0084] Following this adjustment step, the reading step ii) is repeated for the second input memory cell CM2. We recall that the initial configuration of the processing circuit 3 before the reading step of the second input memory cell CM2 depends on the logic value read in the first input memory cell CMi. Two scenarios are then possible: If xl=0, the first reference voltage VREF_cmp is maintained at VREF1 and the sequence of reading step ii) of the second input memory cell CM2 is identical to that described for the first input memory cell CMi. If x 1=1, the first reference voltage VREF_cmp is biased to VREF2. This configures comparator 32 to switch to a high logic state following the accumulation of a quantity of charges equal to 2xQi (if xl=l and x2=l) but also to generate a low digital output signal following the accumulation of a quantity of charges equal to lxQi (if xl=l and x2=0).

[0085] Then the adjustment step (iii) of the first reference voltage VREF_cmp is repeated. Following the reading of the contents of the second input memory cell CM2, the control unit reacts as follows: if xl=l and x2=l, the first reference voltage VREF_cmp is adjusted to the next amplitude step among the sequence of N amplitudes, namely, VREF_cmp = VREF3. if xl=l and x2=0, the first reference voltage VREF_cmp is maintained at the current amplitude level among the sequence of N amplitudes, namely, VREF_cmp = VREF2. if xl=0 and x2=0, the first reference voltage VREF_cmp is maintained at the current amplitude level among the sequence of N amplitudes, namely, VREF_cmp = VREF1.

[0086] Similarly, following this second iteration of the adjustment step, the reading step ii) is repeated for the third input memory cell CM3.

[0087] From an analog point of view, each logical combination of the data corresponds to a cumulative amount of charge in the capacitive feedback impedance CCR. At the end of the N iterations of steps ii) and iii), the capacitive element Capl stores an amount of charge equal to kxQiwith k the number of input memory cells containing logic data at a high state “1”. The tables in Figures 2c and 2d illustrate the state of charge of the capacitive feedback impedance following three iterations of the reading (ii) and adjustment (iii) steps for the three input memory cells.

[0088] The next step consists of a step of adjusting the first reference voltage VREF_cmp according to the type of the logic operation to generate a digital output signal Vsl_cmp corresponding to the result of the logic operation.

[0089] For example, if the logic operation to be performed is of the AND type, this amounts to generating a digital output signal Vsl_cmp=l only when xl=x2=x3=l. This corresponds to the detection of the accumulation of a charge quantity of 3xQi in the capacitive feedback impedance CCR at the end of three successive reading operations. Thus, to perform an AND type logic operation, the control unit 34 is configured to bias the first reference voltage VREF_cmp to the amplitude corresponding to the minimum level VREF3. Thus, the output of the comparator 32 switches to a high logic state only when Vsl_ao= VREFO-VCCR < VREF3.

[0090] The amplitude of the reference voltage VREF3 is the minimum amplitude among VREF1 to VREF3. The minimum amplitude VREF3 is used to detect a maximum amplitude variation of the analog output voltage Vsl_ao. Indeed, the more cumulative charges there are in the capacitive feedback impedance CCR, the lower the voltage Vsl_ao = VREFO-VCCR. Therefore the minimum amplitude VREF3 is the amplitude of the reference voltage for which the comparator 32 is able to detect the variation of the amplitude of the analog output voltage Vsl_ao.

[0091] Alternatively, if the logic operation to be performed is of the OR type, this amounts to generating a digital output signal Vsl_cmp=0 only when xl=x2=x3=0. This corresponds to the detection of the accumulation of a quasi-zero charge quantity Qosi in the capacitive feedback impedance CCR at the end of three successive reading operations. Thus, to perform an OR type logic operation, the control unit 34 is configured to bias the first reference voltage VREF_cmp to the amplitude corresponding to the minimum level VREF1. Thus, the output of the comparator 32 switches to a low logic state only when Vsl_ao= VREFO-VCCR < VREF1.

[0092] We have thus carried out elementary logic operations with N operands stored in memory cells of the memory matrix in the storage circuit itself.

[0093] Advantageously, it is possible to carry out more complex logic operations (of the exclusive OR type for example) by using the same operating principle based on the accumulation of charges in combination with the control of the threshold voltage of the comparator 32.

[0094] [Fig.3a] illustrates an electrical diagram of a second embodiment of the processing circuit 3 according to the invention connected to N=3 ferroelectric memory cells with variable electrical polarization. Structurally, the second embodiment is distinguished from the first embodiment by the realization of the capacitive feedback impedance CCR. Indeed, in the illustrated case, the capacitive feedback impedance CCR is realized by a plurality of capacitive elements Capl, Cap2 and Cap3 connected in parallel between the output sl_ao and the first input el_ao of the operational amplifier AO.

[0095] For each capacitive element among Capl, Cap2 and Cap3, the processing circuit 3 further comprises a feedback activation switch (i2, i2' and i2” here implemented by transistors) between the associated capacitive feedback element and the first input el_ao of the operational amplifier. Thus, during a read operation, each capacitive feedback element is dedicated to receiving the charges supplied by an associated input memory cell. Let Q be the quantity of charge supplied by an input memory cell that stores data in a high logic state. The first capacitive element Capl is capable of receiving a quantity of charge less than or equal to IxQ; the second capacitive element Cap2 is capable of receiving a quantity of charge less than or equal to 2xQ; and the third capacitive element Cap3 is capable of receiving a quantity of charge less than or equal to 3xQ.

[0096] Thus, when the processing circuit 3 is configured to perform an elementary logic operation implementing 3 operands, the feedback activation switch i' ' associated with the third capacitive element Cap3 is closed and the other two feedback activation switches i and i' are open. The electrical connection is established between the third capacitive element Cap3 and the second input / output node BL common to the input memory cells.

[0097] Similarly, if the number of operands is equal to 2, the connection is established between the second capacitive element Cap2 and the second input / output node BL common to the input memory cells.

[0098] In the case where the processing circuit 3 is configured to perform only an operation of reading data from an input memory cell, the first capacitive element Capl is sufficient. Thus, the processing circuit 3 is configured to select the first capacitive element Capl to receive the charges provided by the input memory cell to be read.

[0099] Thus, this embodiment allows the adaptation of the value of the capacity of the capacitive feedback impedance to the number of operands of the elementary logic operation to be performed.

[0100] [Fig.3b] illustrates an electrical diagram of a third embodiment of the processing circuit 3 according to the invention connected to N=3 ferroelectric memory cells with variable electrical polarization. The third embodiment is distinguished from the second embodiment by the dimensioning of the capacitive elements Capl, Cap2 and Cap3. Indeed, each capacitive element among Capl, Cap2 and Cap3 has a capacitance greater than or equal to that of the elementary component of an input memory cell. Each capacitive element among Capl, Cap2 and Cap3 is capable of receiving a quantity of charge greater than or equal to IxQ. The first capacitive element Capl is intended for receiving the charges supplied by the first input memory cell CMi when it is read. The second capacitive element Cap2 is intended for receiving the charges supplied by the second input memory cell CM2 when it is read.The third capacitive element Cap3 is intended for receiving the charges supplied by the third input memory cell CM3 when it is read.

[0101] [Fig.3c] illustrates the operating steps of the processing circuit according to a third embodiment of the invention for carrying out an elementary logic operation.

[0102] The first step (i') is a reset step identical to the reset step of [Fig.2a].

[0103] The next step (ii') consists of reading the first input memory cell CMi while selecting only the first capacitive element Capl. The reading mechanism remains the same compared to what was detailed previously. This results in the accumulation of the charges provided by the first input memory cell CM1 in the first capacitive element Capl.

[0104] The next step consists of reading the second input memory cell CM2 while selecting only the second capacitive element Cap2. The reading mechanism remains the same compared to what was detailed previously. This results in the accumulation of the charges provided by the second input memory cell CM2 in the second capacitive element Cap2.

[0105] The next step consists of reading the third input memory cell CM3 while selecting only the third capacitive element Cap3. The reading mechanism remains the same compared to what was detailed previously. This results in the accumulation of the charges provided by the third input memory cell CM3 in the third capacitive element Cap3.

[0106] The advantage of this embodiment is that there is no need to adjust the amplitude of the first adjustable reference voltage VREF_cmp according to the reading result. This is possible thanks to the distribution of charges resulting from the reading operations successive on separate capacitive elements.

[0107] The last step iv') consists of a step of adjusting the first reference voltage VREF_cmp according to the type of the logic operation in the same manner described previously. During this step, all the switches i2, i2' and i2” are in the on state to evaluate all the quantities of charges distributed on the three capacitive elements.

[0108] In the following section, we will describe an embodiment of the invention making it possible to solve the problem of destructive reading of ferroelectric type memories with variable electrical polarization. Indeed, during a read access, the elementary component NVM receives an electrical reading voltage on the upper electrode so as to rewrite it to a low logic state (x=0). We then observe the dynamics of the transition following the application of the reading voltage. If the electric dipoles of the central layer are previously polarized with an orientation in a “positive” direction (x=1), a relatively large quantity of electrical charges will be emitted by the device during the transition. Conversely, if the electric dipoles of the central layer are previously polarized with an orientation in a “negative” direction (x=0), the quantity of charges delivered during the transition is lower.As a result, the reading procedure consists of estimating the quantity of charges emitted during a polarization to a low logic state (x=0) and therefore erases the logic value of the stored data.

[0109] In this context, a problem to be solved is the destruction of the logical content of a ferroelectric memory cell with variable electrical polarization following a read operation.

[0110] [Fig.4a] illustrates an electrical diagram of a fourth embodiment of the processing circuit 3 making it possible to solve the problem of destructive reading.

[0111] In this embodiment, the sequencer 33 receives the digital output signal Vsl_cmp so as to set up a feedback loop allowing a rewrite operation to be carried out by the reading circuit itself. This makes it possible to overcome the problems of destructive reading without complicating the circuit. In addition, the action of the sequencer makes it possible to carry out the rewrite without transferring the data to external buffer memories.

[0112] [Fig.4b] illustrates the operating steps of the processing circuit 3 according to the fourth embodiment. The illustrated method differs from that described in [Fig.2b] by the addition of a rewriting step after each reading operation according to the logical result of said operation. We recall that the rewriting operation is only required in the case where the data read corresponds to a high logic state. We will describe the progress of a rewriting step applied to an input memory cell.

[0113] [Fig.4c] illustrates a flowchart of the control signals of the input memory cell following the reading of a low logic state (x=0) by the processing circuit 3. In this case, the sequencer 33 receives the digital output signal Vsl_cmp=0. In response to this result, the sequencer 33 is configured to emit a falling edge simultaneously on the SL and WL nodes of the memory cell being read. This makes it possible to isolate the elementary component NVM from the BL node and to maintain the logic state of said elementary component at x=0 obtained following the reading operation, (by pumping the charges during reading).

[0114] Alternatively, [Fig.4d] illustrates a flowchart of the control signals of the input memory cell following the reading of a high logic state (x=l) by the processing circuit 3. In this case, the sequencer 33 receives the digital read signal Vsl_cmp=VDD (x=l). In response to this result, the sequencer 33 is configured to apply a falling edge to the input / output node SL while maintaining the selection node WL in a high state. This results in the following combination: - On the one hand, the first input output node SL is at a low potential (preferably zero) under the action of the sequencer 33; - On the other hand, the second input / output node BL is at a high electrical potential equal to VREFO under the action of the operational amplifier AO; the transistor Tl being in the on state;

[0115] This corresponds to the application of a write voltage SET on the elementary component NVM as explained in [Fig. 1a]. Thus, a rewriting operation of the logic value x=1a was carried out via the action of the sequencer 33 making it possible to carry out a rewriting operation by the reading circuit itself. This makes it possible to overcome the problems of destructive reading without complicating the circuit.

[0116] We will describe the invention in the context of a storage circuit with variable conductive filament resistive type memories. [Fig.5] shows a structural example of an elementary NVM component of a variable conductive filament resistive memory cell compatible with the invention.

[0117] Variable conductive filament resistive operation requires the formation of a conductive filament F through at least a portion of the electrically insulating central layer C2.

[0118] Initially, the elementary component NVM is a MIM (metal, insulator, metal) type structure having an infinite resistance between the two electrodes ELI and EL2. In order to reconfigure the elementary component NVM according to a resistive memory operation, it is necessary to form the filament F starting from the upper electrode EL2 through at least a part of the volume of the central layer C2. The formation of the filament makes it possible to obtain a variable resistance by modulating the length 1 of the conductive filament formed. To form the filament, an electrical voltage of formation on the upper electrode EL2. The formation voltage has a sufficiently high amplitude and / or duration to cause the generation of oxygen vacancies in the central layer C2. Indeed, the applied formation voltage must exceed a predetermined value so as to tear oxygen ions from the crystal lattice of the central metal oxide layer which will migrate towards the upper electrode EL2 and thus form a conductive filament F through the central layer made up of oxygen vacancies.

[0119] Once the conductive filament F is formed, the behavior of a resistive element with a variable resistance R is obtained depending on the length 1 of the conductive filament F. When a positive electrical voltage is applied to the lower electrode ELI, the reverse reaction occurs and oxygen ions will fill part of the oxygen vacancies forming the conductive filament. This results in a reduction in the length of the conductive filament. Thus, the resistance of the resistive element increases. This is referred to as a high resistive state and a RESET type write operation. Conversely, when a positive electrical voltage is applied to the upper electrode EL2, the length of the conductive filament F increases by the same mechanism described for the wire formation operation. Thus, the resistance of the resistive element decreases. This is referred to as a low resistive state and a SET type write operation.

[0120] The following convention is chosen as an example: when an NVM memory component is configured to store binary data in the high logic state (x= 1), a write electrical voltage is temporarily applied to the upper electrode EL2 (SET operation) so as to obtain a low resistive state. Conversely, when an NVM memory component is configured to store binary data in the low logic state (x= 0), a write electrical voltage is temporarily applied to the lower electrode ELI (RESET operation) so as to obtain a high resistive state.

[0121] Reading a resistive NVM memory component involves estimating the resistance between the top electrode and the bottom electrode and comparing it to a threshold value to determine whether the resistive state is a high or low state.

[0122] [Fig.6a] illustrates an electrical diagram of a fifth embodiment of the processing circuit 3 connected to N=3 resistive memory cells with variable conductive filament. In this case, the feedback impedance CCR is achieved by at least one feedback resistor RI connected in parallel between the output sl_ao and the first input el_ao of the operational amplifier AO. Advantageously, the reading circuit 3 comprises a second feedback activation switch i4 between the resistive feedback impedance RCR and the first input el_ao of the operational amplifier A0.

[0123] [Fig.6b] illustrates the operating steps of the processing circuit 3 according to the fifth embodiment of the invention for performing an elementary logical operation.

[0124] The first reset step a) remains unchanged compared to the other embodiments.

[0125] The second step b) consists of reading the input memory cells CMi, CM2> CM3. The selection transistors T1 of the input memory cells are turned on in parallel or sequentially. Then, the sequencer 33 is configured to apply a positive read control signal VSL to their first input / output nodes SL. The amplitude of the positive read control signal VSL is greater than that of the second reference signal VREFO (potential of the second node BL). Each of the resistive elementary components NVM is then subjected to a non-zero potential difference. This results in the circulation of an electric current II to 13 through the resistor NVM. This induces an addition of the currents Itot=I 1+12+13 in the feedback resistor RL. The intensity of the total current Itot depends on the number of input memory cells which store data in a high logic state (x=1).This induces a variation in the voltage VRCR across the resistive feedback impedance RCR which depends on the current intensity Itot. This results in a variation in the electrical potential at the output node sl_ao of the operational amplifier AO.

[0126] The last step c) consists of adjusting the amplitude of the first reference voltage VREF_cmp according to the type of the logic operation to generate a digital output signal Vsl_cmp corresponding to the result of the logic operation. This step remains unchanged compared to the other embodiments of the invention described previously.

Claims

Claims

1. A data storage circuit (1) comprising: a matrix (2) of memory cells (CMy) such that each memory cell (CMy) comprises: • a non-volatile elementary storage component (NVM) having a first electrode (ELI) and a second electrode (EL2), • a first input / output node (SL) connected to the second electrode (EL2), a second input / output node (BL), a selection node (WL); • and a selection transistor (Tl) having a gate connected to the selection node (WL) and connecting the first electrode (ELI) to the second input / output node (BL), a logic processing circuit (3) configured to perform a logic operation having as operands N binary data (xl, x2, x3) stored in N input memory cells (CMi, CM2j CM3) with N>2; the second input / output nodes (BL) of said input memory cells (CMi CM2, CM3) being connected by a common bit line; the logic processing circuit (3) comprising: • a transimpedance amplifier stage (31) configured to provide an analog read signal (Vsl_ao) from the voltage of the common bit line (BL); the capacitive transimpedance amplifier stage (31) comprising: • an operational amplifier (AO) having: a first input (el_ao) connected to the second input / output node (BL) of the input memory cells, and a second input (e2_ao) for receiving a second reference voltage (VREFO); and an output (sl_ao) for providing said analog read signal (Vsl_ao); • a feedback impedance (CCR) mounted between the output (sl_ao) and the first input (el_ao) of the operational amplifier; • a comparator (32) intended to compare the analog reading signal (Vsl_ao) with a first adjustable reference voltage (VREF_cmp) to generate a digital output signal (Vsl_cmp) corresponding to the result of the logic operation; • a control unit (34) configured to adjust the reference voltage (VREF_cmp) to an amplitude chosen from among N distinct predetermined amplitudes (VREF1, VREF2, VREF3), according to the type of the logic operation; the feedback impedance (CCR) being a capacitive impedance and the elementary storage components (NVM) of the input memory cells (CMi CM2, CM3) being of the ferroelectric type with variable electrical polarization; or the feedback impedance (CCR) being a resistive impedance and the elementary storage components (NVM) of the input memory cells (CMi CM2, CM3) being of the resistive type with variable conductive filament.

2. Data storage circuit (1) according to claim 1 further comprising a sequencer (33) configured to apply: - a write and read control signal (VSL) to the first input / output node (SL) of each of the input memory cells (CMi, CM2, CM3); - a selection signal (VWL1, VWL2, VWL3) to the selection node (WL) of each of the input memory cells (CM! CM2j CM3).

3. Data storage circuit (1) according to any one of claims 1 or 2 wherein the first input / output nodes (SL) of said input memory cells (CMi CM2> CM3) are connected by a common source line.

4. Data storage circuit (1) according to any one of claims 1 to 3 wherein the logic processing circuit (3) further comprises a reset switch (il) connected between the output (sl_ao) and the first input (el_ao) of the operational amplifier.

5. Data storage circuit (1) according to any one of claims 1 to 4 wherein: when the feedback impedance (CCR) is a capacitive impedance and in which the elementary storage components (NVM) of the input memory cells (CMi CM2, CM3) are of the ferroelectric type with variable electrical polarization, each memory cell can have a first (“0”) or a second (“1”) logic state corresponding respectively to different levels of charges stored in the associated elementary storage component (NVM).

6. Data storage circuit (1) according to claim 5 wherein each elementary storage component (NVM) of the input memory cells (CMi CM2, CM3) has a first predetermined capacitance, and wherein the feedback impedance (CCR) is a capacitive element (Cl) having a second capacitance greater than N times said first predetermined capacitance.

7. A data storage circuit (1) according to claim 6 wherein the N predetermined amplitudes (VREF1, VREF2, VREF3) are ordered in descending order, and wherein the logic processing circuit (3) is configured to perform a logic operation by executing the following steps: i. a reset step for discharging the capacitive element (Cl), biasing the first input (el_ao) of the operational amplifier to the second reference voltage (VREFO) and adjusting the first reference voltage (VREF_cmp) to the maximum amplitude among the N predetermined amplitudes (VREF1); ii.a step of reading a first input memory cell (CMi) by putting its selection transistor (Tl) into the on state and by applying a read control signal (VSL) to its first input / output node (SL) having an amplitude substantially equal to the second reference voltage (VREFO) so as to generate a transfer of charges from the elementary storage component (NVM) of the selected memory cell to its associated capacitive element (Cl). a step of adjusting the first reference voltage (VREF_cmp) by the control unit (33) by adjusting the amplitude of the first reference voltage to the amplitude. of the next order (VREF2) among the N predetermined amplitudes when the binary data read in the previous step is a high logic state; iii. repeating steps ii) and iii) for the N input memory cells (CM2> CM3); iv. a step of adjusting the first reference voltage (VREF_cmp) to a predetermined value, according to the type of the logic operation, among the N amplitudes by the control unit (33) to generate a digital output signal (Vsl_cmp) corresponding to the result of the logic operation.

8. Data storage circuit (1) according to claim 5 wherein each elementary storage component (NVM) of the input memory cells (CMi CM2, CM3) has a first predetermined capacitance, and wherein the feedback impedance (CCR) is produced by N capacitive elements (Cl, C2, C3) mounted in parallel, each capacitive element (Cl, C2, C3) being associated with an input memory cell (CMi CM2, CM3) and having a second capacitance greater than or equal to said first predetermined capacitance.

9. Data storage circuit (1) according to claim 8 wherein the logic processing circuit (3) is configured to perform a logic operation by executing the following steps: i') a reset step for discharging the capacitive elements (Cl, C2, C3), biasing the first input (el_ao) of the operational amplifier to the second reference voltage (VREFO) and adjusting the first reference voltage (VREF1, VREF2, VREF3) to the maximum amplitude among the N predetermined amplitudes;ii') a step of reading a first input memory cell (CMi) by putting its selection transistor (Tl) into the on state and by applying a read control signal (VSL) to its first input / output node (SL) having an amplitude substantially equal to the second reference voltage (VREFO) so as to generate a transfer of charges from the elementary storage component (NVM) of the selected memory cell to its associated capacitive element (Cl), iii') repeating step ii') for the N input memory cells (CM2> CM 3); iv') a step of adjusting the first reference voltage; (VREF_cmp) to a predetermined value, depending on the type of the logic operation, among the N amplitudes to generate a digital output signal (Vsl_cmp) corresponding to the result of the logic operation.

10. Data storage circuit (1) according to any one of claims 5 to 9 wherein the sequencer circuit (33) is configured to, following the reading of data corresponding to the second logic state (“1”) in a selected memory cell, apply a control signal (VSL), to the first input / output node (SL) of said selected memory cell, having an amplitude lower than the second reference voltage (VREFO) and maintain the selection transistor (Tl) of the selected memory cell in an on state so as to reset, in its elementary storage component (NVM), a charge level corresponding to the second logic state (“1”).

11. Data storage circuit (1) according to any one of claims 2 to 10, wherein said first logic state (“0”) corresponds to an unloaded state of an elementary storage component (NVM), and wherein said sequencer circuit (33) is such that, following the reading of data corresponding to a first logic state (“0”), said sequencer circuit (33) is configured to make said selection transistor (Tl) of the selected memory cell non-conductive before modifying the control signal (VSL) on the first input / output node (SL) to a new value, to maintain the memory cell just read in an unloaded state.

12. Data storage circuit (1) according to any one of claims 5 to 11 in which the elementary storage component (NVM) of an input memory cell (CMiCM2, CM3) is of the FeRAM type or of the ferroelectric tunnel junction FTJ type.

13. Data storage circuit (1) according to any one of claims 1 to 4 wherein when the feedback impedance (CCR) is a resistive impedance and in which the elementary storage components (NVM) of the input memory cells (CMi CM2, CM3) are of the variable conductive filament resistive type, the logic processing circuit (3) is configured to perform a logic operation by executing the following steps: a. a reset step for biasing the first input (el_ao) of the operational amplifier to the second reference voltage (VREFO) and adjusting the first reference voltage (VREF_cmp) to the maximum amplitude (VREF1) among the N predetermined amplitudes; b. a step of reading the input memory cells (CMi, CM2> CM3), by turning on their selection transistors (Tl) in parallel or sequentially, and by applying a positive read control signal (VSL) to their first input / output nodes (SL); c. a step of adjusting the first reference voltage (VREF_cmp) to a predetermined value, according to the type of the logic operation, among the N amplitudes, by the control unit (33), to generate a digital output signal (Vsl_cmp) corresponding to the result of the logic operation.

14. Data storage circuit (1) according to any one of claims 7 or 9 or 13 wherein during the step of adjusting the first reference voltage (VREF_cmp) according to the type of the logic operation, the control unit (33) is configured to adjust the first reference voltage (VREF_cmp) to the minimum amplitude (VREF3) among the N predetermined amplitudes when the logic operation is of the AND type.

15. Data storage circuit (1) according to any one of claims 7 or 9 or 13 wherein during the step of adjusting the first reference voltage (VREF_cmp) according to the type of the logic operation, the control unit (33) is configured to adjust the first reference voltage (VREF_cmp) to the maximum amplitude (VREF1) among the N predetermined amplitudes when the logic operation is of the OR type.

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