Method for manufacturing an electronic device
A novel manufacturing process for semiconductor devices stabilizes semiconductor layers on diverse substrates by converting van der Waals bonds to covalent bonds, reducing costs and improving mechanical resistance and crystalline texture.
Patent Information
- Application Number
- FR2022013810
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-12-19
- Publication Date
- 2026-02-20
- Estimated Expiration
- 2042-12-19
AI Technical Summary
Current manufacturing processes for electronic devices based on semiconductor materials, such as aluminum nitride and gallium nitride, are costly and complex, with buffer layers prone to breakage during cooling steps.
A manufacturing process involving the formation of a lamellar dichalcogenide or chalcogenide layer on a substrate, followed by a thermo-chemical treatment to convert van der Waals bonds into covalent bonds, and subsequent deposition of semiconductor layers, eliminating the need for costly buffer layers and single-crystal silicon substrates.
This process reduces manufacturing costs and improves mechanical resistance by stabilizing semiconductor layers on various substrates, enhancing crystalline texture and eliminating delamination issues.
Smart Images
Figure 00000014_0000 
Figure 00000014_0001 
Figure 00000014_0002
Abstract
Description
Title of the invention: Method for manufacturing an electronic device. Technical field.
[0001] This description relates generally to electronic devices. More specifically, this description relates to the manufacturing processes of electronic devices based on semiconductor materials. Previous technique
[0002] Electronic devices comprising a region made of a semiconductor material, for example an IILN material, i.e., a nitride of an element in the thirteenth column of the periodic table, have been proposed. In particular, aluminum nitride and gallium nitride are direct bandgap IILN semiconductor materials used in various applications such as power electronics, radio frequency communications, lighting, etc.
[0003] However, the implementation of current processes for manufacturing electronic devices based on semiconductor materials proves to be costly and complex. These processes, for example, employ buffer layers to adapt the lattice parameters between a substrate, for example silicon, and the semiconductor material layer(s). The buffer layers are subject to breakage problems during cooling steps following the formation of the semiconductor material layer(s). Summary of the invention
[0004] There is a need to improve existing manufacturing processes for electronic devices based on semiconductor materials.
[0005] To this end, one embodiment provides a process comprising the following successive steps: a) form, on one face of a support substrate, a first layer of a material chosen from a lamellar dichalcogenide or a lamellar chalcogenide comprising a stack of sheets; b) to form, by physical vapor deposition on said face of the support substrate, a second layer of a first semiconductor material IIIN coating the first layer; and c) perform a thermo-chemical treatment of the first layer leading, in the first layer, to a conversion of van der Waals bonds between the sheets of the first layer into covalent bonds.
[0006] According to one embodiment, in step c), the thermo-chemical treatment is a annealing carried out under a reducing atmosphere.
[0007] According to one embodiment, in step c), the thermo-chemical treatment is carried out under a nitrogen atmosphere, preferably under an ammonia or dinitrogen atmosphere.
[0008] According to one embodiment, in step c), the thermo-chemical treatment is carried out under a dihydrogen atmosphere.
[0009] According to one embodiment, in step c), the thermo-chemical treatment further leads to a conversion of van der Waals bonds into covalent bonds between the first layer and the support substrate.
[0010] According to one embodiment, the first semiconductor material is aluminum nitride.
[0011] According to one embodiment, the first III-N semiconductor material is doped, preferably with scandium atoms.
[0012] According to one embodiment, the process further comprises, after step c), a step d) of forming a third layer in a second semiconductor material coating the second layer, the third layer having a thickness greater than that of the second layer.
[0013] According to one embodiment, the second semiconductor material is a III-V semiconductor material, preferably III-N.
[0014] According to one embodiment, the second semiconductor material is silicon carbide.
[0015] According to one embodiment, the second semiconductor material is identical to the first semiconductor material.
[0016] According to one embodiment, the third layer is doped.
[0017] According to one embodiment, the process further comprises, after step d), a step e) of forming at least a fourth layer covering the third layer.
[0018] According to one embodiment, in step c), the thermo-chemical treatment is accompanied by a plasma treatment.
[0019] According to one embodiment, the first layer is made of transition metal dichalcogenide, preferably molybdenum disulfide or tungsten disulfide.
[0020] According to one embodiment, in step c), the thermo-chemical treatment is carried out at a temperature between 300 and 1,500 °C, preferably between 800 and 1,000 °C.
[0021] According to one embodiment, the second layer has a thickness between 0.15 and 50 nm, preferably between 1 and 6 nm. Brief description of the drawings
[0022] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example. relation to the attached figures, among which [Fig.1A], [Fig.1B], [Fig.1C] and [Fig.1D] are schematic and partial cross-sectional views, illustrating successive stages of an example of a manufacturing process for an electronic device based on a semiconductor material according to an embodiment. Description of the implementation methods
[0023] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.
[0024] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the fabrication steps of the electronic device following the fabrication of a layer of semiconductor material, as well as the various applications likely to benefit from such a device, have not been detailed, since the described embodiments are compatible with the usual fabrication steps of an electronic device from a layer of semiconductor material and with the usual applications using such devices.
[0025] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.
[0026] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.
[0027] Unless otherwise specified, the expressions "approximately", "about", "substantially", and "in the order of" mean within 11%, preferably within 5%.
[0028] Figs.1A, 1B, 1C and 1D are schematic and partial cross-sectional views illustrating successive steps of an example of a manufacturing process for an electronic device based on a semiconductor material according to an embodiment.
[0029] By way of example, the steps described below in relation to Figures IA to 1D are part of a method for making a SAW (Surface Acoustic Wave) or BAW (Surface Acoustic Wave) type radio frequency filter. (English "Bulk Acoustic Wave"), a HEMT (High Electron Mobility Transistor) power transistor, a laser or LED (Light-Emitting Diode) device, a beam oscillator sensor, a thermal sensor, etc., or, more generally, any type of manufacturing process for an electronic device comprising at least one region made of an inorganic semiconductor material, for example, a III-N semiconductor material. As an alternative, the steps below can be applied to the formation of a coating layer, for example, a tribological layer, for example, based on aluminum nitride.
[0030] Fig. 1A illustrates more particularly a structure obtained at the end of a formation step, on a face of a support substrate 11 (the upper face of the support substrate 11, in the orientation of Fig. 1A)), of a layer 13 in a transition metal dichalcogenide (“Transition Metal Dichalcogenide” - TMD, in English).
[0031] The support substrate 11 may be made of any material, for example silicon, sapphire, silicon carbide, silicon nitride, alumina, aluminum nitride, borosilicate glass, etc. The support substrate 11 is, for example, a single-crystal silicon wafer having a diameter between 50 and 300 mm, for example approximately 200 mm, the upper face of which is oriented (100). Alternatively, the support substrate 11 is of the SOI (Silicon On Insulator) type and comprises a silicon layer coated with a silicon dioxide layer, which is itself coated with another silicon layer. Furthermore, the support substrate 11 may include active elements not shown in [Fig. 1A], such as transistors, or have a reflective structure, for example, of the Bragg mirror type.
[0032] Depending on the intended application, the support substrate 11 may be unintentionally doped or may, alternatively, have a level of doping giving it, for example, specific thermal and / or electrical properties.
[0033] Furthermore, although [Fig. 1A] illustrates an example in which the support substrate 11 has substantially flat and parallel lower and upper faces, this example is not limiting, as the lower and upper faces of the substrate 11 may, alternatively, each have any shape. By way of example, the upper face of the support substrate 11 may be non-planar and may, for example, have a relief suitable for the subsequent fabrication of vertical light-emitting diodes, for example, a "stepped" shape comprising asperities and protruding parts.
[0034] In the example illustrated in [Fig. 1A], the layer 13 in metal dichalcogenide oftransition exhibits a lamellar or layered structure comprising, from the upper face of the support substrate 11, a vertical stacking of several sheets 15 substantially parallel to the upper face of the support substrate 11 and linked together by van der Waals bonds. Each of the sheets 15, also called two-dimensional layers, 2D layers, or monolayers, exhibits, for example, a hexagonal arrangement of the transition metal atoms to which the chalcogen atoms are bonded by covalent bonds. In the orientation of [Fig. 1A], the lower sheet 15 of the stack, i.e., the sheet 15 closest to the support substrate 11, is, for example, further linked to the upper face of the support substrate 11 by van der Waals bonds and / or by covalent bonds. Although four sheets 15 have been symbolized in [Fig.[lA], this example is not limiting and layer 13 can contain any number of sheets 15, for example between one and fifty.
[0035] The transition metal dichalcogenide has a chemical formula of the type MX2, where M represents the transition metal and X the chalcogen. The transition metal M is, for example, chosen from molybdenum, tungsten, vanadium, niobium, tantalum, titanium, zirconium, hafnium, and alloys of these metals. The chalcogen X is, for example, chosen from sulfur, selenium, and tellurium. By way of example, the transition metal dichalcogenide is a transition metal disulfide having a chemical formula of the type MS2, for example, molybdenum disulfide (MoS2), tungsten disulfide (WS2), or vanadium disulfide (VS2).
[0036] The transition metal dichalcogenide layer 13 is, for example, formed by deposition, for example by ALD (Atomic Layer Deposition), for example according to the process described in French patent no. 3016889, or by CVD (Chemical Vapor Deposition) on the upper face of the support substrate 11. As an alternative, the transition metal dichalcogenide layer 13 can first be formed on one face of a transfer substrate, or handle, and then transferred to the upper face of the support substrate 11.
[0037] By way of example, an amorphous molybdenum disulfide layer coating the upper face of the support substrate 11 is first formed by ALD at a temperature of approximately 90 °C. This amorphous layer is then, for example, sulfided, for example by exposure to ethanedithiol (EDT) at a temperature of approximately 450 °C, so as to modify, or correct, its stoichiometry. Finally, a crystallization anneal under nitrogen, for example at a flow rate of approximately 2 L.min*, under atmospheric pressure, at a temperature of approximately 900 °C and for a duration of approximately 30 s, is carried out so as to form the sheets 15 of the layer 13. In the case where the support substrate 11 is silicon, the substrate 11 can, prior to the formation of the layer 13 in transition metal dichalcogenide, be oxidized from its upper face to a depth for example of the order of 500 nm.
[0038] Fig.1B illustrates more particularly a structure obtained at the end of a further step of formation of a layer 17 in a III-N semiconductor material on the structure obtained at the end of the steps previously described in relation to Fig.1A.
[0039] In the example shown, the III-N semiconductor material layer 17 covers the face of the transition metal dichalcogenide layer 13 opposite the support substrate 11 (the upper face of layer 13, in the orientation of [Fig. 1B]). By way of example, layer 17 has a thickness of between 0.15 and 50 nm, preferably between 1 and 6 nm, for example, approximately 5 nm. The material of layer 17 is a nitride of at least one element from the thirteenth group of the periodic table, also called group IIIB in the IUP AC system and group IIIA in the CAS system, for example, aluminum, gallium, or indium. The material of layer 17 is for example a binary III-N compound, for example aluminium nitride or gallium nitride, or a ternary compound, for example indium-gallium nitride, or even an aluminium nitride-based alloy, for example a compound having a chemical formula of the type Al(i.a)XaN, where X is any element of the periodic table, for example scandium, yttrium, lanthanum, magnesium, titanium, vanadium, chromium or molybdenum, and where a varies between 0 and 0.5, preferably between 0.03 and 0.2. As an alternative, the material of layer 17 is a quaternary compound, for example indium-aluminium-gallium nitride (InGaN:Al).
[0040] Furthermore, if layer 17 is made of a ternary or quaternary III-N semiconductor material, layer 17 may exhibit, from the upper face of the lamellar layer 13, a concentration gradient in at least one of the elements of the compound, for example, one of the elements of the thirteenth group. By way of example, layer 17 may be made of AlGaN and exhibit an increasing gallium content as one moves away from layer 13.
[0041] In the case where layer 17 is made of aluminium nitride, the material of layer 17 is for example crystallized in wurtzite structure with hexagonal lattice, the hexagons being oriented (002) along a direction orthogonal to the upper face of the support substrate 11.
[0042] The III-N semiconductor layer 17 is formed, for example, by physical vapor deposition (PVD), for example according to the process described in French patent no. 3105591. By way of example, the layer 17 is produced by sputtering at a temperature of approximately 350 °C. An argon-nitrogen plasma is, for example, generated and then accelerated, for example by means of a direct current source, towards an aluminum target. Under the action of the plasma, aluminum atoms are ejected from the target. These atoms react with the nitrogen in the plasma and form aluminum nitride, which is deposited onto the transition metal dichalcogenide layer 13. The support substrate 11 is, for example, not subjected to any bias voltage during the formation of layer 17 to avoid damaging layer 13. Alternatively, the semiconductor layer 17 can be formed by PLD (Pulsed Laser Deposition).
[0043] Figure 1B further illustrates a subsequent heat treatment, or annealing, step of the structure comprising the support substrate 11 and the layers 13 and 17. The heat treatment step, symbolized by vertical arrows in Figure 1B, aims to increase the internal cohesion of layer 13 as well as the adhesion of layer 13 to the support substrate 11, the substrate 11 not being intended to be removed during subsequent steps of the device manufacturing process. During the heat treatment, the van der Waals bonds between the adjacent sheets 15 of layer 13 are transformed into covalent bonds, exhibiting bond energies higher than those of the van der Waals bonds initially linking the adjacent sheets 15 together. Similarly, the van der Waals bonds between the lower sheet 15 of layer 13 and the substrate 11 can be transformed into covalent bonds during this step.
[0044] The heat treatment is carried out, for example, under a nitrogen atmosphere in a reducing environment, for example by thermal nitriding in the presence of a nitrogen gas such as ammonia (NH3), dinitrogen, or a nitrogen oxide of the NOx type, or in the presence of a nitrogen propellant, for example hydrazine (N2H4), or even in the presence of a gas or mixture of gases suitable for nitriding layer 13 through layer 15, for example a mixture of dinitrogen and dihydrogen. Nitriding makes it possible to transform, at least partially, the transition metal dichalcogenide of layer 13 into a nitride or oxynitride of said transition metal, for example, to transform, at least partially, molybdenum disulfide into molybdenum nitride (MoN).Depending on the thermal budget applied, the conversion of van der Waals bonds into covalent bonds can lead to the formation of metallic transition metal alone or of transition metal at least partially nitrided, for example metallic molybdenum or partially nitrided molybdenum in the case where layer 13 is MoS2.
[0045] As an alternative, the heat treatment can be carried out under a dihydrogen atmosphere. In this case, layer 13 is, for example, at least partially transformed into metal beads based on the transition metal of layer 13, for example, into metal molybdenum beads.
[0046] The heat treatment is carried out, for example, in a furnace at a temperature between 300 and 1300 °C, preferably between 800 and 1000 °C. The pressure inside the furnace is, for example, less than or equal to 1 bar, for example, on the order of 400 mbar. Alternatively, the pressure inside the furnace may be hyperbaric. Plasma assistance may also be provided, for example, a 1000 W, 2.67 mbar N2 / H2 CCP plasma at 500 °C. More generally, the step illustrated in [Fig. 1B] corresponds to the implementation of a thermochemical treatment.
[0047] By way of example, annealing is carried out: - at a temperature of approximately 1000 °C, for a duration of approximately 1 hour, at an ammonia pressure of approximately 150 mbar and under a flow rate of approximately 3 L.min 1 - at a temperature of approximately 1000 °C, for a period of approximately 10 min, at an ammonia pressure of approximately 400 mbar and under a flow of approximately 3 L.min 1; - at a temperature of approximately 800 °C, for a duration of approximately 10 minutes, at an ammonia pressure of approximately 400 mbar and under a flow rate of approximately 3 L.min; or - at a temperature of approximately 1000 °C, for a duration of approximately 1 hour, at an ammonia pressure of approximately 50 mbar and under a flow rate of approximately 0.05 L.min i
[0048] Fig.1C illustrates more particularly a structure obtained at the end of the thermo-chemical treatment step previously described in relation to Fig.1B.
[0049] As illustrated in [Fig. IC], the thermochemical treatment leads, for example, to a crystalline reorganization of layer 13, initially in the form of a stack of two-dimensional sheets 15, into a three-dimensional structure. This advantageously allows the layer 17, made of IIIN semiconductor material, to be mechanically held on the support substrate 11, layer 17 being bonded to the substrate 11 via layer 13.
[0050] Fig. 1D illustrates more particularly a structure obtained at the end of a subsequent and optional step of resuming epitaxy on layer 17 in semiconductor material IIIN.
[0051] In the example shown, a layer 19 covers the face of the layer 17 made of IIILN semiconductor material opposite the support substrate 11 (the upper face of the layer 17, in the orientation of [Fig. 1D]). By way of example, the layer 19 is made of an IILV semiconductor material, for example, a material selected from the list of materials mentioned above for the layer 17, for example, aluminum nitride. The layer 19 is, for example, made of the same material as the layer 17 and may comprise in addition a transition element, for example scandium, or another dopant compound, for example magnesium-zirconium (MgZr), allowing for example to modify the mechanical and acoustic properties of layer 19. As an example, the material of layer 19 is a binary III-V compound, for example indium phosphide, gallium arsenide or indium arsenide, a ternary III-V compound or a quaternary III-V compound, for example chosen from those mentioned previously for layer 17.
[0052] In a manner analogous to layer 17, layer 19 may exhibit a concentration gradient in at least one of the elements of the compound.
[0053] As an alternative, for example for applications in the field of power electronics, layer 19 can be made of silicon carbide.
[0054] Layer 19, for example, has a thickness greater than that of layer 17. As an example, layer 19 has a thickness greater than 100 nm.
[0055] Layer 19 is, for example, formed in the same or similar manner as layer 17, for example by PVD, for example according to the process described in French patent no. 3105591. The support substrate 11 is, for example, subjected to a bias voltage during the formation of layer 19. Alternatively, the IIIN semiconductor material of layer 19 can be deposited by MOCVD (Metalorganic Chemical Vapor Deposition), for example at a temperature of around 1100 °C. Alternatively, layer 19 is formed by PLD or by inorganic CVD, for example by chlorine CVD.
[0056] By way of example, the step of forming layer 19 on layer 17 is carried out as soon as possible after the heat treatment step. This advantageously avoids or limits the oxidation of the material of layer 17, thus obtaining a layer 19 of optimal crystalline quality. Alternatively, a deoxidizing treatment step and / or a preservation step of layer 17 under a non-oxidizing atmosphere may be provided.
[0057] Although not shown in [Fig. 1D], one or more additional layers, for example based on III-V semiconductor materials or silicon carbide, may subsequently be formed on layer 19, for example so as to form one or more quantum wells, a two-dimensional electron gas, etc. By way of example, where layer 17 is made of aluminum nitride, layer 19 is, for example, made of aluminum nitride and may be coated with another layer of aluminum-gallium nitride, itself coated with yet another layer of gallium nitride.
[0058] Subsequent steps in the manufacturing process of the electronic device can then be implemented from the structure of [Fig. 1D], the support substrate 11 being intended to be preserved after these steps. As an example, photolithography then etching and / or deposition steps can be implemented from the structure illustrated in [Fig.1D].
[0059] An advantage of the process described above, with respect to Figures IA to 1D, lies in the fact that the structure of the transition metal dichalcogenide layer 13 allows it to absorb stresses induced by a mismatch in lattice parameters between the material of layer 15 and that of layer 13. Furthermore, the inclusion of layer 13 makes it possible to form layer 17, and possibly layer 19, on any type of support substrate 11. This has the particular advantage of eliminating the need for a single-crystal silicon substrate. The result is a reduction in the cost of the electronic device obtained using this process.
[0060] Another advantage of the process described above, in relation to Figures IA to 1D, lies in the fact that the lamellar structure of the dichalcogenide layer 13 improves the crystalline texture of layers 17 and 19, particularly the preferred orientation
[002] of the hexagonal unit cell of the III-Ns perpendicular to the growth surface. Providing layer 13 allows the textured layers 17 and 19 to be formed on any type of support substrate 11. This has the particular advantage of eliminating the need for an epitaxial relationship between a single-crystal substrate and an III-N. This results in a reduction in the cost of the electronic device obtained using this process.
[0061] Another advantage of the process described above in relation to figures IA to 1D is that the heat treatment step prevents the occurrence of a delamination phenomenon between layer 13 and the support substrate 11, or between the sheets 15 of layer 13, during the formation of layer 19. This results in an improvement in the mechanical resistance of the device obtained according to this process.
[0062] Although an embodiment in which layer 13 is made of a transition metal dichalcogenide has been described above, this example is not limiting and layer 13 may, alternatively, be made of any type of lamellar chalcogenide or dichalcogenide material. By way of example, layer 13 may be made of a lamellar chalcogenide or monochalcogenide, for example a transition metal chalcogenide having a chemical formula of the type MX (M representing the transition metal and X the chalcogen element) or a depleted metal chalcogenide, for example zinc sulfide, tin sulfide or tin disulfide.
[0063] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.
[0064] Finally, the practical implementation of the embodiments and variants described is to be completed. The scope of the person in the trade is based on the functional specifications given above. In particular, the embodiments described are not limited to the specific examples of materials and dimensions mentioned above.
Claims
Demands
1. A method for manufacturing an electronic device, comprising the following successive steps: a) forming, on one face of a support substrate (11), a first layer (13) of a material selected from a lamellar dichalcogenide or a lamellar chalcogenide comprising a stack of sheets (15); b) forming, by physical vapor deposition on the side of said face of the support substrate, a second layer (17) of a first III-N semiconductor material coating the first layer (13); and c) carrying out a thermo-chemical treatment of the first layer (13) resulting, in the first layer (13), in a conversion of van der Waals bonds between the sheets (15) of the first layer into covalent bonds.
2. A process according to claim 1, wherein, in step c), the thermo-chemical treatment is an annealing carried out under a reducing atmosphere.
3. A process according to claim 1 or 2, wherein, in step c), the thermo-chemical treatment is carried out under a nitrogen atmosphere, preferably under an ammonia or dinitrogen atmosphere.
4. A method according to claim 1 or 2, wherein, in step c), the thermo-chemical treatment is carried out under a di-hydrogen atmosphere.
5. A method according to any one of claims 1 to 4, wherein, in step c), the thermo-chemical treatment further leads to a conversion of van der Waals bonds into covalent bonds between the first layer (13) and the support substrate (11).
6. A method according to any one of claims 1 to 5, wherein the first semiconductor material is aluminum nitride.
7. A method according to any one of claims 1 to 6, wherein the first III-N semiconductor material is doped, preferably with scandium atoms.
8. A method according to any one of claims 1 to 7, further comprising, after step c), a step d) of forming a third layer (19) in a second semiconductor material coating the second layer (17), the third layer (19) having a thickness greater than that of the second layer.
9. A method according to claim 8, wherein the second material se- miconductor is a III-V semiconductor material, preferably III-NT
10. IN. Method according to claim 8, wherein the second semiconductor material is silicon carbide.
11. A method according to claim 8 or 9, wherein the second semiconductor material is identical to the first semiconductor material.
12. A method according to any one of claims 8 to 11, wherein the third layer (19) is doped.
13. A method according to any one of claims 8 to 12, further comprising, after step d), a step e) of forming at least a fourth layer coating the third layer (19).
14. A method according to any one of claims 1 to 13, wherein, in step c), the thermo-chemical treatment is accompanied by a plasma treatment.
15. A method according to any one of claims 1 to 14, wherein the first layer (13) is made of transition metal dichalcogenide, preferably molybdenum disulfide or tungsten disulfide.
16. A method according to any one of claims 1 to 15, wherein, in step c), the thermo-chemical treatment is carried out at a temperature between 300 and 1,500 °C, preferably between 800 and 1,000 °C.
17. A method according to any one of claims 1 to 16, wherein the second layer has a thickness of between 0.15 and 50 nm, preferably between 1 and 6 nm.