Electronic device

Abstract

Electronic Device This description relates to a device comprising a first (20) and second (36) chip, the first chip (20) comprising an electronic circuit and the second chip (36) comprising a capacitor (18) having a density greater than 700 nF / mm², the first and second chips being attached to each other by molecular bonding. Figure for the abstract: Fig. 2

Description

Title of the invention: Electronic device technical field

[0001] This description relates generally to electronic devices and their manufacturing processes. Previous technique

[0002] There is a need to place capacitors close to electronic circuits in order to optimize the power supply to the electronic circuits. In particular, there is a need to significantly reduce parasitic equivalent inductances (ESL) and equivalent resistances (ESR) in order to greatly increase the efficiency of the circuits. Conventionally, capacitors, for example discrete capacitors, are connected to an active chip by wire connections or by metallic balls with dimensions between 100 µm and 1 mm. These connections themselves generate parasitic inductances (5 to 100 pF) and / or resistances (20-100 mOhms). These parasitic inductances or resistances are equivalent to, or even exceed, the parasitic inductances or resistances of very high-performance capacitors (1 pF / mm²). Summary of the invention

[0003] There is a need for very tight interconnections of very high-performance capacitors, i.e., those with high ESR and ESL values, with active devices, for example, transistors, which are increasingly integrated and sensitive to the quality of the power and current supply. Conventional solutions for placing capacitors on printed circuit boards or in packages no longer meet this need, which requires very high-density integration, as close as possible to the transistors, thus resulting in very high connection densities.

[0004] An embodiment overcomes all or part of the drawbacks of chip manufacturing processes comprising known capacitors.

[0005] One embodiment provides a device comprising first and second chips, the first chip comprising an electronic circuit and the second chip comprising a capacitor having a density greater than 700 nF / mmA2, the first and second chips being fixed to each other by molecular bonding.

[0006] Another embodiment provides for a process comprising the formation of a first chip comprising an electronic circuit, and the formation of a second chip comprising a capacitor having a density greater than 700 nF / mmA2, the process further comprising the fixing of the first and second chips by molecular bonding.

[0007] According to one embodiment, the first chip comprises an interconnection network and a semiconductor substrate in and on which electronic circuit components are located.

[0008] According to one embodiment, the capacitor comprises a stack of a first insulating layer between two second conductive layers, the stack being located in a first region of anodized metal.

[0009] According to one embodiment, the second chip comprises a third insulating layer having a first flat face and a second face, the second face being covered with a fourth layer comprising at least the first region.

[0010] According to one embodiment, the first region is surrounded by a fourth insulating region made of anodized metal.

[0011] According to one embodiment, the process comprises the formation, on a support, of the third insulating layer and of an anodizable metal layer.

[0012] According to one embodiment, the fourth layer of the second chip comprises second insulating regions of anodized metal and third regions of metal, the third regions being separated by second regions.

[0013] According to one embodiment, the process includes anodizing the metallic layer at the locations of the first and second regions.

[0014] According to one embodiment, the method includes attaching the first chip to a handle and removing the support so as to expose the flat face of the third layer.

[0015] According to one embodiment, the first and second chips are fixed by hybrid molecular bonding, the third insulating layer and the interconnection network comprising first conductive tracks located in contact with each other.

[0016] According to one embodiment, the face of the substrate opposite the interconnection network is covered by a fifth insulating layer and second conductive tracks, the fifth layer and the second conductive tracks being configured to be fixed to the third layer and the first tracks by molecular bonding.

[0017] According to one embodiment, the chips are fixed by oxide / oxide molecular bonding, the device comprising vias extending into the first and second chips, passing through the third layer and reaching a conductive track buried in the interconnection network.

[0018] According to one embodiment, the vias are formed after the first and second chips are fixed.

[0019] According to one embodiment, each of the terminals of the capacitor is connected to a third region. Brief description of the drawings

[0020] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0021] [Fig.1] schematically represents a method of implementing a manufacturing process for an embodiment of a device comprising a capacitor close to an electronic circuit;

[0022] [Fig.2] represents an embodiment of a device comprising a capacitor close to an electronic circuit;

[0023] [Fig.3] represents a step in an implementation method of the process in [Fig.1];

[0024] [Fig. 4] represents another step in an implementation method of the [Fig.l];

[0025] [Fig.5] represents another step in an implementation method of the process in [Fig.1];

[0026] [Fig.6] represents another step in an implementation method of the process in [Fig.1];

[0027] [Fig.7] represents another step in an implementation method of the process in [Fig.1];

[0028] [Fig.8] represents another step in an implementation method of the process in [Fig.1];

[0029] Figure 9 represents an embodiment of a device comprising a capacitor near an electronic circuit resulting from another embodiment; and

[0030] [Fig. 10] represents an embodiment of a device comprising a capacitor close to an electronic circuit resulting from another embodiment. Description of the implementation methods

[0031] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0032] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0033] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without any intermediate elements other than conductors, and when referring to two coupled elements, this means that these two elements can be connected or linked by through one or more other elements.

[0034] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0035] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0036] Fig. 1 schematically represents an implementation method of manufacturing an embodiment of a device comprising a capacitor close to an electronic circuit.

[0037] The process includes a step 10 in which a first chip is formed. The first chip comprises an electronic circuit. The first chip includes, for example, transistors. The first chip preferably comprises a semiconductor substrate, in and on which transistors are formed, and an interconnection network. The interconnection network includes, for example, insulating layers and a network of conductive traces and conductive vias. The first chip includes a flat surface, suitable for molecular bonding.

[0038] The process includes a step 12 in which a second chip is formed. The second chip comprises at least one Metal-Insulator-Metal capacitor, that is, a capacitor comprising a stack of one insulating layer and two metal layers, the insulating layer being located between the metal layers. The capacitor stack is located on a metal layer comprising at least one anodized region. This region of the metal layer comprises a plurality of cavities, or nanopores, the capacitor stack extending over the walls and bottom of the cavities and over the portions of the layer between the cavities.

[0039] Preferably, the second chip does not include any active electronic components other than capacitors, and possibly resistors. For example, the second chip does not include a transistor. For example, the second chip does not include a semiconductor substrate.

[0040] The second chip includes a flat face, adapted for molecular bonding.

[0041] Steps 10 and 12 can be carried out independently, for example successively or in parallel.

[0042] The process further comprises a step 14 in which the first and second chips are bonded to each other by molecular bonding. More specifically, the flat faces of the first and second chips are bonded to each other by molecular bonding.

[0043] Figure 2 represents an embodiment of a device 16 comprising a capacitor 18, and optionally resistors not shown, resembling an electronic circuit. The device 16 is obtained by a process such as that described in relation to Figure 1.

[0044] The device 16 comprises a chip 20. The chip 20, like the first chip in [Fig. 1], comprises a semiconductor substrate 22. Electronic components, for example transistors, are located in and on the substrate 22. The chip 20 further comprises an interconnection network 24. The interconnection network 24 comprises insulating layers 26, the separations of the different layers not being shown in [Fig. 2]. The interconnection network 24 further comprises conductive vias 28 and conductive tracks 30. The network 24 comprises metallic tracks 32 flush with a face 34 of the network 24. The face 34 is the face furthest from the substrate 22, that is, the face opposite the face of the network 24 in contact with the substrate 22. The tracks 32 are adapted for a hybrid molecular bonding step.

[0045] The vias 28 and the tracks 30, 32 allow electrical connections to be formed between electronic components of the chip 20 and other components of the chip 20 or to components external to the chip, for example the capacitor 18.

[0046] The device 16 further comprises a chip 36. The chip 36 corresponds to the second chip in [Fig. 1]. The chip 36 comprises a capacitor 18, and optionally resistors. Although only one capacitor 18 is shown in [Fig. 2], the chip 36 may comprise several capacitors 18.

[0047] The chip 36 includes an insulating layer 38. The layer 38 has, for example, a thickness of between 10 nm and 1 pm. The insulating layer 38 includes a face 40. The chip 36 further includes metallic tracks 42 in the layer 38. The metallic tracks 42 are flush with the face 40 of the layer 38. Preferably, the tracks 42 pass through the track 38. In other words, the tracks 42 preferably have the same thickness as the layer 38. The face 40 of the layer 38 is fixed by hybrid molecular bonding to the face 34 of the chip 20. Thus, each track 42 is preferably positioned so as to be in contact with a track 32. Connections between the chip 20 and the chip 36 are thus made via the tracks 32 and 42.

[0048] The chip 36 further comprises elements 43 made of insulating material, for example of the same material as layer 38. The elements 43 are located on layer 38, more precisely on the face opposite face 40. The elements 43 preferably do not cover, even partially, the tracks 42. The elements 43 cover some parts of layer 38. The elements 43 do not completely cover layer 38. The elements 43 have, for example, a thickness of between 300 nm and 3 pm.

[0049] The chip 36 includes a layer 44. Layer 44 is located on layer 38, on tracks 42, and on elements 43. More specifically, layer 44 covers the face opposite face 40 of layer 38. Layer 44 has, for example, a thickness less than 20 pm, for example approximately equal to 10 pm.

[0050] The layer 44 comprises regions 46. The regions 46 are conductive regions. The regions 46 are made of an anodizable conductive material, preferably a metal. The regions 46 are, for example, made of aluminum or tantalum. Each track 42 is preferably covered by, and preferably in contact with, a region 46.

[0051] The regions 46 extend, at least in some parts of the layer 44, over the entire height of the layer 44. The regions 46 therefore extend from the upper face of the layer 20 to the upper face of the layer 44. Each region 46 allows the electrical connection of the track 42 with which the region 46 is in contact to continue.

[0052] Regions 46 are, for example, surrounded by regions 48 of layer 44. Regions 48 are insulating regions. Regions 48 are made of the same material as regions 46, for example aluminum, having been anodized, for example, to obtain alumina. Regions 48 are thus porous regions. In other words, regions 48 comprise a plurality of cavities, or nanopores, not shown, extending, for example, over the entire height of region 48.

[0053] The regions 48 are located on the elements 43. Preferably, each element 43 is at least partially, for example mostly, covered by a region 48. Preferably, each region 48 covers an element 43. The elements 43 and the regions 48 allow for the formation of lateral insulation in the layer 44.

[0054] The layer 44 further comprises one or more of the regions 50, in which capacitors 18 are located. Each region 50 comprises, for example, a single capacitor 18. In the example of [Fig.2], the layer 44 comprises only a single capacitor 18, and a single region 50. The capacitor 18 is a high-density capacitor, that is to say, a capacitor having a density greater than 700 nF / mmA2, for example greater than 1 pF / mmA2.

[0055] Region 50 extends opposite a portion of layer 38 not covered by elements 43. Thus, region 50 is not opposite, even partially, an element 43. Region 50 extends from the upper face of layer 44, that is, the face furthest from layer 38. Region 50 is therefore flush with the upper face of layer 44. Region 50 does not, for example, extend as far as layer 38. Preferably, the height of region 50 is substantially equal to the height of the portions of regions 46 in contact with elements 43. Thus, region 50 is separated from layer 38, for example, by a distance substantially equal to the height of regions 43. Preferably, region 50 is separated from layer 38 by a conductive portion 52, for example, a layer of aluminum or an alloy comprising aluminium covered with a layer of tungsten constituting a stop layer to the anodisation of region 50.

[0056] Region 50, like regions 48, is made of the same material as regions 46, for example aluminum, having been anodized, for example to obtain alumina. Region 50 thus comprises a plurality of cavities (not shown), extending, for example, over the entire height of region 50. The cavity density in region 50 is, for example, greater than 40 cavities / pmA2.

[0057] The capacitor 18 is a metal-insulator-metal (MIM) capacitor. The capacitor 18 comprises a stack of layers, not shown in [Fig. 1], of an insulating layer located between two conductive layers, preferably made of metal. The stack of layers of a capacitor 18 is conformally located on the porous structure of the region 50.

[0058] A lower layer of the capacitor stack 18, that is, one of the conductive layers, preferably a metallic layer, conforms to the porous structure, and in particular within the cavities of region 50. The lower layer of a capacitor 18 preferably completely covers the upper surface of region 50, the lateral walls of the cavities, and the bottom of the cavities. The lower layer of a capacitor 18 is therefore in contact with portion 52.

[0059] An intermediate layer of the capacitor stack 18, i.e. the insulating layer, extends conformally over the lower layer. The intermediate layer extends into the cavities. The intermediate layer preferably completely covers the lower layer.

[0060] An upper layer of the capacitor stack 18, i.e., the other conductive layer, for example made of metal, extends conformally over the intermediate layer. The upper layer extends into the cavities. The upper layer fills the cavities, for example. The upper layer preferably completely covers the intermediate layer. The upper layer includes, for example, a flat upper surface extending over the upper surface of the porous structure.

[0061] The layer 44 comprises, for example, one or more insulating regions 54 delimiting the region 50. The region 50 is surrounded by regions 54. The region 50 is thus laterally isolated from the rest of the layer 44. The region 50 is preferably in direct lateral contact with the regions 54. Thus, the region 50 is preferably not separated from the regions 54 by other regions of the layer 44. In particular, the region 50 is preferably not separated from the regions 54 by regions of the material of the regions 46 that have not been anodized and are not porous.

[0062] The regions 54 are insulating regions. The regions 54 are made of the material of the layer 44, for example, anodized aluminum, for example, alumina. The regions 54 are thus porous regions. In other words, the regions 54 comprise a plurality of cavities (not shown), extending, for example, over the entire height of the region 54. Preferably, the height of the regions 54 is substantially equal to the height of region 50. Regions 54 extend from the upper face of layer 44, that is, the face furthest from layer 38. Regions 54 therefore outcrop with the upper face of layer 44. Regions 54 do not, for example, extend to layer 38. Regions 54 are preferably separated from layer 38 by the conductive portion 52.

[0063] The chip 36 further includes insulating portions 56. The insulating portions 56 partially cover the upper surface of the layer 44. The chip 36 further includes a conductive track 58 located on the upper surface of the layer 44 and certain portions 56. The track 58 extends in particular over the upper surface of the region 50, and more specifically over the upper layer of the capacitor stack 18. Preferably, the track 58 completely covers the upper surface of the upper layer of the stack. The track 58 allows connection between an electrode of the capacitor 18 and external elements.

[0064] A portion 52 of a region 46, in contact with the lower layer of the capacitor, allows the connection between another electrode of the capacitor and elements external to the chip. The region 46 comprising the portion 52 extends, for example, around regions 50 and 54. The region 46 comprising the portion 52 is in contact with a track 42.

[0065] The track 58 is electrically connected, preferably in contact with, a region 46. For example, said region 46 is separated from the capacitor 18 by a region 48, at least a part of the region 46 in contact with the lower layer of the stack, and a region 54. The regions 46 opposite which the track 58 extends are covered by portions 56. Thus, the track 58 is completely separated from the regions 46 opposite which the track 58 extends by one or more insulating portions 56.

[0066] Figures 3 to 8 illustrate steps, preferably successive, of an implementation of the process of [Fig. 1]. More specifically, Figures 3 to 8 illustrate steps, preferably successive, of an implementation of a manufacturing process for the device of [Fig. 2].

[0067] Figure 3 represents a step in an implementation of the process of Figure 1. More specifically, Figure 3 represents a manufacturing step of chip 36.

[0068] During this step, the layer 38 is formed on a support 60, more precisely on an upper face of the support 60. The layer 38 is made of an insulating material, for example silicon oxide. The layer 38 preferably covers the entire upper face of the support 60 during its formation.

[0069] The support 60 is, for example, a semiconductor substrate. The support 60 is, for example, made of a material that is selectively etchable with respect to the materials of layer 38 and tracks 42. The upper face of the support 60 is preferably flat.

[0070] The step in [Fig.3] further includes the formation of tracks 42 in layer 38. For example, cavities passing through layer 38, i.e. reaching support 60, are formed in layer 38 at the locations of tracks 42 and are filled with the material from tracks 42.

[0071] The step in [Fig.3] also includes the formation of the elements 43. The elements 43 are made of an insulating material, preferably the same material as the layer 38. For example, the elements 43 are formed on the upper face of the layer 38.

[0072] The step in [Fig. 3] further comprises the formation of a layer 62 of an anodizable conductive material, preferably a metal. The layer 62 is, for example, made of aluminum or tantalum. The layer 62 is made of the material of regions 46.

[0073] The layer 62 preferably does not contain any cavities during its deposition. Preferably, the lower and upper faces of the layer 62, that is, the layer closest to the layer 38 and the layer furthest from the layer 38, are flat and parallel. The layer 62 is, for example, made of aluminum.

[0074] Fig. 4 represents another step in an implementation method of the process in Fig. 1.

[0075] During this step, a mask 64 is formed on the upper face of the layer 62. The mask 64 is, for example, made of the same material as the portions 56. The mask 64 includes openings opposite the locations of the regions 48, 50 and 54.

[0076] The step in [Fig.4] further includes the formation of nanopores at the locations of regions 48, 50 and 54. More specifically, the step in [Fig.4] includes, for example, the formation of nanopores so as to form regions 48 and a region 68 corresponding to the locations of regions 50 and 54. For clarity, the nanopores are not shown.

[0077] In order to form nanopores in regions 48 and 68, the portions of layer 62 corresponding to regions 48 and 68 undergo an anodic oxidation process, making it possible to create a nanostructured insulating layer.

[0078] Anodizing, or the anodic oxidation process, is an electrolytic process carried out in a wet environment. The principle is based on the application of an imposed potential difference between two conductive electrodes immersed in an electrolytic solution, which may, for example, be acidic. In the example of the process shown in Figures 3 to 8, one of the conductive electrodes, for example the anode, is layer 62. Applying a potential to an electrode induces the growth of alumina on its surface if the electrode is made of aluminum. The dissolution of the aluminum electrode in the acid bath causes the formation of nanopores or cavities on the electrode surface.

[0079] The nanopores advantageously have, for example, a diameter of approximately 80 nm and are spaced 50 nm apart. The nanopore density is, for example, 40 cavities / pm2. Moreover, the anodizing process used allows for the production of nanopores opening onto layer 62. In other words, the nanopores can be considered as nano- cylinders, one side of which opens onto layer 52.

[0080] The nanopore formation process is carried out in such a way that the nanopores reach the elements 43 in the regions 48 and do not reach the layer 38 in the region 68. Thus, the portion 52 is formed under the region 68.

[0081] Fig. 5 represents another step in an implementation method of the process in Fig. 1.

[0082] The process of [Fig.5] includes the formation of the stack of layers of the capacitor 18. More specifically, the capacitor 18 comprises a stack of a lower metal layer, an insulating layer and an upper metal layer formed conformally in the region 50, as described in relation to [Fig.2].

[0083] Thus, the lower layer of the capacitor stack 18 conforms to the nanopore structure, and in particular within the nanopores of region 50. In region 50, the lower layer of capacitor 18 preferably completely covers the upper surface of layer 44, the lateral walls of the nanopores, and the bottom of the nanopores. The lower layer of capacitor 18 is therefore flush with the upper surface of portion 52. The lower layer of capacitor 18 is thus electrically connected, preferably in contact, with a region 46 via the portion 52 located beneath capacitor 18.

[0084] The intermediate layer of the capacitor stack 18 extends conformally over the lower layer. The intermediate layer extends into the nanopores. The intermediate layer preferably completely covers the lower layer.

[0085] The upper layer of the capacitor stack 18 extends conformally over the intermediate layer. The upper layer extends into the nanopores. The upper layer fills, for example, the nanopores. The upper layer preferably completely covers the intermediate layer. The upper layer comprises, for example, a flat upper face extending over the upper face of the nanopore structure in the region 50.

[0086] The step in [Fig. 5] further includes the formation of portions of insulating material 56. The portions 56 are obtained, for example, from the mask 64, for example by engraving openings in the locations where the portions 56 are not present. Alternatively, the mask 64 can be removed and replaced by the portions 56.

[0087] The step in [Fig.5] further includes the formation of track 58.

[0088] Figure 6 represents another step in an implementation method of the [Fig.l].

[0089] During this step, a handle 66 is fixed to the chip 36. The handle 66 is fixed to the upper face of the chip 36, that is to say the face opposite the support 60.

[0090] The handle 66 is fixed to the chip 36 by a layer of fixing material by For example, a temporary adhesive layer 68. The temporary adhesive layer 68 is located on the upper surface of the chip 36. More precisely, the temporary adhesive layer 68 is formed so as to cover the entire upper surface of the chip 36. The upper surfaces of the track 58, portions 56, and layer 44 are covered by the temporary adhesive layer 68.

[0091] Fig. 7 represents another step in an implementation method of the process in Fig. 1.

[0092] During this step, the support 60 is removed, for example by a grinding step, for example coarse then fine, followed by chemical etching.

[0093] The step in [Fig. 7] further includes the formation of chip 20. The formation of The chip 20 can be formed in parallel or successively with the formation of the chip 36. Thus, the chip 20 is formed independently of the formation of the chip 36.

[0094] The formation of the chip 20 corresponds, for example, to the formation of an integrated circuit chip.

[0095] The formation of the chip 20 includes the formation of electronic components, for example of an electronic circuit, in the substrate 22. The formation of the chip 20 includes, for example, the formation of transistors in the substrate 22.

[0096] The formation of the chip 20 further includes the formation of an interconnection network 24. The formation of the interconnection network includes the formation of insulating layers 26, and the formation in the layers 26 of a network of conductive tracks 30 and conductive vias 28.

[0097] The formation of the interconnection network 24 further includes the formation, at the level of the upper face 34 of the chip 20, i.e. the face of the interconnection network furthest from the substrate 22, of track 32 flush with the upper face of the network 24. The upper face of the network 24 is a flat face, suitable for molecular bonding.

[0098] Fig. 8 represents another step in an implementation method of the process in Fig. 1.

[0099] During this step, the chips 20 and 36 are fixed to each other by hybrid molecular bonding, by the planar faces 34 and 40. Thus, the tracks 32 and 42 are placed in contact and the upper layer 26 of the lattice stack 24 is placed in contact with the lower face of the layer 38. Preferably, each track 32 is placed in contact with a track 42.

[0100] The molecular bonding of chips 20 and 36 includes an annealing step for example below 450 °C, for example substantially equal to 400 °C.

[0101] Furthermore, the step in [Fig. 8] includes the removal of the handle 66 and the fixing layer 68. The removal of the handle 66 and the fixing layer 68 can be carried out before or after the annealing step, depending on the composition and the thermal budget. glue.

[0102] Figure 9 represents an embodiment of another device 70 comprising a capacitor close to an electronic circuit resulting from another method of implementation.

[0103] Device 70 of [Fig. 9] comprises elements identical to those of device 16 of [Fig. 2], which will not be described again in detail. In particular, device 70 comprises: - a chip 20a, comprising the substrate 22 in and on which electronic components and the interconnection network 24 are formed; - the chip 36a, comprising the insulating layer 38, the regions 48, 50, 54, the capacitor 18, the portions 56 and the track 58.

[0104] Device 70 differs from device 16 in [Fig.2] in that, in device 70, chips 36a and 20a are fixed to each other by oxide / oxide bonding and not by hybrid bonding.

[0105] Thus, chip 20a differs from chip 20 of [Fig. 2] in that the upper face of chip 20a, i.e., the upper face of the lattice 24, i.e., the face of chip 20a furthest from the substrate 22, is adapted for oxide / oxide molecular bonding. Therefore, the upper insulating layer 26 of the lattice 24, i.e., the layer 26 furthest from the substrate, does not include the tracks 42.

[0106] Thus, during the manufacture of the chip 20a, i.e. before the molecular bonding step of the chips 20a and 36a, the upper face of the chip 20a is entirely formed of oxide, i.e. the material of layer 26.

[0107] Furthermore, chip 36a differs from chip 36 of [Fig.2] in that layer 38 does not include tracks 42. In addition, portions 56 cover, for example, all regions 46.

[0108] Thus, during the manufacture of the chip 36a, i.e. before the molecular bonding step of the chips 20a and 36a, the lower face of the chip 20a, i.e. the lower face of the layer 38, is entirely formed of oxide, i.e. the material of the layer 38.

[0109] The device 70 comprises conductive vias 72. The vias 72 extend from chip 20a to chip 36a. More precisely, each via 72 extends, for example, from a conductive trace 32a embedded in the network 24. One end of each via 72 is, for example, in contact with the upper surface of a trace 32a. Each via 72 preferably extends to the upper surface of chip 36a. Preferably, each via 72 passes through layer 38 and an element 43. Preferably, each via 72 passes at least partially, preferably completely, through a region 48. Each via 72 is thus separated from regions 46 and from other vias 72 by layer 38, elements 43, and regions 48. The vias 72 are connected to each other, to capacitors 18, or to external elements. device 70 is connected by conductive elements. In particular, a via 72 is connected to track 58. That is to say, a portion of track 58 extends to, and is in contact with, the upper end of a via 72, i.e., the end flush with the upper face of region 48, i.e., the end opposite the end located in chip 20a in contact with tracks 32a. A first terminal of capacitor 18 is thus connected to a circuit of chip 20 via track 58, a via 72, and the interconnection network 24.

[0110] Another via 72, comprising an end flush with the upper face of a region 48, is connected, for example by a conductive track 74 extending over the upper face of the chip 36a, to the region 46 comprising the portion 52, i.e., the region 56 connected to a second terminal of the capacitor 18. In other words, the track 74, for example a metallic track, is, for example, in contact with the end of the via 72 and with the upper face of the region 46 comprising the portion 52. The track 74 preferably passes through the portion 56 extending above the region 46 comprising the portion 52. In the case where the track 74 extends above other regions 46, the track 74 is preferably separated from the other regions 46 by a portion 56.

[0111] The vias 72 are preferably formed after the molecular bonding step. The top layer 26 and the layer 38 preferably do not include a metallic track, except for the vias 72. Thus, once the chips 20a and 36a are fixed to each other, cavities are formed from the top face of the chip 36a, so as to reach the tracks 32a, and then filled with conductive material.

[0112] Fig. 10 represents an embodiment of a device 76 comprising a capacitor close to an electronic circuit resulting from another embodiment.

[0113] Device 76 of [Fig. 10] comprises elements identical to those of device 16 of [Fig. 2], which will not be described again in detail. In particular, device 76 comprises: - chip 36 as described in relation to [Fig.2]; and - a chip 20b comprising the interconnection network 24 and the substrate 22.

[0114] Device 76 differs from device 16 in that chip 36 is not fixed to the upper face 34 of chip 20b, i.e., the upper face 34 of the interconnection network 24, but to a lower face 78 of chip 20b, i.e., the face opposite face 34 of chip 20b. In other words, chips 20b and 36 are fixed to each other by hybrid molecular bonding between faces 40 and 78.

[0115] The chip 20b, like the chip 20, comprises active electronic components. The chip 20b comprises, for example, transistors 80 shown schematically in [Fig. 10]. The transistors 80 are located in and on the substrate 22. Thus, the transistors 80 comprise regions in the substrate 22, for example, source and drain. Transistors 80 include for example a control terminal located on the substrate, for example on the top face of the substrate, i.e. in the insulating layers 26 of the interconnect network.

[0116] Face 78 of chip 20b is adapted for hybrid molecular bonding, for example, metal-oxide bonding. Chip 20b includes a layer 82 of an insulating material, for example, silicon oxide, covering the underside of substrate 22, i.e., the face of substrate 22 furthest from face 34. Chip 20b includes tracks 84 in layer 82. The tracks 84 are flush with face 78. The tracks 84 are positioned so as to be in contact with tracks 42, thus enabling molecular bonding and electrical connection with chip 36.

[0117] The chip 20b includes vias 86 extending from the tracks 84 to the electronic components of the chip 20b. The vias 86 are, for example, insulated conductive vias, that is to say, vias comprising a conductive core and an insulating sheath.

[0118] The chip 20b comprises, like the chip 20 of [Fig.2], conductive tracks 30 embedded in the network 24, conductive vias 28 and tracks 32 flush with the face 34 of the chip 20b. Thus, the chip 20b is connected by its lower face 78 to the capacitor 18 and can be connected, by the interconnection network 24, to other elements external to the chip.

[0119] According to other embodiments, the transistors 80 can be replaced by other types of transistors.

[0120] One advantage of the embodiments described precisely is that it is possible to form capacitors very close to chips comprising electronic circuits, separated for example only by a level of metallization.

[0121] Another advantage of the described embodiments is that the manufacture of the capacitors does not risk causing damage to the electronic circuits. In particular, the electronic circuits do not incur the thermal cost of capacitor formation, only that of the bonding of the two chips.

[0122] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, although the described steps of the process refer to chips, the steps can be carried out on a silicon wafer so as to form a large number of chips simultaneously. Thus, the chips can be manufactured individually and attached to one another. According to another embodiment, a plurality of chips are formed simultaneously on semiconductor wafers. The chips are then individualized and attached to one another.

[0123] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given herein. above.

Claims

Demands

1. Device comprising first (20, 20a, 20b) and second (36, 36a) chips, the first chip (20, 20a, 20b) comprising an electronic circuit and the second chip (36, 36a) comprising a capacitor (18) having a density greater than 700 nF / mmA2, the first and second chips being fixed to each other by molecular bonding, in which the capacitor (18) comprises a stack of a first insulating layer between two second conductive layers, the stack being located in a first region (50) of anodized metal.

2. Device according to claim 1, wherein the first chip (20, 20a, 20b) comprises an interconnect network (24) and a semiconductor substrate (22) in and on which are located components (80) of the electronic circuit.

3. Device according to claim 1 or 2, wherein the second chip (36, 36a) comprises a third insulating layer (38) having a first flat face (40) and a second face, the second face being covered with a fourth layer (36) comprising at least the first region (50).

4. Device according to claim 3, wherein the first region (50) is surrounded by a fourth insulating region (54) of anodized metal.

5. Device according to claim 3 or 4, wherein the fourth layer (36) of the second chip comprises second insulating regions (48) of anodized metal and third regions (46) of metal, the third regions (46) being separated by second regions (48).

6. Device according to any one of claims 3 to 5, wherein the first (20, 20b) and second (36) chips are fixed by hybrid molecular bonding, the third insulating layer (38) and the interconnection network (24) comprising first conductive tracks located in contact with each other.

7. Device according to claim 6, wherein the face of the substrate opposite the interconnection network is covered by a fifth insulating layer (82) and second conductive tracks, the fifth layer and the second conductive tracks being configured to be fixed to the third layer (38) and the first tracks (42) by molecular bonding.

8. A device according to any one of claims 3 to 5, wherein the chips are fixed by oxide / oxide molecular bonding, the device including vias (72) extending into the first (20a) and second (36a) chips, passing through the third layer (38) and reaching a conductive track (32a) buried in the interconnection network (24).

9. Device according to any one of claims 5 or 6 to 8 in its connection with claim 5, wherein each of the terminals of the capacitor (18) is connected to a third region (46).

10. A method comprising the formation of a first chip (20, 20a, 20b) comprising an electronic circuit, and the formation of a second chip (36, 36a) comprising a capacitor (18) having a density greater than 700 nF / mmA2, the method further comprising the fixing of the first (20, 20a, 20b) and second chips by molecular bonding, in which the capacitor (18) comprises a stack of a first insulating layer between two second conductive layers, the stack being located in a first region (50) of anodized metal.

11. The method according to claim 10 applied to the manufacture of a device according to any one of claims 1 to 9.

12. A method according to claim 11 in relation to claim 3 or 4, comprising the formation, on a support (60), of the third insulating layer (38) and of an anodizable metal layer.

13. A method according to claim 12 as related to claim 5, comprising anodizing the metallic layer at the locations of the first (50) and second (48) regions.

14. A method according to any one of claims 11 to 13 in relation to claim 3, comprising attaching the first chip (20, 20a, 20b) to a handle (66) and removing the support (60) so as to expose the flat face of the third layer (38).

15. A method according to any one of claims 11 to 14 in relation to claim 8, wherein the vias (72) are formed after the first and second chips are fixed.

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