MOS transistor electronic circuit and manufacturing method

Abstract

Electronic circuit with MOS transistors and manufacturing method The present description relates to an electronic circuit (30) comprising a plurality of transistors including:- at least one first MOS transistor (101) of a first conductivity type arranged in and on at least one first active zone (ZA1) of a semiconductor substrate (120);- at least one second MOS transistor (102) of the second conductivity type arranged in and on at least one second active zone (ZA2) of the semiconductor substrate;each first active zone being delimited by a first insulation region (341) which is set back relative to a first face (120A) of the semiconductor substrate by a first depth (P1);andeach second active zone being delimited by a second isolation region (342) which is flush with the first face of the semiconductor substrate, or which is set back from the first face of the semiconductor substrate by a second depth (P2) less than the first depth. Figure for the abstract: Fig. 3;

Description

Title of the invention: MOS transistor electronic circuit and manufacturing method Technical field

[0001] The present description relates generally to electronic circuits, and in particular to the manufacture of NMOS and PMOS transistors of the same electronic circuit. Prior art

[0002] Metal Oxide Semiconductor Field Effect Transistors, or MOSFETs, are transistors comprising a conductive gate region electrically insulated from a semiconductor substrate, generally silicon, or from a well formed in a semiconductor substrate, by a dielectric layer called gate oxide or gate insulator, the gate region surmounting an active zone comprising a source region, a drain region and a channel-forming region between the source region and the drain region. A MOSFET may be referred to as a MOS transistor.

[0003] N-channel MOS transistors, or NMOS transistors, designate transistors whose source and drain regions are N-type doped, for example doped with arsenic or phosphorus atoms. P-channel MOS transistors, or PMOS transistors, designate transistors whose source and drain regions are P-type doped, for example doped with boron or indium atoms.

[0004] MOS transistors can undergo a dislocation phenomenon. A dislocation is an extensive defect in the semiconductor substrate, particularly when this substrate is made of monocrystalline silicon. When it is located between the source region and the drain region, such a dislocation greatly impairs the functionality of the transistor, resulting in particular in a very large current of the transistor in the blocked state (OFF current), which can lead to resistive behavior of the transistor.

[0005] Typically, a dislocation results in the presence in silicon of an additional half-crystalline plane terminated by a vacancy. The origins of the appearance of dislocations are multiple. Among the possible causes, we can cite the implantation of impurities at high doses which will lead to localized amorphization which, when followed by too rapid activation annealing, can create a dislocation. The type of impurities used during doping can have an influence on the appearance of dislocations.

[0006] In this regard, it has been observed that dislocations appear mainly in NMOS transistors and more particularly in NMOS transistors having small active areas, especially when arsenic is used as a dopant. Attempts to modify the dopant type, dosage and / or implantation energy to reduce the risk of dislocations have, however, led to transistors with performance that is reduced compared to the expected performance, especially when phosphorus is used.

[0007] Other possible causes include stresses induced in the active area of ​​the transistor due to the presence of an isolation region, for example of the shallow trench (STI) type, delimiting this active area. For example, the active area may be made of silicon (Si), and the isolation region may be an isolation trench made of silicon dioxide (SiO2), and the Si in the active area may be stressed by the SiO2 in the isolation trench located around the active area.

[0008] A method of manufacturing an NMOS transistor is proposed which makes it possible to reduce, in a simple manner, the risk of dislocation appearing in the active zone of the transistor, in particular when NMOS and PMOS transistors of the same electronic circuit are manufactured on the same manufacturing line, according to a manufacturing method in which some of the manufacturing steps are similar for the two types of transistors. Summary of the invention

[0009] There is a need to improve the manufacturing processes for NMOS and PMOS transistors of the same electronic circuit, in particular to reduce the risk of dislocations of the NMOS transistors appearing.

[0010] One embodiment overcomes all or part of the drawbacks of known MOS transistor electronic circuits.

[0011] One embodiment provides an electronic circuit comprising a plurality of transistors including: - at least one first MOS transistor of a first conductivity type arranged in, and on, at least one first active zone of a semiconductor substrate; - at least one second MOS transistor of the second conductivity type arranged in, and on, at least one second active zone of the semiconductor substrate; each first active area being delimited by a first isolation region which is set back from a first face of the semiconductor substrate by a first depth; and each second active zone being delimited by a second isolation region which is flush with the first face of the semiconductor substrate, or which is set back from the first face of the semiconductor substrate by a second depth less than the first depth.

[0012] One embodiment provides a method of manufacturing an electronic circuit comprising a plurality of transistors including: - at least one first MOS transistor of a first conductivity type arranged in, and on, at least one first active zone of a semiconductor substrate; - at least one second MOS transistor of the second conductivity type arranged in, and on, at least one second active zone of the semiconductor substrate; the manufacturing method comprising forming at least a first and a second isolation region configured such that: each first active zone is delimited by a first isolation region set back from a first face of the semiconductor substrate by a first depth; and each second active zone is delimited by a second insulation region flush with the first face of the semiconductor substrate, or set back from the first face of the semiconductor substrate by a second depth less than the first depth.

[0013] According to one embodiment, the first face of the semiconductor substrate is surmounted by gate regions of the at least one first MOS transistor and of the at least one second MOS transistor, each gate region being isolated from the semiconductor substrate by a gate insulator layer.

[0014] According to one embodiment, the at least one first and one second isolation regions are isolation trenches, for example shallow isolation trenches.

[0015] According to one embodiment, the at least one first and one second isolation regions are joined.

[0016] Alternatively, the at least one first and one second isolation region may be disjointed.

[0017] According to one embodiment, the first depth is greater than or equal to 12 nanometers (nm), and the second depth is less than 12 nm.

[0018] According to one embodiment, the gate region of at least one transistor among the plurality of transistors comprises at least one counter-doping zone of a conductivity type opposite to the conductivity type of said at least one transistor, said at least one counter-doping zone being positioned and dimensioned so as to attenuate the bump effect of said at least one transistor, for example said at least one counter-doping zone is positioned at an overlap zone between the gate region and the active zone of said at least one transistor.

[0019] According to a particular embodiment, the at least one transistor is the at least one first MOS transistor.

[0020] According to one embodiment, the first conductivity type is the N type, each first MOS transistor being an NMOS transistor, and the st the P type, each second MOS transistor being a PMOS transistor.

[0021] According to one embodiment, the semiconductor substrate comprises silicon, and the at least one first and one second isolation region comprises a silicon oxide, for example silicon dioxide.

[0022] According to one embodiment, the electronic circuit is included in a non-volatile memory, for example an electrically erasable and programmable non-volatile memory.

[0023] According to one embodiment, the formation of the at least one first and one second isolation regions comprises the formation of the at least one second isolation region; then the formation of the at least one first isolation region.

[0024] According to one embodiment, the formation of at least one first and one second isolation region comprises a step of etching initial isolation regions delimiting the first active zone and the second active zone, said etching step comprising: - a first etching of the initial isolation regions from the first face of the semiconductor substrate and up to the second depth, so as to form second isolation regions; then - a second etching of at least one of the second isolation regions, from the first face of the semiconductor substrate and up to the first depth, so as to form the at least one first isolation region; the second etching being carried out through a second etching mask configured to access each first transistor and mask each second transistor.

[0025] By "initial isolation regions" is meant isolation regions initially formed in the semiconductor substrate. For example, these initial isolation regions are substantially flush with the first face of the semiconductor substrate.

[0026] According to one embodiment, the first etching is carried out through a first etching mask configured to access each first transistor and each second transistor.

[0027] One embodiment provides an integrated circuit comprising any of the electronic circuits described above. Brief description of the drawings

[0028] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0029] [Fig.1A] represents, by a sectional view, an example of an electronic circuit comprising NMOS and PMOS transistors formed in, and on, the same semiconductor substrate;

[0030] [Fig.lB] represents, by a sectional view, a variant of the electronic circuit of [Fig.lA];

[0031] [Fig.lC] represents, in a top view, one of the transistors of the electronic circuit of [Fig.lB];

[0032] [Fig.2] represents an example of a method of manufacturing an electronic circuit similar to the electronic circuit of [Fig.lA] or [Fig.lB];

[0033] [Fig. 3] represents an electronic circuit according to an embodiment comprising NMOS and PMOS transistors formed in, and on, the same semiconductor substrate; and

[0034] [Fig.4A] represents a manufacturing method according to an embodiment of an electronic circuit comprising NMOS and PMOS transistors in and on the same semiconductor substrate;

[0035] [Fig.4B] represents a variant of the manufacturing method of [Fig.4A];

[0036] [Fig.5A] and [Fig.5B] illustrate examples of positioning of the etching masks and / or openings of the etching masks during the etching step of a manufacturing method according to one embodiment. Description of the embodiments

[0037] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0038] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, not all the steps of the method for manufacturing MOS transistors have been described, being achievable with the usual microelectronics methods. Similarly, not all the details of the MOS transistors have been described. In particular, the contacts and the interconnection circuits of the transistors have not been shown. Furthermore, not all the applications that the described transistors may have have been detailed.

[0039] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0040] In the following description, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., it is made reference unless otherwise specified to the orientation of the figures.

[0041] Unless otherwise specified, the expressions "approximately", "approximately", "sen "possibly", and "in the order of" mean within 10%, preferably within 5%.

[0042] In the following description, to simplify it, a MOSFET type transistor may be designated a MOS transistor, or transistor.

[0043] When referring to an "active region," it refers to an area of ​​a semiconductor substrate of a transistor, for example, an area bounded by isolation regions. An active region typically includes a source region, a drain region, and a channel-forming region, or channel region, between the source region and the drain region. The active region may be formed in the semiconductor substrate or in a well formed in the semiconductor substrate.

[0044] A semiconductor substrate may be a solid substrate, for example made of silicon, or a semiconductor layer of a silicon-on-insulator (SOI) type substrate.

[0045] In the following description, a length corresponds to a dimension in a first direction, corresponding to the X direction identified in the figures, of a main plane XY. The main plane corresponds substantially to the main plane of the semiconductor substrate in, and on, which the transistor is formed. The first direction corresponds to a direction parallel to the conduction direction of the transistor. A width corresponds to a dimension in a second direction of the main plane XY, corresponding to the Y direction identified in the figures, orthogonal to the first direction. A thickness or a depth corresponds to a dimension in the direction perpendicular to the main plane XY, corresponding to the vertical direction Z identified in the figures.

[0046] [Fig. 1 A] represents an example of an electronic circuit 11 comprising two adjacent transistors, a transistor 101 (first transistor) of the NMOS (TrN) type and a transistor 102 (second transistor) of the PMOS (TrP) type, formed in, and on, a semiconductor substrate 120.

[0047] The NMOS transistor 101 comprises, within the semiconductor substrate 120, a P-type well 121, a first active zone ZA1 delimited in the well 121 by one or more isolation regions 140, for example of the shallow trench isolation (STI) type. The first active zone ZA1 comprises a heavily doped N-type (N+) source region 123 (SI) and a drain region 125 (Dl), as well as a channel-forming region between the source region and the drain region.

[0048] The NMOS transistor 101 also comprises, on the upper face 120A (first face) of the substrate 120, above the first active zone ZA1, a gate region 131 insulated by a gate oxide 133. The sides of the gate region 131, as well that a portion of the substrate 120 around the gate region, are covered with an oxide layer 135, itself covered with an insulating spacer 137.

[0049] The PMOS transistor 102 comprises, within the semiconductor substrate 120, an N-type well 122, a second active zone ZA2 delimited in the well 122 by one or more isolation regions 140. The second active zone ZA2 comprises a heavily doped P-type (P+) source region 124 (S2) and a drain region 126 (D2), as well as a channel-forming region between the source region and the drain region.

[0050] The PMOS transistor 102 also comprises, on the upper face 120A (first face) of the substrate 120, above the second active zone ZA2, a gate region 132 insulated by a gate oxide 134. The sides of the gate region 132, as well as a portion of the substrate 120 around the gate region, are covered with an oxide layer 136, itself covered with an insulating spacer 138.

[0051] For example, the active areas are made of silicon (Si). For example, the isolation regions are isolation trenches made of silicon dioxide (SiO2). For example, the gate regions are made of polysilicon. The gate regions may be of the single-gate type or of the multi-gate type, for example, double-gate.

[0052] In order to reduce the risk of dislocation, it may be desired to reduce the stresses induced by the isolation regions on the active zones, for example by reducing the volumes of insulation in these isolation regions.

[0053] Since the isolation regions have the function, in particular, of isolating the NMOS 101 and PMOS 102 transistors from each other, and in particular the P 121 and N 122 wells of these respective transistors, it is generally avoided to reduce the depth of the isolation regions, for example, in order to avoid causing or increasing leakage currents between the active zones delimited by these isolation regions. It is then possible to reduce the volumes of the isolation regions by removing a portion of insulation from each isolation region from the upper face 120A of the semiconductor substrate 120.

[0054] [Fig.lB] represents, by a sectional view, a variant of the electronic circuit of [Fig.lA]. The electronic circuit 12 of [Fig.lB] differs from the electronic circuit 11 of [Fig.lA] in that the insulation regions 141 are set back (have been hollowed out) relative to the upper face 120A of the substrate 120 by a non-zero depth PO, for example equal to approximately 23 nm. In other words, a portion of insulation from each insulation region 141 has been removed over a depth PO from the upper face 120A of the substrate 120. This portion of insulation is removed around the NMOS 101 and PMOS 102 transistors.

[0055] [Fig.lC] represents, in a top view, the PMOS transistor 102 of the electronic circuit of [Fig.lB].

[0056] The gate region 132 has a length Lg in the conduction direction X of the transistor, and it also extends transversely to the active area ZA2 of the transistor 102 in the direction Y, perpendicular to the direction X, for example to allow contacting of said gate region. Thus, the gate region 132 overlaps two opposite edges BD1 and BD2 of the active area ZA2 at two overlapping areas ZCH1 and ZCH2, respectively. In the overlapping areas, a non-uniform thickness of the gate oxide 134 may form, and parasitic transistors TPI and TP2 may form at the edges BD1 and BD2 of the active area ZA2, with between these parasitic transistors a central transistor TP having an expected operation. The parasitic transistors TPI and TP2 have a threshold voltage lower than that of the central transistor TP.Since the threshold voltage of the parasitic transistors is lower than that of the central transistor, the threshold voltage of transistor 102 is lower than expected.

[0057] This effect is known as the hump effect, and we generally seek to avoid and / or correct it. In the preceding description, this phenomenon has been described in relation to the PMOS transistor, but can also occur for the NMOS transistor.

[0058] Furthermore, the further the isolation region 141 is set back from the upper face 120A of the substrate 120, i.e. the greater the depth PO (the more it has been dug), the more the hump effect can occur.

[0059] In other words, one may want to improve the performance of the NMOS transistor, and in particular reduce the probability of the appearance of dislocations in the active zone of the NMOS transistor by adjusting the PO depth, the dislocations appearing essentially in the NMOS transistors, but this may contribute to degrading the performance of the PMOS transistor, in particular increasing the hump effect on the PMOS transistor.

[0060] This is explained in particular by the fact that the removal of the insulating portions of the isolation regions can be achieved by using the same step of a method for manufacturing an electronic circuit having NMOS and PMOS transistors formed in, and on, the same semiconductor substrate. The NMOS and PMOS transistors of the same electronic circuit can in fact be manufactured on the same manufacturing line, according to a manufacturing method in which the maximum number of manufacturing steps are similar for the two types of transistors, in particular for reasons of manufacturing cost.In other words, NMOS and PMOS transistors of an electronic circuit can undergo the same steps of a manufacturing process, with the exception of the doping steps, for example the doping of the wells, and the doping of the source and drain regions, which are different depending on whether the transistor is N-channel or P-channel, these steps generally requiring dedicated implantation masks so that only the regions . to be doped, of the N type or of the P type, are. This is illustrated in relation to [Fig.2] described below.

[0061] [Fig. 2] represents an example of a manufacturing method 200 of an electronic circuit comprising NMOS and PMOS transistors formed in, and on, the same semiconductor substrate, which can be applied to the manufacturing of the electronic circuit 11 of [Fig. 1A] or of the electronic circuit 12 of [Fig. 1B]. The elements identical to those described previously are identified by the same numerical references. Not all of the manufacturing steps have been detailed, only the steps useful for understanding the problem have been represented and only some are detailed in the description which follows, the non-detailed steps being achievable with the usual microelectronics methods. The implantation masks are not represented, their description being sufficient to understand how they can be positioned.

[0062] In Figures 2, 4A and 4B, the steps are represented on a time axis.

[0063] After a step 201 (STI) of forming isolation regions 140 (initial, non-hollowed isolation regions) in a semiconductor substrate 120, for example isolation trenches, to isolate the future NMOS and PMOS transistors, a step 202 (N Well) of N-type doping is carried out in order to form the N-type well 122 for the PMOS transistor, using an implantation mask adapted to hide the regions which must not be N-doped during this step, then a step 203 (P Well) of P-type doping is carried out in order to form the P-type well 121 for the NMOS transistor, using an implantation mask adapted to hide the regions which must not be P-doped during this step. Each doping step is typically carried out by ion implantation.

[0064] These doping steps for forming the wells are generally carried out through a dielectric layer 210 of the ONO type, for "Oxide Nitride Oxide". Such a dielectric layer can, for example, be used to isolate a polysilicon layer intended to form all or part of a gate region of one or more other transistors positioned on and in another portion of the semiconductor substrate.

[0065] On the portions of the semiconductor substrate 120 delimited by the initial isolation regions 140, the dielectric layer 210 is removed, typically using dry etching, followed by a wet etching step 204 (BOE). The wet etching step 204 is generally carried out using a hydrofluoric acid (HF) solution, so as to remove the residual oxide on the upper face 120A of the semiconductor substrate 120, and this, for each of the future NMOS and PMOS transistors. This wet etching step can be designated by the term BOE, for "Buffered Oxide Etch" in English.

[0066] During the wet etching step 204, a portion of insulation from the insulation regions 140 initials can be removed over a given depth, for example the depth PO, resulting in isolation regions 141 set back relative to the upper face 120A of the substrate 120. The insulator etching depth of the isolation regions 141 can be controlled during this wet etching step, in particular by controlling the duration of contact with the etching solution, for example depending on whether the aim is rather to limit the dislocation phenomenon, or rather to reduce the hump effect. For example, the etching depth in the isolation regions is chosen to be approximately 9 nm when the aim is to favor the reduction of the hump effect, or is chosen to be approximately 23 nm when the aim is to favor the reduction of the dislocation phenomenon.

[0067] Next, a step 205 (GO3 Ox) of oxidation of a portion of the semiconductor substrate 120 from its upper face 120A is carried out in order to form the gate oxide layers 133 / 134, on which the gate regions of the future NMOS and PMOS transistors will then be formed. During this oxidation step, the implants deposited during the doping steps 202, 203 described previously will diffuse into the semiconductor substrate 120.

[0068] Then, after the formation of the gate regions 131 / 132 of the NMOS and PMOS transistors, the oxide layer and the insulating spacer on the sides of each gate region (steps not shown), a step 207 (N+SD) of strong N-type doping is carried out in order to form the source 123 and drain 125 regions of the NMOS transistor 101 (TrN) using an implantation mask adapted to hide the regions which must not be N-doped during this step. Then, a step 208 (P+SD) of strong P-type doping is carried out in order to form the source 124 and drain 126 regions of the PMOS transistor 102 (TrP) using an implantation mask adapted to hide the regions which must not be P-doped during this step.

[0069] A disadvantage of this manufacturing method is that the NMOS and PMOS transistors undergo the same wet etching step, which explains why by varying the wet etching parameters and in particular by increasing the PO depth, it is certainly possible to reduce the dislocations which appear essentially in the NMOS transistor, but this can also contribute to degrading the performance of the PMOS transistor, in particular to increasing the hump effect on the PMOS transistor.

[0070] The inventors propose an electronic circuit comprising NMOS and PMOS transistors, as well as a method for manufacturing such an electronic circuit, making it possible to meet the improvement needs described above, and to overcome all or part of the drawbacks of the electronic circuits and manufacturing methods described above. In particular, the inventors propose an electronic circuit comprising NMOS and PMOS transistors, as well as a method for manufacturing such an electronic circuit which makes it possible to improve the performance of the NMOS transistor, and this, without degrading the performance of the PMOS transistor, or vice versa.

[0071] Embodiments of electronic circuits and methods of manufacturing electronic circuits will be described below. The embodiments described are non-limiting and various variations will become apparent to those skilled in the art from the indications of the present description.

[0072] [Fig. 3] represents an electronic circuit 30 according to one embodiment, comprising adjacent NMOS and PMOS transistors formed in, and on, the same semiconductor substrate 120.

[0073] The electronic circuit 30 differs from the electronic circuits 11, 12 of FIGS. 1A and 1B essentially in that the isolation regions comprise a first isolation region 341 delimiting the active zone ZA1 of the NMOS transistor 101 and a second isolation region 342 delimiting the active zone ZA2 of the PMOS transistor 102. The first isolation region 341 is set back (hollowed out) relative to the upper face 120A of the semiconductor substrate 120 by a first non-zero depth P1. The second isolation region 342 may also be set back (hollowed out) relative to the upper face 120A of the semiconductor substrate 120 by a second depth P2 less than the first depth P1, or even much less. For example, the second depth P2 is substantially zero, as shown, where it can be seen that the second isolation region 342 is substantially flush with the upper face 120A of the semiconductor substrate 120.In other words, more insulation has been removed, for example etched, from the upper face 120A of the semiconductor substrate 120, around the NMOS transistor than around the PMOS transistor.

[0074] Thus, it is possible to improve the performance of the NMOS transistor, and in particular to reduce the probability of the appearance of dislocations in the active zone of the NMOS transistor, while avoiding degrading the performance of the PMOS transistor, in particular by avoiding increasing the hump effect on the PMOS transistor.

[0075] For example, the first depth PI is greater than or equal to 12 nm, for example equal to approximately 23 nm, and the second depth P2 is less than 12 nm, for example equal to approximately 9 nm.

[0076] In the example shown, the first and second isolation regions are joined, i.e. form a continuous isolation region with a step between the NMOS transistor and the PMOS transistor. Alternatively, the first and second isolation regions could be disjoint.

[0077] Optionally, in the case where the hump effect occurs or is increased in the NMOS transistor 101, in particular due to the hollowing of the first isolation region 341, it is possible to seek to attenuate or correct the hump effect. One solution for attenuating this hump effect is to counter-dope locally, for example by ion implantation, the gate region 131 of the NMOS transistor 101, preferably in the zone(s) of overlap where the parasitic transistor(s) are formed. In other words, optionally, at least one local counter-doping zone 350 of the conductivity type opposite to the conductivity of the transistor, in the illustrated case a P-type counter-doping zone, can be provided in the gate region of said transistor, this counter-doping zone being positioned and sized so as to attenuate the hump effect of the NMOS transistor.

[0078] The other characteristics of the electronic circuit 30 may be similar to those of the electronic circuits 11, 12 of FIGS. 1A and 1B, in particular the characteristics of the NMOS and PMOS transistors.

[0079] [Fig.4A] represents a manufacturing method 400 according to an embodiment of an electronic circuit comprising NMOS and PMOS transistors formed in, and on, the same semiconductor substrate, which can be applied to the manufacturing of the electronic circuit 30 of [Fig.3]. The elements identical to those described previously are identified by the same numerical references.

[0080] The manufacturing method 400 of [Fig.4A] differs from the manufacturing method 200 of [Fig.2] essentially in that the wet etching step 404 comprises two etches: - a first etching 404A (BOE 090) in which the initial isolation regions 140 are etched to the same depth, corresponding to the second depth P2, making it possible to form second isolation regions 342; this first etching 404A can be carried out through a first etching mask comprising an opening allowing access to the NMOS and PMOS transistors, or can be carried out without an etching mask, for example if it is not necessary to mask other components of the electronic circuit during this first etching; - a second etching 404B (BOE 230) in which the second isolation regions 342 which are not protected by a second etching mask are etched, up to a first depth PI greater than the second depth P2, making it possible to transform at least one of the second isolation regions into a first isolation region 341 around the NMOS transistor; in other words, in this second etching, the first etching is completed around the NMOS transistor by a second etching to a depth equal to the difference between the first depth PI and the second depth P2.

[0081] The second etch mask is configured to mask at least the PMOS transistor and includes an opening allowing access to at least the NMOS transistor. Thus, the second isolation region 342 is retained around the PMOS transistor.

[0082] When it is indicated that an opening in an etching mask allows access to an NMOS and / or PMOS transistor, this means that this opening allows access to said transistor and to the isolation region which surrounds it.

[0083] For example, the first etching 404A is adapted to intentionally etch the initial isolation regions 140 to the second depth P2.

[0084] Alternatively, the first etching 404A may correspond to the removal of the residual oxide on the semiconductor substrate, without intentionally etching the initial isolation regions 140, for example in the case where the second depth P2 is substantially zero.

[0085] The other steps of the manufacturing method 400 may be similar to those of the manufacturing method 200 of [Fig.2].

[0086] [Fig.4B] represents a variant of the manufacturing method of [Fig.4A], in which a step 406 (nLDD) of light doping of the semiconductor substrate 120 has also been represented so as to form a lightly doped drain region 127, known as the LDD region, from the English "Lightly Doped Drain", between the gate region 131 and the first isolation regions 341 of the NMOS transistor. This light doping step 406 is carried out after step 205 allowing the formation of the gate region 131 of the NMOS transistor, and generally after the deposition of the oxide layer on the sides of the gate region, but before the formation of the insulating spacer (steps not shown), and therefore before the step 207 of strong N-type doping. The gate region 131, generally with the oxide layer on its sides, serves as a protective mask during the light doping operation of the semiconductor substrate to form this N-type LDD region 127.

[0087] Another implantation mask, or LDD mask, is further provided to hide the regions which must not be N-doped during this step. This LDD mask can advantageously be used as a second etching mask to carry out the second etching sub-step, which is carried out before the light doping step 406. This makes it possible to avoid the manufacture of an additional mask.

[0088] There is generally also a step of forming a lightly doped drain region for the PMOS transistor (not shown).

[0089] [Fig.5A] and [Fig.5B] illustrate examples of positioning of the etching masks and / or openings of the etching masks during the etching step of a manufacturing method according to one embodiment.

[0090] Figures 5A and 5B correspond, for example, to layouts of several transistors 501A-501D, 502A-502D in an electronic circuit 50. The transistors 501A-501D (TrN) correspond to NMOS transistors, and there are several NMOS transistors next to each other in the X direction. The transistors 502A-502D (TrP) correspond to PMOS transistors, and there are several PMOS transistors next to each other in the X direction. The plurality of NMOS transistors is adjacent to the plurality of PMOS transistors in the Y direction.

[0091] The active area of ​​each NMOS transistor is surmounted by a gate region 531A-531D. The active areas ZA1B of the NMOS transistors 501B-501D are continuous, i.e. not isolated from each other by isolation regions, and the active area ZA1A of the NMOS transistor 501A is entirely isolated by an isolation region.

[0092] The active area of ​​each PMOS transistor is surmounted by a gate region 532A-532D. The active areas ZA2A of the PMOS transistors 502A-502C are continuous, i.e. not isolated from each other by isolation regions, and the active area ZA2D of the PMOS transistor 502D is entirely isolated by an isolation region.

[0093] As shown in [Fig.5A], the gate regions 531A, 532A of the respective NMOS and PMOS transistors 501A, 502A may be common, or continuous, and likewise for the gate regions 531D, 532D of the respective NMOS and PMOS transistors 501D, 502D.

[0094] The structure shown in [Fig.5A] comprises initial isolation regions 540 around the active areas of the NMOS transistors, around the active areas of the PMOS transistors, and between the NMOS and PMOS transistors. A first etching mask 511 has been positioned above the electronic circuit 50, the first etching mask 511 having a first opening 521 allowing access to the NMOS and PMOS transistors (including portions of the isolation regions surrounding them). This first etching mask makes it possible to implement the first etching sub-step. Alternatively, the first etching mask 511 may be omitted, for example if it is not necessary to mask other transistors or other electronic components of the electronic circuit 50 during this first etching.

[0095] In the structure shown in [Fig.5B], a second etching mask 512 has been positioned above the electronic circuit 50, the second etching mask 512 having a second opening 522 allowing access to the NMOS transistors (including portions of the isolation regions surrounding them), and to mask the PMOS transistors. This second etching mask makes it possible to implement the second etching sub-step.

[0096] The embodiments can be applied to EEPROM memories comprising NMOS and PMOS type transistors, for example EEPROM memories produced on an integrated circuit. The embodiments can also be applied to FLASH memories, or any other technology without integrated memory such as digital or similar technologies. More generally, the embodiments can be applied when it is desired to improve the performance of an NMOS type transistor without degrading that of a PMOS type transistor of the same electronic circuit, or vice versa.

[0097] Various embodiments and variations have been described. The person skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will appear to those skilled in the art. In particular, [Fig. 3] shows an electronic circuit with an NMOS transistor and a PMOS transistor positioned next to each other, and isolated from each other, in the first direction X. Alternatively, the NMOS and PMOS transistors may be positioned next to each other, and isolated from each other, in another direction of the main plane, for example in the second direction Y, as shown in Figures 5A and 5B.Alternatively, the electronic circuit may include multiple NMOS transistors and / or multiple PMOS transistors, wherein some of the NMOS and PMOS transistors may be positioned adjacent to each other, and isolated from each other, in the first direction, and other of the NMOS and PMOS transistors may be positioned adjacent to each other, and isolated from each other, in the second direction. The active areas and / or gate regions may be common to multiple transistors. The electronic circuit may also include other types of transistors, and / or other electronic components.

[0098] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Electronic circuit (30) comprising a plurality of transistors including: - at least one first MOS transistor (101) of a first conductivity type arranged in, and on, at least one first active zone (ZA1) of a semiconductor substrate (120); - at least one second MOS transistor (102) of the second conductivity type opposite to the first conductivity type, the at least one second MOS transistor being arranged in, and on, at least one second active zone (ZA2) of the semiconductor substrate (120); each first active zone (ZA1) being delimited by a first insulation region (341) which is set back relative to a first face (120A) of the semiconductor substrate (120) by a first depth (Pi);and each second active zone (ZA2) being delimited by a second isolation region (342) which is flush with the first face of the semiconductor substrate, or which is set back from the first face of the semiconductor substrate by a second depth (P2) less than the first depth (PI).;

2. Electronic circuit according to claim 1, in which the first face (120A) of the semiconductor substrate (120) is surmounted by gate regions (131, 132) of the at least one first MOS transistor (101) and of the at least one second MOS transistor (102), each gate region being isolated from the semiconductor substrate by a gate insulator layer (133, 134).

3. An electronic circuit according to claim 1 or 2, wherein the at least one first and one second isolation region are isolation trenches, for example shallow isolation trenches.

4. An electronic circuit according to any one of claims 1 to 3, wherein the at least one first and one second isolation region are joined.

5. An electronic circuit according to any one of claims 1 to 4, wherein the first depth (PI) is greater than or equal to 12 nm, and the second depth (P2) is less than 12 nm.

6. Electronic circuit according to any one of claims 1 to 5, wherein the gate region of at least one transistor among the plurality of transistors comprises at least one counter-doping zone (350) of a conductivity type opposite to the conductivity type of said at least one transistor, said at least one counter-doping area being positioned and sized so as to attenuate the bump effect of said at least one transistor, for example said at least one counter-doping area is positioned at an overlap area between the gate region and the active area of ​​said at least one transistor.

7. An electronic circuit according to claim 6, wherein the at least one transistor is the at least one first MOS transistor (101).

8. An electronic circuit according to any one of claims 1 to 7, wherein the first conductivity type is N-type, each first MOS transistor being an NMOS transistor, and the second conductivity type is P-type, each second MOS transistor being a PMOS transistor.

9. An electronic circuit according to any one of claims 1 to 8, wherein the semiconductor substrate comprises silicon, and the at least one first and one second isolation region comprises a silicon oxide, for example silicon dioxide.

10. An electronic circuit according to any one of claims 1 to 9, included in a non-volatile memory, for example an electrically erasable and programmable non-volatile memory.

11. A method of manufacturing (400) an electronic circuit comprising a plurality of transistors including: - at least one first MOS transistor (101) of a first conductivity type arranged in, and on, at least one first active area (ZA1) of a semiconductor substrate (120); - at least one second MOS transistor (102) of the second conductivity type opposite to the first conductivity type, the at least one second MOS transistor being arranged in, and on, at least one second active area (ZA2) of the semiconductor substrate (120); the manufacturing method comprising forming at least one first (341) and one second (342) isolation region configured so that: each first active area (ZA1) is delimited by a first isolation region (341) set back from a first face (120A) of the semiconductor substrate (120) by a first depth (Pi);and each second active zone (ZA2) is delimited by a second isolation region (342) flush with the first face of the semi-substrate;

12.

13.

14.

15. conductive, or set back from the first face of the semiconductor substrate by a second depth (P2) less than the first depth (PI). The method of claim 11, wherein forming the at least one first and one second isolation regions comprises forming the at least one second isolation region (342); and then forming the at least one first isolation region (341). Method according to claim 11 or 12, wherein the formation of the at least one first and one second isolation regions comprises a step of etching initial isolation regions (140) delimiting the first active zone (ZA1) and the second active zone (ZA2), said etching step comprising: - a first etching (404A) of the initial isolation regions (140) from the first face (120A) of the semiconductor substrate (120) and up to the second depth (P2), so as to form second isolation regions (342); then - a second etching (404B) of at least one of the second isolation regions (342), from the first face (120A) of the semiconductor substrate (120) and up to the first depth (PI), so as to form the at least one first isolation region (341); the second etching being carried out through a second etching mask (512) configured to access each first transistor and mask each second transistor. The method of claim 13, wherein the first etching is performed through a first etching mask (511) configured to access each first transistor and each second transistor. An integrated circuit comprising an electronic circuit according to any one of claims 1 to 10.

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