MEMORY DEVICE COMPRISING LARGE CONTACT SURFACES BETWEEN THE CONDUCTION CHANNEL AND THE CONTACT REGIONS

Abstract

Memory device (100) comprising a memory stack (158) electrically connected in series with a selection transistor, comprising: - a semiconductor layer (120) of which first zones (122) are superimposed and form a channel; - an electrostatic control gate (110) and a gate dielectric layer (112) such that portions of the gate dielectric layer are each disposed between a portion (106, 108) of the gate and one of the first zones; - dielectric spacers (114) disposed against flanks of the gate; - contact regions (116, 118) electrically coupled to the first zones by second zones (124) of the semiconductor layer extending between the contact regions and the spacers, one of the contact regions (118) comprising the memory stack; and in which the second zones form, with the first zones, a continuous layer. Figure for the abridged version: figure 16.

Description

Title of the invention: MEMORY DEVICE COMPRISING LARGE CONTACT SURFACES BETWEEN THE CONDUCTION CANAL AND CONTACT REGIONS Technical field

[0001] The invention relates to the field of microelectronic devices applied to advanced CMOS technologies. The invention relates in particular to memory devices, for example of the 1T1R, 1T1C, 2T1R, 2T1C type, of the OxRAM (Oxide Random Access Memory) or FeRAM (Ferroelectric Random Access Memory) or CBRAM (Conductive-Bridging Random Access Memory), and the production of such memory devices. State of the prior art

[0002] The miniaturization of electronics is constantly increasing, but the industry is now approaching the scaling limit for conventional materials such as silicon. Lately, 2D materials have emerged as promising candidates for use in miniaturized electronic and optoelectronic devices due to their unique properties and the very thin layers of these materials which can consist of a single layer of atoms or molecules.

[0003] The paper by KP O'Brien et al., "Advancing 2D Monolayer CMOS Through Contact, Channel and Interface Engineering," 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 7.1.1-7.1.4, proposes to produce a MOSFET transistor by integrating a layer of MoS2 to form the conduction channel. This layer is connected to two metallic source and drain regions based on gold, palladium, TiN, tungsten or nickel. The rear gate is formed by a layer of doped silicon positioned on the rear face under a dielectric layer based on SiO2, HfO2 or Al2O3.

[0004] In order to overcome the constraints linked to the deposition of metallic materials of the contact regions (conductive regions through which the conduction channel of the device is electrically accessible, and corresponding for example to the source and drain regions in the case of a transistor) on the 2D material, it is possible to form these regions not on the upper face of the 2D material layer, but against the sides of the 2D material layer. This configuration, called "side contact", is however problematic because the contact surface between the layer of 2D material and the contact regions is low, which results in large contact resistances at the interfaces between the 2D material layer and the contact regions.

[0005] Document US 2022 / 045176 A1 describes several methods for producing gate-last type FET transistors, in which silicon portions serve as a support for the deposition of a layer of 2D material. In addition to the disadvantages linked to the fact that the transistors produced have side contact type channel / source-drain interfaces, the silicon portions used to deposit the 2D material form a potential barrier at the interface with the 2D material, which is not favorable because part of the charge transport can take place in these silicon portions and not in the 2D material.

[0006] These problems are also found for microelectronic devices other than FET transistors, such as for example memory devices including a transistor. Statement of the invention

[0007] An aim of the present invention is to propose a memory device whose structure is compatible with any type of semiconductor material including 2D materials, and which does not have the disadvantages of a “side contact” configuration.

[0008] For this, the present invention proposes a memory device comprising at least one memory stack electrically connected in series with a selection transistor, the memory device comprising a substrate on which the selection transistor comprises: - a semiconductor layer comprising several first zones superimposed on one another, the first zones forming an electrical conduction channel of the selection transistor; - an electrostatic control gate and a gate dielectric layer of the selection transistor, portions of the gate dielectric layer each being disposed between a portion of the electrostatic control gate and one of the first regions of the semiconductor layer; - dielectric spacers arranged against sides of the electrostatic control grid; - contact regions electrically coupled to the first areas of the semiconductor layer by second areas of the semiconductor layer, the second areas of the semiconductor layer extending between the contact regions and the dielectric spacers, the contact regions forming source / drain regions of the selection transistor, wherein one of the contact regions comprises the memory stack interposed between a first conductive portion, electrically connecting the memory stack to the semiconductor layer, and a second conductive portion forming an electrical contact of the memory stack; and wherein the second regions of the semiconductor layer are not arranged directly against the electrostatic control gate and form, with the first regions, a continuous layer.

[0009] The proposed memory device is based on an architecture not comprising a “side contact” type interface between the channel and the contact regions thanks to the second zones of the semiconductor layer providing the electrical coupling between the channel formed by the first zones of the semiconductor layer and the contact regions. These second zones of the semiconductor layer, which extend against at least part of the side walls, or flanks, of the contact regions, form a large contact surface with the contact regions, which makes it possible to reduce the contact resistances of these contact regions. Thus, the electric current flowing in the channel is not reduced because of these contact resistances, which does not reduce the performance of the device.

[0010] Furthermore, with the proposed architecture, the semiconductor layer can be produced after the electrostatic control gate and before the contact regions are produced. Thus, the semiconductor layer, the first areas of which are intended to form the conduction channel, is not damaged by the steps related to the production of the electrostatic control gate. This is particularly advantageous when the semiconductor layer comprises a 2D material.

[0011] Furthermore, the production of such a device does not require preserving portions of silicon to deposit the semiconductor layer intended to form the channel, thus eliminating the problem of potential barrier at the interface with the material of the semiconductor layer.

[0012] The memory device comprises a “GAA stacked-nanosheet” type architecture, or with stacked nanosheets and a fully enclosing gate.

[0013] In the memory device, one of the contact regions corresponds to an access electrode of the memory device, and the other contact region comprises a memory stack, i.e. a stack of materials configured to carry out information storage. Such a memory stack corresponds for example to a MIM (metal - insulator - metal) type stack.

[0014] One or more of these contact regions may be common to several memory devices produced on the same substrate.

[0015] The semiconductor layer may comprise a two-dimensional material or any other semiconductor material deposited by MOCVD (“Metal Organic Chemical Vapor Deposition (Vapor Deposition), CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition). In this case, the memory device can be made with very small dimensions.

[0016] The memory device may be such that: - each of the contact regions is arranged in a cavity comprising side walls formed at least by the dielectric spacers and by a dielectric insulating material; - the second zones of the semiconductor layer cover at least part of the walls of the cavities in which the contact regions are arranged.

[0017] In the above configuration, the contact surfaces of the contact regions with the semiconductor layer are maximized by using the surface of the walls of the cavities, and advantageously the entire surface of the walls of the cavity, to form the contact between the second zones of the semiconductor layer and the contact regions, which makes it possible to have very low contact resistances of these regions, and therefore a higher current flowing through the conduction channel of the device.

[0018] The selection transistor may be such that each of the first zones of the semiconductor layer may be surrounded by the same electrostatic control gate or by an electrostatic control gate different from that surrounding the other first zones of the semiconductor layer.

[0019] In a first embodiment option, the selection transistor may further comprise one or more dielectric portions each surrounded by one of the first zones of the semiconductor layer and such that each of the dielectric portions is surrounded by the first zones of the semiconductor layer. These dielectric portions may be used to fill one or more spaces between the first zones of the semiconductor layer.

[0020] In a second embodiment option, each of the first zones of the semiconductor layer does not surround a dielectric portion.

[0021] The selection transistor may further comprise internal dielectric spacers disposed against flanks of one or more portions of the electrostatic control gate. Such internal spacers are advantageous because they make it possible to reduce parasitic capacitances within the device.

[0022] The memory stack may comprise a layer of ferroelectric material or an oxide layer or an ionic layer.

[0023] The invention also relates to a microelectronic component comprising several memory devices as described previously, and in which: - the electrostatic control gates of the selection transistors of several of the memory devices are common and formed by the same portions of material, and / or - one of the contact regions is common to two neighboring memory device selection transistors.

[0024] The invention also relates to a method for producing at least one memory device comprising at least one memory stack electrically connected in series with a selection transistor, comprising: a) producing, on a substrate, at least one alternating stack of portions of a first material and portions of a second material, the first and second materials being capable of being etched selectively with respect to one another, then b) creation of a temporary grid covering part of an upper face and side faces of the stack, then c) production of dielectric spacers against the sides, or side walls, of the temporary grid, then d) etching of parts of the stack not covered by the temporary gate and dielectric spacers, then

[0025] e) engraving of the temporary grid, then

[0026] f) etching the portions of the first material selectively with respect to the portions of the second material, then

[0027] g) producing at least part of an electrostatic control gate of the selection transistor in a space formed by etching the temporary gate, such that the dielectric spacers are arranged against the sides of the electrostatic control gate, then

[0028] h) etching the portions of the second material, then i) producing a semiconductor layer, advantageously a 2D material whose thickness can be between 1 and 5 atomics, comprising several first zones configured to form an electrical conduction channel of the selection transistor and arranged against the gate in locations formed by the etching of the portions of the second material, the semiconductor layer extending, without discontinuity with the first zones, by forming second zones covering at least part of the sides of the dielectric spacers and which are not arranged directly against the electrostatic control gate, then

[0029] j) producing, on the substrate, contact regions electrically coupled to the first zones of the semiconductor layer by the second zones of the semiconductor layer, each second zone of the semiconductor layer extending between the contact regions and the dielectric spacers, the contact regions forming source / drain regions of the selection transistor, one of the contact regions comprising the memory stack interposed between a first conductive portion, electrically connecting the memory stack to the semiconductor layer, and a second conductive portion forming an electrical contact of the memory stack.

[0030] The method may further comprise, before implementing step c), a deposition of a dielectric insulating material around the dielectric spacers, then an etching of cavities in the dielectric insulating material such that each of the cavities comprises at least one side wall formed by one of the dielectric spacers, and: - step i) can be implemented such that the second zones of the semiconductor layer cover at least part of the side walls of the cavities, and - step j) can be implemented such that each of the contact regions is arranged in one of the cavities.

[0031] The method may further comprise a step of depositing a gate dielectric of the selection transistor implemented: - between steps f) and g), in the space formed by the etching of the temporary gate, the electrostatic control gate of the selection transistor being in this case produced on the gate dielectric, and / or - between steps h) and i), in the locations formed by the etching of the portions of the second material, the semiconductor layer being in this case produced by covering the gate dielectric.

[0032] According to a first embodiment option, step i) can be implemented such that the first zones of the semiconductor layer cover walls of the locations formed by the etching of the portions of the second material, and the method can further comprise, between steps i) and j), a production of dielectric portions in remaining spaces of the locations and such that each of the dielectric portions is surrounded by the first zones of the semiconductor layer.

[0033] According to a second embodiment option, step i) can be implemented such that the first areas of the semiconductor layer fill the locations formed by the etching of the portions of the second material.

[0034] The method may further comprise, between steps d) and e), an etching of parts of the portions of the first material arranged directly above the dielectric spacers, and a production of internal dielectric spacers in place of the etched parts of the portions of the first material.

[0035] Throughout the document, the terms "on" and "under" are used without distinction of the orientation in space of the element to which this term relates. For example, in the characteristic "on a face of the first substrate", this face of the first substrate is not necessarily oriented upwards but may correspond to a face oriented in any direction. Furthermore, the arrangement of a first element on a second element must be understood as being able to correspond to the arrangement of the first element directly against the second element, without any intermediate element between the first and second elements, or as being able to correspond to the arrangement of the first element on the second element with one or more intermediate elements arranged between the first and second elements.

[0036] Throughout the document, the term “layer” may refer to a single layer or a stack of multiple layers.

[0037] Throughout the document, the expression "electrically couple" is used to designate an electrical connection which may be direct or which may be indirect (i.e. made through one or more intermediate electrical elements). Brief description of the drawings

[0038] The present invention will be better understood on reading the description of exemplary embodiments given purely for informational purposes and in no way limiting, with reference to the appended drawings in which: [Fig.l] [Fig.2] [Fig.3] [Fig.4] [Fig.5] [Fig.6] [Fig.7] [Fig.8] [Fig.9] [Fig.10] [Fig.11] [Fig.12] [Fig.13] [Fig.14] [Fig. 15], and

[0039] [Fig. 16] schematically represent the steps of a method for producing a memory device, object of the present invention, according to a particular embodiment; [Fig.17] [Fig.18] [Fig. 19], and [Fig.20] schematically represent part of the steps of a method for producing the memory device, object of the present invention, according to an alternative embodiment.

[0040] Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the transition from one figure to another.

[0041] The different parts represented in the figures are not necessarily on a uniform scale, in order to make the figures more readable.

[0042] The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with each other.

[0043] Detailed description of particular embodiments

[0044] An example of a method for producing a memory device 100 comprising at least one memory stack 158 electrically connected in series to a selection transistor, according to a particular embodiment, is described below in connection with FIGS. 1 to 16. In these figures, the simultaneous production of several memory devices 100 is shown, these devices being part of an electronic component 1000.

[0045] An alternating stack of layers comprising a first material and a second material capable of being selectively etched with respect to one another is first produced on a substrate 102. According to an advantageous example, the first and second materials correspond respectively to Si and SiGe. Other pairs of first and second materials are also possible: SiGe and Ge, Ge and GeSn, SiO 2 and amorphous silicon (a-Si). More generally, it may be envisaged to use, to form this alternation of layers of the first and second materials, two semiconductors capable of being selectively etched with respect to one another, or a dielectric material and an amorphous semiconductor.

[0046] The number of layers of this stack depends on the number of levels of semiconductor material desired to form the channel of the device 100. In the exemplary embodiment described in connection with FIGS. 1 to 16, the stack of layers comprises four layers of silicon stacked alternately with three layers of SiGe. Advantageously, the number of layers of the first material is between 2 and 10, and the number of layers of the second material is between 1 and 10.

[0047] By way of example, each of the layers of the stack has a thickness of between 5 nm and 25 nm, and for example equal to 12 nm.

[0048] In the embodiment described in connection with FIGS. 1 to 16, the substrate 102 corresponds to an SOI substrate, i.e. comprising a surface layer of silicon forming the first layer of the stack produced and which is arranged on a buried dielectric layer 130 comprising for example SiO2. The buried dielectric layer 130 is arranged on a support layer 132 comprising for example silicon. Alternatively, the substrate 102 may correspond to a substrate of type other than SOI, for example a “bulk” substrate, or massive substrate, of semiconductor (for example silicon).

[0049] An etching of the stack of layers produced is then implemented in order to form, on the substrate 102 (on the buried dielectric layer 130 in this example), at least one stack 134 alternating portions 136 of the first material and portions 138 of the second material. In [Fig.l], six distinct stacks 134 are shown, each comprising four portions 136 and three portions 138 stacked alternately on top of each other.

[0050] Each of the stacks 134 has a substantially elongated shape, that is to say has a length (dimension along the X axis) greater than its width (dimension along the Y axis). The width of each stack 134 is for example between 20 nm and 200 nm, and the length of each stack 134 is for example greater than 100 nm.

[0051] A thin dielectric layer 140, the thickness of which is less than 10 nm and for example equal to 7 nm or 4 nm, is then deposited in a conformal manner over the entire structure, that is to say by covering the upper faces and the lateral faces of the stacks 134 and the parts of the substrate 102 (of the buried dielectric layer 130 in the exemplary embodiment described) not covered by the stacks 134. The dielectric layer 140 comprises for example SiO2, which can be obtained from TEOS.

[0052] At least one temporary grid 142 is then produced, covering a portion of an upper face and side faces of the stacks 134.

[0053] For this, a material suitable for producing the temporary gates is deposited over the entire structure. Advantageously, the deposited material is polycrystalline silicon. The thickness of the deposited material is greater than the sum of the thicknesses of one of the stacks 134 and the dielectric layer 140, for example equal to 380 nm. A planarization, for example a CMP (chemical-mechanical planarization), of the deposited material is then implemented so that a given thickness, for example equal to 70 nm, is maintained above the stacks 134. A hard mask 144 is then produced on the material remaining after the planarization, the pattern of this hard mask defining that of the temporary gate(s) 142 to be produced. For example, the hard mask 144 comprises a semiconductor nitride / semiconductor oxide bilayer such as SiN / SiO2.The remaining material suitable for producing the temporary grids is then etched in accordance with the pattern defined by the hard mask 144, forming the temporary grid(s) 142. In the example described, several temporary grids. poraries 142 are made (three temporary grids 142 are visible in [Fig.2], each formed by covering the six stacks 134).

[0054] By way of example, the width (dimension along the X axis visible in [Fig.2]) of each temporary gate 142 is for example between 10 nm and several hundred nm, and the length (dimension along the Y axis visible in [Fig.2]) of each temporary gate 142 depends on the number of stacks 134 on which the temporary gates 142 must be produced, and for example equal to several tens of nm.

[0055] Dielectric spacers 114 are then produced against the sides of the temporary gates 142. For this, a layer of material suitable for producing these spacers 114 is deposited in a conformal manner over the entire structure, i.e. by covering the upper faces and the lateral faces of the stacks 134, the temporary gates 142 and the hard masks 144 and the parts of the substrate 102 (of the buried dielectric layer 130 in the embodiment described) not covered by the stacks 134 and the temporary gates 142. This material suitable for producing the dielectric spacers 114 corresponds for example to SiN, SiCO or SiBCN. The thickness of this layer is for example between 5 nm and 15 nm.

[0056] An anisotropic etching of this layer is then implemented such that remaining portions of this layer arranged against the sides of the temporary gates 142 form the dielectric spacers 114 (see [Fig. 3]). Remaining portions 146 of this layer arranged against the sides of the stacks 134 can be kept at the end of this etching, or advantageously be removed. The anisotropic etching is implemented so as to remove the material located on the upper faces of the temporary gates 142 and the stacks 134. In addition, this etching also removes the parts of the layer 140 which are not covered by the temporary gates 142 and the dielectric spacers 114.

[0057] The parts of the stacks 134 not covered by the temporary gates 142, by the dielectric spacers 114 or by the remaining portions 146 are etched. This etching is stopped on the buried dielectric layer 130. The remaining parts of the portions 136 are then etched partially and selectively with respect to the remaining parts of the portions 138, so as to form, directly above the dielectric spacers 114, spaces 148 above and below the ends of the remaining parts of the portions 138 (see [Fig. 4]). The depth (dimension along the X axis in [Fig. 4]) etched in the remaining parts of the portions 136 is for example between 5 nm and 15 nm.

[0058] The internal dielectric spacers 115 are then made in the spaces 148 previously formed. These internal dielectric spacers 115 are obtained in depositing a dielectric material, for example SiN, SiBCN or SiCO so as to at least fill the spaces 148. The material deposited outside the spaces 148 is etched isotropically so as to retain only the internal dielectric spacers 115 (see [Fig.5]).

[0059] A dielectric insulating material 128, for example SiO2, is then deposited around the dielectric spacers 114. For this, the dielectric insulating material 128 is deposited with a large thickness, then planarization is implemented until the hard mask 144 is reached. The hard mask 144 is then removed for example by wet etching, for example using a diluted H3PO4 solution and used at a temperature of 110°C. The temporary gates 142 are then removed, for example by etching using a 0.5% diluted HF solution combined with a 1% diluted HCl solution and with a 5% TMAH solution. This etching is stopped when the remaining parts of the dielectric layer 140 are reached (see [Fig.6]).

[0060] The remaining portions of the dielectric layer 140 are then etched, and then the remaining portions of the portions 136 are selectively etched with respect to the remaining portions of the portions 138, for example by implementing wet etching. The structure obtained at this stage is shown in [Fig.7].

[0061] At least one layer 112 intended to form the gate dielectrics of the selection transistors of the memory devices 100 is then deposited in a conformal manner, in particular in the spaces formed by the etching of the temporary gates 142 by covering the walls formed by the dielectric spacers 114 and the remaining parts of the portions 138. For example, this layer comprises for example a high-K dielectric material (with high dielectric permittivity) such as HfO2. Alternatively, this layer 112 intended to form the gate dielectrics may comprise SiO2 or Al2O3 or any other suitable material or combination of materials.

[0062] Electrostatic control gates 110 of the selection transistors of the memory devices 100 are produced by depositing one or more conductive materials on the layer 112 intended to form the gate dielectrics of the selection transistors, by a first deposition of a thin layer of TiN (thickness for example equal to 3 nm) on which is stacked a layer of tungsten with a thickness for example equal to 200 nm. In the example visible in [Fig. 8], each of the gates 110 comprises an upper part 106 and other parts 108 surrounding the remaining parts of the portions 138. It is furthermore possible that the gates 110 comprise one or more materials different from TiN and W, such as for example doped polysilicon or any other metal (Mo, etc.).

[0063] A planarization with stop on the dielectric insulation material 128 is implemented to remove the material(s) from the layer 112 intended to form the di electric grids and electrostatic control grids 110 deposited outside the spaces formed by the etching of the temporary grids 142.

[0064] An etching of a portion of the insulating dielectric material 128 is then carried out so as to form cavities 150 comprising side walls formed by the dielectric spacers 114, the internal dielectric spacers 115 and, in the example described here, remaining portions of the insulating dielectric material 128 (see [Fig. 9]). These cavities 150 form locations for the production of the contact regions of the devices 100.

[0065] The portions 138 are then etched, for example by implementing chemical etching using a Hf-H2O2 solution (see figures 10 and 11) when the portions 138 comprise SiGe. As can be seen in [Fig. 11] representing a sectional view along the axis XX' shown in [Fig. 10], this etching forms tunnel-shaped spaces in which the channels of the transistors are intended to be produced.

[0066] A semiconductor layer 120 is then deposited over the entire structure produced at this stage of the process (see FIGS. 12 and 13). First zones 122 of this semiconductor layer 120 which are located in the tunnel-shaped spaces previously formed are intended to form the channels of the selection transistors and are arranged against the gate dielectrics. Second zones 124 of this semiconductor layer 120 which cover the walls (side walls and bottom walls in the example described here) of the cavities 150 are intended to be in contact with the contact regions which will subsequently be produced. The deposition is carried out without discontinuity, or without interruption, between the first and second zones 122 and 124.

[0067] Advantageously, the semiconductor layer 120 comprises at least one 2D semiconductor material, for example a transition metal dichalcogenide such as MoS2, or WSe2, or WS2, or MoTe2. It is also possible that the material of the semiconductor layer 120 corresponds to IGZO, In2O3, IWO, ITO, or an amorphous semiconductor oxide, or any other suitable semiconductor material.

[0068] One or more dielectric layers, comprising for example Al2O3 (or HfO2) and / or SiO2 (or a low-k dielectric, or with low dielectric permittivity), are then deposited and then isotropically etched in order to retain only portions 126 located in the tunnel-shaped spaces (see figures 14 and 15). These portions 126 form dielectric bars each surrounded by one of the first zones 122 of the semiconductor layer 120. Thus, the semiconductor layer 120 comprises several first zones 122 superimposed on each other by means of a succession of bars 126 and parts 108 of the 110 grid and grid dielectrics.

[0069] Finally, contact regions 116, 118 are produced by depositing, in the example described, one or more metallic materials in the cavities 150 (see [Fig. 16]). Before this or these metallic deposits, it is possible to deposit a layer of graphene in the cavities 150, this or these metals then being deposited on the layer of graphene. Advantageously, the contact regions 116, 118 comprise at least one metallic material such as gold, palladium, TiN, W, Ni, etc. According to an exemplary embodiment, each of the contact regions 116, 118 comprises a layer of TiN on which a portion of tungsten is formed. Different metals can be used to form the contact regions 116, 118 in order to promote low contact resistances, such as for example: S, Bi, Sn, Pd, Ru, Cu, Ni, Ti, TiN, W, Au, etc. These materials can also be modified later (to improve their properties), for example by a doping step.These contact regions 116, 118 form the source / drain regions of the selection transistors of the memory devices 100.

[0070] Furthermore, the contact region 118 comprises a memory stack 158, that is to say a stack of materials in which it is possible to carry out information storage. This memory stack 158 may correspond to a stack of materials of the FeRAM type including in this case a layer of ferroelectric material, or OxRAM including in this case an oxide layer, or CB RAM including in this case an ionic layer, for example a stack of the MIM (metal-insulator-metal) type.

[0071] This memory stack 158 is arranged within the metallic material(s) forming the remainder of the contact region 118. A portion of the metallic material(s) is interposed between the memory stack 158 and the portions of the semiconductor layer 120 located in the cavity 150 in which the contact region 118 is made. Thus, the memory stack 158 is interposed between a first conductive portion 157 of the contact region 118, electrically connecting the memory stack 158 to the semiconductor layer 120, and a second conductive portion 156 of the contact region 118 forming an electrical contact of the memory stack 158.

[0072] These contact regions 116 and 118 are electrically coupled to the first zones 122 of the semiconductor layer 120 via the second zones 124 of the semiconductor layer 120 which extend between the contact regions 116, 118 and the dielectric spacers 114 as well as against the other walls of the contact regions 116, 118 located in the cavities 150. The material of these regions deposited outside the cavities 150 is removed by implementing planarization with a stop on the dielectric insulation material 128.

[0073] The devices obtained at the end of this process correspond to the devices 100 shown in [Fig.16].

[0074] In the embodiment described above, the semiconductor layer 120 does not completely fill the spaces formed by the etching of the portions 138, and dielectric portions 126 are produced in the remaining spaces after the deposition of the semiconductor layer 120.

[0075] According to a first variant, it is possible not to produce the dielectric portions 126, the semiconductor layer 120 filling in this case, during its deposition, the remaining spaces formed by the etching of the portions 138. In this case, it is possible to observe the formation of air gaps, that is to say hollows or empty spaces, in the first zones 122 of the semiconductor layer 120. Nevertheless, these air gaps do not prevent continuity between the first zones 122 and the second zones 124 of the semiconductor layer 120.

[0076] According to another variant (which is compatible with the first variant above), it is possible that the layer 112 forming the gate dielectric of the selection transistor of the memory device 100 is not deposited just before the production of the gate 110 as previously described, but that this layer is deposited in the spaces formed by the etching of the portions 138 and in the cavities 1150, just before the deposition of the semiconductor layer 120. In this case, the layer 112 covers the different walls on which the material of the semiconductor layer 120 is intended to be deposited, thus homogenizing the surfaces, and therefore the interfaces, against which the semiconductor layer 120 is then deposited.

[0077] According to another variant (which is compatible with the first variant described above), it is possible for the layer 112 to be deposited during two different steps: firstly just before the production of the gate 110 as previously described in connection with [Fig. 8], then in the spaces formed by the etching of the portions 138 and in the cavities 150, just before the deposition of the semiconductor layer 120. In this case, the parts of the layer 112 located directly above the gate 110 are thicker than the other parts of the layer 112 because these parts combine the thicknesses of material deposited during the two deposition steps.

[0078] In the previously described embodiment, all the side walls of the cavities 150 are covered by the second zones 124 of the semiconductor layer 120. As a variant, it is possible for only a portion of these side walls to be covered by the second zones 124.

[0079] Figures 17 to 20 schematically represent part of the steps of the method implemented combining the two variants described above.

[0080] The steps previously described in connection with Figures 1 to 12 are first implemented.

[0081] Then, unlike the previous embodiment in which the semiconductor layer 120 is deposited, the layer 112 forming the gate dielectrics, advantageously comprising a high-K dielectric material such as HfO2, is deposited over the entire structure (see [Fig. 17]). Parts of this layer 112 are located in the tunnel-shaped spaces previously formed, thus forming the gate dielectrics, and other parts of this layer 112 cover the walls of the cavities 150.

[0082] The semiconductor layer 120 is then deposited over the entire structure, covering the layer 112 forming the gate dielectrics (see [Fig. 18]), so as to completely fill the remaining tunnel-shaped spaces. The cavities 150 are not completely filled by the deposition of the semiconductor layer 120 and the layer 112 forming the gate dielectrics.

[0083] The contact regions 116, 118 are then produced, for example by carrying out a first deposition (for example ALD) of TiN (designated by the reference 154 in [Fig. 19]), then by filling the rest of the available space with tungsten (designated by the reference 156 in [Fig. 20]). In the example described here, this deposition of tungsten also completes the production of the control gate 110. Furthermore, during the deposition of tungsten, it is stopped to produce the memory stack 158 within the contact region 118, then resumed to complete the production of the contact regions 116, 118.

[0084] One of the above variants can be implemented without the other being implemented. For example, it is possible to deposit the layer 112 forming the gate dielectric in the spaces formed by the etching of the portions 138, before the deposition of the semiconductor layer 120, and for empty spaces to still be present after the deposition of the semiconductor layer 120. In this case, the dielectric portions 126 can be produced as previously described in connection with FIGS. 14 and 15.

[0085] In the embodiment shown in [Fig. 16], the control grid 110 is common to several devices 100, that is to say simultaneously controls these different devices, the contact regions 116, 118 of which are electrically isolated from those of the other neighboring devices 100 by the portions of the dielectric insulating material 128. As a variant, it is possible that the grids 110 produced are not common to the different devices 100 produced.

[0086] Furthermore, each of the first zones 122 of the semiconductor layer 120 may be surrounded by the same electrostatic control grid 110, as is the case in the examples previously described, or by an electrostatic control grid different from that surrounding the other first zones 122 of the semiconductor layer 120.

[0087] In the embodiment shown in [Fig.16], each of the regions of contact 116, 118 is arranged in a cavity comprising side walls formed by the dielectric spacers 114, 115 and by a dielectric insulating material 128. In this configuration, the second zones 124 of the semiconductor layer 120 cover the side walls and the bottom walls of the cavities in which the contact regions 116, 118 are arranged.

[0088] Alternatively, it is possible for contact regions to be common to several devices 100. For example, it is possible that for two adjacent devices 100, the dielectric insulation material 128 is not present so that the same contact region, for example the contact region 118 including the memory stack 158, is electrically coupled to the channels of these two neighboring devices 100. Such a configuration allows for example the production of memory devices of the 2T1R or 2T1C type.

Claims

Claims

1. A memory device (100) comprising at least one memory stack (158) electrically connected in series with a selection transistor, the memory device (100) comprising a substrate (102) on which the selection transistor comprises: - a semiconductor layer (120) comprising several first regions (122) superimposed on one another, the first regions (122) forming an electrical conduction channel of the selection transistor; - an electrostatic control gate (110) and a gate dielectric layer (112) of the selection transistor, portions of the gate dielectric layer (112) each being disposed between a portion (106, 108) of the electrostatic control gate (110) and one of the first regions (122) of the semiconductor layer (120); - dielectric spacers (114) arranged against sides of the electrostatic control grid (110);- contact regions (116, 118) electrically coupled to the first areas (122) of the semiconductor layer (120) by second areas (124) of the semiconductor layer (120), the second areas (124) of the semiconductor layer (120) extending between the contact regions (116, 118) and the dielectric spacers (114), the contact regions (116, 118) forming source / drain regions of the selection transistor, wherein one of the contact regions (118) comprises the memory stack (158) interposed between a first conductive portion (157), electrically connecting the memory stack (158) to the semiconductor layer (120), and a second conductive portion (156) forming an electrical contact of the memory stack (158);and wherein the second regions (124) of the semiconductor layer (120) are not disposed directly against the electrostatic control gate (110) and form, with the first regions (122), a continuous layer.;

2. The memory device (100) of claim 1, wherein the semiconductor layer (120) comprises a two-dimensional material or any other semiconductor material deposited by MOCVD, CVD or ALD.

3. Memory device (100) according to one of the preceding claims, wherein: - each of the contact regions (116, 118) is arranged in a cavity (150) comprising side walls formed at least by the dielectric spacers (114) and by a dielectric insulating material (128); - the second zones (124) of the semiconductor layer (120) cover at least part of the walls of the cavities (150) in which the contact regions (116, 118) are arranged.

4. Memory device (100) according to one of the preceding claims, wherein the selection transistor is such that each of the first zones (122) of the semiconductor layer (120) is surrounded by the same electrostatic control gate (110) or by an electrostatic control gate (110) different from that surrounding the other first zones (122) of the semiconductor layer (120).

5. Memory device (100) according to one of the preceding claims, wherein the selection transistor further comprises one or more dielectric portions (126) each arranged between two first zones (122) of the semiconductor layer (120) and such that each of the dielectric portions (126) is surrounded by the first zones (122) of the semiconductor layer (120).

6. A memory device (100) according to one of the preceding claims, wherein the selection transistor further comprises internal dielectric spacers (115) disposed against flanks of one or more portions (108) of the electrostatic control gate (110).

7. Memory device (100) according to one of the preceding claims, wherein the memory stack (158) comprises a layer of ferroelectric material or an oxide layer or an ionic layer.

8. Microelectronic component (1000) comprising several memory devices (100) according to one of the preceding claims, and in which: - the electrostatic control gates (110) of the selection transistors of several of the memory devices (100) are common and formed by the same portions of material, and / or - one of the contact regions (116, 118) is common to two selection transistors of neighboring memory devices (100).

9. Method for producing a memory device (100) comprising at least one memory stack (158) electrically connected in series with a selection transistor, comprising: a) producing, on a substrate (102), at least one stack (134) alternating portions of a first material (136) and portions of a second material (138), the first and second materials being capable of being selectively etched with respect to one another, then b) producing a temporary grid (142) covering part of an upper face and side faces of the stack (134), then c) production of dielectric spacers (114) against sides of the temporary grid (142), then d) etching parts of the stack (134) not covered by the temporary gate (142) and the dielectric spacers (114), then e) engraving of the temporary grid (142), then f) etching the portions of the first material (136) selectively with respect to the portions of the second material (138), then g) producing at least part of an electrostatic control gate (110) of the selection transistor in a space formed by etching the temporary gate (142), such that the dielectric spacers (114) are arranged against the sides of the electrostatic control gate (110), then h) etching the portions of the second material (138), then i) producing a semiconductor layer (120) comprising several first zones (122) configured to form an electrical conduction channel of the selection transistor and arranged against the gate (110) in locations formed by etching the portions of the second material (138), the semiconductor layer (120) extending, without discontinuity with the first zones (122), forming second zones (124) covering at least part of the sides of the dielectric spacers (114) and which are not arranged directly against the electrostatic control gate (110), then j) producing, on the substrate (102), contact regions (116, 118) electrically coupled to the first zones (122) of the semiconductor layer (120) by the second zones (124) of the semiconductor layer (120), each second zone (124) of the semiconductor layer (120) extending between the contact regions (116, 118) and the dielectric spacers (114),the contact regions (116, 118) forming source / drain regions of the selection transistor, one of the contact regions (118) comprising the memory stack (158) interposed between a first conductive portion (157), electrically connecting the memory stack (158) to the semiconductor layer (120), and a second conductive portion (156) forming a contact, electrical of the memory stack (158), wherein the method further comprises providing a gate dielectric layer of the selection transistor such that portions of the gate dielectric layer are each disposed between a portion of the electrostatic control gate and one of the first regions of the semiconductor layer.

10. The method of claim 9, further comprising, between steps d) and e), depositing an insulating dielectric material (128) around the dielectric spacers (114), then etching cavities (150) in the insulating dielectric material (128) such that each of the cavities (150) comprises at least one side wall formed by one of the dielectric spacers (114), and wherein: - step i) is implemented such that the second areas (124) of the semiconductor layer (120) cover at least a portion of the side walls of the cavities (150), and - step j) is implemented such that each of the contact regions (116, 118) is arranged in one of the cavities (150).

11. Method according to one of claims 9 or 10, comprising a step of depositing the gate dielectric layer (112) of the selection transistor implemented: - between steps f) and g), in the space formed by the etching of the temporary gate (142), the electrostatic control gate (110) of the selection transistor being in this case produced on the gate dielectric layer (112), and / or - between steps h) and i), in the locations formed by the etching of the portions of the second material (138), the semiconductor layer (120) then being produced by covering the gate dielectric layer (112).

12. Method according to one of claims 9 to 11, in which step i) is implemented such that the first zones (122) of the semiconductor layer (120) cover walls of the locations formed by the etching of the portions of the second material (138), and the method further comprises, between steps i) and j), a production of dielectric portions (126) in remaining spaces of the locations and such that each of the dielectric portions (126) is surrounded by the first zones (122) of the semiconductor layer (120).

13. Method according to one of claims 9 to 11, in which step i) is implemented such that the first zones (122) of the semi- conductor (120) fill the locations formed by the etching of the portions of the second material (138).

14. Method according to one of claims 9 to 13, further comprising, between steps d) and e), an etching of parts of the portions of the first material (136) arranged directly above the dielectric spacers (114), and a production of internal dielectric spacers (115) in place of the etched parts of the portions of the first material (136).

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